IDT IDT71V3558S133PFG

128K x 36, 256K x 18
3.3V Synchronous ZBT SRAMs
3.3V I/O, Burst Counter
Pipelined Outputs
Description
Features
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IDT71V3556S
IDT71V3558S
IDT71V3556SA
IDT71V3558SA
The IDT71V3556/58 are 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAMS. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or
writes and reads. Thus, they have been given the name ZBTTM, or
Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one
clock cycle, and two cycles later the associated data cycle occurs, be it
read or write.
The IDT71V3556/58 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V3556/58
to be suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is high and the internal device registers will hold
their previous values.
There are three chip enable pins (CE1, CE2, CE2) that allow the user
to deselect the device when desired. If any one of these three are not
asserted when ADV/LD is low, no new memory operation can be
initiated. However, any pending data transfers (reads or writes) will be
completed. The data bus will tri-state two cycles after chip is deselected
or a write is initiated.
128K x 36, 256K x 18 memory configurations
Supports high performance system speed - 200 MHz
(3.2 ns Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and read
cycles
Internally synchronized output buffer enable eliminates the
need to control OE
W (READ/WRITE) control pin
Single R/W
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
BW 1 - BW4) control (May tie active)
Individual byte write (BW
Three chip enables for simple depth expansion
3.3V power supply (±5%), 3.3V I/O Supply (VDDQ)
Optional- Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
Pin Description Summary
A0-A17
Address Inputs
Input
Synchronous
CE1, CE2, CE2
Chip Enables
Input
Synchronous
OE
Output Enable
Input
Asynchronous
R/W
Read/Write Signal
Input
Synchronous
CEN
Clock Enable
Input
Synchronous
BW1, BW2, BW3, BW4
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV/LD
Advance b urst address / Load new address
Input
Synchronous
LBO
Linear / Interleaved Burst Order
Input
Static
TMS
Test Mode Select
Input
Synchronous
TDI
Test Data Input
Input
Synchronous
TCK
Test Clock
Input
N/A
TDO
Test Data Output
Output
Synchronous
TRST
JTAG Reset (Optional)
Input
Asynchronous
ZZ
Sleep Mode
Input
Synchronous
I/O
Synchronous
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
VDD,
Core Power, I/O Power
Supply
Static
Ground
Supply
Static
VSS
VDDQ
5281 tbl 01
SEPTEMBER 2004
1
©2004 Integrated Device Technology, Inc.
DSC-5281/08
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
 Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT
Commercial and Industrial Temperature Ranges
Description continued
The IDT71V3556/58 has an on-chip burst counter. In the burst
mode, the IDT71V3556/58 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
Pin Definition(1)
external address (ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH).
The IDT71V3556/58 SRAMs utilize IDT's latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
Symbol
Pin Function
I/O
Active
Description
A 0-A 17
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,
ADV/LD low, CEN low, and true chip enables.
ADV/LD
Advance / Load
I
N/A
ADV/LD is a synchronous input that is used to load the internal registers with new addres s and control when it
is sampled low at the rising edge of clock with the chip selected. When ADV/ LD is low with the chip
deselected, any burst in progress is terminated. When ADV/ LD is sampled high then the internal burst counter
is advanced for any burst that was in progress. The external addresses are ignored when ADV/ LD is sampled
high.
R/W
Read / Write
I
N/A
R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write
access to the memory array. The data bus activity for the current cycle takes place two clock cycles later.
CEN
Clock Enable
I
LOW
Sync hronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock are
ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the low
to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of clock.
BW1-BW4
Individual Byte
Write Enables
I
LOW
Synchronous byte write enables. Each 9-bit b yte has its own active low byte write enable. On load write cycles
(When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW1-BW4) must be valid. The byte
write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/ W is
sampled high. The appropriate byte(s) of data are written into the de vice two cycles later. BW1-BW4 can all be
tied low if always doing write to the entire 36-bit word.
CE1, CE2
Chip Enables
I
LOW
Synchronous active low chip enable. CE1 and CE2 are used with CE 2 to enable the IDT71V3556/58. (CE1 or
CE2 sampled high or CE 2 sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle.
The ZBTTM has a two cycle deselect, i.e., the data bus will tri-state two clo ck cycles after deselect is initiated.
CE 2
Chip Enable
I
HIGH
Sync hronous active high chip enable. CE 2 is used with CE1 and CE2 to enable the chip. CE 2 has inverted
polarity but otherwise identical to CE1 and CE2.
CLK
Clock
I
N/A
This is the clock input to the IDT71V3556/58. Except for OE, all timing references for the device are made with
respect to the rising edge of CLK.
I/O0-I/O31
I/OP1-I/OP4
Data Input/Output
I/O
N/A
Synchronous data input/output (I/O) pins . Both the data input path and data output path are registered and
triggered by the rising edge of CLK.
LBO
Linear Burst Order
I
LOW
Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low
the Linear burst sequence is selected. LBO is a static input and it must not change during device operation.
OE
Output Enable
I
LOW
Asynchronous output enable. OE must be low to read data from the 71V3556/58. When OE is high the I/O pins
are in a high-impedance state. OE does not need to be actively controlled for read and write cycles. In normal
operation, OE can be tied low.
TMS
Test Mode Select
I
N/A
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
TDI
Test Data Input
I
N/A
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an internal
pullup.
TCK
Test Clock
I
N/A
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured o n rising edge of TCK,
while test outputs are d riven from the falling edge of TCK. This pin has an internal pullup.
TDO
Test Data Output
O
N/A
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the TAP
controller.
TRST
JTAG Reset
(Optional)
I
LOW
Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset
occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can
be left floating. This pin has an internal pullup. Only available in BGA package.
ZZ
Sleep Mode
I
HIGH
Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V3556/3558 to
its lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal
pulldown.
V DD
Power Supply
N/A
N/A
3.3V core power supply.
V DDQ
Power Supply
N/A
N/A
3.3V I/O Supply.
V SS
Ground
N/A
N/A
Ground.
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
2
5281 tbl 02
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
 Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT
Commercial and Industrial Temperature Ranges
Functional Block Diagram
128Kx36 BIT
MEMORY ARRAY
LBO
Address A [0:16]
D
Q
Address
D
Q
Control
C E1, CE2, C E2
R/W
Input Register
C EN
ADV/LD
BW x
D
DI
Q
DO
Control Logic
Clk
Mux
Sel
D
Clk
Clock
Output Register
Q
Gate
OE
5281 drw 01a
TMS
TDI
TCK
TR S T
JTAG
(SA Version)
TDO
(optional)
6.42
3
Data I/O [0:31],
I/O P[1:4]
,
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
 Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT
Commercial and Industrial Temperature Ranges
Functional Block Diagram
256x18 BIT
MEMORY ARRAY
LBO
Address A [0:17]
D
Q
Address
D
Q
Control
C E1, CE2, C E2
R/W
Input Register
C EN
ADV/LD
BW x
DI
D
Q
DO
Control Logic
Clk
Mux
Sel
D
Clk
Clock
Output Register
Q
Gate
OE
5281 drw 01b
TMS
TDI
TCK
TR S T
JTAG
(SA Version)
TDO
(optional)
Recommended DC Operating
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDQ
I/O Supply Voltage
3.135
3.3
3.465
V
VSS
Supply Voltage
0
0
0
V
VIH
Input High Voltage - Inputs
2.0
____
VDD +0.3
2.0
____
VIH
VIL
Input High Voltage - I/O
Input Low Voltage
(1)
-0.3
____
(2)
VDDQ +0.3
0.8
NOTES:
1. VIL (min.) = –1.0V for pulse width less than tCYC /2, once per cycle.
2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.
V
V
V
5281 tbl 04
6.42
4
Data I/O [0:15],
I/O P[1:2]
,
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
 Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT
Commercial and Industrial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage
Grade
Temperature(1)
VSS
VDD
VDDQ
Commercial
0°C to +70°C
0V
3.3V± 5%
3.3V± 5%
Industrial
-40°C to +85°C
0V
3.3V± 5%
3.3V± 5%
5281 tbl 05
NOTES:
1. TA is the "instant on" case temperature.
CE2
BW 4
BW 3
BW 2
BW 1
CE 2
VDD
VSS
CLK
R/W
CEN
OE
ADV/LD
NC(2)
NC(2)
A8
A9
A6
A7
CE 1
Pin Configuration - 128K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP3
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
VDDQ
I/O22
I/O23
VDD(1)
VDD
VDD(1)
VSS
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDDQ
I/O30
I/O31
I/OP4
1
80
2
79
3
78
77
4
5
6
76
75
7
74
8
73
9
72
71
10
11
70
12
69
13
68
14
67
15
66
16
65
64
17
18
19
63
62
20
61
21
60
22
59
23
24
58
57
25
56
26
55
27
54
53
28
29
52
51
30
I/OP2
I/O15
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDDQ
I/O9
I/O8
VSS
VDD(1)
VDD
VSS/ZZ(3)
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
I/OP1
,
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
LBO
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
NC
A10
A11
A12
A13
A14
A15
A16
5281 drw 02
Top View
100 TQFP
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.
2. Pins 83 and 84 are reserved for future 8M and 16M respectively.
3. Pin 64 does not have to be connected directly to V SS as long as the input voltage is ≤ VIL; on the latest die revision this
pin supports ZZ (sleep mode).
6.42
5
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
 Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings (1)
VDD
VSS
CLK
R/W
CEN
OE
ADV/LD
NC(2)
NC(2)
A8
A9
CE2
NC
NC
BW 2
BW 1
C E2
A6
A7
C E1
Pin Configuration - 256K x 18
Symbol
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
NC
1
80
2
79
3
78
VDDQ
VSS
NC
NC
I/O8
I/O9
VSS
VDDQ
I/O10
I/O11
VDD(1)
VDD
VDD(1)
VSS
I/O12
I/O13
VDDQ
VSS
I/O14
I/O15
I/OP2
NC
VSS
VDDQ
NC
NC
NC
4
77
5
6
76
75
7
74
8
73
9
10
11
72
71
70
12
69
13
68
14
67
66
15
16
65
64
17
18
63
62
19
20
21
61
60
22
59
23
24
58
57
25
56
26
55
27
28
54
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A10
NC
NC
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
VDD(1)
VDD
VSS/ZZ(3)
I/O3
I/O2
VDDQ
VSS
I/O1
I/O0
NC
NC
VSS
VDDQ
NC
NC
NC
LBO
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
NC
A11
A12
A13
A14
A15
A16
A17
CI/O
I/O Capacitance
V
VTERM(3,6)
Terminal Voltage with
Respect to GND
-0.5 to VDD
V
VTERM(4,6)
Terminal Voltage with
Respect to GND
-0.5 to VDD +0.5
V
VTERM(5,6)
Terminal Voltage with
Respect to GND
-0.5 to VDDQ +0.5
V
Commercial
Operating Temperature
-0 to +70
o
C
Industrial
Operating Temperature
-40 to +85
o
C
TBIAS
Temperature
Under Bias
-55 to +125
o
C
TSTG
Storage
Temperature
-55 to +125
o
C
PT
Power Dissipation
2.0
IOUT
DC Output Current
50
Conditions
Max.
Unit
Symbol
VIN = 3dV
5
pF
CIN
VOUT = 3dV
7
pF
CI/O
165 fBGA Capacitance(1)
(TA = +25° C, f = 1.0MHz)
Parameter(1)
CIN
Input Capacitance
CI/O
I/O Capacitance
W
mA
(TA = +25° C, f = 1.0MHz)
5281 tbl 07
Symbol
(7)
119 BGA Capacitance(1)
(TA = +25° C, f = 1.0MHz)
Input Capacitance
-0.5 to +4.6
TA
100 Pin TQFP Capacitance(1)
CIN
Terminal Voltage with
Respect to GND
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
7. TA is the "instant on" case temperature.
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as
the input voltage is ≥ VIH .
2. Pins 83 and 84 are reserved for future 8M and 16M respectively.
3. Pin 64 does not have to be connected directly to VSS as long as the input
voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep
mode).
Parameter(1)
Unit
5281 tbl 06
Top View
100 TQFP
Symbol
Commercial &
Industrial Values
VTERM(2)
,
5281 drw 02a
Rating
Conditions
Max.
Unit
VIN = 3dV
TBD
pF
VOUT = 3dV
TBD
pF
5281 tb l 07b
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.42
6
Parameter(1)
Conditions
Max.
Unit
Input Capacitance
VIN = 3dV
7
pF
I/O Capacitance
VOUT = 3dV
7
pF
5281 tbl 07a
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
 Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT
Commercial and Industrial Temperature Ranges
Pin Configuration - 128K x 36, 119 BGA
1
2
3
4
5
6
7
A
VDDQ
A6
A4
NC(2)
A8
A16
VDDQ
ADV/LD
A9
C E2
NC
A12
A15
NC
NC
VSS
I/OP2
I/O15
C E1
VSS
I/O13
I/O14
VSS
OE
VSS
I/O12
VDDQ
BW 3
NC(2)
BW 2
I/O11
I/O10
VSS
R/W
VSS
I/O9
I/O8
VDD(1)
VDD
VDD(1)
VDD
VDDQ
I/O26
VSS
CLK
VSS
I/O6
I/O7
I/O27
BW 4
NC
BW 1
I/O4
I/O5
VDDQ
I/O28
VSS
C EN
VSS
I/O3
VDDQ
I/O29
I/O30
VSS
A1
VSS
I/O2
I/O1
P
I/O31
I/OP4
VSS
A0
VSS
I/OP1
I/O 0
R
NC
A5
LBO
VDD
A13
NC
T
NC
NC
A 10
A11
U
VDDQ
B
NC
CE 2
A3
C
NC
A7
A2
VDD
D
I/O16
I/OP3
VSS
E
I/O17
I/O18
VSS
F
VDDQ
I/O19
G
I/O20
I/O21
H
I/O22
I/O23
J
VDDQ
V DD
K
I/O24
L
I/O25
M
N
VDD(1)
A14
NC
NC/TMS(3) NC/TDI(3) NC/TCK(3) NC/TDO(3) NC/TRST(3,4)
,
NC/ZZ(5)
VDDQ
5281 drw 13A
Top View
Pin Configuration - 256K x 18, 119 BGA
1
2
3
4
5
6
7
A
VDDQ
A6
A4
NC(2)
A8
A16
VDDQ
B
NC
CE2
A3
ADV/LD
A9
C E2
NC
C
NC
A7
A2
VDD
A13
A17
NC
D
I/O8
NC
VSS
NC
VSS
I/OP1
NC
E
NC
I/O9
VSS
CE 1
VSS
NC
I/O7
F
VDDQ
NC
VSS
OE
VSS
I/O6
VDDQ
G
NC
I/O10
BW 2
NC(2)
VSS
NC
I/O5
H
I/O11
NC
VSS
R/W
VSS
I/O4
NC
J
VDDQ
VDD
VDD(1)
VDD
VDD(1)
VDD
VDDQ
K
NC
I/O12
VSS
CLK
VSS
NC
I/O3
L
I/O13
NC
VSS
NC
BW 1
I/O2
NC
M
VDDQ
I/O14
VSS
CEN
VSS
NC
VDDQ
N
I/O15
NC
VSS
A1
VSS
I/O1
NC
P
NC
I/OP2
VSS
A0
VSS
NC
I/O0
R
NC
A5
LBO
VDD
V DD(1)
A12
T
NC
A 10
A15
NC
A14
A11
U
VDDQ
NC
NC/ZZ(5)
NC/TMS(3) NC/TDI(3) NC/TCK(3) NC/TDO(3) NC/TRST(3,4) VDDQ
,
5281drw 13B
Top View
NOTES:
1. J3, J5, and R5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH .
2. G4 and A4 are reserved for future 8M and 16M respectively.
3. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version.
4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
5. Pin T7 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep mode).
6.42
7
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
 Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT
Commercial and Industrial Temperature Ranges
Pin Configuration - 128K x 36, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
A
NC(2)
A7
CE1
BW3
BW2
CE2
CEN
ADV/LD
NC(2)
A8
NC
B
NC
A6
CE2
BW4
BW1
CLK
R/W
OE
NC(2)
A9
NC(2)
C
I/OP3
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
I/OP2
D
I/O17
I/O16
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O15
I/O14
E
I/O19
I/O18
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O13
I/O12
F
I/O21
I/O20
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O11
I/O10
G
I/O23
I/O22
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O9
I/O8
H
VDD(1)
VDD(1)
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
NC/ZZ(5)
J
I/O25
I/O24
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O7
I/O6
K
I/O27
I/O26
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O5
I/O4
L
I/O29
I/O28
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O3
I/O2
M
I/O31
I/O30
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O1
I/O0
N
I/OP4
NC
VDDQ
VSS
NC/TRST (3,4)
NC
VDD(1)
VSS
VDDQ
NC
I/OP1
P
NC
NC(2)
A5
A2
NC/TDI(3)
A1
NC/TDO(3)
A10
A13
A14
NC
R
LBO
NC(2)
A4
A3
NC/TMS (3)
A0
NC/TCK(3)
A11
A12
A15
A16
5281 tbl 25
Pin Configuration - 256K x 18, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
(2)
A
NC
A7
CE1
BW2
NC
CE2
CEN
ADV/LD
NC
A8
A10
B
NC
A6
CE2
NC
BW1
CLK
R/W
OE
NC(2)
A9
NC(2)
C
NC
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
I/OP1
D
NC
I/O8
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
I/O7
E
NC
I/O9
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
I/O6
F
NC
I/O10
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
I/O5
G
NC
I/O11
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
I/O4
H
VDD(1)
VDD(1)
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
NC/ZZ(5)
J
I/O12
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O3
NC
K
I/O13
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O2
NC
L
I/O14
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O1
NC
M
I/O15
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O0
NC
N
I/OP2
NC
VDDQ
VSS
NC/TRST (3, 4)
NC
VDD(1)
(2)
P
NC
R
LBO
(2)
NC
(2)
NC
A5
A4
A2
A3
(3)
NC/TDI
NC/TMS
(3)
A1
A0
VSS
VDDQ
NC
NC
(3)
A11
A14
A15
NC
(3)
A12
A13
A16
A17
NC/TDO
NC/TCK
5281 tbl 25a
NOTES:
1. H1, H2, and N7 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. A9, B9, B11, A1, R2 and P2 are reserved for future 9M, 18M, 36M, 72M, 144M and 288M respectively.
3. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version.
4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
5. Pin H11 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep mode).
6.42
8
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
 Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT
Commercial and Industrial Temperature Ranges
Synchronous Truth Table (1)
CEN
R/W
Chip(5)
Enable
ADV/ LD
BWx
ADDRESS
USED
PREVIOUS CYCLE
CURRENT CYCLE
I/O
(2 cycles later)
L
L
Select
L
Valid
External
X
LOAD WRITE
D(7)
L
H
Select
L
X
External
X
LOAD READ
Q(7)
L
X
X
H
Valid
Internal
LOAD WRITE /
BURST WRITE
BURST WRITE
(Advance burst counter)(2)
D(7)
L
X
X
H
X
Internal
LOAD READ /
BURST READ
BURST READ
(Advance burst counter)(2)
Q(7)
L
X
Deselect
L
X
X
X
DESELECT or STOP(3)
HiZ
L
X
X
H
X
X
DESELECT / NOOP
NOOP
HiZ
H
X
X
X
X
X
X
SUSPEND(4)
Previous Value
5281 tbl 08
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
Partial Truth Table for Writes
(1)
OPERATION
READ
WRITE ALL BYTES
(2)
WRITE BYTE 1 (I/O[0:7], I/OP1)
WRITE BYTE 2 (I/O[8:15], I/OP2)(2)
R/W
BW1
BW2
BW3(3)
BW4(3)
H
X
X
X
X
L
L
L
L
L
L
L
H
H
H
L
H
L
H
H
(2,3)
L
H
H
L
H
(2,3)
WRITE BYTE 4 (I/O[24:31], I/OP4)
L
H
H
H
L
NO WRITE
L
H
H
H
H
WRITE BYTE 3 (I/O[16:23], I/OP3)
5281 tbl 09
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for X18 configuration.
6.42
9
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
 Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT
Commercial and Industrial Temperature Ranges
Interleaved Burst Sequence Table (LBO=V DD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
0
0
1
1
1
0
Third Address
1
0
1
1
0
0
0
1
Fourth Address (1)
1
1
1
0
0
1
0
0
5281 tbl 10
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Linear Burst Sequence Table (LBO=V SS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
1
0
1
1
0
0
Third Address
1
0
1
1
0
0
0
1
1
1
0
0
0
1
1
0
Fourth Address
(1)
5281 tbl 11
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Functional Timing Diagram (1)
CYCLE
n+29
n+30
n+31
n+32
n+33
n+34
n+35
n+36
n+37
A29
A30
A31
A32
A33
A34
A35
A36
A37
C29
C30
C31
C32
C33
C34
C35
C36
C37
D/Q27
D/Q28
D/Q29
D/Q30
D/Q31
D/Q32
D/Q33
D/Q34
D/Q35
CLOCK
(2)
ADDRESS
(A0 - A16)
(2)
CONTROL
(R/W , ADV/LD, BW x)
(2)
DATA
I/O [0:31], I/O P[1:4]
5281 drw 03
,
NOTES:
1. This assumes CEN, CE1, CE2, CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
6.42
10
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
 Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT
Commercial and Industrial Temperature Ranges
Device Operation - Showing Mixed Load, Burst,
Deselect and NOOP Cycles (2)
Cycle
Address
R/ W
ADV/LD
CE(1)
CEN
BWx
OE
I/O
Comments
n
A0
H
L
L
L
X
X
X
Load read
n+1
X
X
H
X
L
X
X
X
Burst read
n+2
A1
H
L
L
L
X
L
Q0
Load read
n+3
X
X
L
H
L
X
L
Q0+1
n+4
X
X
H
X
L
X
L
Q1
NOOP
n+5
A2
H
L
L
L
X
X
Z
Load read
n+6
X
X
H
X
L
X
X
Z
Burst read
n+7
X
X
L
H
L
X
L
Q2
Deselect or STOP
n+8
A3
L
L
L
L
L
L
Q2+1
Load write
n+9
X
X
H
X
L
L
X
Z
Burst write
n+10
A4
L
L
L
L
L
X
D3
Load write
n+11
X
X
L
H
L
X
X
D3+1
n+12
X
X
H
X
L
X
X
D4
NOOP
n+13
A5
L
L
L
L
L
X
Z
Load write
n+14
A6
H
L
L
L
X
X
Z
Load read
n+15
A7
L
L
L
L
L
X
D5
Load write
n+16
X
X
H
X
L
L
L
Q6
Burst write
n+17
A8
H
L
L
L
X
X
D7
Load read
n+18
X
X
H
X
L
X
X
D7+1
Burst read
n+19
A9
L
L
L
L
L
L
Q8
Load write
Deselect or STOP
Deselect or STOP
5281 tbl 12
NOTES:
1. CE = L is defined as CE1 = L, CE2 = L and CE 2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
2. H = High; L = Low; X = Don’t Care; Z = High Impedance.
Read Operation (1)
Cycle
Address
R/ W
ADV/LD
CE(2)
CEN
BWx
OE
I/O
Comments
n
A0
H
L
L
L
X
X
X
Address and Control meet setup
n+1
X
X
X
X
L
X
X
X
Clock Setup Valid
n+2
X
X
X
X
X
X
L
Q0
Contents of Address A0 Read Out
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
11
5281 tbl 13
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
 Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT
Commercial and Industrial Temperature Ranges
Burst Read Operation (1)
Cycle
Address
R/ W
ADV/LD
CE(2)
CEN
BWx
OE
I/O
Comments
n
A0
H
L
L
L
X
X
X
Address and Control meet setup
n+1
X
X
H
X
L
X
X
X
Clock Setup Valid, Advance Counter
n+2
X
X
H
X
L
X
L
Q0
Address A0 Read Out, Inc. Count
n+3
X
X
H
X
L
X
L
Q0+1
Address A0+1 Read Out, Inc. Count
n+4
X
X
H
X
L
X
L
Q0+2
Address A0+2 Read Out, Inc. Count
n+5
A1
H
L
L
L
X
L
Q0+3
Address A0+3 Read Out, Load A1
n+6
X
X
H
X
L
X
L
Q0
Address A0 Read Out, Inc. Count
n+7
X
X
H
X
L
X
L
Q1
Address A1 Read Out, Inc. Count
n+8
A2
H
L
L
L
X
L
Q1+1
Address A1+1 Read Out, Load A2
5281 tbl 14
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance..
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation
(1)
Cycle
Address
R/ W
ADV/LD
CE(2)
CEN
BWx
OE
I/O
Comments
n
A0
L
L
L
L
L
X
X
Address and Control meet setup
n+1
X
X
X
X
L
X
X
X
Clock Setup Valid
n+2
X
X
X
X
L
X
X
D0
Write to Address A0
5281 tbl 15
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Burst Write Operation
(1)
Cycle
Address
R/ W
ADV/LD
CE(2)
CEN
BWx
OE
I/O
Comments
n
A0
L
L
L
L
L
X
X
Address and Control meet setup
n+1
X
X
H
X
L
L
X
X
Clock Setup Valid, Inc. Count
n+2
X
X
H
X
L
L
X
D0
Address A0 Write, Inc. Count
n+3
X
X
H
X
L
L
X
D0+1
Address A0+1 Write, Inc. Count
n+4
X
X
H
X
L
L
X
D0+2
Address A0+2 Write, Inc. Count
n+5
A1
L
L
L
L
L
X
D0+3
Address A0+3 Write, Load A1
n+6
X
X
H
X
L
L
X
D0
Address A0 Write, Inc. Count
n+7
X
X
H
X
L
L
X
D1
Address A1 Write, Inc. Count
n+8
A2
L
L
L
L
L
X
D1+1
Address A1+1 Write, Load A2
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
12
5281 tbl 16
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
 Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT
Commercial and Industrial Temperature Ranges
Read Operation with Clock Enable Used (1)
Cycle
Address
R/ W
ADV/LD
CE(2)
CEN
BWx
OE
I/O
Comments
n
A0
H
L
L
L
X
X
X
Address and Control meet setup
n+1
X
X
X
X
H
X
X
X
Clock n+1 Ignored
n+2
A1
H
L
L
L
X
X
X
Clock Valid
n+3
X
X
X
X
H
X
L
Q0
Clock Ignored. Data Q0 is on the bus.
n+4
X
X
X
X
H
X
L
Q0
Clock Ignored. Data Q0 is on the bus.
n+5
A2
H
L
L
L
X
L
Q0
Address A0 Read out (bus trans.)
n+6
A3
H
L
L
L
X
L
Q1
Address A1 Read out (bus trans.)
n+7
A4
H
L
L
L
X
L
Q2
Address A2 Read out (bus trans.)
5281 tbl 17
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation with Clock Enable Used (1)
Cycle
Address
R/ W
ADV/LD
CE(2)
CEN
BWx
OE
I/O
Comments
n
A0
L
L
L
L
L
X
X
Address and Control meet setup.
n+1
X
X
X
X
H
X
X
X
Clock n+1 Ignored.
n+2
A1
L
L
L
L
L
X
X
Clock Valid.
n+3
X
X
X
X
H
X
X
X
Clock Ignored.
n+4
X
X
X
X
H
X
X
X
Clock Ignored.
n+5
A2
L
L
L
L
L
X
D0
Write Data D0
n+6
A3
L
L
L
L
L
X
D1
Write Data D1
n+7
A4
L
L
L
L
L
X
D2
Write Data D2
5281 tbl 18
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
13
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
 Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT
Commercial and Industrial Temperature Ranges
Read Operation with CHIP Enable Used (1)
Cycle
Address
R/ W
ADV/LD
CE(2)
CEN
BWx
OE
I/O(3)
Comments
n
X
X
L
H
L
X
X
?
Deselected.
n+1
X
X
L
H
L
X
X
?
Deselected.
n+2
A0
H
L
L
L
X
X
Z
Address and Control meet setup
n+3
X
X
L
H
L
X
X
Z
Deselected or STOP.
n+4
A1
H
L
L
L
X
L
Q0
Address A0 Read out. Load A 1.
n+5
X
X
L
H
L
X
X
Z
Deselected or STOP.
n+6
X
X
L
H
L
X
L
Q1
Address A1 Read out. Deselected.
n+7
A2
H
L
L
L
X
X
Z
Address and control meet setup.
n+8
X
X
L
H
L
X
X
Z
Deselected or STOP.
n+9
X
X
L
H
L
X
L
Q2
Address A2 Read out. Deselected.
5281 tbl 19
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
Write Operation with Chip Enable Used (1)
Cycle
Address
R/ W
ADV/LD
CE(2)
CEN
BWx
OE
I/O(3)
Comments
n
X
X
L
H
L
X
X
?
Deselected.
n+1
X
X
L
H
L
X
X
?
Deselected.
n+2
A0
L
L
L
L
L
X
Z
Address and Control meet setup
n+3
X
X
L
H
L
X
X
Z
Deselected or STOP.
n+4
A1
L
L
L
L
L
X
D0
Address D0 Write in. Load A 1.
n+5
X
X
L
H
L
X
X
Z
Deselected or STOP.
n+6
X
X
L
H
L
X
X
D1
Address D1 Write in. Deselected.
n+7
A2
L
L
L
L
L
X
Z
Address and control meet setup.
n+8
X
X
L
H
L
X
X
Z
Deselected or STOP.
n+9
X
X
L
H
L
X
X
D2
Address D2 Write in. Deselected.
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
14
5281 tbl 20
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
 Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V +/-5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
5
µA
|ILI|
Input Leakage Current
VDD = Max., VIN = 0V to V DD
___
|ILI|
LBO, JTAG and ZZ Input Leakage Current(1)
VDD = Max., VIN = 0V to V DD
___
30
µA
5
µA
|ILO|
Output Leakage Current
VOUT = 0V to V DDQ , Device Deselected
___
VOL
Output Low Voltage
IOL = +8mA, VDD = Min.
___
0.4
V
VOH
Output High Voltage
IOH = -8mA, VDD = Min.
2.4
___
V
5281 tbl 21
NOTE:
1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and ZZ will be internally pulled if they are not actively driven in the application.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (1) (VDD = 3.3V +/-5%)
200MHz
Symbol
Parameter
Test Conditions
166MHz
133MHz
100MHz
Com'l Only
Com'l
Ind
Com'l
Ind
Com'l
Ind
Unit
400
350
360
300
310
250
255
mA
IDD
Operating Power
Supply Current
Device Selected, Outputs Open,
ADV/LD = X, VDD = Max.,
VIN > VIH or < VIL, f = fMAX(2)
ISB1
Device Deselected, Outputs Open,
CMOS Standby
Power Supply Current VDD = Max., VIN > VHD or < VLD, f
= 0(2,3)
40
40
45
40
45
40
45
mA
ISB2
Clock Running Power Device Deselected, Outputs Open,
VDD = Max., VIN > VHD or < VLD, f
Supply Current
= fMAX(2.3)
130
120
130
110
120
100
110
mA
ISB3
Idle Power
Supply Current
40
40
45
40
45
40
45
mA
Device Selected, Outputs Open,
CEN > VIH, VDD = Max.,
VIN > VHD or < VLD, f = fMAX(2,3)
5281 tbl 22
NOTES:
1. All values are maximum guaranteed values.
2. At f = f MAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.
AC Test Loads
AC Test Conditions
VDDQ/2
(VDDQ = 3.3V)
50Ω
I/O
6
Input Pulse Levels
Z0 = 50Ω
5281 drw 04
5
,
Figure 1. AC Test Load
4
Input Rise/Fall Times
2ns
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
AC Test Load
∆tCD 3
(Typical, ns)
2
0 to 3V
See Figure 1
5281 tbl 23
1
20 30 50
80 100
Capacitance (pF)
,
200
5281 drw 05
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
15
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
 Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V +/-5%, Commercial and Industrial Temperature Ranges)
166MHz
200MHz(6)
Symbol
Parameter
133MHz
100MHz
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tCYC
Clock Cycle Time
5
____
6
____
7.5
____
10
____
ns
tF(1)
Clock Frequence
____
200
____
166
____
133
____
100
MHz
tCH(2)
Clock High Pulse Width
1.8
____
1.8
____
2.2
____
3.2
____
ns
tCL(2)
Clock Low Pulse Width
1.8
____
1.8
____
2.2
____
3.2
____
ns
____
3.2
____
3.5
____
4.2
____
5
ns
Output Parameters
tCD
Clock High to Valid Data
tCDC
Clock High to Data Change
1
____
1
____
1
____
1
____
ns
tCLZ(3,4,5)
Clock High to Output Active
1
____
1
____
1
____
1
____
ns
tCHZ(3,4,5)
Clo ck High to Data High-Z
1
3
1
3
1
3
1
3.3
ns
tOE
Output Enable Access Time
____
3.2
____
3.5
____
4.2
____
5
ns
tOLZ(3,4)
Output Enable Low to Data Active
0
____
0
____
0
____
0
____
ns
tOHZ(3,4)
Output Enable High to Data High-Z
____
3.5
____
3.5
____
4.2
____
5
ns
Set Up Times
tSE
Clock Enable Setup Time
1.5
____
1.5
____
1.7
____
2.0
____
ns
tSA
Address Setup Time
1.5
____
1.5
____
1.7
____
2.0
____
ns
1.5
____
1.7
____
2.0
____
ns
tSD
Data In Setup Time
1.5
____
tSW
Read/Write (R/W) Setup Time
1.5
____
1.5
____
1.7
____
2.0
____
ns
tSADV
Advance/Load (ADV/ LD) Setup Time
1.5
____
1.5
____
1.7
____
2.0
____
ns
tSC
Chip Enable/Select Setup Time
1.5
____
1.5
____
1.7
____
2.0
____
ns
tSB
Byte Write Enable (BWx) Setup Time
1.5
____
1.5
____
1.7
____
2.0
____
ns
tHE
Clock Enable Hold Time
0.5
____
0.5
____
0.5
____
0.5
____
ns
tHA
Address Hold Time
0.5
____
0.5
____
0.5
____
0.5
____
ns
tHD
Data In Hold Time
0.5
____
0.5
____
0.5
____
0.5
____
ns
tHW
Read/Write (R/W) Hold Time
0.5
____
0.5
____
0.5
____
0.5
____
ns
tHADV
Advance/Load (ADV/ LD) Hold Time
0.5
____
0.5
____
0.5
____
0.5
____
ns
0.5
____
0.5
____
0.5
____
ns
0.5
____
0.5
____
0.5
____
ns
Hold Times
tHC
Chip Enable/Select Hold Time
0.5
____
tHB
Byte Write Enable (BWx) Hold Time
0.5
____
5281 tbl 24
NOTES:
1. tF = 1/tCYC.
2. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ,
which is a Max. parameter (worse case at 70 deg. C, 3.135V).
6. Commercial temperature range only.
6.42
16
6.42
17
1
4
OE
- BW
A1
tSADV
tHA
tHW
tHE
tCLZ
tHC
Pipeline
Read
tSC
A2
tSA
tSW
tSE
tCD
Pipeline
Read
Q(A1)
tHADV
tCH
Q(A2)
tCDC
tCL
Q(A2+1)
Q(A2+2)
(CEN high, eliminates
current L-H clock edge)
Burst Pipeline Read
tCD
Q(A2+2)
tCDC
Q(A2+3)
tCHZ
Q(A2)
5281 drw 06
(Burst Wraps around
to initial state)
,
,
NOTES:
1. Q (A1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the burst sequence
of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are
loaded into the SRAM.
DATAOUT
BW
C E 1, CE 2
(2)
ADDRESS
R/W
ADV/LD
C EN
CLK
tCYC
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
 Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle (1,2,3,4)
(2)
6.42
18
DATAIN
OE
tHW
tHB
tHC
Pipeline
Write
tSB
tSC
tHA
A2
tSA
tSW
tHE
tHD
Pipeline
Write
D(A1)
tSD
tHADV
tCH
D(A2)
tCL
D(A2+1)
Burst Pipeline Write
(CEN high, eliminates
current L-H clock edge)
tSD
D(A2+2)
tHD
D(A2)
5281 drw 07
D(A2+3)
(Burst Wraps around
to initial state)
,
,
NOTES:
1. D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence of
the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are
loaded into the SRAM.
5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before
the actual data is presented to the SRAM.
A1
tSADV
tSE
Timing Waveform of Write Cycles
BW 1 - BW 4
C E1, C E2
ADDRESS
R/W
ADV/LD
C EN
CLK
tCYC
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
 Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT
Commercial and Industrial Temperature Ranges
(1,2,3,4,5)
6.42
19
4
OE
BW
DATAIN
1-
DATAOUT
BW
C E 1, C E 2(2)
ADDRESS
R/W
ADV/LD
C EN
CLK
tHW
tCD
tHB
tHC
Read
tSB
tSC
tHA
A2
tSA
tSW
tHE
A3
Q(A1)
tCHZ
Write
tHADV
tCH
tCLZ
Read
D(A2)
tSD tHD
A4
tCL
Q(A3)
tCDC
Write
A5
D(A4)
A6
Read
D(A5)
A7
Q(A6)
A8
,
Q(A7)
A9
5281 drw 08
,
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before
the actual data is presented to the SRAM.
A1
tSADV
tSE
tCYC
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
 Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Read and Write Cycles (1,2,3)
,
6.42
20
A1
tSE
tSADV
tHE
tHW
tHC
tCD
tCLZ
tHB
B(A2)
tSB
tSC
tHA
A2
tSA
tSW
tCH
tHADV
Q(A1)
tCL
tCHZ
tCDC
Q(A1)
A3
D(A2)
tSD tHD
A4
A5
5281 drw 09
Q(A3)
,
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not occur. All
internal registers in the SRAM will retain their previous state.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before
the actual data is presented to the SRAM.
DATAOUT
DATAIN
OE
BW 1 - BW 4
C E 1, C E 2(2)
ADDRESS
R/W
ADV/LD
C EN
CLK
tCYC
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
 Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT
Commercial and Industrial Temperature Ranges
Timing Waveform of CEN Operation (1,2,3,4)
6.42
21
(2)
A1
tSADV
tHW
tHE
tSC
tCLZ
tCD
tHC
tHA
A2
tSA
tSW
tSE
Q(A1)
tHADV
tCH
tCDC
tCHZ
tHB
Q(A2)
tSB
A3
tCL
D(A3)
tSD tHD
A4
Q(A4)
A5
5281 drw 10
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not occur. All
internal registers in the SRAM will retain their previous state.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before
the actual data is presented to the SRAM.
DATAOUT
DATAIN
OE
BW 1 - BW 4
C E1, C E 2
ADDRESS
R/W
ADV/LD
C EN
CLK
tCYC
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
 Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT
Commercial and Industrial Temperature Ranges
Timing Waveform of CS Operation (1,2,3,4)
,
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
 Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT
Commercial and Industrial Temperature Ranges
JTAG Interface Specification (SA Version only)
tJF
tJCL
tJCYC
tJR
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJS
Device Outputs(2)/
TDO
tJDC
tJH
tJRSR
tJCD
TRST(3)
x
M5281 drw 01
tJRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
JTAG AC Electrical
Characteristics(1,2,3,4)
Symbol
Parameter
Min.
Max.
Units
tJCYC
JTAG Clock Input Period
100
____
ns
tJCH
JTAG Clock HIGH
40
____
ns
tJCL
JTAG Clock Low
40
____
ns
tJR
JTAG Clock Rise Time
____
5(1)
ns
tJF
JTAG Clock Fall Time
____
5(1)
ns
JTAG Identification (JIDR)
tJRST
JTAG Reset
50
____
ns
Boundary Scan (BSR)
tJRSR
JTAG Reset Recovery
50
____
ns
tJCD
JTAG Data Output
____
20
ns
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.
0
____
ns
ns
ns
tJDC
JTAG Data Output Hold
tJS
JTAG Setup
25
____
tJH
JTAG Hold
25
____
Scan Register Sizes
Register Name
Bit Size
Instruction (IR)
4
Bypass (BYR)
1
32
Note (1)
I5281 tbl 03
I5281 tbl 01
NOTES:
1. Guaranteed by design.
2. AC Test Load (Fig. 1) on external output signals.
3. Refer to AC Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
6.42
22
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
 Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT
Commercial and Industrial Temperature Ranges
JTAG Identification Register Definitions (SA Version only)
Instruction Field
Value
Revision Number (31:28)
Description
0x2
IDT Device ID (27:12)
0x208, 0x20A
IDT JEDEC ID (11:1)
0x33
ID Register Indicator Bit (Bit 0)
Reserved for version number.
Defines IDT part number 71V3556SA and 71V3558SA, respectively.
Allows unique identification of device vendor as IDT.
1
Indicates the presence of an ID register.
I5281 tbl 02
Available JTAG Instructions
Instruction
Description
OPCODE
EXTEST
Forces contents of the boundary scan cells onto the device outputs (1).
Places the boundary scan register (BSR) between TDI and TDO.
0000
SAMPLE/PRELOAD
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) and outputs(1) to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
0001
DEVICE_ID
Loads the JTAG ID register (JIDR) with the vendor ID code and places
the register between TDI and TDO.
0010
HIGHZ
Places the bypass register (BYR) between TDI and TDO. Forces all
device o utput drivers to a High-Z state.
0011
RESERVED
RESERVED
RESERVED
0100
Several combinations are reserved. Do not use codes other than those
identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,
VALIDATE and BYPASS instructions.
RESERVED
CLAMP
0101
0110
0111
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the byp ass registe r (BYR) between TDI and TDO.
RESERVED
1000
1001
RESERVED
1010
Same as above.
RESERVED
1011
RESERVED
1100
VALIDATE
Automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits '01'
are mand ated by the IEEE std. 1149.1 specification.
1101
RESERVED
Same as above.
1110
BYPASS
The BYPASS instruction is used to truncate the boundary scan register
as a single bit in length.
1111
I5281 tbl 04
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
6.42
23
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
 Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT
Commercial and Industrial Temperature Ranges
100-Pin Plastic Thin Quad Flatpack (TQFP) Package Diagram Outline
6.42
24
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
 Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT
Commercial and Industrial Temperature Ranges
119 Ball Grid Array (BGA) Package Diagram Outline
6.42
25
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
 Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT
Commercial and Industrial Temperature Ranges
165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline
6.42
26
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
 Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT
Commercial and Industrial Temperature Ranges
Timing Waveform of OE Operation (1)
OE
tOE
tOHZ
tOLZ
DATAOUT
Valid
5281 drw 11
NOTE:
1. A read operation is assumed to be in progress.
Ordering Information
IDT
XXXX
XX
XX
XX
Device
Type
Power
Speed
Package
X
X
Process/
Process/
Temperature Temperature
Range
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G
Restricted Hazardous Substance Device
PF**
BG
BQ
100-pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 Fine Pitch Ball Grid Array (fBGA)
200*
166
133
100
Clock Frequency in Megahertz
S
SA
Standard Power
Standard Power with JTAG interface
IDT71V3556
IDT71V3558
128Kx36 Pipelined ZBT SRAM with 3.3V I/O
256Kx18 Pipelined ZBT SRAM with 3.3V I/O
,
5281 drw 12
* C o m m e rc ia l te m p e ra tu re ra n g e o n ly
** J T A G (S A V e rs io n ) is n o t a va ila b le w ith 1 0 0 -p in T Q FP p a c k a g e
6.42
27
,
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
 Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
ZBT
Commercial and Industrial Temperature Ranges
Datasheet Document History
6/30/99
8/23/99
Pg. 4, 5
Pg. 6
Pg. 14
Pg. 15
Pg. 22
Pg. 24
Pg. 14
Pg. 15
10/4/99
12/31/99
04/30/00
Pg. 5, 6
Pg. 6
Pg. 5,6, 7
Pg. 21
05/26/00
07/26/00
Pg. 23
Pg. 5-8
Pg. 8
Pg. 23
10/25/00
1/24/02
9/30 /04
Pg. 8
Pg. 1-8, 15,22,23,27
Pg. 7
Pg. 27
Updated to new format
Added Smart ZBT functionality
Added Note 4 and changed Pins 38, 42, and 43 to DNU
Changed U2–U6 to DNU
Added Smart ZBT AC Electrical Characteristics
Improved tCD and tOE(MAX) at 166MHz
Revised tCHZ(MIN) for f ≤ 133 MHz
Revised tOHZ (MAX) for f ≤ 133 MHz
Improved tCH, tCL for f ≤ 166 MHz
Improved setup times for 100–200 MHz
Added BGA package diagrams
Added Datasheet Document History
Revised AC Electrical Characteristics table
Revised tCHZ to match tCLZ and tCDC at 133MHz and 100MHz
Removed Smart functionality
Added Industrial Temperature range offerings at the 100 to 166MHz speed grades.
Insert clarification note to Recommended Operating Temperature and Absolute Max
Ratings tables
Add BGA capacitance table
Add note to TQFP and BGA Pin Configurations; corrected typo in pinout
Add 100pinTQFP package Diagram Outline
Add new package offering, 13 x 15mm 165 fBGA
Correct 119BGA Package Diagram Outline
Add ZZ sleep mode reference note to BG119, PK100 and BQ165 pinouts
Update BQ165 pinout
Update BG119 package diagram outline dimensions
Remove Preliminary status
Add note to pin N5 on BQ165, reserved for JTAG TRST
Added JTAG "SA" version functionality
Updated pin configuration for the 119 BGA-reordered I/O signals on P6, P7 (128K x 36)
and P7, N6, L6, K7, H6, G7, F6, E7, D6 (256K x 18).
Adding "Restricted hazardous substance device" to ordering information.
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
for Tech Support:
[email protected]
800-544-7726
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
ZBT® and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
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