IDT IDT71V67802

256K X 36, 512K X 18
3.3V Synchronous SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs, Single Cycle Deselect
Features
◆
◆
◆
◆
◆
◆
◆
◆
IDT71V67602
IDT71V67802
Description
256K x 36, 512K x 18 memory configurations
Supports high system speed:
– 166MHz 3.5ns clock access time
– 150MHz 3.8ns clock access time
– 133MHz 4.2ns clock access time
LBO input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW), byte
write enable (BWE), and byte writes (BWx)
3.3V core power supply
Power down controlled by ZZ input
2.5V I/O supply (VDDQ)
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array.
The IDT71V67602/7802 are high-speed SRAMs organized as
256K x 36/512K x 18. The IDT71V676/78 SRAMs contain write, data,
address and control registers. Internal logic allows the SRAM to generate
a self-timed write based upon a decision which can be left until the end of
the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V67602/7802 can provide four cycles of
data for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.
The IDT71V67602/7802 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array (fBGA).
Pin Description Summary
A0-A18
Address Inputs
Input
Synchronous
CE
Chip Enable
Input
Synchronous
CS 0, CS1
Chip Selects
Input
Synchronous
OE
Output Enable
Input
Asynchronous
GW
Global Write Enable
Input
Synchronous
BWE
Byte Write Enable
Input
Synchronous
BW1, BW2, BW3, BW4(1)
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV
Burst Address Advance
Input
Synchronous
ADSC
Address Status (Cache Controller)
Input
Synchronous
ADSP
Address Status (Processor)
Input
Synchronous
LBO
Linear / Interleaved Burst Order
Input
DC
ZZ
Sleep Mode
Input
Asynchronous
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
I/O
Synchronous
VDD, VDDQ
Core Power, I/O Power
Supply
N/A
VSS
Ground
Supply
N/A
5311 tbl 01
NOTE:
1. BW3 and BW4 are not applicable for the IDT71V67802.
NOVEMBER 2002
1
©2002 Integrated Device Technology, Inc.
DSC-5311/05
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Definitions(1)
Symbol
Pin Function
I/O
Active
Description
A0-A18
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combination of the
rising edge of CLK and ADSC Low or ADSP Low and CE Low.
ADSC
Address Status
(Cache Controller)
I
LOW
Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is
used to load the address registers with new addresses.
ADSP
Address Status
(Processor)
I
LOW
Synchronous Address Status from Processor. ADSP is an active LOW input that is used to
load the address registers with new addresses. ADSP is gated by CE.
ADV
Burst Address
Advance
I
LOW
Synchronous Address Advance. ADV is an active LOW input that is used to advance the
internal burst counter, controlling burst access after the initial address is loaded. When the
input is HIGH the burst counter is not incremented; that is, there is no address advance.
BWE
Byte Write Enable
I
LOW
Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the
rising edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is
HIGH then the byte write inputs are blocked and only GW can initiate a write cycle.
BW1-BW4
Individual Byte
Write Enables
I
LOW
Synchronous byte write enables. BW1 controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc.
Any active byte write causes all outputs to be disabled.
CE
Chip Enable
I
LOW
Synchronous chip enable. CE is used with CS 0 and CS1 to enable the IDT71V67602/7802.
CE also gates ADSP.
CLK
Clock
I
N/A
This is the clock input. All timing references for the device are made with respect to this
input.
CS0
Chip Select 0
I
HIGH
Synchrono us active HIGH chip select. CS0 is used with CE and CS1 to enable the chip.
CS1
Chip Select 1
I
LOW
Synchronous active LOW chip select. CS1 is used with CE and CS0 to enable the chip.
GW
Global Write
Enable
I
LOW
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW
on the rising edge of CLK. GW supersedes individual byte write enables.
I/O0-I/O31
I/OP1-I/OP4
Data Input/Output
I/O
N/A
Synchronous data input/output (I/O) pins. Both the data input path and data output path are
registered and triggered by the rising edge of CLK.
LBO
Linear Burst Order
I
LOW
Asynchronous burst order selection input. When LBO is HIGH, the interleaved burst
sequence is selected. When LBO is LOW the Linear burst sequence is selected. LBO is a
static input and must not change state while the device is operating.
OE
Output Enable
I
LOW
Asynchronous output enable. When OE is LOW the data output drivers are enabled on the
I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a highimpedance state.
VDD
Power Supply
N/A
N/A
3.3V core power supply.
VDDQ
Power Supply
N/A
N/A
2.5V I/O Supply.
VSS
Ground
N/A
N/A
Ground.
NC
No Connect
N/A
N/A
NC pins are not electrically connected to the device.
ZZ
Sleep Mode
I
HIGH
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
IDT71V67602/7802 to its lowest power consumption level. Data retention is guaranteed in
Sleep Mode.
5311 tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
2
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Functional Block Diagram
LBO
ADV
CLK
2
Binary
Counter
ADSC
Burst
Logic
Q0
CLR
ADSP
Q1
CLK EN
ADDRESS
REGISTER
A0–A17/18
GW
BWE
INTERNAL
ADDRESS
Burst
Sequence
CEN
2
A0,A1
18/19
A0*
A1*
A2–A18
256K x 36/
512K x 18BIT
MEMORY
ARRAY
36/18
18/19
Byte 1
Write Register
36/18
Byte 1
Write Driver
BW1
9
Byte 2
Write Register
Byte 2
Write Driver
BW2
9
Byte 3
Write Register
Byte 3
Write Driver
BW3
9
Byte 4
Write Register
Byte 4
Write Driver
BW4
9
OUTPUT
REGISTER
CE
CS0
CS1
D
Q
Enable
Register
DATA INPUT
REGISTER
CLK EN
ZZ
Powerdown
D
Q
Enable
Delay
Register
OE
OE
I/O0–I/O31
I/OP1–I/OP4
OUTPUT
BUFFER
36/18
5311 drw 01
6.42
3
,
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Absolute Maximum Ratings(1)
Sym bol
Rating
Com m ercial
Unit
V TE RM (2)
Te rm inal Vo ltag e with
Re sp e c t to G ND
-0.5 to + 4.6
V
V TE RM (3,6)
Te rm inal Vo ltag e with
Re sp e c t to G ND
-0.5 to V DD
V
V TE RM (4,6)
Te rm inal Vo ltag e with
Re sp e c t to G ND
-0.5 to V DD + 0.5
V
V TE RM (5,6)
Te rm inal Vo ltag e with
Re sp e c t to G ND
-0.5 to V DDQ + 0.5
V
TA (7)
Co m m e rcial
-0 to + 70
o
C
Ind ustrial
-40 to + 85
o
C
TB IA S
Te m p e rature
Und e r B ias
-55 to + 125
o
C
TS TG
S to rag e
Te m p e rature
-55 to + 125
PT
P o we r Diss ip atio n
2.0
W
IO UT
DC O utp ut Curre nt
50
mA
o
Commercial and Industrial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage
Grade
Temperature(1)
VSS
VDD
VDDQ
Commercial
0°C to +70°C
0V
3.3V±5%
2.5V±5%
Industrial
-40°C to +85°C
0V
3.3V±5%
2.5V±5%
5311 tbl 04
NOTE:
1. TA is the "instant on" case temperature.
Recommended DC Operating
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDQ
I/O Supply Voltage
2.375
2.5
2.625
V
VSS
Ground
0
0
0
V
VIH
Input High Voltage - Inputs
1.7
____
VDD+0.3
V
1.7
____
VDDQ +0.3
V
____
0.7
V
C
VIH
VIL
Input High Voltage - I/O
Input Low Voltage
-0.3
(1)
5311 tbl 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.
7. TA is the "instant on" case temperature.
100-pin TQFP Capacitance
Parameter(1)
CIN
Input Capacitance
CI/O
I/O Capacitance
(TA = +25°C, f = 1.0MHz)
Max.
Unit
Symbol
VIN = 3dV
5
pF
CIN
Input Capacitance
VOUT = 3dV
7
pF
CI/O
I/O Capacitance
119 BGA Capacitance
(TA = +25°C, f = 1.0MHz)
Parameter(1)
CIN
Input Capacitance
CI/O
I/O Capacitance
Parameter(1)
Conditions
5311 tbl 07
Symbol
5311 tbl 06
165 fBGA Capacitance
(TA = +25°C, f = 1.0MHz)
Symbol
NOTE:
1. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
Conditions
Max.
Unit
V IN = 3dV
7
pF
VOUT = 3dV
7
pF
5311 tbl 07a
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.42
4
Conditions
Max.
Unit
V IN = 3dV
TDB
pF
VOUT = 3dV
TDB
pF
5311 tbl 07b
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
A6
A7
CE
CS0
BW4
BW3
BW2
BW1
CS1
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
Pin Configuration – 256K x 36, 100-Pin TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP3
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
VDDQ
I/O22
I/O23
VDD / NC(1)
VDD
NC
VSS
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDDQ
I/O30
I/O31
I/OP4
1
80
2
79
3
78
77
4
5
6
76
75
7
74
8
73
9
72
71
10
11
70
12
69
13
68
14
67
15
66
16
65
64
17
18
19
63
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
28
54
53
29
52
30
51
I/OP2
I/O15
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDDQ
I/O9
I/O8
VSS
NC
VDD
ZZ(2)
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
I/OP1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
VSS
VDD
NC
A17
A10
A11
A12
A13
A14
A15
A16
LBO
A5
A4
A3
A2
A1
A0
5311 drw 02
Top View
NOTES:
1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
5
,
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
A6
A7
CE
CS0
NC
NC
BW2
BW1
CS1
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
Pin Configuration – 512K x 18, 100-Pin TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
NC
1
80
2
79
3
VDDQ
VSS
NC
NC
I/O8
I/O9
VSS
VDDQ
I/O10
I/O11
VDD / NC(1)
VDD
NC
VSS
I/O12
I/O13
VDDQ
VSS
I/O14
I/O15
I/OP2
NC
VSS
VDDQ
NC
NC
NC
4
78
77
5
6
76
75
7
74
8
73
9
72
71
10
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
19
63
62
20
61
21
60
22
59
23
24
58
57
25
56
26
55
27
28
54
53
29
52
30
51
A10
NC
NC
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
NC
VDD
ZZ(2)
I/O3
I/O2
VDDQ
VSS
I/O1
I/O0
NC
NC
VSS
VDDQ
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
VSS
VDD
NC
A18
A11
A12
A13
A14
A15
A16
A17
LBO
A5
A4
A3
A2
A1
A0
NC
5311 drw 03
Top View
NOTES:
1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
6
,
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration – 256K x 36, 119 BGA
1
2
3
4
5
6
7
A
VDDQ
A6
A4
ADSP
A8
A16
VDDQ
B
NC
A3
ADSC
A9
A17
NC
CS0(4)
C
NC
A7
A2
VDD
A12
A15
NC
D
I/O16
I/OP3
VSS
NC
VSS
I/OP2
I/O15
E
I/O17
I/O18
VSS
CE
VSS
I/O13
I/O14
F
VDDQ
I/O19
VSS
OE
VSS
I/O12
VDDQ
G
I/O20
I/O21
BW3
ADV
BW 2
I/O11
I/O10
H
I/O22
I/O23
VSS
GW
VSS
I/O9
I/O8
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
I/O24
I/O26
VSS
CLK
VSS
I/O6
I/O7
L
I/O25
I/O27
BW4
NC
BW1
I/O4
I/O5
M
VDDQ
I/O28
VSS
BWE
VSS
I/O3
VDDQ
N
I/O29
I/O30
VSS
A1
VSS
I/O2
I/O1
P
I/O31
I/OP4
VSS
A0
VSS
I/O0
I/OP1
A13
NC
NC
ZZ (2)
VDD / NC(1)
R
NC
A5
LBO
VDD
T
NC
NC
A10
A11
A14
U
VDDQ
DNU(3)
DNU(3)
DNU(3)
DNU(3)
DNU(3)
,
VDDQ
5311 drw 04
Top View
Pin Configuration – 512K x 18, 119 BGA
1
2
3
4
5
6
7
A
VDDQ
A6
A4
ADSP
A8
A16
VDDQ
B
NC
CS0(4)
A3
ADSC
A9
A18
NC
C
NC
A7
A2
VDD
A13
A17
NC
D
I/O8
NC
VSS
NC
VSS
I/O7
NC
E
NC
I/O9
VSS
CE
VSS
NC
I/O6
F
VDDQ
NC
VSS
OE
VSS
I/O5
VDDQ
G
NC
I/O10
BW2
ADV
VSS
NC
I/O4
H
I/O11
NC
VSS
GW
VSS
I/O3
NC
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
NC
I/O12
VSS
CLK
VSS
NC
I/O2
L
I/O13
NC
VSS
NC
BW1
I/O1
NC
M
VDDQ
I/O14
VSS
BWE
VSS
NC
VDDQ
N
I/O15
NC
VSS
A1
VSS
I/O0
NC
P
NC
I/OP2
VSS
A0
VSS
NC
I/OP1
R
NC
A5
LBO
VDD
A12
NC
T
NC
A10
A15
NC
A14
A11
ZZ(2)
DNU(3)
DNU(3)
DNU(3)
DNU(3)
U
VDDQ
DNU(3)
VDD / NC(1)
,
VDDQ
5311 drw 05
Top View
NOTES:
1. R5 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. T7 can be left unconnected and the device will always remain in active mode.
3. Pin U6 will be internally pulled to VDD if not actively driven. To disable the TAP controller without interfering with normal operation, TRST should be tied low
and TCK, TDI, and TMS should be pulled through a resistor to 3.3V. TDO should be left unconnected.
4. On future 18M device CS0 will be removed, B2 will be be used for address expansion.
6.42
7
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration – 256K x 36, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
A
NC(3)
A7
CE
BW3
BW2
CS1
BWE
ADSC
ADV
A8
NC
B
NC
A6
CS0
BW4
BW1
CLK
GW
OE
ADSP
A9
NC(3)
C
I/OP3
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
I/OP2
D
I/O17
I/O16
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O15
I/O14
E
I/O19
I/O18
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O13
I/O12
F
I/O21
I/O20
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O11
I/O10
G
I/O23
I/O22
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O9
I/O8
H
VDD(1)
NC
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ(2)
J
I/O25
I/O24
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O7
I/O6
K
I/O27
I/O26
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O5
I/O4
L
I/O29
I/O28
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O3
I/O2
M
I/O31
I/O30
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O1
I/O0
NC
N
I/OP4
P
NC
R
LBO
NC
(3)
NC
(3)
NC
VDDQ
A5
A4
VSS
A2
A3
(3)
NC
NC
(4)
DNU
A1
(4)
DNU
A0
VSS
VDDQ
NC
I/OP1
(4)
A10
A13
A14
A17
(4)
A11
A12
A15
A16
DNU
DNU
5311 tbl 17a
Pin Configuration – 512K x 18, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
A
NC
A7
CE
BW2
NC
CS1
BWE
ADSC
ADV
A8
A10
B
NC
A6
CS 0
NC
BW1
CLK
GW
OE
ADSP
A9
NC(3)
C
NC
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
I/OP1
D
NC
I/O8
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
I/O7
E
NC
I/O9
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
I/O6
F
NC
I/O10
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
I/O5
G
NC
(3)
I/O11
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
I/O4
H
VDD
(1)
NC
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ(2)
J
I/O12
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O3
NC
K
I/O13
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O2
NC
L
I/O14
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O1
NC
M
I/O15
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O0
NC
N
I/OP2
NC
VDDQ
VSS
NC
NC(3)
NC
VSS
VDDQ
NC
NC
P
NC
NC(3)
A5
A2
DNU(4)
A1
DNU(4)
A11
A14
A15
A18
R
LBO
NC(3)
A4
A3
DNU(4)
A0
DNU(4)
A12
A13
A16
A17
5311 tbl 17b
NOTES:
1. H1 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. H11 can be left unconnected and the device will always remain in active mode.
3. Pin N6, B11, A1, R2 and P2 are reserved for 18M, 36M, 72M, and 144M and 288M respectively.
6.42
8
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VDD = Max., VIN = 0V to V DD
___
5
µA
|ILI|
Input Leakage Current
|ILZZ|
ZZ and LBO Input Leakage Current
VDD = Max., VIN = 0V to V DD
___
30
µA
|ILO|
Output Leakage Current
VOUT = 0V to VDDQ , Device Deselected
___
5
µA
0.4
V
___
V
(1)
VOL
Output Low Voltage
IOL = +6mA, VDD = Min.
___
VOH
Output High Voltage
IOH = -6mA, VDD = Min.
2.0
5311 tbl 08
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to V SS if not actively driven.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1)
166MHz
Symbol
Parameter
150MHz
133MHz
Unit
Test Conditions
Com'l Only
Com'l
Ind
Com'l
Ind
Operating Power Supply Current
Device Selected, Outputs Open, V DD = Max.,
VDDQ = Max., VIN > VIH or < VIL, f = fMAX(2)
340
305
325
260
280
mA
ISB1
CMOS Standby Power Supply
Current
Device Deselected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VHD or < VLD, f = 0(2,3)
50
50
70
50
70
mA
ISB2
Clock Running Power
Supply Current
Device Deselected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VHD or < VLD, f = fMAX(2,3)
160
155
175
150
170
mA
50
50
70
50
70
mA
IDD
ZZ > VHD, VDD = Max.
IZZ
Full Sleep Mode Supply Current
5311 tbl 09
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
AC Test Conditions
AC Test Load
(VDDQ = 2.5V)
Input Pulse Levels
Input Rise/Fall Times
50Ω
0 to 2.5V
I/O
Z0 = 50Ω
2ns
5311 drw 06
Input Timing Reference Levels
VDDQ /2
Output Timing Reference Levels
VDDQ /2
6
See Figure 1
5
AC Test Load
VDDQ/2
,
Figure 1. AC Test Load
5311 tbl 10
4
∆tCD 3
(Typical, ns)
2
1
20 30 50
80 100
Capacitance (pF)
200
5311 drw 07
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
9
,
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Synchronous Truth Table(1,3)
Address
Used
CE
CS 0
CS1
ADSP
ADSC
ADV
GW
BWE
BWx
OE
(2)
CLK
I/O
Deselected Cycle, Power Down
None
H
X
X
X
L
X
X
X
X
X
-
HI-Z
Deselected Cycle, Power Down
None
L
X
H
L
X
X
X
X
X
X
-
HI-Z
Deselected Cycle, Power Down
None
L
L
X
L
X
X
X
X
X
X
-
HI-Z
Deselected Cycle, Power Down
None
L
X
H
X
L
X
X
X
X
X
-
HI-Z
Deselected Cycle, Power Down
None
L
L
X
X
L
X
X
X
X
X
-
HI-Z
Read Cycle, Begin Burst
External
L
H
L
L
X
X
X
X
X
L
-
DOUT
Read Cycle, Begin Burst
External
L
H
L
L
X
X
X
X
X
H
-
HI-Z
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
H
X
L
-
DOUT
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
H
L
-
DOUT
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
H
H
-
HI-Z
Write Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
L
X
-
DIN
Write Cycle, Begin Burst
External
L
H
L
H
L
X
L
X
X
X
-
DIN
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
H
X
L
-
DOUT
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
H
X
H
-
HI-Z
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
X
H
L
-
DOUT
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
X
H
H
-
HI-Z
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
H
X
L
-
DOUT
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
H
X
H
-
HI-Z
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
X
H
L
-
DOUT
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
X
H
H
-
HI-Z
Write Cycle, Continue Burst
Next
X
X
X
H
H
L
H
L
L
X
-
DIN
Write Cycle, Continue Burst
Next
X
X
X
H
H
L
L
X
X
X
-
DIN
Write Cycle, Continue Burst
Next
H
X
X
X
H
L
H
L
L
X
-
DIN
Write Cycle, Continue Burst
Next
H
X
X
X
H
L
L
X
X
X
-
DIN
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
H
X
L
-
DOUT
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
H
X
H
-
HI-Z
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
X
H
L
-
DOUT
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
X
H
H
-
HI-Z
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
H
X
L
-
DOUT
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
H
X
H
-
HI-Z
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
X
H
L
-
DOUT
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
X
H
H
-
HI-Z
Write Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
L
L
X
-
DIN
Write Cycle, Suspend Burst
Current
X
X
X
H
H
H
L
X
X
X
-
DIN
Write Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
L
L
X
-
DIN
Write Cycle, Suspend Burst
Current
H
X
X
X
H
H
L
X
X
X
-
Operation
DIN
5311 tbl 11
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. OE is an asynchronous input.
3. ZZ = low for this table.
6.42
10
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Synchronous Write Function Truth Table(1, 2)
Operation
GW
BWE
BW1
BW2
BW3
BW4
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write all Bytes
L
X
X
X
X
X
Write all Bytes
H
L
L
L
L
L
(3)
H
L
L
H
H
H
(3)
H
L
H
L
H
H
(3)
H
L
H
H
L
H
(3)
H
L
H
H
H
L
Write Byte 1
Write Byte 2
Write Byte 3
Write Byte 4
5311 tbl 12
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. BW3 and BW4 are not applicable for the IDT71V67802.
3. Multiple bytes may be selected during the same cycle.
Asynchronous Truth Table(1)
Operation(2)
OE
ZZ
I/O Status
Power
Read
L
L
Data Out
Active
Read
H
L
High-Z
Active
Write
X
L
High-Z – Data In
Active
Deselected
X
L
High-Z
Standby
Sleep Mode
X
H
High-Z
Sleep
5311 tbl 13
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
0
0
1
1
1
0
Third Address
1
0
1
1
0
0
0
1
1
1
1
0
0
1
0
0
Fourth Address
(1)
5311 tbl 14
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Linear Burst Sequence Table (LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
1
0
1
1
0
0
Third Address
1
0
1
1
0
0
0
1
Fourth Address (1)
1
1
0
0
0
1
1
0
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
6.42
11
5311 tbl 15
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)
166MHz
Symbol
Parameter
150MHz
133MHz
Min.
Max.
Min.
Max.
Min.
Max.
Unit
6
____
6.7
____
7.5
____
ns
tCYC
Clock Cycle Time
tCH(1)
Clock High Pulse Width
2.4
____
2.6
____
3
____
ns
tCL(1)
Clock Low Pulse Width
2.4
____
2.6
____
3
____
ns
____
3.5
____
3.8
____
4.2
ns
1.5
____
1.5
____
ns
Output Parameters
tCD
Clock High to Valid Data
tCDC
Clock High to Data Change
1.5
____
tCLZ(2)
Clock High to Output Active
0
____
0
____
0
____
ns
tCHZ(2)
Clock High to Data High-Z
1.5
3.5
1.5
3.8
1.5
4.2
ns
tOE
Output Enable Access Time
____
3.5
____
3.8
____
4.2
ns
tOLZ(2)
Output Enab le Low to Output Active
0
____
0
____
0
____
ns
tOHZ(2)
Output Enab le High to Output High-Z
____
3.5
____
3.8
____
4.2
ns
1.5
____
1.5
____
1.5
____
ns
1.5
____
1.5
____
1.5
____
ns
1.5
____
1.5
____
ns
Set Up Times
tSA
tSS
Address Setup Time
Address Status Setup Time
tSD
Data In Setup Time
1.5
____
tSW
Write Setup Time
1.5
____
1.5
____
1.5
____
ns
tSAV
Address Advance Setup Time
1.5
____
1.5
____
1.5
____
ns
1.5
____
1.5
____
1.5
____
ns
tSC
Chip Enable/Select Setup Time
Hold Times
tHA
Address Hold Time
0.5
____
0.5
____
0.5
____
ns
tHS
Address Status Hold Time
0.5
____
0.5
____
0.5
____
ns
tHD
Data In Hold Time
0.5
____
0.5
____
0.5
____
ns
0.5
____
0.5
____
0.5
____
ns
0.5
____
0.5
____
ns
tHW
Write Hold Time
tHAV
Address Advance Hold Time
0.5
____
tHC
Chip Enable/Select Hold Time
0.5
____
0.5
____
0.5
____
ns
Sleep Mode and Configuration Parameters
tZZPW
ZZ Pulse Width
100
____
100
____
100
____
ns
tZZR(3)
ZZ Recovery Time
100
____
100
____
100
____
ns
tCFG (4)
Configuration Set-up Time
24
____
27
____
30
____
ns
5311 tbl 16
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
6.42
12
6.42
13
Output
Disabled
tSC
tSA
tSS
tHS
Ax
Pipelined
Read
tOLZ
tOE
tHC
tHA
O1(Ax)
Ay
(1)
tCH
tCLZ
tOHZ
tCD
tSW
tCL
O1(Ay)
tCDC
tSAV
tHAV
O2(Ay)
tHW
Burst Pipelined Read
O3(Ay)
ADV HIGH suspends
burst
O4(Ay)
(Burst wraps around
to its initial state)
O1(Ay)
tCHZ
O2(Ay)
5311 drw 08
,
NOTES:
1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in
the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. ZZ input is LOW and LBO is Don't Care for this cycle.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
DATAOUT
OE
ADV
(Note 3)
CE, CS1
GW,BWE,BWx
ADDRESS
ADSC
ADSP
CLK
tCYC
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Pipelined Read Cycle(1,2)
6.42
14
tSA
tHA
tSS
tHS
tCLZ
tCD
Single Read
Ax
(2)
tOE
O1(Ax)
tOHZ
tSW
Ay
tCH
Pipelined
Write
I1(Ay)
tSD tHD
tCL
tHW
Az
tOLZ
tCD
O2(Az)
Pipelined Burst Read
O1(Az)
tCDC
5311 drw 09
O3(Az)
,
NOTES:
1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH.
2. ZZ input is LOW and LBO is Don't Care for this cycle.
3. O1 (Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay; O1 (Az) represents the first output from the external address
Az; O2 (Az) represents the next output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state
of the LBO input.
DATAOUT
DATAIN
OE
ADV
GW
ADDRESS
ADSP
CLK
tCYC
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Pipelined Read and Write Cycles(1,2,3)
6.42
15
O4(Aw)
Ax
Burst Read
tHC
O3(Aw)
tSC
tSA
tHA
tSS
tHS
Ay
tCL
Single
Write
tOHZ
I1(Ax)
I1(Ay)
I2(Ay)
Burst Write
I2(Ay)
(ADV HIGH suspends burst)
tSAV
GW is ignored when ADSP initiates a cycle and is sampled on the next clock rising edge
tCH
I3(Ay)
tHAV
I4(Ay)
tSD
I1(Az)
tHW
tSW
Az
I3(Az)
5311 drw 10
Burst Write
I2(Az)
tHD
NOTES:
1. ZZ input is LOW, BWE is HIGH and LBO is Don't Care for this cycle.
2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input
from the external address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the
sequence defined by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
DATAOUT
DATAIN
OE
ADV
(Note 3)
CE, CS1
GW
ADDRESS
ADSC
ADSP
CLK
tCYC
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 — GW Controlled(1,2,3)
,
6.42
16
tHC
Burst
Read
O3(Aw)
tSC
tSA
tHA
tSS
tHS
O4(Aw)
Ax
Ay
tCL
Single
Write
tOHZ
I1(Ax)
I1(Ay)
Burst Write
I2(Ay)
(ADV suspends burst)
BWx is ignored when ADSP initiates a cycle and is sampled on next clock rising edge
BWE is ignored when ADSP initiates a cycle and is sampled on next clock rising edge
tCH
I2(Ay)
I3(Ay)
I4(Ay)
tSD
Extended
Burst Write
I1(Az)
tSAV
tHW
tSW
tHW
tSW
Az
I2(Az)
tHD
5311 drw 11
I3(Az)
,
NOTES:
1. ZZ input is LOW, GW is HIGH and LBO is Don't Care for this cycle.
2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input
from the external address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the
sequence defined by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
DATAOUT
DATAIN
OE
ADV
(Note 3)
CE, CS1
BWx
BWE
ADDRESS
ADSC
ADSP
CLK
tCYC
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 — Byte Controlled(1,2,3)
6.42
17
tSS
tSC
tSA
tHS
Ax
Single Read
tOLZ
tOE
tHC
tHA
O1(Ax)
tCH
tCL
tZZPW
Snooze Mode
tZZR
NOTES:
1. Device must power up in deselected Mode
2. LBO is Don't Care for this cycle.
3. It is not necessary to retain the state of the input registers throughout the Power-down cycle.
4. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
ZZ
DATAOUT
OE
ADV
(Note 4)
CE, CS1
GW
ADDRESS
ADSC
ADSP
CLK
tCYC
Az
5311 drw 12
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3)
,
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
ADSC
ADDRESS
Av
Aw
Ax
Ay
Az
GW, BWE, BWx
CE, CS1
CS0
OE
(Av)
DATAOUT
(Aw)
(Ax)
(Ay)
NOTES:
1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles, ADSP and ADSC function identically and are therefore interchangable.
,
5311 drw 14
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
ADSC
ADDRESS
Av
Aw
Ax
Ay
Az
(Ax)
(Ay)
(Az)
GW
CE, CS1
CS0
DATAIN
(Av)
(Aw)
NOTES:
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles, ADSP and ADSC have different limitations.
6.42
18
,
5311 drw 15
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
100-Pin Thin Plastic Quad Flatpack (TQFP) Package Diagram Outline
6.42
19
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
119 Ball Grid Array (BGA) Package Diagram Outline
6.42
20
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline
6.42
21
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Ordering Information
IDT
XXX
S
X
Device
Type
Power
Speed
XX
XX
Package Process/Temp
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
BG
BQ
100-pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 fine pitch Ball Grid Array
166*
150
133
Frequency in Megahertz
71V67602
71V67802
256K x 36 Pipelined Burst Synchronous SRAM
512K x 18 Pipelined Burst Synchronous SRAM
* Industrial temperature not available on 166MHz devices
5311 drw 13
6.42
22
,
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Datasheet Document History
12/31/99
04/26/00
05/24/00
07/12/00
08/27/02
10/28/02
11/19/02
Created datasheet from 71V676 and 71V678 datasheets.
I/O voltage and speed grade offerings have been split into separate part numbers.
See the following datasheets for:
3.3V I/O, 133–166MHz
71V67603
2.5V I/O, 133–166MHz
71V67602
3.3V I/O, 183–200MHz
71V67613
2.5V I/O, 183–200MHz
71V67612
Pg. 4
Add capacitance for BGA package; Insert clarification note to Absolute Max Ratings and Recommended
Operating Temperature tables.
Pg. 7
Replace Pin U6 with TRST pin in BGA pin configuration; Add pin description note in pinout
Pg. 18
Inserted 100 pin TQFP Package Diagram Outline
Pg. 1,4,8,21 Add new package offering, 13 x 15 fBGA
22
Pg. 5,6,7,8 Correct note 2 on BGA and TQFP pin configuration
Pg. 20
Correction in the 119 BGA Package Diagram Outline
Pg. 5,6,8
Remove note from TQFP and BQ165 pinouts
Pg. 7
Remove/Add reference note from BG119 pinout
Pg. 20
Update BG119 Package Diagram Outline
Pg. 4,9,12 Added Industrial information to the datasheet.
22
Pg. 1-23
Changed datasheet from Advanced Information to Final Release.
Pg. 1,9,12,22Added 166MHz to datasheet.
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
23
for Tech Support:
[email protected]
800-544-7726, x4033