IDT72264
IDT72274
VARIABLE WIDTH SUPERSYNC FIFO
8,192 x 18 or 16,384 x 9
16,384 x 18 or 32,768 x 9
Integrated Device Technology, Inc.
• Industrial temperature range (-40OC to +85OC) is available, tested to military electrical specifications
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Select 8192 x 18 or 16384x 9 organization (IDT72264)
Select 16384 x 18 or 32678 x 9 organization (IDT72274)
Flexible control of read and write clock frequencies
Reduced dynamic power dissipation
Auto power down minimizes power consumption
15 ns read/write cycle time (10 ns access time)
Retransmit Capability
Master Reset clears entire FIFO, Partial Reset clears
data, but retains programmable settings
Empty, full and half-full flags signal FIFO status
Programmable almost empty and almost full flags, each
flag can default to one of two preselected offsets
Program partial flags by either serial or parallel means
Select IDT Standard timing (using EF and FF flags) or
First Word Fall Through timing (using OR and IR flags)
Easily expandable in depth and width
Independent read and write clocks (permits simultaneous
reading and writing with one clock signal)
Available in the 64-pin Thin Quad Flat Pack (TQFP), 64pin Slim Thin Quad Flat Pack (STQFP) and the 68-pin
Pin Grid Array (PGA)
Output enable puts data outputs into high impedance
High-performance submicron CMOS technology
DESCRIPTION:
The IDT72264/72274 are monolithic, CMOS, high capacity, high speed, low power first-in, first-out (FIFO) memories
with clocked read and write controls. These FIFOs have three
main features that distinguish them among SuperSync FIFOs:
First, the data path width can be changed from 9-bits to 18bits; as a result, halving the depth. A pin called Memory Array
Select (MAC) chooses between the two options. This feature
helps reduce the need for redesigns or multiple versions of PC
cards, since a single layout can be used for both data bus
widths.
Second, IDT72264/72274 offer the greatest flexibility for
setting and varying the read and write clock (WCLK and
RCLK) frequencies. For example, given that the two clock
frequencies are unequal, the slower clock may exceed the
faster by, at most, twice its frequency. This feature is especially useful for communications and network applications
where clock frequencies are switched to permit different data
rates.
FUNCTIONAL BLOCK DIAGRAM
WEN
•
D0 -D n
WCLK
•
INPUT REGISTER
••
WRITE CONTROL
LOGIC
LD SEN
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
HF
FLAG
LOGIC
FWFT/SI
RAM ARRAY
8192 x 18 or 16384 x 9
16384 x 18 or 32768 x 9
WRITE POINTER
READ POINTER
••
MAC
MEMORY ARRAY
CONFIGURATION
OUTPUT REGISTER
MRS
PRS
RESET
LOGIC
FS
TIMING
•
READ
CONTROL
LOGIC
•
RCLK
•
OE
RT
REN
Q0 -Qn
3218 drw 01
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGES
1997 Integrated Device Technology, Inc
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
MAY 1997
DSC-3218/2
1
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
Finally,of all SuperSync FIFOs, the IDT72264/72274 offer
the lowest dynamic power dissipation.
These devices meet a wide variety of data buffering needs.
In addition to those already mentioned, applications include
such as optical disk controllers, Local Area Networks (LANs),
and inter-processor communication.
Both FIFOs have an 18-bit input port (Dn) and an 18-bit
output port (Qn). The input port is controlled by a free-running
clock (WCLK) and a data input enable pin (WEN). Data is
written into the synchronous FIFO on every clock when WEN
is asserted. The output port is controlled by another clock pin
(RCLK) and enable pin (REN). The read clock can be tied to
the write clock for single clock operation or the two clocks can
run asynchronously for dual clock operation. An output
enable pin (OE) is provided on the read port for three-state
control of the outputs.
The IDT72264/72274 have two modes of operation: In the
IDT Standard Mode, the first word written to the FIFO is
deposited into the memory array. A read operation is required
to access that word. In the First Word Fall Through Mode
(FWFT), the first word written to an empty FIFO appears
automatically on the outputs, no read operation required. The
state of the FWFT/SI pin during Master Reset determines the
mode in use.
The IDT72264/72274 have five flag functions, EF/OR
(Empty Flag or Output Ready), FF/IR (Full Flag or Input
Ready), and HF (Half-full Flag). The EF and FF functions are
selected in the IDT Standard Mode.
The IR and OR functions are selected in the First Word Fall
Through Mode. IR indicates that the FIFO has free space to
receive data. OR indicates that data contained in the FIFO is
available for reading.
HF is a flag whose threshold is fixed at the half-way point in
memory. This flag can always be used irrespective of mode.
PAE and PAF can be programmed independantly to any
point in memory. They, also, can be used irrespective of
mode. Programmable offsets determine the flag threshold
and can be loaded by two methods: parallel or serial. Two
default offset settings are also provided, such that PAE can be
set at 127 or 1023 locations from the empty boundary and the
PAF threshold can be set at 127 or 1023 locations from the full
boundary. All these choices are made with LD during Master
Reset.
RCLK
REN
RT
OE
VCC
PAE
EF/OR
FF/IR
PAF
HF
GND
FWFT/SI
PRS
MRS
LD
WCLK
PIN CONFIGURATIONS
PIN 1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
WEN
SEN
1
2
48
47
FS
VCC
MAC
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
3
4
5
46
45
44
6
7
43
42
8
9
41
40
10
11
12
39
38
37
13
14
36
35
15
16
34
33
Q17
Q16
GND
Q15
Q14
VCC
Q13
Q12
Q11
GND
Q10
Q9
Q8
Q7
Q6
GND
Q4
Q5
Q1
GND
Q2
Q3
VCC
GND
Q0
D1
D0
D4
D3
D2
D6
D5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
3218 drw 02
TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)
TOP VIEW
NOTES:
1. When the data path is selected to be 9 bits wide (MAC is HIGH), D9 - D17 may either be tied to ground or left open, Q9 - Q17 must be left open.
2
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
In the serial method, SEN together with LD are used to load
the offset registers via the Serial Input (SI). In the parallel
method, WEN together with LD can be used to load the offset
registers via Dn. REN together with LD can be used to read the
offsets in parallel from Qn regardless of whether serial or
parallel offset loading is selected.
During Master Reset (MRS), the read and write pointers are
set to the first location of the FIFO. The FWFT line selects IDT
Standard Mode or FWFT Mode. The LD pin selects one of two
partial flag default settings (127 or 1023) and, also, serial or
parallel programming. The flags are updated accordingly.
The Partial Reset (PRS) also sets the read and write
pointers to the first location of the memory. However, the
mode setting, programming method, and partial flag offsets
are not altered. The flags are updated accordingly. PRS is
useful for resetting a device in mid-operation, when reprogramming offset registers may not be convenient.
The Retransmit function allows the read pointer to be reset
to the first location in the RAM array. It is synchronized to
RCLK when RT is LOW. This feature is convenient for
sending the same data more than once.
If, at any time, the FIFO is not actively performing a function,
the chip will automatically power down. This occurs if neither
a read nor a write occurs within 10 cycles of the faster clock,
RCLK or WCLK. During the Power Down state, supply current
consumption (ICC2) is at a minimum. Initiating any operation
(by activating control inputs) will immediately take the device
out of the Power Down state.
The IDT72264/72274 are depth expandable. The addition
of external components is unnecessary. The IR and OR
functions, together with REN and WEN, are used to extend the
total FIFO memory capacity.
The FS line ensures optimal data flow through the FIFO. It
is tied to GND if the RCLK frequency is higher than the WCLK
frequency or to Vcc if the RCLK frequency is lower than the
WCLK frequency
The IDT72264/72274 is fabricated using IDT’s high speed
submicron CMOS technology.
PIN CONFIGURATIONS (CONT.)
11
DNC Q5
10
Q6 GND Q4
09
Q8
Q7
08
Q10
Q9
07
Q11 GND
D13 D12
06
Q13 Q12
D15 D14
05
Q14 VCC
D17 D16
Q2
Q1 GND D1
Q3 GND Q0
D0
D2
D3
D5
D4
D6
D7
D9
D8
D11 D10
Pin 1 Designator
04 GND Q15
03
VCC
VCC MAC
SEN
Q17 Q16
02 DNC
01
A
FS
/
OE REN GND PAE HF FF
IR DNC LD WCLK WEN
/
FWFT/
RT RCLK EF
OR VCC PAF GND SI MRS PRS
B
C
D
E
F
G
H
J
K
L
3218 drw 03
PGA (G68-1, order code: G)
TOP VIEW
NOTES:
1. When the data path is selected to be 9 bits wide (MAC is HIGH), D9 - D17 may be tied to ground or left open, Q9 - Q17 must be left open.
2. DNC = Do not connect
3
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Symbol
D0–D17
MRS
Name
Data Inputs
Master Reset
I/O
I
I
PRS
Partial Reset
I
RT
FWFT/SI
WCLK
WEN
RCLK
REN
OE
SEN
LD
Retransmit
First Word Fall
Through/Serial In
Write Clock
I
I
Write Enable
Read Clock
I
I
Read Enable
I
Output Enable
Serial Enable
Load
I
I
I
I
MAC
Memory Array
Configuration
I
FS
Frequency Select
I
Full Flag/
Input Ready
O
Empty Flag/
Output Ready
O
Programmable
Almost Full Flag
O
O
Q0–Q17
VCC
Programmable
Almost Empty
Flag
Half-full Flag
Data Outputs
Power
GND
Ground
FF/IR
EF/OR
PAF
PAE
HF
O
O
Description
Data inputs for a 18-bit bus.
MRS initializes the read and write pointers to zero and sets the output register to
all zeroes. During Master Reset, the FIFO is configured for either FWFT or IDT
Standard Mode, one of two programmable flag default settings, and serial or
parallel programming of the offset settings.
PRS initializes the read and write pointers to zero and sets the output register to
all zeroes. During Partial Reset,the existing mode (IDT or FWFT), programming
method (serial or parallel), and programmable flag settings are all retained.
Allows data to be resent starting with the first location of FIFO memory.
During Master Reset, selects First Word Fall Through or IDT Standard mode.
After Master Reset, this pin functions as a serial input for loading offset registers
When enabled by WEN, the rising edge of WCLK writes data into the FIFO and
offsets into the programmable registers.
WEN enables WCLK for writing data into the FIFO memory and offset registers.
When enabled by REN, the rising edge of RCLK reads data from the FIFO
memory and offsets from the programmable registers.
REN enables RCLK for reading data from the FIFO memory and offset registers.
OE controls the output impedance of Qn.
SEN enables serial loading of programmable flag offsets.
During Master Reset, LD selects one of two partial flag default offsets (127 and
1023) and determines programming method, serial or parallel. After Master
Reset, this pin enables writing to and reading from the offset registers.
MAC selects 8192 x 18 or 16384x 9 memory array organization for the IDT72264.
It selects 16384 x 18 or 32678 x 9 memory array organization for the IDT72274.
FS selects selects WCLK or RCLK, whichever is running at a higher frequency,
to synchronize the FIFO's internal state machine.
In the IDT Standard Mode, the FF function is selected. FF indicates whether or
not the FIFO memory is full. In the FWFT mode, the IR function is selected. IR
indicates whether or not there is space available for writing to the FIFO memory.
In the IDT Standard Mode, the EF function is selected. EF indicates whether or
not the FIFO memory is empty. In FWFT mode, the OR function is selected.
OR indicates whether or not there is valid data available at the outputs.
PAF goes HIGH if the number of free locations in the FIFO memory is more than
offset m which is stored in the Full Offset register. PAFgoes LOW if the
number of free locations in the FIFO memory is less than m.
PAE goes LOW if the number of words in the FIFO memory is less than offset n
which is stored in the Empty Offset register. PAE goes HIGH if the number of
words in the FIFO memory is greater than offset n.
HF indicates whether the FIFO memory is more or less than half-full.
Data outputs for a 18-bit bus.
+5 volt power supply pins.
Ground pins.
4
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Commercial
Unit
Terminal Voltage
with respect to GND
–0.5 to +7.0
V
Operating
Temperature
0 to +70
°C
TBIAS
Temperature Under
Bias
–55 to +125
°C
TSTG
Storage
Temperature
–55 to +125
°C
IOUT
DC Output Current
50
mA
VTERM
TA
RECOMMENDED DC
OPERATING CONDITIONS
Symbol
VCCC
Parameter
Commercial Supply
Voltage
GND
Supply Voltage
VIH
Input High Voltage
Commercial
Input Low Voltage
Commercial
VIL(1,2)
Min.
4.5
Typ.
5.0
Max.
5.5
Unit
V
0
0
0
V
2.0
—
—
V
—
—
0.8
V
NOTE:
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maimum rating conditions for extended periods may
affect reliabilty.
1. Does not apply to MAC which can only be tied to Vcc or GND.
2. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)
IDT72264L
IDT72274L
Commercial
tCLK = 15, 20ns
Symbol
Parameter
Min.
Type
Max
Unit
-1
—
1
µA
ILI(1)
Input Leakage Current (any input except MAC)
ILO(2)
Output Leakage Current
-10
—
10
µA
VOH
Output Logic "1" Voltage, IOH = -2mA
2.4
—
—
V
VOL
Output Logic "0" Voltage, IOL = 8mA
—
—
0.4
V
MAS = VCC
—
—
115
mA
MAS = GND
—
—
135
mA
Power Down Current (All inputs = VCC - 0.2V or
GND + 0.2V, RCLK and WCLK are free-running)
—
—
115
mA
ICC1(3)
ICC2(3,4)
Active Power Supply Current
NOTES:
1. Measurements with 0.4 < V IN < VCC.
2. OE + VIH
3. Tested at f = 20 MHz with outputs uploaded.
4. No data written or read for more than 10 cycles.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
(2)
CIN
Input
Capacitance
VIN = 0V
10
pF
COUT(1,2)
Output
Capacitance
VOUT = 0V
10
pF
NOTES:
1. With output deselected, (OE=HIGH).
2. Characterized values, not currently tested.
5
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)
Commercial
72264L15
72274L15
Symbol
Parameter
Commercial
72264L20
72274L20
Min.
Max.
Min.
Max.
Unit
fS
Clock Cycle Frequency
—
66.7
—
50
MHz
tA
Data Access Time
2
10
2
12
ns
tCLK
Clock Cycle Time
15
—
20
—
ns
tCLKH
Clock High Time
6
—
8
—
ns
tCLKL
Clock Low Time
6(2)
—
8
—
ns
tDS
Data Set-up Time
4
—
5
—
ns
tDH
Data Hold Time
1
—
1
—
ns
tENS
Enable Set-up Time
4
—
5
—
ns
tENH
Enable Hold Time
1
—
1
—
ns
tLDS
Load Set-up Time
4
—
5
—
ns
tLDH
Load Hold Time
10
—
10
—
ns
tRS
Reset Pulse Width(3)
15
—
20
—
ns
tRSS
Reset Set-up Time
15
—
20
—
ns
tRSR
Reset Recovery Time
15
—
20
—
ns
tRSF
Reset to Flag and Output Time
—
15
—
20
ns
Mode Select Time
0
—
0
—
ns
tFWFT
tRTS
Retransmit Set-Up Time
4
—
5
—
ns
tOLZ
Output Enable to Output in Low Z(4)
0
—
0
—
ns
tOE
Output Enable to Output Valid
3
8
3
10
ns
(4)
tOHZ
Output Enable to Output in High Z
3
8
3
10
ns
tWFF
Write Clock to FF or IR
—
10
—
12
ns
—
10
—
12
ns
—
—
—
10
10
20
—
—
—
12
12
22
ns
ns
ns
tREF
tPAF
tPAE
tHF
Read Clock to EF or OR
Write Clock to PAF
Read Clock to PAE
Clock to HF
tSKEW1
Skew time between RCLK and WCLK
for FF and IR
12
—
15
—
ns
tSKEW2
Skew time between RCLK and
WCLK for PAE and PAF
21
—
25
—
ns
NOTES:
1. All AC timings apply to both Standard IDT Mode and First Word Fall
Through Mode.
2. For the RCLK line: tCLKL (min.) = 7 ns only when reading the offsets from
the programmable flag registers; otherwise, use the table value. For the
WCLK line, use the tCLKL (min.) value given in the table.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
5V
1.1K
D.U.T.
680Ω
30pF*
GND to 3.0V
3ns
3218 drw 04
1.5V
1.5V
See Figure 1
Figure 1. Output Load
* Includes jig and scope capacitances.
3037 tbl 08
6
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
SIGNAL DESCRIPTIONS:
INPUTS:
DATA IN (D0 - D17)
All 18 data inputs (D0 - D17) function when the Memory
Array Configuration input (MAC) is tied to ground. Only 9-data
inputs ( D0 - D8) function when MAC is connected to Vcc. The
other data inputs (D9 - D17) do not function and may either be
tied to ground or left open.
CONTROLS:
MEMORY ARRAY CONFIGURATION (MAC)
The MAC line determines whether the FIFO will operate
with a nine-bit-wide data bus or an 18-bit wide data bus. A
FIFO is configured for 18-bit wide operation has half the
memory depth of the same FIFO configured for 9-bit wide
operation. MAC must be tied to either GND or Vcc. Connecting MAC to Vcc will configure the FIFO's input and output data
buses to be 9 bits wide. In this case, the IDT72264 will have
a 16384x 9 organization, and the IDT72274 will have a 32678
x 9 organization.
Connecting MAC to GND will configure the FIFO's input
and output data buses to be 18 bits wide. In this case, the
IDT72264 will have a 8192 x 18 organization, and the IDT72274
will have a 16384 x 18 organization. MAC must be set before
Master Reset; afterwards, it cannot be dynamically varied.
MASTER RESET (MRS)
A Master Reset is accomplished whenever the MRS input
is taken to a LOW state. This operation sets the internal read
and write pointers to the first location of the RAM array. PAE
will go LOW, PAF will go HIGH, and HF will go HIGH.
If FWFT is LOW during Master Reset then the IDT
Standard Mode, along with EF and FF are selected. EF will
go LOW and FF will go HIGH. If FWFT is HIGH, then the First
Word Fall through Mode (FWFT), along with IR and OR, are
selected. OR will go HIGH and IR will go LOW.
If LD is LOW during Master Reset, then PAE is assigned a
threshold 127 words from the empty boundary and PAF is
assigned a threshold 127 words from the full boundary; 127
words corresponds to an offset value of 07FH. Following
Master Reset, parallel loading of the offsets is permitted, but
not serial loading.
If LD is HIGH during Master Reset, then PAE is assigned
a threshold 1023 words from the empty boundary and PAF is
assigned a threshold 1023 words from the full boundary;
1023 words corresponds to an offset value of 3FFH. Following
Master Reset, serial loading of the offsets is permitted, but not
parallel loading.
Regardless of whether serial or parallel offset loading has
been selected, parallel reading of the registers is always
permitted. (See section describing the LD line for further
details).
During a Master Reset, the output register is initialized to
all zeroes. A Master Reset is required after power up, before
a write operation can take place. MRS is asynchronous
COMMERCIAL TEMPERATURE RANGES
PARTIAL RESET (PRS)
A Partial Reset is accomplished whenever the PRS input
is taken to a LOW state. As in the case of the Master Reset,
the internal read and write pointers are set to the first location
of the RAM array, PAE goes LOW, PAF goes HIGH, and HF
goes HIGH.
Whichever mode is active at the time of partial reset, IDT
Standard Mode or First Word Fall-through, that mode will
remain selected. If the IDT Standard Mode is active, then FF
will go HIGH and EF will go LOW. If the First word Fall-through
Mode is active, then OR will go HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain unchanged. The programming method (parallel
or serial) currently active at the time of Partial Reset is also
retained. The output register is initialized to all zeroes. PRS
is asynchronous.
A Partial Reset is useful for resetting the device during the
course of operation, when reprogramming flag settings may
not be convenient.
RETRANSMIT (RT)
The Retransmit operation allows data that has already
been read to be accessed again. There are two stages: first,
a setup procedure that resets the read pointer to the first
location of memory, then the actual retransmit, which consists
of reading out the memory contents, starting at the beginning
of memory.
Retransmit Setup is initiated by holding RT LOW during a
rising RCLK edge. REN and WEN must be HIGH before
bringing RT LOW. At least one word, but no more than Full - 2
words should have been written into the FIFO between Reset
(Master or Partial) and the time of Retransmit Setup. (For the
IDT72264, 8,192 when MAC is LOW, 16,384 when MAC is
HIGH; For the IDT72274, Full = 16,384 words when MAC is
LOW, 32,768 when MAC is LOW).
If IDT Standard mode is selected, the FIFO will mark the
beginning of the Retransmit Setup by setting EF LOW. The
change in level will only be noticeable if EF was HIGH before
setup. During this period, the internal read pointer is initialized
to the first location of the RAM array.
When EF goes HIGH, Retransmit Setup is complete and
read operations may begin starting with the first location in
memory. Since IDT Standard Mode is selected, every word
read including the first word following Retransmit Setup requires a LOW on REN to enable the rising edge of RCLK.
Writing operations can begin after one of two conditions have
been met: EF is HIGH or 14 cycles of the faster clock (RCLK
or WCLK) have elapsed since the RCLK rising edge enabled
by the RT pulse.
The deassertion time of EF during Retransmit Setup is
variable. The parameter tRTF1, which is measured from the
rising RCLK edge enabled by RT to the rising edge of EF is
described by the following equation:
tRTF1 max. = 14*Tf + 3*TRCLK (in ns)
where Tf is either the RCLK or the WCLK period, whichever is
shorter, and TRCLK is the RCLK period.
7
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
Regarding FF: Note that since no more than Full - 2 writes
are allowed between a Reset and a Retransmit Setup, FF will
remain HIGH throughout the setup procedure.
For IDT Standard mode, updating the PAE, HF, and PAF
flags begins with the "first" REN-enabled rising RCLK edge
following the end of Retransmit Setup (the point at which EF
goes HIGH). This same RCLK rising edge is used to access
the "first" memory location. HF is updated on the first RCLK
rising edge. PAE is updated after two more rising RCLK edges.
PAF is updated after the "first" rising RCLK edge, followed by
the next two rising WCLK edges. (If the tskew2 specification
is not met, add one more WCLK cycle.)
If FWFT mode is selected, the FIFO will mark the beginning
of the Retransmit Setup by setting OR HIGH. The change in
level will only be noticeable if OR was LOW before setup.
During this period, the internal read pointer is set to the first
location of the RAM array.
When OR goes LOW, Retransmit Setup is complete; at the
same time, the contents of the first location are automatically
displayed on the outputs. Since FWFT Mode is selected, the
first word appears on the outputs, no read request necessary.
Reading all subsequent words requires a LOW on REN to
enable the rising edge of RCLK. Writing operations can begin
after one of two conditions have been met: OR is LOW or 14
cycles of the faster clock (RCLK or WCLK) have elapsed since
the RCLK rising edge enabled by the RT pulse.
The assertion time of OR during Retransmit Setup is
variable. The parameter tRTF2, which is measured from the
rising RCLK edge enabled by RT to the falling edge of OR is
described by the following equation:
tRTF2 max. = 14*Tf + 4*TRCLK (in ns)
where Tf is either the RCLK or the WCLK period, whichever is
shorter, and TRCLK is the RCLK period. Note that a Retransmit
Setup in FWFT mode requires one more RCLK cycle than in
IDT Standard mode.
Regarding IR: Note that since no more than Full - 2 writes
are allowed between a Reset and a Retransmit Setup, IR will
remain LOW throughout the setup procedure.
For FWFT mode, updating the PAE, HF, and PAF flags
begins with the "last" rising edge of RCLK before the end of
Retransmit Setup. This is the same edge that asserts OR and
automatically accesses the first memory location. Note that,
in this case, REN is not required to initiate flag updating. HF
is updated on the "last" RCLK rising edge. PAE is updated
after two more rising RCLK edges. PAF is updated after the
"last" rising RCLK edge, followed by the next two rising WCLK
edges. (If the tSKEW2 specification is not met, add one more
WCLK cycle.)
RT is synchronized to RCLK. The Retransmit operation is
useful in the event of a transmission error on a network, since
it allows a data packet to be resent.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is a dual purpose pin. During Master Reset, the state
of the FWFT/SI input helps determine whether the device will
COMMERCIAL TEMPERATURE RANGES
operate in IDT Standard mode or First Word Fall Through
(FWFT) mode.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT
Standard mode will be selected. This mode uses the Empty
Flag (EF) to indicate whether or not there are any words
present in the FIFO memory. It also uses the Full Flag function
(FF) to indicate whether or not the FIFO memory has any free
space for writing. In IDT Standard mode, every word read
from the FIFO, including the first, must be requested using the
Read Enable (REN) line.
If, at the time of Master Reset, FWFT/SI is HIGH, then
FWFT mode will be selected. This mode uses Output Ready
(OR) to indicate whether or not there is valid data at the data
outputs (Qn). It also uses Input Ready (IR) to indicate whether
or not the FIFO memory has any free space for writing. In the
FWFT mode, the first word written to an empty FIFO goes
directly to Qn, no read request necessary. Subsequent words
must be accessed using the Read Enable (REN) line.
After Master Reset, FWFT/SI acts as a serial input for
loading PAE and PAF offsets into the programmable registers.
The serial input function can only be used when the serial
loading method has been selected during Master Reset.
FWFT/SI functions the same way in both IDT Standard and
FWFT modes.
WRITE CLOCK (WCLK)
A write cycle is initiated on the rising edge of the WCLK
input. Data set-up and hold times must be met with respect to
the LOW-to-HIGH transition of the WCLK. The write and read
clocks can either be asynchronous or coincident.
WRITE ENABLE (WEN)
When the WEN input is LOW, data can be loaded into the
input register on the rising edge of every WCLK cycle. Data
is stored in the RAM array sequentially and independently of
any on-going read operation.
When WEN is HIGH, the input register holds the previous
data and no new data is loaded into the FIFO.
To prevent data overflow in the IDT Standard Mode, FF will
go LOW , inhibiting further write operations. Upon the completion of a valid read cycle, FF will go HIGH allowing a write to
occur. WEN is ignored when the FIFO is full.
To prevent data overflow in the FWFT mode, IR will go
HIGH, inhibiting further write operations. Upon the completion
of a valid read cycle, IR will go LOW allowing a write to occur.
WEN is ignored when the FIFO is full.
READ CLOCK (RCLK)
Data can be read on the outputs, on the rising edge of the
RCLK input, when Output Enable (OE) is set LOW. The write
and read clocks can be asynchronous or coincident.
READ ENABLE (REN)
When Read Enable is LOW, data is loaded from the RAM
array into the output register on the rising edge of the RCLK.
8
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
When the REN input is HIGH, the output register holds the
previous data and no new data is loaded into the output
register.
In the IDT Standard Mode, every word accessed at Qn,
including the first word written to an empty FIFO, must be
requested using REN. When all the data has been read from
the FIFO, the Empty Flag (EF) will go LOW, inhibiting further
read operations. REN is ignored when the FIFO is empty.
Once a write is performed, EF will go HIGH after tFWL1 +tREF
and a read is permitted.
In the FWFT Mode, the first word written to an empty FIFO
automatically goes to the outputs Qn, no need for any read
request. In order to access all other words, a read must be
executed using REN . When all the data has been read from
the FIFO, Output Ready (OR) will go HIGH, inhibiting further
read operations. REN is ignored when the FIFO is empty.
LD
WEN REN SEN
WCLK
Once a write is performed, OR will go LOW after tFWL2 +tREF,
when the first word appears at Qn ; if a second word is written
into the FIFO, then REN can be used to read it out.
SERIAL ENABLE (SEN)
The SEN input is an enable used only for serial programming of the offset registers. The serial programming method
must be selected during Master Reset. SEN is always used
in conjunction with LD. When these lines are both LOW, data
at the SI input can be loaded into the input register one bit for
each LOW-to-HIGH transition of WCLK.
When SEN is HIGH, the programmable registers retains
the previous settings and no offsets are loaded.
SEN functions the same way in both IDT Standard and
FWFT modes.
RCLK
Selection
MAC = Vcc
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Parallel write to registers:
Empty Offset
Full Offset
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Parallel read from registers:
Empty Offset
Full Offset
X
Serial shift into registers:
28 bits for the 72264
30 bits for the 72274
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Serial shift into registers:
26 bits for the 72264
28 bits for the 72274
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
X
No Operation
No Operation
X
Write Memory
Write Memory
Read Memory
Read Memory
No Operation
No Operation
X
0
0
1
1
0
1
0
1
0
1
1
0
X
1
1
1
1
0
X
X
1
X
0
X
X
1
1
1
X
X
X
X
MAC = GND
X
3218 tbl 01
NOTES:
1. Only one of the two offset programming methods, serial or parallel, is available for use at any given time.
2. The programming method can only be selected at Master Reset.
3. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
4. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 2. Partial Flag Programming Sequence
9
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
OUTPUT ENABLE (OE)
When Output Enable is enabled (LOW), the parallel output
buffers receive data from the output register. When OE is
HIGH, the output data bus (Qn) goes into a high impedance
state.
LOAD (LD)
This is a dual purpose pin. During Master Reset, the state
of the LD input determines one of two default values (127 or
1023) for the PAE and PAF flags, along with the method by
which these flags can be programmed, parallel or serial. After
Master Reset, LD enables write operations to and read
operations from the registers. Only the offset loading method
currently selected can be used to write to the registers. Aside
from Master Reset, there is no other way change the loading
method. Registers can be read only in parallel; this can be
accomplished regardless of whether serial or the parallel
loading has been selected.
Associated with each of the programmable flags, PAE and
PAF, is one register which can either be written to or read from.
Offset values contained in these registers determine how
many words need to be in the FIFO memory to switch a partial
flag. A LOW on LD during Master Reset selects a default PAE
offset value of 07FH ( a threshold 127 words from the empty
boundary), a default PAF offset value of 07FH (a threshold 127
words from the full boundary), and parallel loading of other
offset values. A HIGH on LD during Master Reset selects a
default PAE offset value of 3FFH (a threshold 1023 words from
the empty boundary), a default PAF offset value of 3FFH (a
threshold 1023 words form the full boundary), and serial
loading of other offset values.
The act of writing offsets (in parallel or serial) employs a
dedicated write offset register pointer. The act of reading
offsets employs a dedicated read offset register pointer. The
two pointers operate independently; however, a read and a
write should not be performed simultaneously to the offset
registers. A Master Reset initializes both pointers to the
Empty Offset (LSB) register. A Partial Reset has no effect on
the position of these pointers.
It is important to note that the MAC setting configures the
offset register architecture to suit the memory array dimensions being selected. Therefore, the way offsets are programmed will vary according to whether MAS is tied to Vcc or
GND.
Consider the case where serial offset loading has been
selected. If MAC = GND (18-bit operation), then programming
PAE and PAF proceeds as follows: When LD and SEN are set
LOW, data on the SI input are written, one bit for each WCLK
rising edge, starting with the Empty Offset (13 bits for the
72264, 14 bits for the 72274) and ending with the Full Offset
(13 bits for the 72264, 14 bits for the 72274). A total of 26 bits
are necessary to program the 72264; a total of 28 bits are
necessary to program the 72274.
If serial offset loading has been selected and MAC = Vcc
(9-bit operation), then programming PAE and PAF proceeds
as follows: When LD and SEN are set LOW, data on the SI
input are written, one bit for each WCLK rising edge, starting
with the Empty Offset LSB (8 bits for both the 72264 and
COMMERCIAL TEMPERATURE RANGES
72274), then the Empty Offset MSB (6 bits for the 72264, 7 bits
for the 72274) , then the Full Offset LSB (8 bits for both the
72264 and 72274), ending with the Full Offset MSB (6 bits for
the 72264, 7 bits for the 72274). A total of 28 bits are
necessary to program the 72264; a total of 30 bits are
necessary to program the 72274.
For either MAC setting, individual registers cannot be
loaded serially; rather, all offsets must be programmed in
sequence, no padding allowed. PAE and PAF can show a
valid status only after the full set of bits have been entered.
The registers can be re-programmed as long as all offsets are
loaded. When LD is LOW and SEN is HIGH, no serial write to
the registers can occur.
Consider the case where parallel offset loading has been
selected. If MAC = GND (18-bit operation), then programming
PAE and PAF proceeds as follows: When LD and WEN are
set LOW, data on the inputs Dn are written into the Empty
Offset Register on the first LOW-to-HIGH transition of WCLK.
Upon the second LOW-to-HIGH transition of WCLK, data at
the inputs are written into the Full Register. The third transition
of WCLK writes, once again, to the Empty Offset Register.
If parallel offset loading has been selected and MAC = Vcc
(9-bit operation), then programming PAE and PAF proceeds
as follows: When LD and WEN are set LOW, data on the
inputs Dn are written into the LSB Empty Offset Register on the
first LOW-to-HIGH transition of WCLK. Upon the second
LOW-to-HIGH transition of WCLK, data at the inputs are
written into the MSB Empty Offset Register. Upon the third
LOW-to-HIGH transition of WCLK, data at the inputs are
written into the LSB Full Offset Register. Upon the fourth
LOW-to-HIGH transition of WCLK, data at the inputs are
written into the MSB Full Offset Register. The fifth transition of
WCLK writes, once again, to the LSB Empty Offset Register.
To ensure proper programming (serial or parallel) of the
offset registers, no read operation is permitted from the time
of reset (master or partial) to the time of programming. (During
this period, the read pointer must be pointing to the first
location of the memory array.) After the programming has
been accomplished, read operations may begin.
Write operations to memory are allowed before and during
the parallel programming sequence. In this case, the programming of all offset registers does not have to occur at one
time. One or two offset registers can be written to and then,
by bringing LD HIGH, write operations can be redirected to the
FIFO memory. When LD is set LOW again, and WEN is LOW,
the next offset register in sequence is written to. As an
alternative to holding WEN LOW and toggling LD, parallel
programming can also be interrupted by setting LD LOW and
toggling WEN.
Write operations to memory are allowed before and during
the serial programming sequence. In this case, the programming of all offset bits does not have to occur at once. A select
number of bits can be written to the SI input and then, by
bringing LD and SEN HIGH, data can be written to FIFO
memory via Dn by toggling WEN. When WEN is brought HIGH
with LD and SEN restored to a LOW, the next offset bit in
sequence is written to the registers via SI. If a mere interruption of serial programming is desired, it is sufficient either to set
10
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
LD LOW and deactivate SEN or to set SEN LOW and deactivate LD. Once LD and SEN are both restored to a LOW level,
serial offset programming continues from where it left off.
Note that the status of a partial flag (PAE or PAF) output is
invalid during the programming process. From the time
parallel programming has begun, a partial flag output will not
be valid until the appropriate offset word has been written to
the register(s) pertaining to that flag. From the time serial
programming has begun, neither partial flag will be valid until
the full set of bits required to fill all the offset registers has been
written. Measuring from the rising WCLK edge that achieves
either of the above criteria; PAF will be valid after two more
rising WCLK edges plus tPAF, PAE will be valid after the next
two rising RCLK edges plus tPAE (Add one more RCLK cycle
if tSKEW2 is not met.)
The act of reading the offset registers employs a dedicated
read offset register pointer. The contents of the offset registers can be read on the output lines when LD is set LOW and
72264 with MAC = GND (8,192 x 18–BIT)
72274 with MAC = GND (16,384 x 18–BIT)
17
17
0
12
0
13
EMPTY OFFSET REGISTER
EMPTY OFFSET REGISTER
DEFAULT VALUE
07FH if LD is LOW at Master Reset,
3FFH if LD is HIGH at Master Reset
DEFAULT VALUE
07FH if LD is LOW at Master Reset,
3FFH if LD is HIGH at Master Reset
17
17
0
12
0
13
FULL OFFSET REGISTER
FULL OFFSET REGISTER
DEFAULT VALUE
07FH if LD is LOW at Master Reset,
3FFH if LD is HIGH at Master Reset
DEFAULT VALUE
07FH if LD is LOW at Master Reset,
3FFH if LD is HIGH at Master Reset
3218 drw 06a
3218 drw 05a
72264 with MAC = Vcc (16,384 x 9–BIT)
8
8
7
72274 with MAC = Vcc (32,768 x 9–BIT)
0
8
7
0
EMPTY OFFSET (LSB) REG.
EMPTY OFFSET (LSB) REG.
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
0
5
8
0
6
EMPTY OFFSET (MSB) REG.
EMPTY OFFSET (MSB) REG.
00H
8
8
7
00H
0
8
7
0
FULL OFFSET (LSB) REG.
FULL OFFSET (LSB) REG.
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
0
5
8
0
6
FULL OFFSET (MSB) REG.
FULL OFFSET (MSB) REG.
00H
00H
3218 drw 05b
NOTE:
1. Any bits of the offset register not being programmed should be set to zero.
Figure 3. Offset Register Location and Default Values
3218 drw 06b
11
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
REN is set LOW.
If MAC = GND (18-bit operation), then data
are read via Qn from the Empty Offset Register on the first
LOW-to-HIGH transition of RCLK. Upon the second LOW-toHIGH transition of RCLK, data are read from the Full Offset
Register. The third transition of RCLK reads, once again, from
the Empty Offset Register.
If MAC = Vcc (9-bit operation ) when reading the offset
registers, then data are read via Qn from the LSB Empty Offset
Register on the first LOW-to-HIGH transition of RCLK. Upon
the second LOW-to-HIGH transition of RCLK, data are read
from the MSB Empty Offset Register. Upon the third LOW-toHIGH transition of RCLK, data are read from the LSB Full
Offset Register. Upon the fourth LOW-to-HIGH transition of
RCLK, data are read from the MSB Full Offset Register. The
fifth transition of RCLK reads, once again, from the LSB Empty
Offset Register.
It is permissible to interrupt the offset register access
sequence with reads or writes to memory . The interruption is
accomplished by deasserting REN, LD, or both together.
When REN and LD are restored to a LOW level, access of the
registers continues where it left off.
LD functions the same way in both IDT Standard and
FWFT modes.
FREQUENCY SELECT INPUT (FS)
An internal state machine manages the movement of data
through the SuperSync FIFO. The FS line determines whether
RCLK or WCLK will synchronize the state machine. The clock
tied to the state machine is referred to as the "selected clock".
The clock that is not tied to the state machine is referred to as
the "non-selected clock". To set FS, follow the guidelines
presented in Figure 3; this ensures efficient handling of the
data within the FIFO. Once having determined the FS setting,
it is permissible to vary the WCLK and RCLK frequencies, as
long as the inequalities corresponding to the chosen FS level
hold true. (See Figure 3.)
For example, if FS is set LOW, then the selected clock is
RCLK, whose frequency, fRCLK, may vary anywhere from
fWCLK/2 to the maximum allowable clock frequency a speed
grade permits (fs max. from AC Electrical Characteristics
table). The non-selected clock is WCLK, whose frequency,
fWCLK, may vary anywhere from 0 to 2 fRCLK (as long fs max.
as is not exceeded).
FS
COMMERCIAL TEMPERATURE RANGES
If FS is set HIGH, then the selected clock is WCLK, whose
frequency, fWCLK, may vary anywhere from fRCLK/2 to the
maximum allowable clock frequency a speed grade permits
(fs max.). The non-selected clock is RCLK, whose frequency,
fRCLK, may vary anywhere from 0 to 2 fWCLK (as long fs max.
as is not exceeded).
The selected clock must be continuous. It is, however,
permissible to stop the non-selected clock. Note, as long as
RCLK is idle, EF/OR and PAE will not be updated. Likewise,
as long as WCLK is idle, FF/IR and PAF will not be updated.
Changing the FS setting during FIFO operation (i.e. reading or writing) is not permitted; however, such a change at the
time of Master Reset or Partial Reset is all right. FS is an
asynchronous input.
OUTPUTS:
FULL FLAG (FF/IR)
This is a dual purpose pin. In IDT Standard Mode, the Full
Flag (FF) function is selected. When the FIFO is full (i.e. the
write pointer catches up to the read pointer), FF will go LOW,
inhibiting further write operation. When FF is HIGH, the FIFO
is not full. If no reads are performed after a reset (either MRS
or PRS), FF will go LOW after 8,192 writes for the IDT72264
and 16,384 writes to the IDT72274 when MAC = GND. If MAC
= Vcc, FF will go LOW after 16,384 writes for the IDT72264 and
32,768 writes to the IDT72274.
In FWFT Mode, the Input Ready (IR) function is selected.
IR goes LOW when memory space is available for writing in
data. When there is no longer any free space left, IR goes
HIGH, inhibiting further write operation. If no reads are
performed after a reset (either MRS or PRS), IR will go HIGH
after 8,193 writes for the IDT72264 and 16,385 writes for the
IDT72274 when MAC = GND. If MAC = Vcc, IR will go HIGH
after 16,385 writes for the IDT72264 and 32,769 writes to the
IDT72274.
The IR status not only measures the contents of the FIFO
memory, but also counts the presence of a word in the output
register. Thus, in FWFT mode, the total number of writes
necessary to deassert IR is one greater than needed to assert
FF in IDT Standard mode.
FF/IR is synchronized to WCLK. It is double-registered to
enhance metastable immunity.
Clock Identity
Clock Frequency
Range
Selected Clock = RCLK
fWCLK/2 < fRCLK ≤ fs max.
Non-selected Clock = WCLK
0 ≤ fWCLK < 2fRCLK
Selected Clock = WCLK
fRCLK/2 < fWCLK ≤ fs max.
Non-selected Clock = RCLK
0 ≤ fRCLK < 2fWCLK
LOW
HIGH
Figure 3. Guidelines for Determining the FS Setting and the Range of Allowable Clock Frequency Variation
12
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
EMPTY FLAG (EF/OR)
This is a dual purpose pin. In the IDT Standard Mode, the
Empty Flag (EF) function is selected. When the FIFO is empty
(i.e. the read pointer catches up to the write pointer), EF will go
LOW, inhibiting further read operations. When EF is HIGH, the
FIFO is not empty.
When writing the first word to an empty FIFO, the deassertion
time of EF is variable, and can be represent by the First Word
Latency parameter, tFWL1, which is measured from the rising
WCLK edge that writes the first word to the rising RCLK edge
that updates the flag. tFWL1 includes any delays due to clock
skew and can be expressed as follows:
the first word can be available at Qn. This delay has no effect
on the reading of subsequent words.
EF/OR is sychronized to the RCLK. It is double-registered
to enhance metastable immunity.
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
The Programmable Almost-Full Flag (PAF) will go LOW
when the FIFO reaches the Almost-Full condition as specified
by the offset m stored in the Full Offset register.
At the time of Master Reset, depending on the state of LD,
one of two possible default offset values are chosen. If LD is
LOW, then m = 07FH and the PAF switching threshold is 127
words from the Full boundary, if LD is HIGH, then m = 3FFH
and the PAF switching threshold is 1023 words away from the
Full boundary.
Any integral value of m from 0 to the maximum FIFO depth
minus 1 (8,191 words for the 72264 and 16,383 words for the
72274 when MAC = GND; 16,383 words for the 72264 and
32,767 words for the 72274 when MAC = Vcc) can be
programmed into the Full Offset register.
In IDT Standard Mode with MAC = GND, if no reads are
performed after reset (MRS or PRS), PAF will go LOW after
(8,192-m) writes to the IDT72264, and (16,384-m) writes to
the IDT72274. If MAC = Vcc, PAF will go LOW after (16,384-m)
writes to the IDT72264, and (32,768-m) writes to the IDT72274.
In FWFT Mode with MAC = GND, if no reads are performed
after reset (MRS or PRS), PAF will go LOW after (8,193-m)
writes to the IDT72264, and (16,385-m) writes to the IDT72274.
If MAC = Vcc, PAF will go LOW after (16,385-m) writes to the
IDT72264, and (32,679-m) writes to the IDT72274. In FWFT
Mode, the first word written to an empty FIFO does not stay in
memory, but goes unrequested to the output register; therefore, it has no effect on determining the state of PAF.
Note that even though PAF is programmed to switch LOW
during the first word latency period (tFWL), attempts to read
data will be ignored until EF goes HIGH indicating that data is
available at the output port. This is true for both timing modes.
PAF is synchronous and updated on the rising edge of
WCLK. It is double-registered to enhance metastable immunity.
tFWL1 max. = 10*Tf + 2*TRCLK (in ns)
where Tf is either the RCLK or the WCLK period, whichever is
shorter, and TRCLK is the RCLK period. Since no read can
take place until EF goes HIGH, the tFWL1 delay determines
how early the first word can be available at Qn. This delay has
no effect on the reading of subsequent words.
In FWFT Mode, the Output Ready (OR) function is selected.
OR goes LOW at the same time that the first word written to an
empty FIFO appears valid on the outputs. OR goes HIGH one
cycle after RCLK shifts the last word from the FIFO memory
to the outputs. Then further data reads are inhibited until OR
goes LOW again.
When writing the first word to an empty FIFO, the assertion
time of OR is variable, and can be represented by the First
Word Latency parameter, tFWL2, which is measured from the
rising WCLK edge that writes the first word to the rising RCLK
edge that updates the flag. tFWL2 includes any delay due to
clock skew and can be expressed as follows:
tFWL2 max. = 10*Tf + 3*TRCLK (in ns)
where Tf is either the RCLK or the WCLK period, whichever is
shorter, and TRCLK is the RCLK period. Note that the First
Word Latency in FWFT mode is one RCLK cycle longer than
in IDT Standard mode. The tFWL2 delay determines how early
TABLE I –– STATUS FLAGS FOR IDT STANDARD MODE
Number of Words in FIFO Memory(1)
72264
MAC =GND
72274
MAC = Vcc
MAC = GND
MAC = Vcc
FF PAF HF PAE EF
0
0
0
0
H
H
H
L
L
1 to n(2)
1 to n(2)
1 to n(2)
1 to n (2)
H
H
H
L
H
(n+1) to 8,192
(n+1) to 16,384
(n+1) to 4,096
(n+1) to 8,192
H
H
H
H
H
4,097 to (8,192-(m+1))
8,193 to (16,384-(m+1))
8,193 to (16,384-(m+1)) 16,385 to (32,768-(m+1))
H
H
L
H
H
(8,192-m)(3) to 8,191
(16,384-m)(3) to 16,383
(16,384-m)(3) to 16,383
(32,768-m)(3) to 32,767
H
L
L
H
H
8,192
16,384
16,384
32,768
L
L
L
H
H
NOTES:
1. Data in the output register does not count as a 'word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes
unrequested to the output register (no read operation necessary), it is not included in the FIFO memory count.
2. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n=1023 when serial offset loading is selected.
3. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or n=1023 when serial offset loading is selected.
13
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
The Programmable Almost-Empty Flag (PAE) will go LOW
when the FIFO reaches the Almost-Empty condition as specified by the offset n stored in the Empty Offset register.
At the time of Master Reset, depending on the state of LD,
one of two possible default offset values are chosen. If LD is
LOW, then n = 07FH and the PAE switching threshold is 127
words from the Empty boundary, if LD is HIGH, then n = 3FFH
and the PAE switching threshold is 1023 words away from the
Empty boundary.
Any integral value of n from 0 to the maximum FIFO depth
minus 1 (8,191 words for the 72264 and 16,383 words for the
72274 when MAC = GND; 16,383 words for the 72264 and
32,767 words for the 72274 when MAC = Vcc) can be
programmed into the Empty Offset register.
In IDT Standard Mode, if no reads are performed after reset
(MRS or PRS), the PAE will go HIGH after (n + 1) writes to the
IDT72264/72274.
In FWFT Mode, if no reads are performed after reset (MRS
or PRS), the PAE will go HIGH after (n+2) writes to the
IDT72264/72274. In this case, the first word written to an
empty FIFO does not stay in memory, but goes unrequested
to the output register; therefore, it has no effect on determining
the state of PAE.
Note that even though PAE is programmed to switch HIGH
during the first word latency period (tFWL), attempts to read
data will be ignored until EF goes HIGH indicating that data is
available at the output port. This is true for both timing modes.
PAE is synchronous and updated on the rising edge of
RCLK. It is double-registered to enhance metastable immunity.
HALF-FULL FLAG (HF)
This output indicates a half-full memory. The rising WCLK
edge that fills the memory beyond half-full sets HF LOW. The
flag remains LOW until the difference between the write and
read pointers becomes less than or equal to half of the total
depth of the device; the rising RCLK edge that accomplishes
this condition also sets HF HIGH.
In IDT Standard Mode, if no reads are performed after reset
(MRS or PRS), HF will go LOW after (D/2 + 1) writes, where D
is the maximum FIFO depth (8,192 words for the 72264 and
16,384 words for the 72274 when MAC = GND; 16,384 words
for the 72264 and 32,768 words for the 72274 when MAC =
Vcc).
In FWFT Mode, if no reads are performed after reset (MRS
or PRS), HF will go LOW after (D/2+2) writes to the IDT72264/
72274. In this case, the first word written to an empty FIFO
does not stay in memory, but goes unrequested to the output
register; therefore, it has no effect on determining the state of
HF.
Because HF uses both RCLK and WCLK for synchronization purposes, it is asynchronous.
DATA OUTPUTS (Q0-Q17)
All 18 data outputs (Q0 - Q17) function when the Memory
Array Configuration input (MAC) is tied to ground. Only 9-data
inputs (Q0 - Q8) function when MAC is connected to Vcc. The
other data inputs (Q9 - Q17), though they do not function, are
nevertheless active and should be left open.
TABLE II –– STATUS FLAGS FOR FWFT MODE
Number of Words in FIFO Memory(1)
72264
72274
MAC = GND
MAC = Vcc
MAC = GND
MAC = Vcc
IR
0
0
0
0
L
H
H
L
H(4)
L
H
H
L
L
(2)
1 to n
(2)
1 to n
(2)
1 to n
(n+1) to 8,192
1 to n
(2)
(n+1) to 16,384
PAF HF PAE OR
(n+1) to 4,096)
(n+1) to 8,192
L
H
H
H
L
4,097 to (8,192-(m+1))
8,193 to (16,384-(m+1))
8,193 to (16,384-(m+1)) 16,385 to (32,768-(m+1))
L
H
L
H
L
(8,192-m)(3) to 8,191
(16,384-m)(3) to 16,383
(16,384-m)(3) to 16,383
(32,768-m)(3) to 32,767
L
L
L
H
L
8,192
16,384
16,384
32,768
H
L
L
H
L
NOTES:
1.Data in the output register does not count as a 'word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO
goes unrequested to the output register (no read operation necessary), it is not included in the FIFO memory count.
2. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n=1023 when serial offset loading is selected.
3. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or n=1023 when serial offset loading is selected.
4. Following a reset (Master or Partial), the FIFO memory is empty and OR = HIGH. After writing the first word, the FIFO memory remains empty,
the data is placed into the output register, and OR goes LOW. In this case, or any time the last word in the FIFO memory has been read into the
output register; a rising RCLK edge, enabled by REN, will set OR HIGH.
14
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
tRS
MRS
tRSS
tRSR
tRSS
tRSR
REN
WEN
tRSR
tFWFT
FWFT/SI
tRSS
LD
tRSR
(1)
tRSS
RT
tRSS
SEN
tRSF
If FWFT = HIGH, OR = HIGH
EF/OR
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
tRSF
FF/IR
If FWFT = HIGH, IR = LOW
tRSF
PAE
tRSF
PAF, HF
tRSF
OE = HIGH
(1)
Q0 - Qn
OE = LOW
3218 drw 07
Figure 4. Master Reset Timing
NOTE:
1. Use MAC to select the memory array configuration by connecting it to either GND (18-bit operation) or Vcc (9-bit operation) before Master Reset
15
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
PRS
COMMERCIAL TEMPERATURE RANGES
tRS
tRSS
tRSR
tRSS
tRSR
REN
WEN
tRSS
RT
tRSS
SEN
tRSF
EF/OR
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
tRSF
FF/IR
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
tRSF
PAE
tRSF
PAF, HF
tRSF
OE = HIGH
Q 0 - Qn
Figure 5. Partial Reset Timing
OE = LOW
(1)
3218 drw 08
16
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
tCLK
tCLKH
WCLK
1
tCLKL
2
tDS
tDH
tENS
tENH
D 0 - Dn
DATAIN VALID
WEN
NO OPERATION
tWFF
tWFF
FF
tSKEW1
(1)
RCLK
REN
3218 drw 09
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle plus tWFF).
If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then the FF deassertion may be delayed an extra WCLK
cycle.
2. LD = HIGH
Figure 6. Write Cycle Timing (IDT Standard Mode)
17
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
tCLK
tCLKH
tCLKL
RCLK
tENS tENH
REN
NO OPERATION
tREF
tREF
EF
tA
Q 0 - Qn
LAST WORD
tOLZ
tOE
tOHZ
OE
(1)
tFWL1
WCLK
tENH
WEN
tENS
tDHS
tDS
D 0 - Dn
FIRST WORD
3218 drw 10
NOTES:
1. tFWL1 contributes a variable delay to the overall first word latency (this parameter includes delays due to skew):
tFWL1 max. (in ns) = 10*Tf + 2* TRCLK
where Tf is either the RCLK or the WCLK period, whichever is shorter, and TRCLK is the RCLK period
2. LD = HIGH
Figure 7. Read Cycle Timing (IDT Standard Mode)
18
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
WCLK
tDS
D 0 - Dn
D0
D1
first valid write
tENS
WEN
(1)
tFWL1
RCLK
tREF
EF
REN
tA
tA
D0
Q 0 - Qn
D1
tOLZ
OE
tOE
3218 drw 11
NOTES:
1. tFWL1 max. (in ns) = 10* Tf + 2* TRCLK
Where Tf is either the RCLK or the WCLK period, whichever is shorter, and TRCLK is the RCLK period
2. LD = HIGH
Figure 8. First Data Word Latency (IDT Standard Mode)
19
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
NO WRITE
NO WRITE
WCLK
1
2
1
tSKEW1 (1)
tSKEW1
tDS
D 0 - Dn
(1)
2
DATA
WRITE
tDS
Wd
tWFF
tWFF
tWFF
FF
WEN
RCLK
tENH
REN
OE
tENS
LOW
tA
Q 0 - Qn
tENH
tENS
DATA IN OUTPUT REGISTER
tA
DATA READ
NEXT DATA READ
3218 drw 12
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus tWFF).
If the time between the rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed an extra
WCLK cycle.
2. LD = HIGH
Figure 9. Full Flag Timing (IDT Standard Mode)
20
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
WCLK
tDS
tDS
DATA WRITE 1
D 0 - Dn
DATA WRITE 2
tENH
tENS
tENS
tENH
WEN
(1)
(1)
tFWL1
tFWL1
RCLK
tREF
tREF
tREF
EF
REN
OE
LOW
tA
Q 0 - Qn
DATA IN OUTPUT REGISTER
NOTES:
1. tFWL1 max. (in ns) = 10*Tf + 2*TRCLK
Where Tf is either the RCLK or the WCLK period, whichever is shorter, and TRCLK is the period.
2. LD = HIGH
WORD 1
3218 drw 13
Figure 10. Empty Flag Timing (IDT Standard Mode)
21
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
WCLK
tENH
tENS
tENH
SEN
tLDH
tLDS
tLDH
LD
tDS
SI
BIT 0
BIT X
(1)
BIT 0
EMPTY OFFSET
BIT X
(1)
FULL OFFSET
3218 drw 14
Figure 11. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT modes)
NOTE:
1. If MAC is tied to GND, X = 12 for the 72264 and X = 13 for the 72274. If MAC is tied to Vcc, X = 5 for the 72264 and X = 6 for the 72274.
tCLK
tCLKH
tCLKL
WCLK
tLDS
tLDH
LD
tENS
tENH
WEN
tDS
tDH
D 0 - Dn
PAE OFFSET
PAF OFFSET
3218 drw 15
Figure 12. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT modes)
22
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
tCLK
tCLKL
tCLKH
RCLK
tLDS
tLDH
tENS
tENH
tLDH
LD
tENH
REN
tA
tA
DATA IN OUTPUT REGISTER
Q0 - Qn
PAE OFFSET
PAF OFFSET
3218 drw 16
Figure 13. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT modes)
NOTE:
1. OE=LOW
tCLKL
tCLKH
WCLK
tENH
tENS
WEN
PAE
n words in FIFO memory
(1,2)
n Words
in FIFO
memory
n+1 words in FIFO memory
(3)
tPAE
tPAE
tSKEW2
RCLK
1
1
2
tENS
2
tENH
REN
3218 drw 17
NOTES:
1. PAE offset = n
2. Data in the output register does not count as a "word in FIFO memory". Since, in FWFT mode, the first word written to an empty FIFO goes unrequested
to the output register (no read operation necessary), it is not included in the FIFO memory count.
3. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to go HIGH (after one RCLK cycle plus tPAE). If the time
between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
Figure 14. Programmable Almost Empty Flag Timing (IDT Standard and FWFT modes)
23
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
tCLKL
tCLKH
WCLK
tENS
1
2
1
2
tENH
WEN
tPAF
t PAF
PAF
D - m Words in (1,2)
FIFO Memory
D - (m+1) Words in
FIFO Memory
D-(m+1)
Words in FIFO
Memory
(3)
tSKEW2
RCLK
tENS
tENH
REN
3218 drw 18
NOTES:
1. PAF offset = m; maximum FIFO depth = D = 8,192 for IDT 72264 with MAC = GND; D = 16,384 for IDT 72274 with MAC = GND; D = 16,384 for IDT 72264
with MAC = Vcc; D = 32,768 for IDT 72274 with MAC = Vcc.
2. Data in the output register does not count as a "word in FIFO memory". Since, in FWFT mode, the first word written to an empty FIFO goes unrequested
to the output register (no read operation necessary), it is not included in the FIFO memory count.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to go HIGH (after one WCLK cycle plus tPAF). If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed an extra WCLK cycle.
Figure 15. Programmable Almost Full Flag Timing (IDT Standard and FWFT modes)
tCLKH
tCLKL
WCLK
tENS tENH
WEN
tHF
HF
D/2 Words
D/2 + 1 Words
D/2 Words
tHF
RCLK
tENS
REN
3218 drw 19
NOTE:
1. D = 8,192 for IDT 72264 with MAC = GND; D = 16,384 for IDT 72274 with MAC = GND; D = 16,384 for IDT 72264 with MAC = Vcc; D = 32,768 for IDT
72274 with MAC = Vcc.
Figure 16. Half - Full Flag Timing (IDT Standard and FWFT modes)
24
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
WCLK
2
1
tENS tENH
tRTS
tENS
tENH
tDS
tDH
WEN
tDS
D 0 - Dn
tDH
Wx
W [x + 1]
tSKEW2
RCLK
(3)
tENS
tENH
1
tRTS
tRTF1
2
3
(1,2)
tENS
tENH
REN
tA
Q 0 - Qn
tA
W [y+1]
Wy
tENS
W1
tENH
RT
tREF
tREF
EF
tPAE
PAE
tHF
HF
tPAF
PAF
FF (4)
3218 drw 20
NOTES:
1. tRTF1 contributes a variable delay to the overall retransmit recovery time:
tRFTF1 max = 14*Tf + 3*TRCLK (in ns)
Where Tf is either the RCLK or the WCLK period, whichever is shorter, and TRCLK is the RCLK period.
2. Retransmit set up is complete after EF returns HIGH, only then can a read operation begin. Write operations are permitted after one of two conditions
have been met: EF is HIGH or 14 cycles of the faster clock (RCLK or WCLK) have elapsed since the RCLK rising edge enabled by the RT pulse.
3. Following Retransmit Setup, the rising edge of RCLK that accesses the first memory location also initiates the updating of HF, PAE, and PAF.
4. No more than D-2 words should have been written to the FIFO between Reset (Master or Partial) and Retransmit Setup. Therefore, FF will be HIGH
throughout the Restransmit Setup procedure. (D = 8,192 for IDT 72264 with MAC = GND; D = 16,384 for IDT 72274 with MAC = GND; D = 16,384 for
IDT 72264 with MAC = Vcc; D = 32,768 for IDT 72274 with MAC = Vcc.)
5. OE=LOW
Figure 17. Retransmit Timing (IDT Standard mode)
25
W1
W2
tREF
tA
tFWL2 (1)
tDH
DATA IN OUTPUT REGISTER
tDS
tENS
Wn+1
tDS
W1
W[n +2]
W[n+3]
1
tSKEW2 (2)
2
tPAE
W[n+4]
W[D/2+1]
tDS
W[D/2+2]
tHF
W[D/2+3]
W[D-m)]
tDS
W[D-m+1]
W[D-m+2]
1
W[D-m+3]
2
tPAF
W[D-m+4]
WD
W[D+1]
3218 drw 21
tWFF
tENH
Figure 18. Write Timing (First Word Fall Through Mode)
NOTES:
1. tFWL2 max. (in ns) = 10*Tf + 3*TRCLK
where Tf is either the RCLK or the WCLK period, whichever is shorter, and TRCLK is the RCLK period.
2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to go HIGH (after one RCLK cycle plus tPAE). If the time between the rising edge of WCLK and the
rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
3. LD = HIGH, OE = LOW
4. PAE offset = n; PAF offset = m; D = 8,192 for IDT 72264 with MAC = GND; D = 16,384 for IDT 72274 with MAC = GND; D = 16,384 for IDT 72264 with MAC = Vcc; D = 32,768 for IDT 72274
with MAC = Vcc.
IR
PAF
HF
PAE
OR
Q0 - Q n
REN
RCLK
D0 - Dn
WEN
WCLK
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
26
tENS
tDH
W1
tOHZ
W[D+1]
tDS
tENS
t WFF
tENH
tOE
W1
tA
W2
tSKEW1 (1)
1
tA
2
t WFF
W3
Wm+1
tA
W[m+2]
tSKEW2 (2)
1
2
tPAF
W [m+3]
W[D/2]
tHF
tA
W[D/2+1]
W[D-n]
tA
W[D-n+1]
1
W[D-n+2]
2
W[D-n+3]
tPAE
tA
WD
tA
tREF
3218 drw 22
W[D+1]
Figure 19. Read Timing (First Word Fall Through Mode)
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR will go LOW (after one WCLK cycle plus tWFF). If the time between the rising ege of RCLK
and the rising edge of WCLK is less than tSKEW1, then the IR assertion may be delayed an extra WCLK cycle.
2. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to go HIGH (after one WCLK cycle plus tPAF). If the time between the rising edge of RCLK and the rising
edge of WCLK is less than tSKEW2, then the PAF deassertion may be delayed an extra WCLK cycle.
3. LD = HIGH
4. PAE Offset = n; PAF offset = m; D = 8,192 for IDT 72264 with MAC = GND; D = 16,384 for IDT 72274 with MAC = GND; D = 16,384 for IDT 72264 with MAC = Vcc; D = 32,768 for IDT 72274 with
MAC = Vcc.
IR
PAF
HF
PAE
OR
Q0 - Qn
OE
REN
RCLK
D0 - D n
WEN
WCLK
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
27
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
WCLK
1
tENS tENH
2
tRTS
tENS
tENH
tDS
tDH
WEN
tDS
D 0 - Dn
tDH
Wx
W [x + 1]
tSKEW2
RCLK
tENS
tENH
1
tRTS
tRTF1
(3)
2
3
(1,2)
tENS
tENH
REN
tA
Q 0 - Qn
tA
tA
W [y+1]
Wy
tENS
W2
W1
tENH
RT
tREF
tREF
OR
tPAE
PAE
tHF
HF
tPAF
PAF
IR (4)
NOTES:
3218 drw 23
1. tRTF2 contribute a variable delay to the overall retransmit time:
tRTF2 max = 14*Tf + 4*TRCLK (in ns)
Where Tf is either the RCLK or the WCLK period, whichever is shorter, and TRCLK is the RCLK period.
2. Retransmit set up is complete after OR returns LOW, only then can a read operation begin. Write operations are permitted after one of two conditions
have been met: OR is LOW or 14 cycles of the faster clock (RCLK or WCLK) have elapsed since the RCLK rising edge enabled by the RT pulse.
3. Following Retransmit Setup, the rising edge of RCLK that accesses the first memory location also initiates the updating of HF, PAE, and PAF.
4. No more than D-2 words should have been written to the FIFO between Reset (Master or Partial) and Retransmit Setup. Therefore, IR will be LOW
throughout the Retransmit Setup procedure. (D = 8,192 for IDT 72264 with MAC = GND; D = 16,384 for IDT 72274 with MAC = GND; D = 16,384 for
IDT 72264 with MAC = Vcc; D = 32,768 for IDT 72274 with MAC = Vcc.)
5. OE=LOW
Figure 20. Retransmit Timing (FWFT mode)
28
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
(MAC = GND) or 16,384/32,768 for a 9-bit data path (MAC =
Vcc). The IDT72264/72274 can always be used in Single
Device Configuration, whether IDT Standard Mode or FWFT
SINGLE DEVICE CONFIGURATION
Mode has been selected. No special set up procedure is
A single IDT72264/72274 may be used when the applicanecessary.
tion requires depths up to 8,192/16,384 for an 18-bit data path
OPERATING CONFIGURATIONS
PARTIAL RESET (PRS)
MASTER RESET (MRS)
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
READ ENABLE (REN)
WRITE ENABLE (WEN)
OUTPUT ENABLE (OE)
LOAD (LD)
DATA IN (D0 - Dn)
SERIAL ENABLE(SEN)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
DATA OUT (Q0 - Qn)
IDT
72264/
72274
FULL FLAG/INPUT READY (FF/IR)
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST EMPTY (PAE)
HALF FULL FLAG (HF)
PROGRAMMABLE ALMOST FULL (PAF)
FREQUENCY
SELECT (FS)
MEMORY ARRAY
CONFIGURATION
(MAC)
3218 drw 24
Figure 21. Block Diagram of IDT72264/74 FIFO in single device configuration:
8,192 x 18 or 16,384 x 18 if MAC = GND; 16,384 x 9 or 32,678 x 9 if MAC = Vcc
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control signals of multiple devices. Status flags can
be detected from any one device. The exceptions are the EF
and FF functions in IDT Standard mode and the IR and OR
functions in FWFT mode. Because of variations in skew
between RCLK and WCLK, it is possible for EF/FF deassertion
and IR/OR assertion to vary by one cycle between FIFOs. In
IDT Standard mode, such problems can be avoided by creating composite flags, that is, ANDing EF of every FIFO, and
separately ANDing FF of every FIFO. In FWFT mode, composite flags can be created by ORing OR of every FIFO, and
separately ORing IR of every FIFO.
Figure 22 demonstrates a width expansion using two
IDT72264/72274s. If MAC = GND for both FIFOs, then D0 D17 from each device, taken together, form a 36-bit wide input
bus and Q0 - Q17 from each device, taken together, form a 36bit wide output bus. If MAC = Vcc for both FIFOs, then D0 - D8
from each device, taken together, form an 18-bit wide input
bus and Q0 - Q8 from each device, taken together, form an 18bit wide output bus. (In this case, both FIFOs' D9 - D17 and Q9
- Q17 do not function.) Any word width can be attained by
adding additional IDT72264/72274s.
29
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
m+n
D0 - Dn
m
D0 - Dm
DATA IN
n
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
READ ENABLE (REN )
WRITE ENABLE (WEN)
OUTPUT ENABLE (OE)
LOAD (LD)
IDT
72264/
72274/
FULL FLAG/INPUT READY (FF/IR) #1
(1)
IDT
72264/
72274/
FULL FLAG/INPUT READY (FF/IR) #2
GATE
PROGRAMMABLE (PAE)
EMPTY FLAG/OUTPUT READY (EF/OR) #1
(1)
EMPTY FLAG/OUTPUT READY (EF/OR) #2
PROGRAMMABLE (PAF)
#1
HALF FULL FLAG (HF)
#2
n
m+n
Q0 - Qn
DATA OUT
m
FREQUENCY SELECT (FS)
Q0 - Qm
MEMORY ARRAY
CONFIGURATION
(MAC)
GATE
MEMORY ARRAY
CONFIGURATION
(MAC)
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NOTE:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
Figure 22. Block Diagram of IDT72264/74 Width Expansion: 8,192 x 36 or 16,384 x 36 if MAC = GND; 16,384 x 18 or 32,768 x 18 if MAC = Vcc
Care should be taken to select FWFT mode during Master
Reset for all FIFOs in the depth expansion configuration. The
first word written to an empty configuration will pass from one
FIFO to the next ("ripple down") until it finally appears at the
outputs of the last FIFO in the chain–no read operation is
necessary. Each time the data word appears at the outputs
of one FIFO, that device's OR line goes LOW, enabling a write
to the next FIFO in line.
The OR assertion time is variable and is described with the
help of the tFWL2 parameter, which includes including delay
caused by clock skew:
DEPTH EXPANSION CONFIGURATION
The IDT72264/72274 can easily be adapted to applications
requiring depths greater than 8,192/16,384 with an18- bit bus
width (MAC = GND) or 16,384/32,768 words with a 9-bit bus
width (MAC = Vcc). In FWFT mode, the FIFOs can be
connected in series (the data outputs of one FIFO connected
to the data inputs of the next)–no external logic necessary.
The resulting configuration provides a total depth equivalent
to the sum of the depths associated with each single FIFO.
Figure 23 shows a depth expansion using two IDT72264/
72274s.
TRANSFER CLOCK
WRITE CLOCK
WRITE ENABLE
INPUT READY
WCLK
RCLK
OR
WEN
72264/
72274
IR
REN
OE
DATA IN
•
n
Qn
Dn
FS
MAC
WCLK
RCLK
WEN
REN
72264/
72274
IR
GND
n
READ CLOCK
READ ENABLE
OR
OUTPUT READY
OE
OUTPUT ENABLE
n
DATA OUT
Qn
Dn
FS
MAC
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Figure 23. Block Diagram of IDT72264/74 Depth Expansion: 16,384 x 18 or 32,768 x 18 if MAC = GND; 32,768 x 9, 65,536 x 9 if MAC = Vcc
30
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
tFWL2 max.= 10*Tf + 3*TRCLK
where TRCLK is the RCLK period and Tf is either the RCLK or
the WCLK period, whichever is shorter.
The maximum amount of time it takes for a word to pass
from the inputs of the first FIFO to the outputs of the last FIFO
in the chain is the sum of the delays for each individual FIFO:
the previous one until it finally moves into the first FIFO of the
chain. Each time a free location is created in one FIFO of the
chain, that FIFO's IR line goes LOW, enabling the preceding
FIFO to write a word to fill it.
The amount of time it takes for IR of the first FIFO in the chain
to assert after a word is read from the last FIFO is the sum of
the delays for each individual FIFO:
tFWL2(1) + tFWL2(2) + ... + tFWL2(N)+ N*TRCLK
N*(3*TWCLK)
where N is the number of FIFOs in the expansion.
Note that the additional RCLK term accounts for the time it
takes to pass data between FIFOs.
The ripple down delay is only noticeable for the first word
written to an empty depth expansion configuration. There will
be no delay evident for subsequent words written to the
configuration.
The first free location created by reading from a full depth
expansion configuration will "bubble up" from the last FIFO to
where N is the number of FIFOs in the expansion and TWCLK
is the WCLK period. Note that one of the three WCLK cycle
accounts for TSKEW1 delays.
In a SuperSync depth expansion, set FS individually for
each FIFO in the chain. The Transfer Clock line should be tied
to either WCLK or RCLK, whichever is faster. Both these
actions result in moving, as quickly as possible, data to the
end of the chain and free locations to the beginning of the
chain.
ORDERING INFORMATION
IDT
XXXXX
Device Type
X
Power
XX
Speed
X
Package
X
Process /
Temperature
Range
BLANK
Commercial (0°C to +70°C)
G
PF
TF
Pin Grid Array (PGA, G68-1)
Thin Plastic Quad Flatpack (TQFP, PN64-1)
Slim Thin Quad Flatpack (STQFP, PP64-1)
15 Commercial
20 Commercial
Clock Cycle Time (tCLK)
Speed in Nanoseconds
L
Low Power
72264
72274
8,192 x 18 or 16,384x 9 SuperSync FIFO
16,384 x 18 or 32,678 x 9 SuperSync FIFO
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31