3.3 VOLT MULTIMEDIA FIFO 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, and 4,096 x 8 IDT72V10081, IDT72V11081 IDT72V12081, IDT72V13081 IDT72V14081 FEATURES DESCRIPTION • • • • • The IDT72V10081/72V11081/72V12081/72V13081/72V14081 devices are low-power First-In, First-Out (FIFO) memories with clocked read and write controls. These devices have a 256, 512, 1,024, 2,048 and 4,096 x 8-bit memory array, respectively. These FIFOs are applicable for a wide variety of data buffering needs such as graphics and interprocessor communication. These FIFOs have 8-bit input and output ports. The input port is controlled by a free-running clock (WCLK) and Write Enable pin (WEN). Data is written into the Multimedia FIFO on every rising clock edge when the Write Enable pin is asserted. The output port is controlled by another clock pin (RCLK) and Read Enable pin (REN). The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. An Output Enable pin (OE) is provided on the read port for three-state control of the output. The Multimedia FIFOs have two fixed flags, Empty (EF) and Full (FF). These FIFOs are fabricated using IDT's submicron CMOS technology. • • • • • • • 256 x 8-bit organization array (IDT72V10081) 512 x 8-bit organization array (IDT72V11081) 1,024 x 8-bit organization array (IDT72V12081) 2,048 x 8-bit organization array (IDT72V13081) 4,096 x 8-bit organization array (IDT72V14081) 15 ns read/write cycle time 5V input tolerant Independent Read and Write clocks Empty and Full Flags signal FIFO status Output Enable puts output data bus in high-impedance state Available in 32-pin plastic Thin Quad FlatPack (TQFP) Industrial temperature range (–40°°C to +85°° C) FUNCTIONAL BLOCK DIAGRAM WCLK WEN RCLK READ CONTROL WRITE CONTROL REN OE FIFO ARRAY D0 - D7 Data In x8 Q0 - Q 7 Data Out x8 RESET LOGIC FLAG OUTPUTS EF RS FF 6161 drw01 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGES NOVEMBER 2003 1 2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-6161/2 IDT72V10081/11081/12081/13081/14081 3.3V MULTIMEDIA FIFO 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8 INDUSTRIAL TEMPERATURE RANGE D0 RS D1 D2 D3 D4 INDEX GND D5 PIN CONFIGURATION 32 31 30 29 28 27 26 25 D6 1 24 D7 2 23 WCLK DNC(1) 3 22 VCC DNC(1) 4 21 VCC GND 5 20 Q0 REN 6 19 Q1 RCLK 7 18 Q2 GND 8 17 Q3 WEN 9 10 11 12 13 14 15 16 DNC(1) Q4 Q5 Q6 FF Q7 OE EF 6161 drw02 NOTE: 1. DNC = Do Not Connect. TQFP (PR32-1, order code: PF) TOP VIEW PIN DESCRIPTIONS Symbol D0-D7 Name I/O EF Data Inputs Empty Flag I O FF Full Flag O OE Output Enable I Q0-Q7 RCLK REN Data Outputs Read Clock Read Enable O I I RS Reset I WCLK WEN Write Clock Write Enable I I V CC GND Power Ground I I Description Data inputs for a 8-bit bus. When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK. When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO is not full. FF is synchronized to WCLK. When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance state. Data outputs for a 8-bit bus. Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN is asserted. When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data will not be read from the FIFO if the EF is LOW. When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF goes HIGH, and EF goes LOW. A Reset is required before an initial Write after power-up. Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write Enable is asserted. When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. Data will not be written into the FIFO if the FF is LOW. 3.3V volt power supply. Ground pin. 2 IDT72V10081/11081/12081/13081/14081 3.3V MULTIMEDIA FIFO 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8 ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Industrial –0.5 to +5 Unit V TSTG Storage Temperature –55 to +125 °C IOUT DC Output Current –50 to +50 mA INDUSTRIAL TEMPERATURE RANGE RECOMMENDED OPERATING CONDITIONS Symbol VCC GND VIH VIL TA NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminal only. Parameter Min. Typ. Supply Voltage Industrial Supply Voltage Input High Voltage Industrial Input Low Voltage Industrial Operating Temperature Industrial 3.0 0 2.0 -0.5 -40 3.3 0 — — — Max. Unit 3.6 0 5.5 0.8 85 V V V V °C DC ELECTRICAL CHARACTERISTICS (Industrial: VCC = 3.3V ± 0.3V, TA = -40°C to +85°C) IDT72V10081 IDT72V11081 IDT72V12081 IDT72V13081 IDT72V14081 Industrial tCLK = 15 ns Symbol Min. Typ. Max. Unit Input Leakage Current (Any Input) –1 — 1 µA ILO Output Leakage Current –10 — 10 µA VOH Output Logic “1” Voltage, IOH = –2mA 2.4 — — V VOL Output Logic “0” Voltage, IOL = 8mA — — 0.4 V ICC1 Active Power Supply Current — — 20 mA ICC2(3,6) Standby Current — — 5 mA ILI (1) (2) (3,4,5) Parameter NOTES: 1. Measurements with 0.4 ≤ VIN ≤ VCC. 2. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC. 3. Tested with outputs disabled (IOUT = 0). 4. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz. 5. Typical ICC1 = 0.17 + 0.48*fS + 0.02*CL*fS (in mA) with VCC = 3.3V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF). 6. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz. CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol CIN(2) Parameter Input Capacitance Conditions VIN = 0V Max. 10 Unit pF COUT(1,2) Output Capacitance VOUT = 0V 10 pF NOTES: 1. With output deselected (OE ≥ VIH). 2. Characterized values, not currently tested. 3 IDT72V10081/11081/12081/13081/14081 3.3V MULTIMEDIA FIFO 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8 INDUSTRIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS(1) (Industrial: VCC = 3.3 ±0.3V, TA = -40°C to + 85°C) Industrial IDT72V10081L15 IDT72V11081L15 IDT72V12081L15 IDT72V13081L15 IDT72V14081L15 Symbol fS Parameter Clock Cycle Frequency Min. — Max. 66.7 Unit MHz tA Data Access Time 2 10 ns tCLK Clock Cycle Time 15 — ns tCLKH Clock High Time 6 — ns tCLKL Clock Low Time 6 — ns tDS Data Setup Time 4 — ns tDH Data Hold Time 1 — ns tENS Enable Setup Time 4 — ns tENH Enable Hold Time 1 — ns tRS Reset Pulse Width(1) 15 — ns tRSS Reset Setup Time 10 — ns tRSR Reset Recovery Time 10 — ns tRSF Reset to Flag and Output Time — 15 ns tOLZ Output Enable to Output in Low-Z(2) 0 — ns tOE Output Enable to Output Valid 3 8 ns tOHZ Output Enable to Output in High-Z(2) 3 8 ns tWFF Write Clock to Full Flag — 10 ns tREF Read Clock to Empty Flag — 10 ns tSKEW1 Skew time between Read Clock & Write Clock for Empty Flag &Full Flag 6 — ns NOTES: 1. Pulse widths less than minimum values are not allowed. 2. Values guaranteed by design, not currently tested. 3.3V 330Ω D.U.T. 510Ω AC TEST CONDITIONS In Pulse Levels 30pF* GND to 3.0V 6161 drw03 Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels Output Load 1.5V or equivalent circuit See Figure 1 Figure 1. Output Load *Includes jig and scope capacitances. 4 IDT72V10081/11081/12081/13081/14081 3.3V MULTIMEDIA FIFO 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8 INDUSTRIAL TEMPERATURE RANGE READ ENABLES (REN) When both Read Enable (REN) is LOW, data is read from the FIFO array to the output register on the LOW-to-HIGH transition of the Read Clock (RCLK). When Read Enable (REN) is HIGH, the output register holds the previous data and no new data is allowed to be loaded into the register. When all the data has been read from the FIFO, the Empty Flag (EF) will go LOW, inhibiting further read operations. Once a valid write operation has been accomplished, the Empty Flag (EF) will go HIGH after tREF and a valid read can begin. The Read Enable (REN) is ignored when the FIFO is empty. SIGNAL DESCRIPTIONS INPUTS DATA IN (D0 - D7) Data inputs for 8-bit wide data. CONTROLS RESET (RS) Reset is accomplished whenever the Reset (RS) input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is required after power-up before a write operation can take place. The Full Flag (FF) will be reset to HIGH after tRSF. The Empty Flag (EF) will be reset to LOW after tRSF. During reset, the output register is initialized to all zeros. OUTPUT ENABLE (OE) When Output Enable (OE) is enabled (LOW), the parallel output buffers receive data from the output register. When Output Enable (OE) is disabled (HIGH), the Q output data bus is in a high-impedance state. WRITE CLOCK (WCLK) A write cycle is initiated on the LOW-to-HIGH transition of the Write Clock (WCLK). Data setup and hold times must be met in respect to the LOW-to-HIGH transition of the Write Clock (WCLK). The Full Flag (FF) is synchronized with respect to the LOW-to-HIGH transition of the Write Clock (WCLK). The Write and Read clocks can be asynchronous or coincident. OUTPUTS FULL FLAG (FF) The Full Flag (FF) will go LOW, inhibiting further write operation, when the device is full. If no reads are performed after Reset (RS), the Full Flag (FF) will go LOW after 256 writes for the IDT72V10081, 512 writes for the IDT72V11081, 1,024 writes for the IDT72V12081, 2,048 writes for the IDT72V13081 and 4,096 writes for the IDT72V14081. The Full Flag (FF) is synchronized with respect to the LOW-to-HIGH transition of the Write Clock (WCLK). WRITE ENABLE (WEN) When Write Enable (WEN) is low, data can be loaded into the input register and FIFO array on the LOW-to-HIGH transition of every Write Clock (WCLK). Data is stored in the FIFO array sequentially and independently of any on-going read operation. To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, the Full Flag (FF) will go HIGH after tWFF, allowing a valid write to begin. Write Enable (WEN) is ignored when the FIFO is full. EMPTY FLAG (EF) The Empty Flag (EF) will go LOW, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating the device is empty. The Empty Flag (EF) is synchronized with respect to the LOW-to-HIGH transition of the Read Clock (RCLK). DATA OUTPUTS (Q0 - Q7) Data outputs for a 8-bit wide data. READ CLOCK (RCLK) Data can be read on the outputs on the LOW-to-HIGH transition of the Read Clock (RCLK). The Empty Flag (EF)is synchronized with respect to the LOWto-HIGH transition of the Read Clock (RCLK). The Write and Read clocks can be asynchronous or coincident. 5 IDT72V10081/11081/12081/13081/14081 3.3V MULTIMEDIA FIFO 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8 INDUSTRIAL TEMPERATURE RANGE tRS RS tRSS tRSR tRSS tRSR REN WEN tRSF EF tRSF FF tRSF (1) OE = 1 Q0 - Q7 OE = 0 6161 drw06 NOTES: 1. After reset, the outputs will be LOW if OE = 0 and high-impedance if OE = 1. 2. The clocks (RCLK, WCLK) can be free-running during reset. Figure 2. Reset Timing tCLK tCLKH tCLKL WCLK tDS tDH D0 - D7 DATA IN VALID tENH tENS NO OPERATION WEN tWFF tWFF FF tSKEW1(1) RCLK REN 6161 drw07 NOTE: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge. Figure 3. Write Cycle Timing 6 IDT72V10081/11081/12081/13081/14081 3.3V MULTIMEDIA FIFO 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8 INDUSTRIAL TEMPERATURE RANGE tCLK tCLKL tCLKH RCLK tENS tENH REN NO OPERATION tREF tREF EF tA VALID DATA Q0 - Q7 tOLZ tOHZ tOE OE tSKEW1(1) WCLK WEN 6161 drw08 NOTE: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then EF may not change state until the next RCLK edge. Figure 4. Read Cycle Timing WCLK tDS D1 D0 - D 7 D2 D3 D0 (First Valid Write) tENS WEN (1) tFRL tSKEW1 RCLK tREF EF tENS REN tA tA D0 Q0 - Q 7 tOLZ D1 tOE OE 6161 drw09 NOTE: 1. When tSKEW1 ≥ minimum specification, tFRL = tCLK + tSKEW1 When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1 The Latency Timings apply only at the Empty Boundary (EF = LOW). Figure 5. First Data Word Latency Timing 7 IDT72V10081/11081/12081/13081/14081 3.3V MULTIMEDIA FIFO 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8 INDUSTRIAL TEMPERATURE RANGE NO WRITE NO WRITE NO WRITE WCLK tSKEW1 tSKEW1 tDS D 0 - D7 tWFF tWFF tWFF FF (1) tENS tENH tENS WEN RCLK tENH tENS REN OE LOW tENS tENH tA tA Q0 - Q7 DATA READ DATA IN OUTPUT REGISTER NEXT DATA READ 6161 drw10 Figure 6. Full Flag Timing WCLK tDS tDS DATA WRITE 1 D0 - D7 tENS DATA WRITE 2 tENH tENS tENH WEN (1) tSKEW1 (1) tFRL tSKEW1 tFFL RCLK tREF tREF tREF EF REN OE LOW tA Q0 - Q7 DATA READ DATA IN OUTPUT REGISTER 6161 drw11 NOTE: 1. When tSKEW1 ≥ minimum specification, tFRL = tCLK + tSKEW1 When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1 The Latency Timings apply only at the Empty Boundary (EF = LOW). Figure 7. Empty Flag Timing 8 ORDERING INFORMATION IDT XXXXX Device Type X Power XX Speed X Package X Process/ Temperature Range I Industrial (-40°C to +85°C) PF Plastic Thin Quad Flatpack (TQFP, PR32-1) 15 Industrial L Low Power 72V10081 72V11081 72V12081 72V13081 72V14081 256 x 8 512 x 8 1,024 x 8 2,048 x 8 4,096 x 8 Clock Cycle Time (tCLK) Speed in Nanoseconds 3.3V Multimedia FIFO 3.3V Multimedia FIFO 3.3V Multimedia FIFO 3.3V Multimedia FIFO 3.3V Multimedia FIFO 6161 drw18 DATASHEET DOCUMENT HISTORY 11/17/2003 pg. 1. CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 9 for Tech Support: 408-330-1753 email: [email protected]