Integrated Device Technology, Inc. FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS IDT74FCT16601AT/CT/ET IDT74FCT162601AT/CT/ET PRODUCT PREVIEW bit registered transceivers are built using advanced dual metal CMOS technology. These high-speed, low-power 18-bit reg• Common features: istered bus transceivers combine D-type latches and D-type – 0.5 MICRON CMOS Technology flip-flops to allow data flow in either direction in a transparent, – High-speed, low-power CMOS replacement for latched or clocked mode. Each direction has an independent ABT functions latch enable, an independent clock with a clock enable, and an – Typical tSK(o) (Output Skew) < 250ps independent output enable. The package is organized with a – Low input and output leakage ≤1µA (max.) flow-through signal pin organization to ease board layout. All – ESD > 2000V per MIL-STD-883, Method 3015; inputs are designed with hysteresis for improved noise mar> 200V using machine model (C = 200pF, R = 0) gin. – Packages include 25 mil pitch SSOP, 19.6 mil pitch This transceiver is ideally suited for high speed memory TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack interfaces which utilize high speed synchronous writes, by – Extended commercial range of -40°C to +85°C clocking the data into a high speed register. Reads can then – VCC = 5V ±10% be performed in a transparent or latched mode utilizing the • Features for FCT16601AT/CT/ET: same transceiver. – High drive outputs (-32mA IOH, 64mA IOL) The FCT16601AT/CT/ET are ideally suited for driving – Power off disable outputs permit “live insertion” high-capacitance loads and low-impedance backplanes. The – Typical VOLP (Output Ground Bounce) < 1.0V at output buffers are designed with power off disable capability VCC = 5V, TA = 25°C to allow "live insertion" of boards when used as backplane • Features for FCT162601AT/CT/ET: drivers. – Balanced Output Drivers: ±24mA The FCT162601AT/CT/ET have balanced output drive – Reduced system switching noise with current limiting resistors. This offers low ground bounce, – Typical VOLP (Output Ground Bounce) < 0.6V at minimal undershoot, and controlled output fall times–reducing VCC = 5V,TA = 25°C the need for external series terminating resistors. The FCT162601AT/CT/ET are plug-in replacements for the DESCRIPTION: FCT16601AT/CT/ET and ABT16601 for on-board bus interThe FCT16601AT/CT/ET and FCT162601AT/CT/ET 18- face applications. FEATURES: W IE V E R P T C FUNCTIONAL BLOCK DIAGRAM OEAB CLKENAB CLKAB LEAB LEBA CLKBA CLKENBA OEBA A1 U 1 56 D 55 2 O 28 R 30 P 29 27 CE 1D C1 CLK 3 54 B1 CE 1D C1 CLK 3247 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. TO 17 OTHER CHANNELS COMMERCIAL TEMPERATURE RANGE 1996 Integrated Device Technology, Inc. AUGUST 1996 5.9 DSC-3247/- 1 IDT74FCT16601AT/CT/ET, 162601AT/CT/ET FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATIONS OEAB 1 56 CLKENAB LEAB 2 55 CLKAB A1 3 54 B1 GND 4 53 GND A2 5 52 B2 6 51 B3 VCC 7 50 VCC A4 8 49 B4 A5 9 48 B5 A6 10 47 B6 GND 11 46 GND A7 12 45 B7 A8 13 44 B8 A9 B9 A10 14 SO56-1 43 SO56-2 15 SO56-3 42 A11 16 41 B11 A12 17 40 B12 GND 18 39 GND A13 19 38 B13 A14 20 37 B14 A15 21 36 B15 VCC 22 35 VCC A16 23 34 B16 A17 24 33 B17 GND 25 32 GND A18 26 31 B18 OEBA 27 30 CLKBA LEBA 28 29 CLKENBA PIN DESCRIPTION Pin Names OEAB OEBA mA DC Output Current °C –60 to +120 IE CAPACITANCE (TA = +25°C, f = 1.0MHz) V Symbol Parameter(1) CIN Input Capacitance CI/O I/O Capacitance E Conditions VIN = 0V Typ. 3.5 VOUT = 0V 3.5 R Max. Unit 6.0 pF 8.0 NOTE: 1. This parameter is measured at characterization but not tested. pF 3247 lnk 04 P T C U D O 3247 drw 02 P Description A-to-B Output Enable Input (Active LOW) A-to-B Latch Enable Input LEBA B-to-A Latch Enable Input CLKAB A-to-B Clock Input CLKBA B-to-A Clock Input Ax A-to-B Data Inputs or B-to-A 3-State Outputs Bx B-to-A Data Inputs or A-to-B 3-State Outputs FUNCTION TABLE(1,4) CLKENAB OEAB Inputs LEAB CLKAB A Outputs B X H X X X Z X L H X L L X L H X H H H L L X X B0(2) L L L ↑ L L L L L ↑ H H L L L L X B0(2) L L L H X B0(3) NOTES: 3247 tbl 02 1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA and CLKBA. 2. Output level before the indicated steady-state input conditions were established. 3. Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. 4. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-impedance ↑ = LOW-to-HIGH Transition B-to-A Output Enable Input (Active LOW) LEAB CLKENAB CLKENBA I OUT V W B10 R Unit V 3247 lnk 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXXT Output and I/O terminals. 3. Output and I/O terminals for FCT162XXXT. A3 SSOP/ TSSOP/TVSOP TOP VIEW Symbol Description Max. VTERM(2) Terminal Voltage with Respect to –0.5 to +7.0 GND –0.5 to VTERM(3) Terminal Voltage with Respect to GND VCC +0.5 TSTG Storage Temperature –65 to +150 A to B Clock Enable Input B to A Clock Enable Input 3247 tbl 01 5.9 2 IDT74FCT16601AT/CT/ET, 162601AT/CT/ET FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = –40°C to +85°C, VCC = 5.0V ± 10% Parameter Input HIGH Level Test Conditions(1) Guaranteed Logic HIGH Level VIL Input LOW Level II H Input HIGH Current (Input pins) Symbol VIH Min. 2.0 Typ.(2) — Max. Guaranteed Logic LOW Level — — 0.8 V VCC = Max. — — ±1 µA — — ±1 VI = VCC Input HIGH Current (I/O pins) II L Input LOW Current (Input pins) VI = GND Input LOW Current (I/O pins) I OZH High Impedance Output Current I OZL (3-State Output pins) VIK Clamp Diode Voltage VCC = Max. VO = 2.7V VO = 0.5V I OS Short Circuit Current VCC = Max., VO = VH Input Hysteresis I CCL I CCH I CCZ Quiescent Power Supply Current — — ±1 — — ±1 — — ±1 IE — VCC = Max., VIN = GND or VCC — ±1 –1.2 V –80 –140 –225 mA — 100 — mV — 5 500 µA V E OUTPUT DRIVE CHARACTERISTICS FOR FCT16601T µA –0.7 W GND (3) Unit V — — VCC = Min., IIN = –18mA — 3247 lnk 05 Symbol IO Parameter Output Drive Current Test Conditions(1) VCC = Max., VO = 2.5V(3) Min. –50 Typ.(2) — Max. –180 Unit mA VOH Output HIGH Voltage VCC = Min. I OH = –3mA 2.5 3.5 — V I OH = –15mA 2.4 3.5 — V I OH = –32mA (4) 2.0 3.0 — V — 0.2 0.55 V — — ±1 µA R VIN = VIH or V IL VOL Output LOW Voltage I OFF Input/Output Power Off Leakage P T VCC = Min. I OL = 64mA VIN = VIH or V IL VCC = 0V, VIN or V O ≤ 4.5V C U 3247 lnk 06 OUTPUT DRIVE CHARACTERISTICS FOR FCT162601T Symbol I ODL Parameter Output LOW Current I ODH Output HIGH Current VOH Output HIGH Voltage VOL Output LOW Voltage P R O D Test Conditions(1) VCC = 5V, VIN = V IH or VIL, VOUT = 1.5V (3) Min. 60 Typ.(2) 115 Max. 200 Unit mA VCC = 5V, VIN = V IH or V IL, VOUT = 1.5V(3) –60 –115 –200 mA VCC = Min. VIN = VIH or V IL VCC = Min. VIN = VIH or V IL I OH = –24mA 2.4 3.3 — V I OL = 24mA — 0.3 0.55 V NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25°C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. Duration of the condition can not exceed one second. 5.9 3247 lnk 07 3 IDT74FCT16601AT/CT/ET, 162601AT/CT/ET FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS COMMERCIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS Symbol Test Conditions(1) Parameter ∆ICC Quiescent Power Supply Current TTL Inputs HIGH ICCD Dynamic Power Supply Current(4) IC Total Power Supply Current(6) VCC = Max. VIN = 3.4V(3) Min. Typ.(2) Max. Unit — 0.5 1.5 mA VCC = Max., Outputs Open GND One Input Toggling 50% Duty Cycle VIN = VCC VIN = GND — 75 120 µA/ MHz VCC = Max., Outputs Open fCP = 10MHz (CLKBA) 50% Duty Cycle OEAB = VCC OEBA = GND LEAB = GND CLKENBA = GND One Bit Toggling fi = 5MHz 50% Duty Cycle VIN = VCC VIN = GND — 0.8 1.7 mA VIN = 3.4V VIN = GND — 1.3 3.2 VCC = Max., Outputs Open fCP = 10MHz (CLKBA) 50% Duty Cycle OEAB = VCC OEBA = GND LEAB = GND CLKENBA = GND Eighteen Bits Toggling fi = 2.5MHz 50% Duty Cycle VIN = VCC VIN = GND — 3.8 6.5(5) — 8.5 20.8(5) OEAB = VCC OEBA = W IE E V VIN = 3.4V VIN = GND R P NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi 3247 tbl 09 T C U D O R P 5.9 4 IDT74FCT16601AT/CT/ET, 162601AT/CT/ET FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS COMMERCIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE Symbol FCT16601CT/ FCT16601ET/ FCT162601CT FCT162601ET Condition(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit fMAX CLKAB or CLKBA frequency(4) CL = 50pF — 150 — 150 — 150 MHz tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU Propagation Delay RL = 500Ω Ax to Bx or Bx to Ax Propagation Delay LEBA to Ax, LEAB to Bx Propagation Delay CLKBA to Ax, CLKAB to Bx Output Enable Time OEBA to Ax, OEAB to Bx Output Disable Time OEBA to Ax, OEAB to Bx Set-up Time, HIGH or LOW Ax to CLKAB, Bx to CLKBA Hold Time HIGH or LOW Ax after CLKAB, Bx after CLKBA Set-up Time HIGH or LOW Clock LOW 1.5 4.9 1.5 4.4 1.5 3.8 ns 1.5 5.2 1.5 4.7 1.5 4.2 ns 1.5 4.7 1.5 4.5 1.5 4.2 ns 1.5 5.8 1.5 5.3 1.5 4.8 ns 1.5 6.2 1.5 5.7 1.5 5.2 ns 4.0 — 3.0 — 2.4 — ns 0 — 0 — 0 — ns 1.0 — 1.0 — 1.0 — ns Ax to LEAB, Bx to LEBA 2.5 — V 2.0 — 1.5 — ns 2.0 — 1.5 — 0.5 — ns — 2.5 — 2.0 — ns — 0 — 0 — ns — 2.5 — 2.5 — ns 3.0 — 3.0 — 3.0 — ns — 0.5 — 0.5 — 0.5 tH tSU tH tSU tH Parameter FCT16601AT/ FCT162601AT Clock HIGH Hold Time, HIGH or LOW Ax after LEAB, Bx after LEBA Set-up Time, CLKEN to CLK R 2.5 Hold Time, CKLEN after CLK 0 tW LEAB or LEBA Pulse Width HIGH(4) tW CLKAB or CLKBA Pulse Width HIGH or LOW(4) tSK(o) Output Skew (3) 2.5 T C E P W IE NOTES: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 4. This parameter is guaranteed but not tested. ns 3247 tbl 09 U D O R P 5.9 5 IDT74FCT16601AT/CT/ET, 162601AT/CT/ET FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS SWITCH POSITION TEST CIRCUITS FOR ALL OUTPUTS V CC 500Ω Switch Open Drain Disable Low Closed Enable Low V OUT VIN Pulse Generator Test 7.0V Open All Other Tests D.U.T. 50pF RT 3247 lnk 10 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 500Ω CL 3247 drw 04 SET-UP, HOLD AND RELEASE TIMES DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. 3V 1.5V 0V 3V 1.5V 0V tH tSU tREM tSU 3V 1.5V 0V 3V 1.5V 0V tH W IE V LOW-HIGH-LOW PULSE E 1.5V tW R HIGH-LOW-HIGH PULSE 1.5V P 3247 drw 06 T 3247 drw 05 C PROPAGATION DELAY U D SAME PHASE INPUT TRANSITION tPLH tPHL O OUTPUT R tPLH OPPOSITE PHASE INPUT TRANSITION PULSE WIDTH P tPHL ENABLE AND DISABLE TIMES ENABLE 3V 1.5V 0V DISABLE 3V 1.5V 0V CONTROL INPUT tPZL VOH 1.5V VOL OUTPUT NORMALLY LOW 3V 1.5V 0V SWITCH CLOSED tPLZ tPZH OUTPUT NORMALLY HIGH 3247 drw 07 SWITCH OPEN 3.5V 3.5V 1.5V 0.3V VOL tPHZ 0.3V 1.5V 0V VOH 0V 3247 drw 08 NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns 5.9 6 IDT74FCT16601AT/CT/ET, 162601AT/CT/ET FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT X Temperature Range FCT XXXX X Device Type Package PV PA PF Shrink Small Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) 16601AT Non-Inverting 18-Bit Registered Transceiver 16601CT 16601ET 162601AT 162601CT 162601ET W IE –40°C to +85°C 74 V E R P T C U D O R P 5.9 7