ETC IDT77V500S25PF

IDT77V500
SwitchStarTM ATM Cell Based
1.2Gbps non-blocking
Integrated Switch Controller
◆
One IDT77V500 can manage up to eight IDT77V400's
without derating for larger switch configurations
Industrial temperature range (-40° C to +85° C) is available
Single +3.3V ± 300mV power supply
Available in a 100-pin Thin Plastic Quad Flat Pack (TQFP)
and 144-ball BGA
◆
Single chip controller for IDT77V400 Switching Memory
One IDT77V500 and one IDT77V400 form the core required
for a 1.2Gbps 8 x 8 port non-blocking switch
◆ Supports up to 8192 Virtual Connections (VCs)
◆
Per VC queuing for fairness, with four priorities per VC
available for each output port of the switch
◆
Capable of supporting CBR, VBR, UBR, and ABR (EFCI)
service classes
◆ Low power dissipation
– 430mW (typ.)
◆
Optional header modification operation
◆ Multicasting and Broadcasting capability
◆
Provides congestion management support through EFCI,
CLP, and EPD functionality
◆
System clock cycle times as fast as 25ns (40MHz)
◆ Option available for resolving contention issues between
multiple IDT77V500 configurations
◆
◆
◆
◆
The IDT77V500 ATM Cell Based Switch Controller, when paired with
the IDT77V400 Switching Memory, forms the core control logic and
switch fabric for a 1.2Gbps non-blocking ATM switch. The IDT77V500
manages all of the switch traffic moving through the IDT77V400,
commanding the storage of incoming ATM cells and interpreting and
modifying the cell header information as necessary for data flow through
the switch. It then uses the header information, including priority indicators, to queue and direct the individual cells for transmission out the
appropriate output port of the IDT77V400.
External Interface
for Global Setup
and Control
8-bit Processor//
Call Setup
Manager
Data
IDT77V500
Control
Switch
Controller
(for example,
IDT77V550
IDT79RV3041,
IDT79R36100,
or IDT79RV4640)
Data
IDT77155
155Mbps
PHY
Control
Port 0
Port 0
IDT77155
155Mbps
PHY
IDT77V400
Switching
Memory
IDT77155
155Mbps
PHY
Port 7
Port 7
IDT77155
155Mbps
PHY
,
3607 drw 01
SwitchStar and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 12
 2000 Integrated Device Technology, Inc.
January 30, 2001
DSC 3607/4
IDT77V500
The IDT77V500 utilizes Per Virtual Connection (VC) Queuing to keep
track of each call, and has the capacity to keep track of as many as 8192
individual VC queues. There are four possible priorities available for
each of the assigned outputs of the Switching Memory, and CBR, VBR,
UBR, and ABR-EFCI service classes are supported by the Switch
Controller. Multicasting and broadcasting services are provided,
requiring only the appropriate header information to execute these operations automatically without requiring multiple Switching Memory
entries.
The IDT77V500 also has a mode for managing and transmitting
packetized data, enabling easy transition between packet oriented
networks such as Ethernet and FDDI and ATM cell oriented networks.
The IDT77V500 has an 8-bit Manager Bus interface, MDATA0-7, to a
Call Setup Manager processor for the configuration activity and call
setup operation. When a Call Setup Cell is received by the IDT77V400,
the cell is directed to a specified output port and the payload processed
by the Call Setup Manager. The new Virtual Connection (VC) is then
established in the Queue Manager of the IDT77V500, with all operations
executed across the 8-bit Manager Bus. Subsequent cells of that particular VC are then prioritized and directed by the Switch Controller as they
are received by the IDT77V400; no further interaction with the Call
Manager processor is required for ongoing queue and cell management.
The IDT77V500 supports a major subset of the available commands
and configurations of the IDT77V400 Switching Memory. Please refer to
the SwitchStar User Manual for additional feature details and implementation information.
The IDT77V500 is fully 3.3V LVTTL compatible, and is packaged in
an 100-pin Thin Plastic Quad Flatpack (TQFP) and 144-ball BGA.
!
!
MD/C
MR/W
MSTRB
Call
Setup
Manager
State
Machine
MDATA0-7
OFRM0-7
CBRCLK2
CBRCLK3
SCLK
RESETI
Output
Service
and
Arbitration
Control
Logic
SFRM
2
Queue Manager
Output Queues
and
Link Registers
SCLK1
Reset1
RESETO
2
Switching Memory Interface
32
IOD0-31
6
CMD0-5
2
3607 drw 02
CRCERR
1
SCLK and Reset are inputs to all blocks.
2
Outputs are always enabled (active).
2 of 12
January 30, 2001
IDT77V500
"
" !
!
NC
NC
MDATA6
MDATA5
MDATA4
VSS
VCC
MDATA3
MDATA2
MDATA1
MDATA0
VCC
VCC
VCC
CRCERR
IOD0
IOD1
IOD2
IOD3
VCC
VSS
IOD4
IOD5
IOD6
NC
All Vcc pins must be connected to power supply. All Vss pins must be connected to ground supply. Package body is approximately 14mm x 14mm
x 1.4mm.
Index
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
MDATA7
MD/C
MR/W
MSTRB
NC
NC
CMD5
CMD4
CMD3
VSS
VCC
CMD2
CMD1
CMD0
NC
NC
RESETI
SCLK
RESETO
CBRCLK2
NC
CBRCLK3
NC
SFRM
OFRM7
1
75
2
74
3
4
73
72
5
71
6
7
70
69
8
68
9
NC
NC
IOD7
IOD8
IOD9
IOD10
IOD11
VCC
VSS
IOD12
IOD13
IOD14
IOD15
IOD16
IOD17
IOD18
IOD19
VCC
VSS
IOD20
IOD21
IOD22
IOD23
NC
NC
67
10
66
IDT77V500PF
PN100-11
11
65
12
64
100-Pin TQFP
Top View2
13
14
63
62
15
16
61
60
17
59
18
19
58
57
20
56
21
55
22
54
23
53
24
25
52
NC
NC
OFRM6
OFRM5
VSS
VCC
OFRM4
OFRM3
OFRM2
OFRM1
OFRM0
VSS
VSS
VSS
IOD31
IOD30
IOD29
IOD28
VSS
VCC
IOD27
IOD26
IOD25
IOD24
NC
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
,
3607 drw 03
1
This package code is used to reference the package diagram.
This text does not indicate orientation of the actual part marking.
2
#$$%
&
1
2
3
4
5
6
7
8
9
10
11
A
VCC
NC
OFRM4 OFRM7 CBRCLK2 SCLK
B
VSS
OFRM2 OFRM3 NC
NC
VCC
CMD4
NC
MDATA7 NC
A
VSS
CMD5
MSTRB
MD/C
B
C
NC
NC
NC
OFRM5 SFRM
NC
NC
CMD1 CMD3
MR/W
MDATA5 NC
C
D
NC
NC
NC
OFRM1 OFRM6
NC
NC
CMD0 NC
NC
VSS
D
E
NC
NC
NC
NC
OFRM0
VCC
NC
NC
NC
MDATA3 MDATA1 NC
F
NC
NC
VSS
VSS
NC
NC
CMD2
VCC
MDATA2 MDATA0 NC
NC
F
G
VCC
VSS
NC
NC
IOD28
IOD19
CRCERR VCC
NC
NC
NC
NC
G
H
IOD31 IOD30
NC
IOD27
VCC
IOD12
IOD8
VCC
NC
NC
NC
NC
H
J
IOD29 NC
VSS
IOD24
IOD17
IOD14
VCC
IOD6
NC
IOD0
NC
IOD1
J
K
NC
IOD26
IOD25
IOD20
NC
IOD15
IOD13
VSS
VCC
IOD3
IOD2
NC
K
L
NC
NC
IOD22
VSS
NC
NC
NC
IOD10 IOD7
NC
VSS
IOD4
L
M
NC
NC
IOD23
IOD21
IOD18
IOD16
NC
IOD11 IOD9
NC
NC
IOD5
M
1
2
3
4
5
6
7
8
10
11
12
CBRCLK3 RESETO RESETI
3 of 12
9
12
MDATA6
MDATA4
E
January 30, 2001
IDT77V500
'""
18
SCLK
I
System clock: Refererence clock input for all synchronous pins of the IDT77V500 Switch Controller. All synchronous signals are referenced to the rising edge of SCLK.
22,20
CBRCLK3,
CBRCLK2
I
CBR Clocks 3 and 2: External clock signals used when Constant Bit Rate (CBR) Service classes are utilized.
These clock signals correspond to Output Port priorities 3 and 2 respectively and are used to determine the
constant bit rate for the controller. Priority 3 is the highest priority. If CBR mode is not used these pins should
be pulled up to Vcc with a resistor with a recommended value of 5K ohm or less.
86
CRCERR
I
Cyclical Redundancy Check Error: Synchronous input on the rising edge of SCLK. CRCERR asserted LOW
by the IDT77V400 Switching Memory during a store operation indicates that a HEC CRC error has occured in
the cell header.
2
MD/C
I
Manager Control: Selects the data or control registers of the IDT77V500 for the Manager Bus Operation. MD/
C asserted HIGH selects the data registers, and MD/C LOW selects the command/status registers of the
IDT77V500.
3
MR/W
I
Manager Read/Write: MR/W LOW will write the data on the Manager Bus into the registers selected by the
MD/C input. In write mode (MR/W LOW) the data on MDATA0-7 is written synchronously with respect to the
rising edge of MSTRB; in read mode (MR/W HIGH) the data is accessed asynchronously.
4
MSTRB
I
Manager Strobe: Input which acts as a clock for the Manager Bus (MDATA0-7). Other Manager Bus inputs are
synchronous to the rising edge of MSTRB during write operations (MR/W LOW) and must meet the specified
Setup and Hold parameters. MSTRB performs an asynchronous Output Enable function when a read operation (MR/W HIGH) is executed on the Manager Bus. When MSTRB is LOW and MR/W is HIGH (Read Mode)
the Manager Bus is enabled in output mode and the contents of the IDT77V500 registers (determined by the
MD/C input) are available to be read on MDATA0-7.
17
RESETI
I
Reset Input: When asserted HIGH, this signal asynchronously initiates the internal reset sequence of the
IDT77V500.
19
RESETO
O
Reset Output: Asserted HIGH upon initiating the reset of the IDT77V500 (RESETI HIGH). In multiple
IDT77V500 configurations, this output is connected to the RESETI input of the next controller in the chain.
RESETO will remain HIGH until a START command is received from the Call Setup Manager.
7-9, 12-14
CMD0-5
O
Command Bus: Synchronized with SCLK, instructions to be executed by the IDT77V400 Switching memory
are output by the IDT77V500 on this 6-bit bus.
24
SFRM
O
Synchronize Output Frame: Synchronous output used when multiple IDT77V500's contend for a common bus.
The Master IDT77V500 generates this signal which then drives the OFRM0 input of the other IDT77V500s.
40-43, 46-49, 53-56, 59-66, IOD0-31
69-73, 77-79, 82-85
I/O
Control Data Bus: Synchronous with SCLK and one cycle latent to the Command Bus (CMD0-5). Used for
transfer of the header bytes, configuration register, error and status registers, and the cell memory address
between the IDT77V500 and the IDT77V400 Switching Memory.
1, 90-93, 96-98
MDATA0-7
I/O
Manager Bus: Communications between the Call Setup Manager and the IDT77V500 occur over this 8-bit bidirectional bus. MD/C, MR/W, and MSTRB dtermine the mode and data type transferred across the MDATA
bus. Write operations are synchronous with respect to MSTRB, while MDATA behaves asynchronously for
read operations.
25, 28-29, 32-35, 36
OFRM1-7
OFRM0
I/O
Output Frame: Asynchronous input pins used by the IDT77V500 to detect when the next cell can be loaded to
the specified IDT77V400 output port 0 through 7. When in multiple IDT77V500 configurations, the OFRM1-7
are redefined as CBUS1-7 for arbitration. OFRM0 is always an input pin (There is no CBUS0).
11, 31, 45, 58, 68, 81, 8789, 94
VCC
Power
Power Supply (+3.3V ±300mV)
10, 30, 37-39, 44, 57, 67,
80, 95
VSS
Power
Ground
5-6, 15-16, 21, 23, 26-27,
50-52, 74-76, 99-100
NC
____
No Connect
()"
A6
SCLK
I
System clock: Refererence clock input for all synchronous pins of the IDT77V500 Switch Controller. All synchronous signals are referenced to the rising edge of SCLK.
4 of 12
January 30, 2001
IDT77V500
B5, A5
CBRCLK3,
CBRCLK2
I
CBR Clocks 3 and 2: External clock signals used when Constant Bit Rate (CBR) Service classes are utilized.
These clock signals correspond to Output Port priorities 3 and 2 respectively and are used to determine the
constant bit rate for the controller. Priority 3 is the highest priority. If CBR mode is not used these pins should
be pulled up to Vcc with a resistor with a recommended value of 5K ohm or less.
G7
CRCERR
I
Cyclical Redundancy Check Error: Synchronous input on the rising edge of SCLK. CRCERR asserted LOW
by the IDT77V400 Switching Memory during a store operation indicates that a HEC CRC error has occured in
the cell header.
B11
MD/C
I
Manager Control: Selects the data or control registers of the IDT77V500 for the Manager Bus Operation. MD/
C asserted HIGH selects the data registers, and MD/C LOW selects the command/status registers of the
IDT77V500.
C10
MR/W
I
Manager Read/Write: MR/W LOW will write the data on the Manager Bus into the registers selected by the
MD/C input. In write mode (MR/W LOW) the data on MDATA0-7 is written synchronously with respect to the
rising edge of MSTRB; in read mode (MR/W HIGH) the data is accessed asynchronously.
B10
MSTRB
I
Manager Strobe: Input which acts as a clock for the Manager Bus (MDATA0-7). Other Manager Bus inputs are
synchronous to the rising edge of MSTRB during write operations (MR/W LOW) and must meet the specified
Setup and Hold parameters. MSTRB performs an asynchronous Output Enable function when a read operation (MR/W HIGH) is executed on the Manager Bus. When MSTRB is LOW and MR/W is HIGH (Read Mode)
the Manager Bus is enabled in output mode and the contents of the IDT77V500 registers (determined by the
MD/C input) are available to be read on MDATA0-7.
B7
RESETI
I
Reset Input: When asserted HIGH, this signal asynchronously initiates the internal reset sequence of the
IDT77V500.
B6
RESETO
O
Reset Output: Asserted HIGH upon initiating the reset of the IDT77V500 (RESETI HIGH). In multiple
IDT77V500 configurations, this output is connected to the RESETI input of the next controller in the chain.
RESETO will remain HIGH until a START command is received from the Call Setup Manager.
D8, C8, F7, C9, A9, B9
CMD0-5
O
Command Bus: Synchronized with SCLK, instructions to be executed by the IDT77V400 Switching memory
are output by the IDT77V500 on this 6-bit bus.
C5
SFRM
O
Synchronize Output Frame: Synchronous output used when multiple IDT77V500's contend for a common bus.
The Master IDT77V500 generates this signal which then drives the OFRM0 input of the other IDT77V500s.
J10, J12, K11, K10, L12,
IOD0-31
M12, J8, L9, H7, M9, L8,
M8, H6, K7, J6, K6, M6, J5,
M5, G6, K4, M4, L3, M3, J4,
K3, K2, H4, G5, J1, H2, H1
I/O
Control Data Bus: Synchronous with SCLK and one cycle latent to the Command Bus (CMD0-5). Used for
transfer of the header bytes, configuration register, error and status registers, and the cell memory address
between the IDT77V500 and the IDT77V400 Switching Memory.
F10, E11, F9, E10, D12,
C11, B12, A11
MDATA0-7
I/O
Manager Bus: Communications between the Call Setup Manager and the IDT77V500 occur over this 8-bit bidirectional bus. MD/C, MR/W, and MSTRB dtermine the mode and data type transferred across the MDATA
bus. Write operations are synchronous with respect to MSTRB, while MDATA behaves asynchronously for
read operations.
D4, B2, B3, A3, C4, D5,
A4, E5
OFRM1-7
OFRM0
I/O
Output Frame: Asynchronous input pins used by the IDT77V500 to detect when the next cell can be loaded to
the specified IDT77V400 output port 0 through 7. When in multiple IDT77V500 configurations, the OFRM1-7
are redefined as CBUS1-7 for arbitration. OFRM0 is always an input pin (There is no CBUS0).
A1, A8, E6, F8, G1, G8,
H5, H8, J7, K9
VCC
Power
Power Supply (+3.3V ±300mV)
B1, B8, D11, F3, F4, G2,
J3, K8, L4, L11
VSS
Power
Ground
____
No Connect
A2, A7, A10, A12, B4, C1, NC
C2, C3, C6, C7, C12, D1,
D2, D3, D6, D7, D9, D10,
E1, E2, E3, E4, E7, E8, E9,
E12, F1, F2, F5, F6, F11,
F12, G3, G4, G9, G10,
G11, G12, H3, H9, H10,
H11, H12, J2, J9, J11, K1,
K5, K12, L1, L2, L5, L6, L7,
L10, M1, M2, M7, M10, M11
5 of 12
January 30, 2001
IDT77V500
! !
"!
VCC
Supply Voltage
3.0
3.3
3.6
V
Terminal Voltage with
Respect to GND
-0.5 to +3.9
VSS
Ground
0
0
0
V
TBIAS
Temperature Under Bias
-55 to +125
°C
____
VCC+0.3V1, 2
V
TSTG
StorageTemperature
-55 to +125
°C
____
0.8
V
VTERM2
DC Output Current
IOUT
50
V
VIH
VIL
mA
!"#
"# $ %&'
(
'
() *+, 0V
3.3V ± 0.3V
Industrial
0V
3.3V ± 0.3V
-40°C to +85°C
"! CIN
Input Capacitance
VIN = 3dV
9
pF
COUT3
Output Capacitance
VOUT = 3dV
10
pF
1.
Commercial 0°C to +70°C
1.
Input Low Voltage
VTERM must not exceed Vcc + 0.3V or Vss – 0.3V.
2.
VTERM must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to ≤ 20mA for the period of VTERM ≥ Vcc + 0.3V.
3.
VIL≥ -1.5V for pulse width less than 10ns.
Stresses greater than those listed in this table may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2.
VTERM must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to ≤ 20mA for the period of VTERM ≥ Vcc + 0.3V.
-0.51,3
1.
1.
Input High Voltage 2.0
These parameters are determined by device characterization, but are not production
tested.
2.
3dV references the interpolated capacitance when the input and output switch from 0V
to 3V or from 3V to 0V.
3.
COUT also references CI/O.
This is the parameter TA.
-
-
. /
/ .
. 0&0 1 '&0)
'&0)
##$%%
Min
Max
|ILI|
Input Leakage Current
Vcc = 3.6V, VIN = 0V to Vcc
___
10
µA
|ILO|1
Output Leakage Current
RESTI = VIH, VOUT = 0V to Vcc
___
10
µA
VOL
Output Low Voltage
IOL = +4mA
___
0.4
V
VOH
Output High Voltage
IOH = -4mA
2.4
___
V
1.
For MDATA, IOD, and OFRM pins only.
-
-
. /
/ .
. 0&0 1 '&0)
##$%%&$'&#(
##$%%&$'&#(
Min
Max
Min
Max
ICC
Operating Current
Vcc = 3.6V, RESTI = VIL, f = fMAX1
130
200
130
175
mA
IOCR
Reset Current
Vcc = 3.6V, RESTI = VIH, f = fMAX1
150
325
150
300
mA
1.
At f = fmax SCLK is cycling at maximum frequency and all inputs are cycling at 1/tCYC1, using AC input levels of VSS to 3.0V.
)*
*
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
VSS to 3.0V
3ns Max.
1.5V
1.5V
Figures 1 and 2
3.3V
3.3V
590Ω
590Ω
DATAOUT
DATAOUT
435Ω
50pF
3607 drw 04
Figure 1 AC Output Test Load
6 of 12
435Ω
5pF*
3607 drw 05
Figure 2 Output Test Load
(for High-Impedance parameters) *Including scope and jig.
January 30, 2001
IDT77V500
)+
,-
,
!
.
.
%
/010210&
##$%%&$ ) ##$%%&# ) Min.
Max.
Min.
Max.
tCYC
System Clock Cycle Time
25
—
27
—
ns
tCH
tCL
Systen Clock High Time
System Clock Low Time
10
10
—
—
11
11
—
—
ns
ns
tR
tF
Clock Rise Time
Clock Fall Time
—
—
3
3
—
—
3
3
ns
ns
tMCYC
tMCH
Manager Clock Cycle Time
Manager Clock High Time
25
6
—
—
27
7
—
—
ns
ns
tMCL
tSM
Manager Clock Low Time
MD/C Setup Time to MSTRB High
19
10
—
—
20
10
—
—
ns
ns
tHM
tSMRW
MD/C Hold Time after MSTRB High
MR/W Setup Time to MSTRB High
2
10
—
—
2
10
—
—
ns
ns
tHMRW
tSMD
MR/W Hold Time after MSTRB High
MDATA Setup Time to MSTRB High
2
10
—
—
2
10
—
—
ns
ns
tHMD
tSCRC
MDATA Hold Time after MSTRB High
CRCERR Setup Time to SCLK High
2
5
—
—
2
5
—
—
ns
ns
tHCRC
tSIO
CRCERR Hold Time after SCLK High
IOD Setup Time to SCLK High
2
5
—
—
2
5
—
—
ns
ns
tHIO
tOFP
IOD Hold Time after SCLK High
OFRM High Pulse Width
2
5
—
—
2
5
—
—
ns
ns
tCDC
tDCC
SCLK to CMD Valid
CMD Output Hold after SCLK High
—
2
18
—
—
2
20
—
ns
ns
tCDS
tDCS
SCLK to SFRM Valid
SFRM Output Hold after SCLK High
—
2
18
—
—
2
20
—
ns
ns
tCDIO
tDCIO
SCLK to IOD Valid
IOD Output Hold after SCLK High
—
2
18
—
—
2
20
—
ns
ns
tAMD
tOHMD
MSTRB Low to MDATA Valid
MDATA Output Hold after MSTRB High
—
2
18
—
—
2
20
—
ns
ns
tCDOF
tDCOF
SCLK to OFRM/CBUS Valid
OFRM/CBUS Output Hold after SCLK High
—
2
18
—
—
2
20
—
ns
ns
tRSI
tRSO
RESETI High Pulse Width1
RESETO High after RESETI High
8
—
—
2
8
—
—
2
tCYC
tCYC
tCDR
tCKHZ
SCLK to RESETO Valid
SCLK High to Output High-Z2
—
—
18
10
—
—
20
10
ns
ns
tCKLZ
tCYC3
SCLK High to Output Low-Z2
CBRCLK3 Clock Cycle Time3
2
3
—
—
2
3
—
—
ns
tCYC
tCH3
tCL3
CBRCLK3 Clock High Time3
CBRCLK3 Clock Low Time3
1.2
1.2
—
—
1.2
1.2
—
—
tCYC
tCYC
tCYC2
tCH2
CBRCLK2 Clock Cycle Time3
CBRCLK2 Clock High Time3
3
1.2
—
—
3
1.2
—
—
tCYC
tCYC
tCL2
CBRCLK2 Clock Low Time3
1.2
—
1.2
—
tCYC
1.
RESETI must be held High for 8 SCLK cycles. After RESETI transitions Low, 8191 cycles are required before the Status Acknowledge bits will indicate that the internal reset process in
complete.
2.
Transition is measured +/-200mV from Low or High impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characterization, but is not production
tested.
3.
Cycle units insure that the SCLK recognizes the state of CBRCLK.
7 of 12
January 30, 2001
IDT77V500
!
33- !
This waveform describes the command interaction across the IOD Bus to the IDT77V400 Switching Memory.
tCYC
tCH
tCL
SCLK
CMD0-5
GET
STATUS
tCDIO
tDCC
tCDC
GET 1
STATUS
GET
HEADER ISAM
STORE
ISAM
tSIO
IOD0-31
STATUS
1
STATUS
tCDIO
PUT
HEADER
tHIO
Input Old Header
CRCERR
[ AVAILABLE FOR NEXT COMMAND ]
tDCIO
tDCIO
Output -
Output -
Cell Addr
New Header
[ CRC ERROR = LOW ]
tSCRC tHCRC
3607 drw 06
1
The result of this GET STATUS command is that an ISAM is full and ready to be stored to the Cell Memory of the IDT77V400.
!!*
!!*
*
* * + $,%-
MSb
LSb
5
4
3
2
1
0
GHIx
Get Header from ISAMx2
0
0
1
n3
n3
n3
GST
Get ISAM Status Register Bits
0
1
0
0
1
0
GER
Get Error Register Bits
0
1
0
1
1
0
STEx
Store Cell in ISAMx2 and Edit Buffer in Memory
1
0
0
n3
n3
n3
LDOx
Load Cell from Memory into OSAMx2
1
1
0
n3
n3
n3
PHE
Put new Header in Edit Buffer
1
1
1
1
0
0
PHEC
Put new Header and new CRC byte in Edit Buffer
1
1
1
1
0
1
REF
Refresh Fusion Memory
0
1
0
1
1
1
LDC
Load Configuration Register
1
1
1
0
1
0
OHE
Put new Header in Output Edit Register
1
1
1
1
1
0
OHEC
Put new Header and new CRC byte in Output Edit Register
1
1
1
0
0
1
1.
CMD bus commands not defined in this table are undefined and are not implemented by the IDT77V500.
"x" represents the specific ISAM or OSAM being accessed (IP0-IP7 or OP0-OP7 respectively).
3.
"n" represents the appropriate bit of the binary representation of the ISAM or OSAM being accessed (000 to 111).
2.
.4565*
*
33- !
*,.4
!
SCLK
tOFP
OFRM
OFRM/CBUS
tCDOF
tDCOF
tCDS
tDCS
1
SFRM
3607 drw 07
1
OFRM1-7 become CBUS1-7 (Outputs) during cell bus operations to arbitrate between multiple IDT77V500's.
8 of 12
January 30, 2001
IDT77V500
4
4
!!*
!!*
*
+ ."-
WRSL
Write Service Link Memory
Write into Service Link Memory to initialize scheduled service lists.
03
STAT
Read IDT77V500 status
Reads the internal status of the IDT77V500. Available information includes various
error registers and counts.
07
LDCFG
Load IDT77V400 Configuration Bits Passes configuration information to the IDT77V400.
SUP
Call setup
Writes the appropriate information into an entry of the Per VC Memory to perform the 09
call setup function.
INT
Initialize IDT77V500
Initializes the internal configuration registers of the IDT77V500.
0A
SEL
Select a IDT77V500
Selects the IDT77V500 to be enabled in a multiple device configuration.
0B
START
End of IDT77V500 Initialization
Sets the IDT77V500 into an enabled state after it has been initialized.
0C
CBR
Set up a CBR Scheduler
Sets up a selected output service list in the Constant Bit Rate (CBR) mode.
0D
PARM
Set Parameters
Sets various parameters in the IDT77V500, including the CLP low water mark, the
EFCI low water mark, and the EPD low water mark.
0E
1.
08
Manager Command codes not defined in this table are not to be used.
4
4
.*
*
!
33- !
Write operations, both for Commands and Data, are synchronous to the rising edge of MSTRB. The data placed on the MDATA pins is determined
by the state of the MD/C pin.
tMCYC
tMCL
tMCH
1
MSTRB
MD/C
tSM
tSM
tHM
tSMRW
tSMRW
tHMRW
MR/W
tSMD
tHMD
tOHMD
tOHMD
tAMD
CMDIN
ADDRIN
ADDRIN
MDATA
tAMD
DATAOUT
DATAOUT
DATAOUT
2
Write first
8 ADDR bits
Acknowledge Read
Write CycleRead Command
Write last
8 ADDR bits
Acknowledge Read
DATAOUT
DATAOUT
3
4
Read Byte 0
Acknowledge Read –
Valid Command Acknowledge
Read Byte 1
3607 drw 08
1
The combination of MSTRB Low and MR/W High (Read mode) asynchronously enables the MDATA pins as outputs. That is, data is available to be read one asynchronous tAMD
time after the falling edge of MSTRB if MR/W is High.
2
After the Command is written, the Manager must take MR/W High (Read mode) to wait for a valid Command Acknowledge from the IDT77V500 before proceeding. Reading a High
Bit 7 of the status register under these conditions indicates the command has been acknowledged by the IDT77V500. This may take multiple IDT77V500 SCLK cycles based on possible
higher priority operations that the IDT77V500 must support.
3
A valid Acknowledge from the IDT77V500 is indicated by a High Command Acknowledge bit (Bit 7 of the Status Register).
4
Waveform illustrates first two bytes of data only. Additional bytes may be available based on command used.
4
4
3
!
33- !
Write operations, both for Commands and Data, are synchronous to the rising edge of MSTRB. The data placed on the MDATA pins is determined
by the state of the MD/C pin.
tMCH
MSTRB
T0
tSM
tMCYC
tMCL
2
T12
tHM
tSM
MD/C
tSMRW tHMRW
tSMRW
MR/W
tSMD tHMD
MDATA
DATAIN
tOHMD
tAMD
DATAIN
CMDIN
DATAOUT
DATAOUT
DATAOUT
3
1
Write Data Byte 0
Write Data Byte 12
Write CycleWrite Command
Acknowledge Read
Acknowledge Read
Acknowledge Read
DATAOUT
4
Acknowledge Read –
Valid Command Acknowledge
3607 drw 09
1
Either a Read cycle was completed or a Status Acknowledge was executed immediately prior to the first MSTRB of this write waveform.
2
The combination of MSTRB Low and MR/W High (Read mode) asynchronously enables the MDATA pins as outputs. The data placed on the MDATA pins is determined by the state
of the MD/C pin.
3
After the Command is written, the Manager must take MR/W High (Read mode) to wait for a valid Command Acknowledge from the IDT77V500 before proceeding. Reading a High
Bit 7 of the status register under these conditions indicates the command has been acknowledged by the IDT77V500. This may take multiple IDT77V500 SCLK cycles based on possible
higher priority operations that the IDT77V500 must support.
4
A valid Acknowledge from the IDT77V500 is indicated by a High Command Acknowledge bit (Bit 7 of the Status Register).
9 of 12
January 30, 2001
IDT77V500
.
.
The Constant Bit Rate (CBR) functionality of the IDT77V500 provides
both the opportunity for scheduling priority traffic at a regular interval and
traffic shaping capability. Two external CBR clocks, CBRCLK3 and
CBRCLK2, are available and associated with Output Priority 3 (Highest
Priority) and Priority 2 respectively. Calls assigned to a particular CBR
VC in the IDT77V500 Per VC Table are linked together in a CBR Per VC
list by output, so that a cell from each VC of a particular CBR Per VC list
are serviced on each cycle through the list. The CBR Per VC List is identified by both the output and CBR priority on that output; for example,
OPyCBRx VC list represents Output y (Output number 0-7) and CBR
priority x (CBR priority 3 or 2). Figure 3 is an example of an OPyCBRx
VC List with four VCs in the list: 100 (the first entry in the list), 200, 300
and 400. The arrows indicate the linking sequence in this VC List. Figure
3 will be used with the CBR Clock Functional Waveforms to illustrate two
basic functional implementations using the CBR Clocks.
CBR Clock Functional Waveform Example 1 uses the CBR clocks to
frame execution of the OPyCBRx VC List. A cell from a specific VC on
the OPyCBRx VC List is scheduled on each rising clock edge of SCLK
after a falling edge of CBRCLKx. The cell will then be transmitted when
output y is available and other previously scheduled Input and Output
ports of the IDT77V400 have been serviced. This delay can be as long
as 65 SCLK cycles maximum for each cell in the Service Class 3 CBR
VC List , although it will typically be significantly less. The Service Class
2 delay can be larger if there is higher priority traffic to be transmitted.
This delay needs to be taken into account, as the next cell in the
OPyCBRx VC List will not be scheduled until the previous cell in the list
has been serviced. Thus enough CBRCLKx pulses need to be provided
to make sure all potential cells in the OPyCBRx VC List are scheduled.
This waveform illustrates the ideal case of each cell being immediately
transmitted after scheduling, enabling the scheduling and transmission
of the next cell in the OPyCBRxVC List on the next SCLK rising edge.
CBRCLKx HIGH for eight SCLK cycles or more tells the controller that
the pointer should be moved back to the top of the CBR VC List if all the
VCs in the list have been serviced. Thus the user can establish a frame
duration and be assured that a cell from each VC in the OPyCBRx VC
List is transmitted in each frame time. Sub lists can also be established
within the CBR VC List so that a particular VC could be weighted to ship
more cells per frame than the others.
Example 2 illustrates using very slow CBR clocks (tCHx greater than
or equal to 8 SCLKs) to shape traffic in a VBR form of implementation. A
cell from a VC on the OPyCBRx VC List is again scheduled on each
rising clock edge of SCLK after a falling edge of CBRCLKx, but since
tCHx is HIGH for more than eight SCLKs, there is more direct control
over the exact time in which each cell of the VC List is scheduled. The
single cell will then be transmitted when the output is available and other
previously scheduled Input and Output ports of the IDT77V400 have
been serviced (there is again the potential delay based on other traffic
passing through the IDT77V400). The IDT77V500 will service all of the
VCs in the OPyCBRx VC List because the count will prevent the pointer
from returning to the top of the CBR VC List until all VCs on the list with
cells have been serviced. The user can thus more closely manage the
transmission of cells with this slower CBR clock rate because it is more
directly related to individual CBRCLKx High-to-Low transitions.
Beginning
100
200
300
400
End
3607 drw 10
Figure 3 OPyBRx VC Example
.
. "
"!
!
"x" for this waveform represents either 2 or 3, depending on which CBRCLK is used (CBRCLK2 or CBRCLK3).
tCYCx
tCLx
tCHx
CBRCLKx
3607 drw 11
10 of 12
January 30, 2001
IDT77V500
.
. 33- !+!
!#7.
.!
!!!
%
.
.89
!
!
!
&
&
This example shows the procedure recommended for use of direct CBR scheduling. "x" for this waveform represents either 2 or 3, depending on
which CBRCLK is used (CBRCLK2 or CBRCLK3) ("y" represents the specific output (0-7)). The OPyCBRx VC List for this example is defined in
Figure 3.
SCLK
1
2
1
CBRCLKx
2
3
100
200
300
400
100
200
300
400
3607 drw 12
1
A cell from a VC on the OPyCBRx VC List is scheduled on each rising clock edge of SCLK after a falling edge of CBRCLKx if the previous VC has completed internal processing.
This example shows four VC's in the OPyCBRx VC List. The number of VC's in the OPxCBRx VC List may be as large as 8192.
3
The period between reinitiation of the OPyCBRx VC List defines the frame size; that is, the amount of time between starting the transmissions from the top of the OPyCBRx VC List.
CBRCLKx must be HIGH for eight clocks or more to reinitiate the transmission sequence at the start of the OPyCBRx VC List.
2
.
. 33- !+!
!:7.;
.;.!!
%(<89&
This example shows the use of a slower CBRCLK (tCHx > 8 SCLK) to provide VBR/CBR traffic shaping. For this waveform "x" represents either 2
or 3, depending on which CBRCLK is used (CBRCLK2 or CBRCLK3). ("y" represents the specific output (0-7)) The OPyCBRx VC List for this
example is defined in Figure 3.
SCLK
see cont'd
waveform
1
2
CBRCLKx
100
200
300
cont'd
waveform
3
400
100
3607 drw 13
1
A cell from a VC on the OPyCBRx VC List is scheduled on each rising edge of SCLK after a falling edge of CBRCLKx.
2
tCHx > 8 SCLK so that a cell is scheduled after each falling edge of CBRCLKx.
3
The pointer has moved back to the beginning of the OPyCBRx VC List.
.33- !
1
2
7
8
1
2
8190
8191
1
2
SCLK
tRSI 1
RESETI
2 clock cycles max.
2
RESETO
3607 drw 14
1
RESETI must be held HIGH for 8 SCLK cycles. When RESETI goes Low again 8191 cycles are used prior to the Status Acknowledge bits showing the internal reset process is
complete.
2
This delay should typically be much less than two SCLK cycles. RESETO remains High until START Command is received from the Call Setup Manager.
11 of 12
January 30, 2001
IDT77V500
,*
*
!
!
IDT XXXXX
Device
Type
A
99
A
A
Power
Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
BC
100-pin TQFP (PN100-1)
144-Ball BGA (BC-144-1)
27
25
Commercial & Industrial
S
Standard Power
,
System Clock Period in ns
77V500 ATM Cell Based Switch Controller
3607 drw sp15
!
!=
3/1/99:
Updated to new format.
Added Industrial Specifications.
Added S25 Speed Grade.
Pg. 3
Package Diagram notes added for clarification.
Pg. 4
Pin description table descriptions corrected. OFRM and Vss pin number corrections made.
Pg. 5
VTERM in Maximum ratings table reduced to 3.9V.
Pg. 10
Manager Bus Sequence Waveforms on page 8 and page 9 and their notes modified for clarity.
Pg. 14
Updated Ordering Information for S156 speed grade and Industrial temperature product. Added Preliminary Datasheet definition and
Datasheet Document History.
12/11/00:
Moved to final.
Updated general format and SwitchStar logo.
1/30/01:
Pg. 6
Corrected tDCC, tDCS, tDCIO, tOHMD, and tDCOF test limits to minimum values instead of maximum values.
Pg. 8
Clarified OFRM signal on SFRM, CBUS, and OFRM timing waveforms.
Pg. 10
Clarified CBR delays in text.
Pg. 11
Clarified SCLK timing in CBR Clock Functional Waveform Example 1 and added information to footnote 1.
Pg. 12
Corrected package designator to PN100-1. Updated Tech Support phone number.
Added BGA package to pages 1, 2, 3, 4 ,5, and 12.
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015
fax: 831-754-4608
www.idt.com
for Tech Support:
[email protected]
phone: 831-775-4002
SwitchStar and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
12 of 12
January 30, 2001