IDT IDT7MP4060S15Z 128k x 32 cmos static ram module Datasheet

IDT7MP4060
IDT7MP4095
128K x 32
CMOS STATIC RAM
MODULES
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High density 4 megabit static RAM modules
• Low profile 64-pin ZIP (Zig-zag In-line vertical Package),
64-lead, 72-lead SIMMs (Single In-line Memory Modules)
• Fast access time: 15ns (max.)
• Surface mounted plastic components on an epoxy
laminate (FR-4) substrate
• Single 5V (±10%) power supply
• Multiple GND pins and decoupling capacitors for maximum noise immunity
• Inputs/outputs directly TTL compatible
• Gold plated fingers on the SIMM version
The IDT7MP4095/7MP4060 are 128K x 32 static RAM
modules constructed on an epoxy laminate (FR-4) substrate
using four 128K x 8 static RAMs in plastic SOJ packages. The
IDT7MP4095/7MP4060 are available with access times as
fast as 15ns with minimal power consumption.
The IDT7MP4095 is packaged in a 64-pin FR-4 ZIP (Zigzag In-line vertical Package) or a 64-lead SIMM (Single In-line
Memory Module). The IDT7MP4060 is packaged in a 72-lead
SIMM. The ZIP configuration allows 64 pins to be placed on
a package 3.65 inches long and 0.21 inches thick. At only 0.60
inches high, this low-profile package is ideal for systems with
minimum board spacing, while the SIMM configuration allows
use of edge mounted sockets to secure the module.
All inputs and outputs of the IDT7MP4095/7MP4060 are
TTL compatible and operate from a single 5V supply. Full
asynchronous circuitry requires no clocks or refresh for operation and provides equal access and cycle times for ease of
use.
PIN CONFIGURATION – 7MP4095
PD0
I/O0
I/O1
I/O2
I/O3
VCC
A7
A8
A9
I/O4
I/O5
I/O6
I/O7
WE
A14
CS1
CS3
A16
GND
I/O16
I/O17
I/O18
I/O19
A10
A11
A12
A13
I/O20
I/O21
I/O22
I/O23
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
GND
PD1
I/O8
I/O9
I/O10
I/O11
A0
A1
A2
I/O12
I/O13
I/O14
I/O15
GND
A15
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
CS4
PD0 - OPEN
PD1 - OPEN
FUNCTIONAL BLOCK DIAGRAM
CS1
ADDRESS
CS2
CS3
CS4
17
128K x 32
RAM
WE
OE
CS2
NC
8
8
8
8
OE
I/O24
I/O25
I/O26
I/O27
A3
A4
A5
VCC
A6
I/O28
I/O29
I/O30
I/O31
I/O 0-31
3147 drw 01
PIN NAMES
I/O0–31
Data Inputs/Outputs
A0–16
Addresses
CS1–4
WE
OE
ZIP, SIMM
TOP VIEW
Chip Selects
Write Enable
Output Enable
VCC
Power
GND
Ground
NC
No Connect
3147 tbl 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1996 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
SEPTEMBER 1996
DSC-3147/7
7.09
1
IDT7MP4060/7MP4095
128K x 32 CMOS STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION – 7MP4060
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Parameter(1)
Symbol
NC
PD 3
PD 0
I/O0
I/O1
I/O2
I/O3
VCC
A7
A8
A9
I/O4
I/O5
I/O6
I/O7
WE
A14
CS1
CS3
A16
GND
I/O16
I/O17
I/O18
I/O19
A10
A11
A12
A13
I/O20
I/O21
I/O22
I/O23
GND
NC
NC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
NC
PD 2
GND
PD 1
I/O8
I/O9
I/O10
I/O11
A0
A1
A2
I/O12
I/O13
I/O14
I/O15
GND
A15
PD 0 - OPEN
PD 1 - OPEN
PD 2 - OPEN
PD 3 - GND
Conditions
Max.
Unit
CIN(D)
Input Capacitance
(Data and CS)
V(IN) = 0V
12
pF
CIN(A)
Input Capacitance
(Address, WE, OE)
V(IN) = 0V
40
pF
COUT
Output Capacitance
V(OUT) = 0V
12
pF
NOTE:
1. This parameter is guaranteed by design but not tested.
3147 tbl 04
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
CS2
CS4
Parameter
Min.
Typ.
Max.
Unit
VCC
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
VIH
Input High Voltage
VIL
NC
Input Low Voltage
0
0
0
V
2.2
—
5.8
V
—
0.8
V
–0.5
(1)
NOTE:
1. VIL (min) = –3.0V for pulse width less than 10ns.
OE
I/O24
I/O25
I/O26
I/O27
A3
A4
A5
VCC
A6
I/O28
I/O29
I/O30
I/O31
NC
NC
3147 tbl 05
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Ambient
Temperature
GND
Commercial
0°C to +70°C
0V
VCC
5.0V ± 10%
3147 tbl 06
TRUTH TABLE
Mode
3147 drw 13
SIMM
TOP VIEW
CS
OE
WE
Output
Power
Standby
H
X
X
High Z
Standby
Read
L
L
H
DATAOUT
Active
Write
L
X
L
DATAIN
Active
Read
L
H
H
High-Z
Active
3147 tbl 02
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Value
Unit
–0.5 to +7.0
V
0 to +70
°C
VTERM
Terminal Voltage with
Respect to GND
TA
Operating Temperature
TBIAS
Temperature Under Bias
–10 to +85
°C
TSTG
Storage Temperature
–55 to +125
°C
IOUT
DC Output Current
50
mA
NOTES:
3147 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
7.09
2
IDT7MP4060/7MP4095
128K x 32 CMOS STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V ±10%, TA = 0°C to +70°C)
Symbol
|ILI|
Parameter
Test Conditions
Input Leakage
Min.
Max.
Unit
VCC = Max.; VIN = GND to VCC
—
10
µA
VCC = Max.; VIN = GND to VCC
—
40
µA
—
10
µA
(Data and CS)
|ILI|
Input Leakage
(Address, WE, and OE)
|ILO|
Output Leakage
VCC = Max.; CS = VIH, VOUT = GND to VCC
VOL
Output Low
VCC = Min., IOL = 8mA
—
0.4
V
VOH
Output High
VCC = Min., IOH = –4mA
2.4
—
V
Symbol
Parameter
Test Conditions
Max.
Unit
ICC
Dymanic Operating
f = fMAX; CS = VIL
760
mA
160
mA
60
mA
Current
VCC = Max.; Output Open
ISB
Standby Supply
Current
≥ VIH, VCC = Max.
Outputs Open, f = fMAX
ISB1
Full Standby
Supply Current
CS ≥ VCC – 0.2V; f = 0
VIN > VCC – 0.2V or < 0.2V
CS
3147 tbl 07
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
Output Load
1.5V
See Figures 1 and 2
3147 tbl 08
+5 V
+5 V
480 Ω
480 Ω
DATA
OUT
DATA
OUT
255Ω
255Ω
30 pF*
* Includes scope and jig.
Figure 1. Output Load
5 pF*
3147 drw 03
Figure 2. Output Load
(for tOLZ, tOHZ, tCHZ, tCLZ,
tWHZ, tOW)
7.09
3
IDT7MP4060/7MP4095
128K x 32 CMOS STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(VCC = 5V ±10%, TA = 0°C to +70°C)
-15
Symbol Parameter
Read Cycle
-20
Min.
Max.
Min.
Max.
Unit
tRC
Read Cycle Time
15
—
20
—
ns
tAA
Address Access Time
—
15
—
20
ns
tACS
Chip Select Access Time
—
15
—
20
ns
tCLZ(1)
Chip Select to Output in Low Z
3
—
3
—
ns
tOE
Output Enable to Output Valid
—
8
—
10
ns
tOLZ(1)
Output Enable to Output in Low Z
0
—
0
—
ns
tCHZ(1)
Chip Deselect to Output in High Z
—
8
—
12
ns
tOHZ
(1)
Output Disable to Output in High Z
—
8
—
12
ns
tOH
Output Hold from Address Change
3
—
3
—
ns
tPU(1)
Chip Select to Power-Up Time
0
—
0
—
ns
Chip Deselect to Power-Down Time
—
15
—
20
ns
tPD
(1)
Write Cycle
tWC
Write Cycle Time
15
—
20
—
ns
tCW
Chip Select to End of Write
12
—
18
—
ns
tAW
Address Valid to End of Write
12
—
18
—
ns
tAS
Address Set-up Time
0
—
0
—
ns
tWP
Write Pulse Width
12
—
18
—
ns
tWR
Write Recovery Time
0
—
3
—
ns
tWHZ(1)
Write Enable to Output in High Z
—
8
—
13
ns
tDW
Data to Write Time Overlap
10
—
12
—
ns
tDH
Data Hold from Write Time
0
—
0
—
ns
tOW(1)
Output Active from End of Write
3
—
3
—
ns
NOTE:
1. This parameter is guaranteed by design, but not tested.
3147 tbl 10
7.09
4
IDT7MP4060/7MP4095
128K x 32 CMOS STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
t RC
ADDRESS
t AA
OE
t OH
t OE
t OLZ
CS
t ACS
t CLZ (5)
(5)
t OHZ (5)
t CHZ (5)
DATA OUT
3147 drw 04
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
t RC
ADDRESS
t AA
t OH
DATA OUT
t OH
PREVIOUS DATA VALID
DATA VALID
3147 drw 05
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
CS
t ACS
t CLZ
(5)
t CHZ
(5)
DATA OUT
3147 drw 06
NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected. CS = VIL.
3. Address valid prior to or coincident with CS transition low.
4. OE = VIL.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.
7.09
5
IDT7MP4060/7MP4095
128K x 32 CMOS STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1, 2, 3, 7)
t WC
ADDRESS
OE
t AW
CS
t WP
t AS
(7)
t WR
WE
t OHZ (6)
t WHZ (6)
t OHZ
DATA OUT
(6)
t OW
(6)
(4)
(4)
t DH
t DW
DATA IN
DATA VALID
3147 drw 07
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1, 2, 3, 5)
t WC
ADDRESS
t AW
CS
t AS
t CW
t WR
WE
t DW
DATA IN
t DH
DATA VALID
3147 drw 08
NOTES:
1. WE or CS must be high during all address transitions.
2. A write occurs during the overlap (tWP) of a low CS and a low WE.
3. tWR is measured from the earlier of CS or WE going high to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW).
7.09
6
IDT7MP4060/7MP4095
128K x 32 CMOS STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS – IDT7MP4095
SIMM VERSION
3.840
3.860
3.574
3.594
0.210
MAX.
0.620
0.640
0.250
TYP.
PIN 1
0.240
0.260
0.070
0.090
0.050
TYP.
0.045
0.055
0.390
0.410
FRONT VIEW
SIDE VIEW
0.062 R
BACK VIEW
0.060
0.064
PIN 1
3147 drw 09
ZIP VERSION
3.640
3.660
0.210
MAX.
0.600
MAX.
PIN 1
0.015
0.025
0.100
TYP.
0.250
TYP.
0.100
TYP.
0.050
TYP.
0.125
0.175
SIDE VIEW
FRONT VIEW
BACK VIEW
3147 drw 10
7.09
7
IDT7MP4060/7MP4095
128K x 32 CMOS STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS – IDT7MP4060
FRONT VIEW
SIDE VIEW
4.240
4.260
0.640
0.660
0.210 MAX
3.974
3.994
0.240
0.260
0.390
0.410
PIN 1
0.250 TYP
0.050 TYP
0.045
0.055
0.070
0.090
0.062 R
0.060
R
0.064
PIN 1
BACK VIEW
3147 drw 11
ORDERING INFORMATION
IDT
XXXXX
X
X
X
X
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
Commercial (0°C to +70°C)
M
Z
FR-4 SIMM (Single In-line Memory Module)
FR-4 ZIP (Zig-zag In-line Package)
15
20
S
Speed in Nanoseconds
Standard Power
IDT7MP4060 128K x 32 Static RAM Module (SIMM only)
IDT7MP4095 128K x 32 Static RAM Module
3147 drw 12
7.09
8
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