IDT IDT7MPV6255S15M 256kb and 512kb secondary cache modules for the powerpco Datasheet

256KB AND 512KB SECONDARY
CACHE MODULES FOR THE
PowerPC
IDT7MPV6253
IDT7MPV6255/56
Integrated Device Technology, Inc.
x 8 asynchronous static RAMs and the IDT7MPV6255/56 use
IDT’s 71V432 32K x 32 pipelined synchronous burst static
RAMs in plastic surface mount packages mounted on a
multilayer epoxy laminate (FR-4) board. In addition, each of
the modules uses the IDT 71216 16K x 15 Cache-Tag static
RAM and IDT FCT logic. Extremely high speeds are achieved
using IDT’s high-reliability, low cost CMOS technology.
The low profile card edge package allows 178 signal leads
to be placed on a package 5.06" long, a maximum of 0.250"
thick and a maximum of 1.08" tall. The module space savings
versus discrete components allows the OEM to design additional functions onto the system or to shrink the size of the
motherboard for reduced cost.
All inputs and outputs are LVTTL-compatible, and operate
from separate 5V (±5%) and 3.3V (+10/-5%) power supplies.
Multiple GND pins and on-board decoupling capacitors ensure maximum protection from noise.
FEATURES
• For CHRP based PowerPC systems.
• Asynchronous and pipelined burst SRAM options in the
same module pinout
• Low-cost, low-profile card edge module with 178 leads
• Uses Burndy Computerbus connector, part number
ELF182KSC-3Z50
• Operates with external PowerPC CPU speeds up to
66MHz
• Separate 5V (±5%) and 3.3V (+10/-5%) power supplies
• Multiple GND pins and decoupling capacitors for maximum noise immunity
• Presence Detect output pins allow the system to determine the particular cache configuration.
DESCRIPTION
The IDT7MPV6253/55/56 modules belong to a family of
secondary caches intended for use with PowerPC CPUbased systems. The IDT7MPV6253 uses IDT’s 71V256 32K
FUNCTIONAL BLOCK DIAGRAM
13
A14 - A26
Latch
IDT7MPV6253 – 256KB ASYNCHRONOUS VERSION
PD0
PD1
13
PD2
ALE
ADDRA0
ADDRA1
ADDRA1
SRAM OE1
WE#0
32K x 8
Asynchronous
SRAM
WE#1
32K x 8
Asynchronous
SRAM
WE#2
32K x 8
Asynchronous
SRAM
WE#3
32K x 8
Asynchronous
SRAM
STANDBY
A14 - A26
TWE#
TOE#
PD3
ADDRA0
13
STANDBY
TCLR#
TVALID
DIRTYIN
CLK2
SRAM OE0
8
8
8
8
8K x 2
Status
WE#4
32K x 8
Asynchronous
SRAM
DH8 - DH15
WE#5
32K x 8
Asynchronous
SRAM
DH16 - DH23 WE#6
32K x 8
Asynchronous
SRAM
DH24 - DH31 WE#7
32K x 8
Asynchronous
SRAM
STANDBY
12
8K x 12
Tag Field
DH0 - DH7
8
8
8
8
DL0 - DL7
DL8 - DL15
DL16 - DL23
DL24 - DL31
A2 - A13
TMATCH
DIRTYOUT
drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc. PowerPC is a trademark of IBM. Computerbus is trademark of Burndy.
COMMERCIAL TEMPERATURE RANGE
JUNE 1996
1996 Integrated Device Technology, Inc.
DSC-3608/2
1
IDT7MPV6253/55/56
256KB/512KB CMOS SECONDARY CACHE MODULES FOR THE PowerPC
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
IDT7MPV6255 – 256KB PIPELINED BURST VERSION
WE#0
32K x 32
Pipelined
Burst
SRAM
WE#1
WE#2
WE#3
CLK 1
32
DH 0-31
CLK0
WE#4
WE#5
32K x 32
Pipelined
Burst
SRAM
WE#6
WE#7
32
DL0-31
SRAM OE#0
SRAM ADS#0
CNT EN#0
STANDBY
BURST MODE
A14 - A28
PD0
PD1
PD2
PD3
15
A14 - A26
TWE#
TOE#
13
12
8K x 12
Tag Field
STANDBY
TCLR#
TVALID
DIRTYIN
CLK2
A2 - A13
TMATCH
8K x 2
Status
DIRTYOUT
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RECOMMENDED DC
OPERATING CONDITIONS
Symbol
ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
Value
Unit
–0.5 to +4.6
V
Operating Temperature
0 to +70
°C
Temperature Under Bias
–10 to +85
°C
–55 to +125
°C
50
mA
Parameter
Min.
Typ.
Max.
Unit
VCC3
Supply Voltage
3.14
3.3
3.6
V
VTERM Terminal Voltage with Respect
for VCC3 to GND
VCC5
Supply Voltage
4.75
5.0
5.25
V
TA
Supply Voltage
0
0
0.0
V
TBIAS
VIH
Input High Voltage
2.2
—
VCC + 0.3
V
TSTG
Storage Temperature
VIL
Input Low Voltage –0.5(1)
—
0.8
V
IOUT
DC Output Current
GND
NOTE:
1. VIL = –1.0V for pulse width less than 5ns, once per cycle.
NOTE:
tbl 03
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
tbl 01
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
SRAM ACCESS TIMES
Power Plane
Ambient Temperature
GND
VCC
VCC3
0°C to +70°C
0V
3.3V +10/-5%
Module Speed
Asych
Burst(1)
Tag
VCC5
0°C to +70°C
0V
5.0V ± 5%
66MHz
15ns
8.5ns
10ns
tbl 02
NOTE:
1. Burst SRAMs are measured by Clock to Data Out (tCD).
2
tbl 04
IDT7MPV6253/55/56
256KB/512KB CMOS SECONDARY CACHE MODULES FOR THE PowerPC
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
IDT7MPV6256 – 512KB PIPELINED BURST VERSION
WE#0
WE#1
WE#2
WE#3
CLK1
32K x 32
Pipelined
Burst
SRAM
WE#0
WE#1
WE#2
WE#3
CLK1
32
32K x 32
Pipelined
Burst
SRAM
32
DH0-31
WE#4
WE#5
WE#6
WE#7
CLK0
32K x 32
Pipelined
Burst
SRAM
DH0-31
WE#4
WE#5
WE#6
WE#7
CLK0
32
32K x 32
Pipelined
Burst
SRAM
32
DL0-31
DL0-31
SRAM OE#0
SRAM ADS#0
CNT EN#0
STANDBY
BURST MODE
A13 - A28
SRAM OE#1
SRAM ADS#1
CNT EN#1
STANDBY
BURST MODE
16
A13 - A26
TWE#
TOE#
14
12
STANDBY
TCLR#
TVALID
DIRTYIN
CLK2
A1 - A12
16K x 12
Tag Field
TMATCH
16K x 2
Status
DIRTYOUT
PD0
PD1
PD2
PD3
drw 03
CAPACITANCE (IDT7MPV6253 )(1)
CAPACITANCE (IDT7MPV6255/56 )(1)
(TA = +25°C, f = 1.0 MHz)
(TA = +25°C, f = 1.0 MHz)
(1)
Symbol
Parameter
CIN1
Input Capacitance
(Address)
Input Capacitance
CIN2
(ADDR0-1)
CIN3
Input Capacitance
(OE#)
Input Capacitance
CIN4
(WE#, TWE#)
CI/O
I/O Capacitance
Condition
VIN = 0V
Max.
15
Unit
pF
VIN = 0V
25
pF
VIN = 0V
45
pF
VIN = 0V
8
pF
VOUT = 0V
10
pF
NOTES:
1. These parameters are guaranteed by design but not tested.
Symbol
Parameter(1)
CIN1
Input Capacitance
(Address)
Input Capacitance
CIN2
(ADDR0-1)
CIN3
Input Capacitance
(OE#)
Input Capacitance
CIN4
(WE#, TWE#)
CI/O
I/O Capacitance
Condition
VIN = 0V
Max.
20
Unit
pF
VIN = 0V
—
pF
VIN = 0V
15
pF
VIN = 0V
8
pF
VOUT = 0V
10/20
pF
NOTES:
1. These parameters are guaranteed by design but not tested.
tbl 05
3
tbl 06
IDT7MPV6253/55/56
256KB/512KB CMOS SECONDARY CACHE MODULES FOR THE PowerPC
PIN CONFIGURATION(1)
COMMERCIAL TEMPERATURE RANGE
PIN NAMES
GND
PD1
PD3
DH31
DH29
DH27
DH25
VCC3
SRAM WE3
DH23
DH21
DH18
GND
DH16
SRAM WE2
DH14
DH13
VCC5
DH10
DH8
SRAM WE1
DH6
VCC3
DH4
GND
CLK 0
GND
DH1
SRAM WE0
DL31
DL30
GND
DL29
DL27
DL25
VCC5
SRAM WE7
DL23
DL21
DL19
GND
DL17
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
GND
PD0
PD2
DH 30
DH 28
DH 26
DH 24
VCC3
DP3 (1)
DH 22
DH 20
DH 19
GND
DH 17
DP2 (1)
DH 15
DH 12
VCC5
DH 11
DH 9
DP1 (1)
DH 7
VCC3
DH 5
DH 3
DH 2
DH 0
DP0 (1)
GND
CLK 1
GND
DL 28
DL 26
DL 24
DP7 (1)
VCC5
DL 22
DL 20
DL 18
DL 16
GND
DP6 (1)
SRAM WE6
DL15
DL13
GND
DL10
DL 8
SRAM WE5
DL 6
VCC3
DL 5
DL 2
GND
(1)
CLK 3
GND
(1) CLK 4
GND
SRAM WE4
(3,4)
SRAM ALE
VCC3
(3,4)
ADDR1
(1)
RSVD
(2)
SRAM CNT EN0
(2,3)
SRAM CNT EN1
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
DL 14
DL 12
DL 11
GND
DL 9
DP5 (1)
DL 7
DL 4
VCC3
DL 3
DL 1
DL 0
GND
CLK 2 (TAG)
GND
DP4 (1)
SRAM OE 0
SRAM OE 1 (3)
VCC 3
ADDR0 (3,4)
RSVD (1)
SRAM ADS0 (2)
SRAM ADS1 (2,3)
A27
A24
A22
A20
GND
A18
A16
A15
A14
VCC3
A10
A8
A6
GND
A4
A2
(2,3)
A1
BURST MODE
VCC5
TAG VALID
TAG WE
STANDBY
DIRTYOUT
GND
155
156
167
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
A28
A26
A25
A23
GND
A21
A19
A17
A13
VCC3
A12
A11
A9
GND
A7
A5
A3
A0 (1)
VCC5
TAG CLR
TAG MATCH
TAG OE
DIRTYIN
GND
A0 – A28
ADDR0 - ADDR1
CLK0 - CLK4
DH0 - DH31
DL0 - DL31
PD0 – PD3
Address Inputs
Address Inputs (Asynchronous SRAMs only)
Clock Inputs
High Order Cache Data
Low Order Cache Data
Presence Detect Pins
SRAM ADS0 -
SRAM Address Strobe
SRAM ADS1
SRAM ALE
SRAM Address Latch Enable
SRAM CNT EN0 - SRAM Control Enable
SRAM CNT EN1
SRAM OE0 -
SRAM Output Enable
SRAM OE1
SRAM WE0 -
SRAM Write Enable
SRAM WE1
BURST MODE
Burst Mode: 0=Linear, 1=Interleaved
TAG CLR
Tag Clear
TAG MATCH
Tag Match
TAG VALID
Tag Valid
TAG OE
Tag Output Enable
TAG WE
Tag Write Enable
DIRTYIN
Dirty Input Bit
DIRTYOUT
Dirty Output Bit
STANDBY
Stand By Mode
VCC3
VCC5
3.3 Volt Power Supply
5 Volt Power Supply
GND
Ground
NC
No Connect
RSVD
Reserved
tbl 07
PRESENCE DETECT TABLE
PD3
PD2
PD1
PD0
Module
NC
NC
No cache present
NC
NC
NC
GND
GND
GND
NC
NC
IDT7MPV6255
GND
NC
NC
NC
IDT7MPV6256
GND GND
IDT7MPV6253
tbl 08
NOTES:
1. These pins are NC (No Connect) on 7MPV6253/55/56.
2. These pins are NC on 7MPV6253.
3. These pins are NC on 7MPV5255.
4. These pins are NC on 7MPV6256.
LOW PROFILE CARD EDGE MODULE
TOP VIEW
drw 04
4
IDT7MPV6253/55/56
256KB/512KB CMOS SECONDARY CACHE MODULES FOR THE PowerPC
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
(VCC5 = 5.0V ± 5%, VCC3 = 3.3V ± 10%, TA = 0°C to 70°C)
Symbol
|ILI|
|ILI|
|ILO|
VOL
VOH
ICC3
ICC5
ISB3
ISB31
ISB5
Parameter
Input Leakage Current
(Address)
Input Leakage Current
(Data and Control)
Output Leakage Current
Output Low Voltage
Output HighVoltage
Operating 3.3V Power
Supply Current
Operating 5V Power
Supply Current
Standby 3.3V Power
Supply Current
Full Standby 3.3V Power
Supply Current
Standby 5V Power
Supply Current
Test Condition
VCC5 = Max, VIN = GND to VCC
VCC3 = Max
VCC5 = Max, VIN = GND to VCC
VCC3 = Max
VOUT = 0V to VCC3, VCC3 = Max.
IOL = 8mA, VCC3 = Min.
IOH= –4mA, VCC3 = Min.
VCC3 = Max., STANDBY ≤ VIL,
f = fMAX, Outputs Open
VCC5 = Max., STANDBY ≤ VIL,
f = fMAX, Outputs Open
VCC3 = Max., STANDBY ≥ VIH,
f = fMAX, Outputs Open
VCC3 = Max., STANDBY ≥ VCC3 - 0.2V, f = 0,
VIN ≤ 0.2V or VIN ≥ VCC3 - 0.2V,
Outputs Open
VCC5 = Max., STANDBY ≥ VIH
f = fMAX, Outputs Open
Min.
—
’53
Max.
20
’55
Max.
30
’56
Max.
50
—
10
10
20
µA
—
—
2.4
—
10
0.4
—
1000
10
0.4
—
500
20
0.4
—
590
µA
V
V
mA
—
290
290
290
mA
—
100
100
190
mA
—
30
30
50
mA
—
30
30
30
mA
Unit
µA
tbl 09
AC TEST CONDITIONS – 3.3V POWER SUPPLY
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figures 1 and 2
tbl 10
+3.3V
+3.3V
320Ω
320Ω
DATA OUT
DATA OUT
350Ω
350Ω
30pF*
*including scope and jig capacitances
5pF*
*including scope and jig capacitances
Figure 2. Output Load
(for tOHZ, tCHZ, tOLZ and tCLZ)
Figure 1. Output Load
drw 05
drw 06
5
IDT7MPV6253/55/56
256KB/512KB CMOS SECONDARY CACHE MODULES FOR THE PowerPC
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS - IDT7MPV6253
SIDE VIEW
FRONT VIEW
0.225 MAX
5.050
5.070
1.060
1.080
0.072
0.076
PIN 90
0.075
0.081
4 X 0.200
2 X 0.195
1.240
1.260
2.150
2.170
1.250
1.270
0.055
0.069
N/A
0.050 TYP
PIN 1
BACK VIEW
drw 07
IDT7MPV6255
SIDE VIEW
FRONT VIEW
0.200 MAX
5.050
5.070
1.060
1.080
0.072
0.076
PIN 90
0.075
0.081
4 X 0.200
2 X 0.195
1.240
1.260
2.150
2.170
1.250
1.270
0.055
0.069
N/A
0.050 TYP
PIN 1
BACK VIEW
drw 08
6
IDT7MPV6253/55/56
256KB/512KB CMOS SECONDARY CACHE MODULES FOR THE PowerPC
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS - IDT7MPV6256
SIDE VIEW
FRONT VIEW
0.250 MAX
5.050
5.070
1.060
1.080
0.072
0.076
PIN 90
0.075
0.081
4 X 0.200
1.240
1.260
2.150
2.170
2 X 0.195
1.250
1.270
0.050 TYP
0.055
0.069
PIN 1
BACK VIEW
drw 09
ORDERING INFORMATION
IDT
XXXXX
A
999
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
Commercial (0°C to +70°C)
M
178 lead Module, Card Edge Low
Profile (CELP)
15
66
Speed in Nanoseconds (Asynchronous)
Speed in Megahertz (Pipelined Burst)
S
Standard Power
7MPV6253 256KB Asynchronous Cache Module
7MPV6255 256KB Pipelined Burst Cache Module
7MPV6256 512KB Pipelined Burst Cache Module
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7
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