QUAD PCM CODEC WITH PROGRAMMABLE GAIN IDT821034 FEATURES: DESCRIPTION: • The IDT821034 is a single-chip, four channel PCM CODEC with onchip filters and programmable gain setting. This device provides both µ-Law and A-Law companding digital-to-analog and analog-to-digital conversions based on ITU-T G.711 - G.714 specifications. The digital filters in IDT821034 provides the necessary transmit and receive filtering for voice telephone circuit to interface with time-division multiplexed systems. The IDT821034 has a flexible PCM interface with software selectable timing modes and independently programmable time slot for each transmit and receive channel. It also integrates the SLIC signaling functions through internal registers. The CODEC and SLIC control/status registers are accessed via the Serial Control Interface. The IDT821034 can be used in digital telecommunication applications such as PBX, Central Office Switch, Digital Telephone and Integrated Voice/ Data Access Unit. • • • • • • • • • • • • • 4 channel CODEC with on-chip digital filters Software Selectable A-law/µ-law companding Programmable gain setting Automatic master clock frequency selection: 2.048MHz, 4.096 MHz or 8.192MHz Flexible PCM interface with up to 128 programmable time slots, data rate from 512 kbits/s to 8.192 Mbits/s 5 SLIC signaling pins per channel Flexible Serial Control Interface to microcontroller Software programmable timing modes TTL and CMOS compatible digital I/O Meets or exceeds ITU-T G.711 - G.714 requirements +5 V single power supply Low power consumption: 100mW Typ. Operating temperature range: -40 °C to +85 °C Packages available: 52 pin PQFP FUNCTIONAL BLOCK DIAGRAM GSX0 VFXI0 + +2.5V A/D Channel 0 D/A VFRO0 O_0(4 - 2) I/O_0(1 - 0) PCM Interface DX DR FS BCLK TSX DSP SLIC Interface I/O Channel 1 Serial Control Interface CO CI CS CCLK Timing MCLK Channel 2 Channel 3 The IDT logo is a registered trademark of Integrated Device Technology, Inc INDUSTRIAL TEMPERATURE RANGE MAY 13, 2003 1 2003 Integrated Device Technology, Inc. DSC-6032/3 IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN INDUSTRIAL TEMPERATURE RANGE VFXI0 GSX0 VFRO0 CNF O1_4 O1_3 O1_2 I/O1_1 I/O1_0 O0_4 O0_3 O0_2 I/O0_1 39 38 37 36 35 34 33 32 31 30 29 28 27 PIN CONFIGURATIONS GNDA 40 26 I/O0_0 GNDA 41 25 GND VFXI1 42 24 CS GSX1 43 23 CI VFRO1 44 22 CO VDDA 45 21 CCLK GNDA 46 20 BCLK VDDA 47 19 MCLK VFRO2 48 18 FS GSX2 49 17 TSX VFXI2 50 16 DR GNDA 51 15 VDD GNDA 52 14 DX 1 2 3 4 5 6 7 8 9 10 11 12 13 VFXI3 GSX3 VFRO3 O2_4 O2_3 O2_2 I/O2_1 I/O2_0 O3_4 O3_3 O3_2 I/O3_1 I/O3_0 52-Pin PQFP PIN DESCRIPTION Name GNDA Type -- VDDA -- VFRO3 VFRO2 VFRO1 VFRO0 GSX3 GSX2 GSX1 GSX0 VFXI3 VFXI2 VFXI1 VFXI0 O3_4 O3_3 O3_2 O2_4 O2_3 O2_2 O O I O O Pin Number 46 51 52 40 41 47 45 3 48 44 37 2 49 43 38 1 50 42 39 9 10 11 4 5 6 Description Analog Ground. All ground pins should be connected to the ground plane of the circuit board. +5 V Analog Power Supply. This pin should be bypassed to ground using 0.1µF capacitor. All power supply pins should be connected to the power plane of the circuit board. Voice Frequency Receiver Output. This is the output of receive power amplifier. It can drive 2000 Ω (or greater) load. Gain Setting Transmit Amplifier Output. This pin is the output of the gain setting amplifier, and the input to the differential transmit filter. It should be connected to the corresponding VFXI pin through a resistive network to set the transmit gain. Refer to Figure 5 for details. Voice Frequency Transmitter Input. This pin is the input to the gain setting amplifier in the transmit path. SLIC Signaling Output for Channel 3. SLIC Signaling Output for Channel 2. 2 IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN INDUSTRIAL TEMPERATURE RANGE PIN DESCRIPTION (CONTINUED) Name O1_4 O1_3 O1_2 O0_4 O0_3 O0_2 I/O3_1 I/O3_0 I/O2_1 I/O2_0 I/O1_1 I/O1_0 I/O0_1 I/O0_0 Type DX O 14 VDD -- 15 DR I 16 TSX O 17 FS I 18 MCLK I 19 BCLK I 20 CCLK I 21 CO O 22 CI I 23 CS I 24 GND -- 25 CNF O 36 O O I/O I/O I/O I/O Pin Number 35 34 33 30 29 28 12 13 7 8 32 31 27 26 Description SLIC Signaling Output for Channel 1. SLIC Signaling Output for Channel 0. SLIC Signaling I/O for Channel 3. SLIC Signaling I/O for Channel 2. SLIC Signaling I/O for Channel 1. SLIC Signaling I/O for Channel 0. Transmit PCM Data Output. PCM data is shifted out of DX on rising edges of BCLK. +5 V Digital Power Supply. All power supply pins should be connected to the power plane of the circuit board. Receive PCM Data Input. PCM data is shifted into DR on falling edges of BCLK. Time Slot Indicator Output, Open Drain This pin pulses low during the active time slot of each channel. A low level on this pin indicates active DX output. Frame Synchronization. The FS pulse serves as the reference to time slots. The width of the FS pulse should be at least one BCLK cycle. Master Clock. Master Clock provides the clock for DSP. It can be 2.048 MHz, 4.096 MHz or 8.192 MHz. It must be synchronous to FS. Bit Clock. Bit Clock shifts out PCM data on DX pin and shifts in PCM data on DR pin. The clock can vary from 512 kHz to 8.192 MHz at 64 kHz increment, depending on the time slot requirement of the system. Serial Control Interface Clock. This is the clock for Serial Control Interface. It can be up to 8.192 MHz. Serial Control Interface Data Tri-State Output. This pin is used to monitor SLIC working status. It is in high impedance state when CS is high. Serial Control Interface Data Input. Data input on this pin can control both CODEC and SLIC. Chip Select. A low level on this pin enables the Serial Control Interface. Ground. All ground pins should be connected to the ground plane of the circuit board. Capacitor For Noise Filter. This pin should be connected to GNDA via a 0.1 µF capacitor. 3 IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN INDUSTRIAL TEMPERATURE RANGE FUNCTIONAL DESCRIPTION information retain the data in this mode. Each of the four channels in the IDT821034 can be in either normal mode or standby mode. The mode selection of each channel is done by the microcontroller via the Serial Control Interface. When in normal mode, each channel of the IDT821034 is able to transmit and receive both PCM and analog information. This is the operating mode when a telephone call is in progress. The IDT821034 contains four channel PCM CODEC with on chip digital filters. It provides the four-wire solution for the subscriber line circuitry in digital switches. The device converts analog voice signal into digital PCM samples, and converts digital PCM samples back to analog signal. Digital filters are used to bandlimit the voice signals during conversion. The frequency of the master clock (MCLK) can be 2.048 MHz, 4.096 MHz or 8.192 MHz. Internal circuitry determines the master clock frequency automatically. Four channels of serial PCM data are time multiplexed via two pins, DX and DR. The time slots of the four channels can be programmed dynamically. The control words can be written by a microcontroller via the Serial Control Interface. Dynamic time-slot assignment can accommodate 8 to 128 time slots corresponding to the bit clock (BCLK) frequency from 512 kHz to 8.192 MHz. The IDT821034 offers two timing modes, delay mode and non-delay mode. Mode selection is done by programming the Configuration Register. The two modes are distinguished by time slot zero definition. In delay mode, the time slot zero is defined as starting on the first rising edge of BCLK after FS = ‘1’ is detected by the falling edge of BCLK (Figure 7). While in non-delay mode, the time slot zero starts when both BCLK and FS are high (Figure 8). The device provides a programmable interface to SLIC (Subscriber Line Interface Circuit). Each channel of the IDT821034 has three output pins and two I/O pins for SLIC signaling. These interface pins are mapped to internal registers and are accessed by the microcontroller via the Serial Control Interface. In this way, the IDT821034 provides high level of integration in line card design. The Serial Control Interface of IDT821034 consists of four pins (CI, CO, CS and CCLK), as shown in Figure 1, for the communication to a microcontroller. Via this interface, the microcontroller can control the CODEC and SLIC working modes as well as monitor the SLIC status. Gain Programming Transmit gain and receive gain of each channel in IDT821034 can be varied by programming DSP digital filter coefficients. Transmit gain can be varied within the range of -3 dB to +13 dB; while receive gain can be varied within the range of -13 dB to +3 dB. This function allows the IDT821034 to be used with SLICs of different gain requirement. Gain programming coefficient can be written into IDT821034 via Serial Control Interface. The detailed operation will be covered in Serial Control Interface description. The gain programming coefficients should be calculated as: Transmit : Coeff_X = round [ gain_X0dB × gain_X ] Receive: Coeff_R = round [ gain_R0dB × gain_R ] where: gain_X0dB = 1820; gain_X is the target gain; Coeff_X should be in the range of 0 to 8192. gain_R0dB = 2506; gain_R is the target gain; Coeff_R should be in the range of 0 to 8192. A gain programming coefficient is 14-bit wide and in binary format. The 7 Most Significant Bits of the coefficient is called GA_MSB_Transmit for transmit path, or is called GA_MSB_Receive for receive path; The 7 Least Significant Bits of the coefficient is called GA_LSB_ Transmit for transmit path, or is called GA_LSB_Receive for receive path. An example is given below to clarify the calculation of the coefficient. To program a +3 dB gain in transmit path and a -3.5 dB gain in receive path: OPERATION CONTROL The following operation description applies to all four channels of the IDT821034. Linear Code of +3 dB = 103/20 = 1.412537545 Initial State The IDT821034 has a built-in power on reset circuit. After initial power up, the device defaults to the following mode: 1. A-law is selected; 2. Delay mode is selected; 3. I/O pins of SLIC interface are set to input mode; 4. SLIC Control and Status Register bits are set to ‘0’; 5. All four channels are placed in standby mode; 6. All transmit and receive time slots are disabled with Time Slot Registers set to zero; 7. DX is set to high impedance state. Coeff_X = round (1820 × 1.412537545) = 2571 = 0010100, 0001011 (in binary format ) GA_MSB_Transmit GA_LSB_Transmit = 0010100 = 0001011 Linear Code of -3.5 dB = 10(-3.5/20) = 0.668343917 Operating Modes There are two operating modes for each transmit or receive channel: standby mode and normal mode. When the IDT821034 is first powered on, standby mode is the default mode. Microcontroller can also set the device into this mode via the Serial Control Interface. In standby mode, the Serial Control Interface remains active to receive commands from the microcontroller. All other circuits are powered down with the analog outputs placed in high impedance state. All circuits which contain programmed 4 Coeff_R = round (2506 × 0.668343917) = 1675 = 0001101, 0001011 (in binary format) GA_MSB_Receive GA_LSB_Receive = 0001101 = 0001011 IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN INDUSTRIAL TEMPERATURE RANGE SIGNAL PROCESSING Serial Control Interface A Serial Control Interface is provided for a microprocessor to access the control and status registers of IDT821034. The control registers include Configuration Register, Time Slot Registers, SLIC Control Registers and Gain Adjustment Registers. They are used to program the working modes of CODEC and SLIC. The status registers include SLIC Status Registers. They are used to monitor SLIC functions. All registers are 8 bits wide. The Serial Control Interface consists of CO, CI, CS and CCLK pins (see Figure 1). A microprocessor initiates a write or read cycle after low level is asserted on CS pin. In the microprocessor write cycle, 8 bits of serial data on CI pin are shifted into the device at falling edges of CCLK. In the microprocessor read cycle, 8 bits of serial data are shifted out of the device on CO pin at rising edges of CCLK. At the end of each 8-bit transaction, the microprocessor sets CS high to terminate the cycle. Multiple accesses to the device are separated by an idle state (high level) of CS. The width of CS high level is at least three CCLK cycles. The IDT821034 has a Configuration Register. Its register bits are designated CR.7 - CR.0. The definition of the bits in Configuration Register is shown in Table 1. If the leading data bit on CI pin is ‘1’ in a microprocessor write cycle, the 8-bit data on CI pin is latched into Configuration Register with MSB first. There are eight Time Slot Registers for four transmit channels and four receive channels. The definition of the bits in Time Slot Register is shown in Table 2. Since PCM sample rate is 8k samples/sec and each sample is 8 bits wide, each time slot occupies 64 kbits/sec of data rate. The number of time slots in a frame is equal to the ratio of the bit clock frequency (BCLK) to 64 kHz. For the maximum BCLK frequency of 8.192 MHz, the number of time slots in a frame is 8.192MHz/64kHz, or 128. The minimum number of time slots (corresponding to the minimum BCLK frequency of 512 kHz) in a frame is 8. The relationship between frequently used BCLK frequencies and the number of time slots in a frame is shown in Table 3. Bit 6-0 in each Time Slot Register identify the time slot number (0 to 127) of the corresponding transmit or receive channel. Time Slot Registers can be accessed by specifying the transmit/ receive select (CR.1 and CR.0) and channel address (CR.3 and CR.2) in Configuration Register. If CR.6 = ‘0’ and the leading data bit on CI pin is ‘0’ in a microprocessor write cycle, the 8-bit data on CI pin is latched into the selected Time Slot Register with MSB first. There are four SLIC Control Registers for four channel SLIC signaling control. The definition of the bits in a SLIC Control Register is shown in Table 4. SLIC Control Registers can be accessed by specifying the channel address (CR.3 and CR.2) in Configuration Register. If CR[6:4] = ‘101’ and the leading data bit on CI pin is ‘0’ in a microprocessor write or read cycle, the 8-bit data on CI pin is latched into the selected SLIC Control Register with MSB first. There are four SLIC Status Registers for four channel SLIC monitoring. The bits in each SLIC Status Register are mapped to the SLIC signaling output and I/O pins of the corresponding channel as shown in Table 5. It should be noted that the last 3 bits of the SLIC Status Register are always mapped to I/O1_0, I/O2_0 and I/O3_0. This feature allows a rapid read process of the SLIC status when Channel 0 is selected. The SLIC Status Registers can be accessed by specifying the channel address (CR.3 and CR.2) in the Configuration Register. If CR[6:4] = ‘101’, as a result of the previous write to the Configuration Register, the subsequent microprocessor cycle is a read cycle. The content of the selected SLIC Status Register is shifted out of the device on CO pin with MSB first. There are 16 Gain Adjustment Registers for both transmit and receive paths of four channels. For each path, there are two High performance oversampling Analog-to-Digital Converters (ADC) and Digital-to-Analog Converters (DAC) are used in the IDT821034 to provide the required conversion accuracy. The associated decimation and interpolation filters are realized with both dedicated hardware and Digital Signal Processor (DSP). The DSP also handles all other necessary functions such as PCM bandpass filtering and sample rate conversion. Transmit Signal Processing In the transmit path, the analog input signal is received with a gain setting amplifier. The signal gain is set by the resistive feedback network as shown in the application circuit (Figure 5). The output of the gain setting amplifier is connected internally to the input of the anti-alias filter for the oversampling ADC. The digital output of the oversampling ADC is decimated and sent to the DSP. The transmit filter is implemented in the DSP as a digital bandpass filter. The filtered signal is further decimated and compressed to PCM format. Transmit PCM Interface The transmit PCM interface clocks the PCM data out of DX pin on rising edges of BCLK according to the time slot assignment. The frame sync (FS) pulse identifies the beginning of a transmit frame, or time slot zero. The time slots for all channels are referenced to FS. The IDT821034 contains user programmable Transmit Time Slot Register for each transmit channel. The register is 7 bits wide and can accommodate up to 128 time slots (corresponding to the maximum BCLK frequency of 8.192 MHz) in each frame. The PCM Data is transmitted serially on DX pin with the Most Significant Bit (MSB), or Bit 7, first. When the device is first powered up, all transmit time slots are disabled with Transmit Time Slot Registers set to zero. DX pin remains in highimpedance state. To power up or power down each transmit channel, Configuration Register and the corresponding Time Slot Register must be programmed. Receive Signal Processing In the receive path, the PCM code is received at the rate of 8,000 samples per second. The PCM code is expanded and sent to the DSP for interpolation and receive channel filtering function. The receive filter is implemented in the DSP as a digital lowpass filter. The filtered signal is then sent to an oversampling DAC. The DAC output is post-filtered and then delivered at VFRO pin by a power amplifier. The amplifier can drive resistive load higher than 2 kΩ. Receive PCM Interface The receive PCM interface clocks the PCM data into DR pin on falling edges of BCLK according to the time slot assignment. The receive time slot definition and programming is similar to that of the transmit time slot. The IDT821034 contains a user programmable Receive Time Slot Register for each receive channel. The register is 7 bits wide and can accommodate up to 128 time slots (corresponding to the maximum BCLK frequency of 8.192 MHz) in each frame. The PCM Data is received serially on DR pin with the MSB (Bit 7) first. When the device is first powered up, all receive time slots are disabled with Receive Time Slot Registers set to zero. Data on DR pin is ignored. To power up or power down each receive channel, Configuration Register and the corresponding Time Slot Register must be programmed. 5 IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN INDUSTRIAL TEMPERATURE RANGE corresponding 8-bit Gain Adjustment Registers: MSB GA Register, which stores the 7 Most Significant bits of gain adjustment coefficient; and LSB GA Register, which stores the 7 Least Significant bits of gain adjustment coefficient. All Gain Adjustment Registers start with ‘0’. Gain Adjustment Registers can be accessed by specifying the channel address (CR.3 and CR.2) in Configuration Register. If CR[6:4] = ‘100’, CR.0 = ‘1’ and the leading data bit on CI pin is ‘0’ in a microprocessor write cycle, the 8-bit data on CI pin is latched into the selected MSB GA Register with MSB first; If CR[6:4] = ‘100’, CR.0 = ‘0’ and the leading data bit on CI pin is ‘0’ in a microprocessor write cycle, the 8-bit data on CI pin is latched into the selected LSB GA Register with MSB first. All microprocessor cycles are either write cycles or read cycles. In typical applications, the microprocessor will write control registers as ordered pairs for CODEC Mode programming (Figure 2), SLIC Mode programming (Figure 3), or Gain Mode programming (Figure 4). The first write in the pair is to Configuration Register. This is identified by a leading ‘1’ on CI pin. If CR.6 = ‘0’ after writing Configuration Register, the programming is for CODEC mode and the succeeding operation is a write cycle with a leading ‘0’ on CI pin. The write is intended for the selected Time Slot Register. The timing diagram for CODEC Mode programming is shown in Figure 11. If CR.6 = ‘1’ and CR.5 = ‘0’ and CR.4 = ‘1’ after writing Configuration Register, the programming is for SLIC control function and the succeeding operation is a read/write cycle. The write, also with a leading ‘0’ on CI pin, is intended for the selected SLIC Control Register, while the simultaneous read is from the SLIC Status Register of the same channel. The timing diagram for SLIC Mode programming is shown in Figure 10. If CR.6 = ‘1’, CR.5 = ‘0’ and CR.4 = ‘0’ after writing Configuration Register, the programming is for Gain adjustment function and the succeeding operation is a write cycle with a leading ‘0’ on CI pin. The write is intended for the selected Gain Adjustment Register. The timing diagram for Gain Mode programming is shown in Figure 13. Configuration Register, Time Slot Registers, SLIC Control Registers and Gain Adjustment Registers are write only registers while SLIC Status Registers are read only registers. Refer to Figure 12 for the detail timing of the Serial Control Interface. An alternative method of receiving data from SLIC Status Register is designed for IDT821034. This procedure is initiated when a ‘1111-1110’ command appears on CI. To read from the SLIC Status Registers when using this method, Configuration Register should be set to indicate the following operation is a SLIC programming, and then assert a ‘1111-1111’ command on CI. The data from SLIC Status Registers will clock out of CO pin on CCLK rising edges when CS is low. The timing diagram of this method is shown in Figure 14. When using this method, CO and CI pins can be connected together. Either CO or CI will be in high Z state, depending on the Serial Control Interface is in write cycle or read cycle. When a command of ‘1111-1101’ appears on CI, the device will terminate this procedure. CO Serial Control Interface CI CS CCLK Figure 1. Serial Control Interface Signals Configuration Register '1' '0' b5 b4 b3 b2 b1 b0 Register A/µ-Law Channel Indicator Select Address Timing CODEC Transmit/Receive Mode Mode Select Time Slot Register '0' b6 b5 b4 Register Indicator b3 b2 b1 b0 Time Slot Figure 2. Registers for CODEC Mode Programming Configuration Register '1' '1' Register Indicator SLIC Control Register '0' Register Indicator SLIC Status Register b7 '0' '1' SLIC Mode b6 b5 b5 b2 Channel Address b4 Reserved b6 b3 b3 b2 b1 b0 I/O Configuration b1 b0 Output Data b4 b3 '0' '0' '0' Image Data Figure 3. Registers for SLIC Mode Programming Configuration Register '1' '1' Register Indicator Gain Adjustment Register '0' Register Indicator '0' '0' Gain Mode b6 b5 b3 b2 b1 b0 Channel MSB/LSB Address Transmit/ Receive b4 b3 b2 b1 b0 7 bits of Gain Adjustment Coefficient Figure 4. Registers for Gain Mode Programming 6 IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN Bit Name CR.7 CR.6 CR.5 Value Register Indicator CR.1 CR.0 Description Always ‘1’ Mode Select 1 Mode Select 0 00 01 10 11 µ-Law CODEC Mode (This is global setting for all channels.) A-Law CODEC Mode (This is global setting for all channels.) SLIC/Gain Mode Reserved (This mode should not be programmed for normal operation.) CODEC Mode (CR.6 = ‘0’) Timing Mode Select 0 1 Non-delay Mode (This is global setting for all channels.) Delay Mode (This is global setting for all channels.) SLIC/Gain Mode (CR.6 = ‘1’) SLIC/Gain Mode Select 0 1 Gain Mode SLIC Mode 00 01 10 11 Select Channel 0 for CODEC or SLIC programming Select Channel 1 for CODEC or SLIC programming Select Channel 2 for CODEC or SLIC programming Select Channel 3 for CODEC or SLIC programming CODEC Mode (CR.6 = ‘0’) Transmitter Select Receiver Select 00 01 10 11 Channel power down Channel power up with receive time slot assignment Channel power up with transmit time slot assignment Channel power up with both receive and transmit time slot assignment SLIC Mode (CR.6 = ‘1’, CR.4 = ‘1’) I/O_1 Configuration I/O_0 Configuration 00 01 10 11 Configure I/O_1 as an output pin and I/O_0 as an output pin Configure I/O_1 as an output pin and I/O_0 as an input pin Configure I/O_1 as an input pin and I/O_0 as an output pin Configure I/O_1 as an input pin and I/O_0 as an input pin CR.1: Transmit/Receive Select 0 1 Receive gain will be adjusted Transmit gain will be adjusted 0 Indicates the following 8 bits contain the 7 Least Significant bits of gain adjustment coefficient Indicates the following 8 bits contain the 7 Most Significant bits of gain adjustment coefficient CR.4 CR.3 CR.2 INDUSTRIAL TEMPERATURE RANGE Channel Address 1 Channel Address 0 Gain Mode (CR.6 = ‘1’, CR.4 = ‘0’) CR.0: MSB/LSB Select 1 Table 1. Description of Configuration Register Bit 7 6 5 4 3 2 1 0 Name Description Always ‘0’ Bit 6-0 indicate which time slot is selected for the transmit/receive channel. Time Slot 0 is aligned to FS. Register Indicator Time Slot Bit 6 Time Slot Bit 5 Time Slot Bit 4 Time Slot Bit 3 Time Slot Bit 2 Time Slot Bit 1 Time Slot Bit 0 Table 2. Definition of Time Slot Register BCLK Frequency Number of Time Slot 512 kHz 8 1.544 MHz 24 2.048 MHz 32 4.096 MHz 64 Table 3. Relationship between BCLK Frequency and Time Slot Number 7 8.192 MHz 128 IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN Bit INDUSTRIAL TEMPERATURE RANGE Name Description 7 Register Indicator Always ‘0’ 6 -- Reserved, always ‘0’ 5 -- Reserved, always ‘0’ 4 O_4 Data Output data on O_4 pin of the selected channel 3 O_3 Data Output data on O_3 pin of the selected channel 2 O_2 Data Output data on O_2 pin of the selected channel 1 I/O_1 Data Output data on I/O_1 pin (if defined as an output) of the selected channel 0 I/O _0 Data Output data on I/O_0 pin (if defined as an output) of the selected channel Table 4. Definition of SLIC Control Register Bit Name Description 7 I/On_0 Image Mapped to I/On_0 pin of the selected channel n 6 I/On_1 Image Mapped to I/On_1 pin of the selected channel n 5 On_2 Image Mapped to On_2 pin of the selected channel n 4 On_3 Image Mapped to On_3 pin of the selected channel n 3 On_4 Image Mapped to On_4 pin of the selected channel n 2 I/O1_0 Image Always mapped to the I/O1_0 pin 1 I/O2_0 Image Always mapped to the I/O2_0 pin 0 I/O3_0 Image Always mapped to the I/O3_0 pin Table 5. Definition of SLIC Status Register APPLICATION NOTE The IDT821034 is mainly used in line card application. Figure 5 shows a typical system with telephony line interface. The IDT821034 offers not only encoding/decoding function, but also a signaling channel, which can simplify the circuit design of the control interface. In addition, the dynamic time slot assignment of IDT821034 reduces the hardware requirement for PCM interface. The device also supports 8.192 Mbps PCM data rate, which can increase the time slot density up to 128. Signal to total distortion ratio (both STDX and STDR) are guaranteed over -55 dBm0 to +3 dBm0 range with a specific gain setting (0 dB for both transmit path and receive path). Since there is a finite noise floor associated with the quantization effect of both data converters and digital filter coefficients, the overall signal to total distortion ratio of each path is a function of the gain setting. In system design, attention should be paid to the gain setting for the best signal to total distortion performance. Generally, a channel gain of a line-card system is contributed by both SLIC and CODEC. In a system design using IDT821034, the SLIC gain should be taken into account to optimize the SNR. In the transmit path of IDT821034, there are two resistors (R1 and R3 in Figure 5) which enable the analog gain to be adjusted around 0 dB. Further gain adjustment can be obtained by programming the DSP filters. Since this adjustment is close to 0 dB, the SNR remains at the optimum value. In the receive path of IDT821034, analog gain adjustment is not available. Thus, the adjustment of CODEC gain will be performed only by programming the DSP filters. In this way, the SLIC gain should be such that the DSP gain is closest to 0 dB. This will maximize the achievable SNR in the overall system. For example, if the design target for receive path gain is -3.5 dB and -7 dB for local and long distance calls respectively, the recommended solution is to set SLIC gain at -3.5 dB. As a result, the gain of CODEC, which is adjusted by programming DSP coefficients, will be 0 dB and -3.5 dB. 8 Ring Test BUS K3 K2 5Ω 5Ω 100 Ω K1 100 Ω 100 Ω protector 9 line reverse V4in K1 K2 off / on hook SLIC V4out K3 R2 R3 R1 2k 2k 2k VCC 0.1µF 0.1µF 68K Figure 5. Typical Application Circuit Note: 1. Recommended value for R1 is between 40 kΩ and 100 kΩ . 2. The value of R3 is chosen to implement the desired transmit gain. The CODEC Transmit Gain = R1/R3. 3. The value of R2 is chosen to cancel the echo due to hybrid and impedance mismatch. Assume the receive level is VFRO(t) and the 4-line output with SLIC input properly terminated is V4out(t), the value of R2 should be chosen as follows: VFRO(t)/R2 = V4out(t)/R3 CH0 Tip 100 Ω O0_4 O0_3 O0_2 I/O0_1 I/O0_0 VFRO VFXI GSX0 GNDA VDDA I D T 8 2 1 0 3 4 VDD FS TSX DX DR GND CS CI CCLK CO BCLK MCLK CNF 6 Control Bus Ring BUS +5V SUPPLY 4 IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN INDUSTRIAL TEMPERATURE RANGE PCM Bus IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN ABSOLUTE MAXIMUM RATINGS Rating Power Supply Voltage Voltage on Any Pin with Respect to Ground Package Power Dissipation Storage Temperature Total SLIC Control pins output current per device Source from VDD : Sink from GND: Com’I & Ind’I ≤ 6.5 -0.5 to 5.5 Unit V V ≤ 600 -65 to +150 mW °C 50 50 mA INDUSTRIAL TEMPERATURE RANGE RECOMMENDED DC OPERATING CONDITIONS Parameter Operating Temperature Power Supply Voltage Min. -40 4.75 Typ. Max. +85 5.25 Unit °C V NOTE: MCLK: 2.048 MHz, 4.096 MHz or 8.192 MHz with tolerance of ± 50 ppm NOTE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ELECTRICAL CHARACTERISTICS Digital Interface Parameter VIL VIH VOL V OH II I OZ CI Description Input Low Voltage Input High Voltage Output Low Voltage Min Typ Max 0.8 2.0 0.4 Output High Voltage VDD - 0.2 -10 -10 Test Conditions All digital inputs All digital inputs DX, TSX, CO, IL = 14 mA 0.8 V All other digital outputs, IL = 4 mA. 0.2 V All digital pins, IL = 1 mA. V DX, CO, IH = -7 mA. All other digital outputs, IH = -4 mA. All digital pins, IH = -1 mA All digital inputs, GND<VIN<VDD DX VDD - 0.6 Input Current Output Current in High-impedance State Input Capacitance Units V V V 10 10 5 V µA µA pF Note: The I/O_n and O_n outputs are resistive for less than a 0.8 V drop. Total current must not exceed absolute maximum ratings. Power Dissipation Parameter IDD1 IDD0 Description Operating Current Standby Current Min Typ 25 4 Max 40 6 Note: Power measurements are made at MCLK = 4.096 MHz, outputs unloaded. 10 Units mA mA Test Conditions All channels are active. All channels are powered down, with MCLK present. IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN INDUSTRIAL TEMPERATURE RANGE Analog Interface Parameter V FXI VFRO1 VFRO2 RI RG RO RL II IZ CG CL AV fU Description Input Voltage, VFXI Output Voltage, VFRO Output Voltage Swing, VFRO Input Resistance, VFXI Load Resistance, GSX Output Resistance VFRO Load Resistance, VFRO Input Leakage Current, VFXI Output Leakage Current, VFRO Load Capacitance, GSX Load Capacitance, VFRO DC Voltage Gain, VFXI to GSX Unity Gain Bandwidth, VFXI to GSX Min 2.3 2.25 3.25 2.0 10 Typ 2.4 2.4 Max 2.55 2.6 Units V V Vp-p MΩ kΩ Ω Ω µA µA pF pF 20 2000 -1.0 -10 5000 1 1.0 10 50 100 3 Test Conditions Alternating ±zero µ-law PCM code applied to DR RL = 2000 Ω 0.25 V < VFXI < 4.75 V 0 dBm0, 1020 Hz PCM code applied to DR. External loading 0.25 V < VFXI < VDD -0.25 V Power down External loading MHz TRANSMISSION CHARACTERISTICS 0 dBm0 is defined as 0.775 Vrms for A-law and 0.769 Vrms for µ-law, both for 600 W load. Unless otherwise noted, the analog input is a 0 dBm0, 1020 Hz sine wave; the input amplifier is set for unity gain. The digital input is a PCM bit stream equivalent to that obtained by passing a 0 dBm0, 1020 Hz sine wave through an ideal encoder. The output level is sin(x)/x-corrected. Absolute Gain Parameter GXA GRA Description Transmit Gain, Absolute Receive Gain, Absolute Typ 0.00 -0.15 Deviation ± 0.25 ± 0.25 Units dB dB Test Conditions Signal input of 0 dBm0, µ-law or A-law Measured relative to 0 dBm0, µ-law or A-law, PCM input of 0 dBm0 1020 Hz , RL = 10 kΩ Gain Tracking Parameter GTX GTR Description Transmit Gain Tracking +3 dBm0 to - 40 dBm0 -40 dBm0 to -50 dBm0 -50 dBm0 to -55 dBm0 Receive Gain Tracking +3 dBm0 to - 40 dBm0 -40 dBm0 to -50 dBm0 -50 dBm0 to -55 dBm0 Min Typ Max Units -0.10 -0.25 -0.50 0.10 0.50 0.50 dB dB dB -0.10 -0.25 -0.50 0.10 0.50 0.50 dB dB dB Test Conditions Tested by Sinusoidal Method, µ-law/Alaw Tested by Sinusoidal Method, µ-law/Alaw Frequency Response Parameter GXR GRR Description Transmit Gain, Relative to GXA f = 50 Hz f = 60 Hz f = 300 Hz to 3400 Hz f = 3600 Hz f = 4600 Hz and above Receive Gain, Relative to GRA f below 300 Hz f = 300 Hz to 3400 Hz f = 3600 Hz f = 4600 Hz and above Min Typ -0.15 -0.15 11 Max Units -40 -40 0.15 -0.1 -35 dB dB dB dB dB 0 0.15 -0.2 -35 dB dB dB dB Test Conditions IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN INDUSTRIAL TEMPERATURE RANGE Group Delay Parameter DXA DXR DRA DRR Description Transmit Delay, Absolute * Transmit Delay, Relative to 1800 Hz f = 500 Hz – 600 Hz f = 600 Hz –1000 Hz f = 1000 Hz – 2600 Hz f = 2600 Hz – 2800 Hz Min Typ Receive Delay, Absolute * Receive Delay, Relative to 1800 Hz f = 500 Hz – 600 Hz f = 600 Hz –1000 Hz f = 1000 Hz – 2600 Hz f = 2600 Hz – 2800 Hz Max 340 Units µs 280 150 80 280 260 µs µs µs µs µs 50 80 120 150 µs µs µs µs Test Conditions Note*: Minimum value in transmit and receive path. Distortion Parameter STDX SFDX Description Transmit Signal to Total Distortion Ratio Input level = 0 dBm0 Input level = -30 dBm0 Input level = -40 dBm0 Input level = -45 dBm0 Receive Signal to Total Distortion Ratio Input level = 0 dBm0 Input level = -30 dBm0 Input level = -40 dBm0 Input level = -45 dBm0 Single Frequency Distortion, Transmit SFDR Single Frequency Distortion, Receive -42 dBm0 IMD Intermodulation Distortion -50 dBm0 Max 18 -68 12 -78 -53 Units dBrnC0 dBm0p dBrnC0 dBm0p dBm0 STDR Min Typ* Max Units 36 36 30 24 dB dB dB dB 36 36 30 24 -42 dB dB dB dB dBm0 Test Conditions ITU-T O.132 Sine Wave Method (C-message weighted for µ-law; Psophometrically weighted for Alaw) ITU-T O.132 Sine Wave Method (C-message weighted for µ-law; Psophometrically weighted for Alaw) 200 Hz - 3400 Hz, 0 dBm0 input, output any other single frequency ≤ 3400 Hz 200 Hz - 3400 Hz, 0 dBm0 input, output any other single frequency ≤ 3400 Hz Four Tone Method Noise Parameter NXC NXP NRC NRP NRS PSRX PSRR SOS Description Transmit Noise, C Message Weighted for µ-law Transmit Noise, P Message Weighted for A-law Receive Noise, C Message Weighted for µ-law Receive Noise, P Message Weighted for A-law Noise, Single Frequency f = 0 kHz – 100 kHz Power Supply Rejection Transmit f = 300 Hz – 3.4 kHz f = 3.4 kHz – 20 kHz Power Supply Rejection Receive f = 300 Hz – 3.4 kHz f = 3.4 kHz – 20 kHz Spurious Out-of-Band Signals at VFRO Relative to Input PCM code applied: 4600 Hz – 20 kHz 20 kHz – 50 kHz Min Typ Test Conditions VFXI = 0 Vrms, tested at VFRO VDD = 5.0 VDC + 100 mVrms 40 25 dB dB 40 25 dB dB PCM code is positive one LSB, VDD = 5.0 VDC + 100 mVrms 0 dBm0, 300 Hz – 3400 Hz input -40 -30 12 dB dB IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN INDUSTRIAL TEMPERATURE RANGE Interchannel Crosstalk Parameter XTX-R Description Transmit to Receive Crosstalk XTR-X Min Typ -85 Max -78 Units dB Receive to Transmit Crosstalk -85 -80 dB XT X-X Transmit to Transmit Crosstalk -85 -78 dB XTR-R Receive to Receive Crosstalk -85 -80 dB Test Conditions 300 Hz – 3400 Hz, 0 dBm0 signal into VFXI of interfering channel. Idle PCM code into channel under test. 300 Hz – 3400 Hz, 0 dBm0 PCM code into interfering channel. VFXI = 0 Vrms for channel under test. 300 Hz – 3400 Hz, 0 dBm0 signal into VFXI of interfering channel. VFXI = 0 Vrms for channel under test. 300 Hz – 3400 Hz, 0 dBm0 PCM code into interfering channel. Idle PCM code into channel under test. Note: Crosstalk into the transmit channels (VFXI) can be significantly affected by parasitic capacitive coupling from GSX and VFRO outputs. PCB layouts should be arranged to minimize these parasitics. The resistor value of Rf (from GSX to VFXI) should be kept as low as possible to minimize crosstalk. The limits given above are based on Rf < 200 kΩ. Intrachannel Crosstalk Parameter XTX-R Description Transmit to Receive Crosstalk XTR-X Receive to Transmit Crosstalk Min Typ -80 Max -70 Units dB -80 -70 dB Test Conditions 300 Hz – 3400 Hz, 0 dBm0 signal into VFXI. Idle PCM code into DR. 300 Hz – 3400 Hz, 0 dBm0 PCM code into DR. VFXI = 0 Vrms. Note: Crosstalk into the transmit channels (VFXI) can be significantly affected by parasitic capacitive coupling from GSX and VFRO outputs. PCB layouts should be arranged to minimize these parasitics. The resistor value of Rf (from GSX to VFXI) should be kept as low as possible to minimize crosstalk. The limits given above are based on Rf < 200 kΩ. 13 IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN INDUSTRIAL TEMPERATURE RANGE TIMING CHARACTERISTICS Clock Parameter t1 t2 t3 t4 t5 Description BCLK Duty Cycle BCLK Rise and Fall Time MCLK Duty Cycle MCLK Rise and Fall Time CCLK Rise and Fall Time Min 40 Typ Max 60 15 60 15 15 40 Units % ns % ns ns Test Conditions BCLK = 512 kHz to 8.192 MHz BCLK = 512 kHz to 8.192 MHz MCLK = 2.048 MHz, 4.096 MHz or 8.192 MHz MCLK = 2.048 MHz, 4.096 MHz or 8.192 MHz CCLK ≤ 8.192 MHz Transmit Parameter t11 t12 t13 t14 t15 t16 t17 t21 t22 Description Data Enabled Delay Time Data Delay Time from BCLK Data Float Delay Time Frame sync Hold Time Frame sync High Setup Time TSX Enable Delay Time TSX Disable Delay Time Receive Data Setup Time Receive Data Hold Time Min Typ 3 25 25 Max 25 25 8 25 25 30 15 Note: Timing parameter t12 is referenced to a high-impedance state. MCLK t4 t4 Figure 6. MCLK Timing 14 Units ns ns ns ns ns ns ns ns ns Test Conditions CLOAD = 100 pF CLOAD = 100 pF CLOAD = 0 pF CLOAD = 100 pF CLOAD = 100 pF IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN INDUSTRIAL TEMPERATURE RANGE Time Slot BCLK 1 2 3 t14 4 5 t2 t15 6 7 8 1 t2 FS DX t13 t12 t11 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 DR BIT 2 BIT 7 BIT 8 t22 t21 BIT 1 BIT 6 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 t16 t17 TSX Figure 7. Transmit and Receive Timing in Delay Mode Time Slot BCLK 1 2 3 4 5 t2 t15 6 7 8 1 t2 FS DX t13 t12 t11 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 1 BIT 2 BIT 7 BIT 8 t22 t21 DR BIT 6 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 t17 t16 TSX Figure 8. Transmit and Receive Timing in Non-Delay Mode 15 IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN INDUSTRIAL TEMPERATURE RANGE Time Slot 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 FS DX X0 X1 DR R0 X2 R1 X3 R2 R3 TSX Figure 9. Typical Frame Sync Timing (2 MHz Operation) Serial Control Interface Timing Parameter t31 t32 t33 t34 t35 t36 t37 t38 Description CS Hold Time CS Setup Time CS to CO Valid Delay Time CO Float Delay Time CI Setup Time CI Hold Time CS Idle Time CCLK to CO Valid Delay Time Min 30 30 Typ Max 30 10 30 30 3 30 Units ns ns ns ns ns ns cycles of CCLK ns Test Conditions CCLK CS CI Note * 7 t37 Note * 6 5 4 3 2 1 0 CO 7 6 5 7 6 5 I/On_0 I/On_1 On_2 Figure 10. SLIC Programming Mode Timing Note *: CCLK should have one cycle before CS goes low, and two cycles after CS goes high. 16 4 3 2 1 0 4 3 2 1 0 On_3 On_4 I/O1_0 I/O2_0 I/O3_0 IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN INDUSTRIAL TEMPERATURE RANGE CCLK t37 CS CI 7 6 5 4 3 2 1 7 0 6 5 4 3 2 1 0 CO (High Z) Figure 11. CODEC Programming Mode Timing t31 CCLK t32 t5 t5 t31 CS t32 t38 t33 CO t35 t36 CI Figure 12. Serial Control Interface Timing 17 t34 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 18 CO CI CS CCLK 7 5 4 3 2 1 0 7 6 t37 7 6 5 4 3 2 1 0 6 5 4 I/On_0 I/On_1 On_2 7 5 3 2 2 1 1 0 0 Note * On_3 On_4 I/O1_0 I/O2_0 I/O3_0 4 3 t37 Figure 14. Timing Diagram of the Alternative Method to Read From SLIC Status Register 6 0 Figure 13. Gain Programming Mode Timing Note * t37 Note *: Whether MSB GA Register is accessed first or LSB GA Register is accessed can be ignored. CO (High Z) CI CS CCLK 7 6 5 4 3 2 1 0 IDT821034 QUAD PCM CODEC WITH PROGRAMMABLE GAIN INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XXXXXX Device Type XX X Package Process/ Temperature Range Blank Industrial (-40 °C to +85 °C) DN Plastic Quad Flat Pack (PQFP, DN52) 821034 Quad PCM CODEC with Programmable Gain Data Sheet Document History 01/16/2002 01/08/2003 05/13/2003 pgs. 1, 4-8, 10 pgs. 1, 19 pgs. 2, 5, 8, 15, 16, 18 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* 19 for Tech Support: 408-330-1552 email: [email protected]