Freescale IMX53AEC Automotive and infotainment applications processor Datasheet

Freescale Semiconductor
Data Sheet: Advance Information
Document Number: IMX53AEC
Rev. 2, 5/2011
MCIMX53xA
i.MX53xA Automotive and
Infotainment Applications
Processors
Package Information
Plastic Package
Case TEPBGA-2 19 x 19 mm, 0.8 mm pitch
Ordering Information
See Table 1 on page 3
1
Introduction
The MCIMX53xA (i.MX53xA) automotive
infotainment processor is Freescale Semiconductor’s
latest addition to a growing family of
multimedia-focused products offering high performance
processing with a high degree of functional integration
aimed at the growing automotive infotainment,
telematics, HMI, and display-based cluster markets. This
device includes 3D and 2D graphics processors, 1080i/p
video processing, and dual display, and provides a
variety of interfaces.
The i.MX53xA processor features Freescale’s advanced
implementation of the ARM™ core, which operates at
clock speeds as high as 800 MHz and interfaces with
DDR2/LVDDR2-800, LPDDR2-800, or DDR3-800
DRAM memories. This device is well suited for
graphics rendering for HMI, navigation, high
performance speech processing with large databases,
video processing and display, audio playback, and many
other applications.
1.
2.
3.
4.
5.
6.
7.
The flexibility of the i.MX53xA architecture allows for
its use in a wide variety of applications. As the heart of
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© 2011 Freescale Semiconductor, Inc. All rights reserved.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 3
1.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1. Special Signal Considerations . . . . . . . . . . . . . . . 17
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1. Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . 17
4.2. Power Supplies Requirements and Restrictions . 24
4.3. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 27
4.4. Output Buffer Impedance Characteristics . . . . . . 34
4.5. I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 38
4.6. System Modules Timing . . . . . . . . . . . . . . . . . . . . 45
4.7. External Peripheral Interfaces Parameters . . . . . . 67
4.8. XTAL Electrical Specifications . . . . . . . . . . . . . . 148
Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . 149
5.1. Boot Mode Configuration Pins . . . . . . . . . . . . . . 149
5.2. Boot Devices Interfaces Allocation . . . . . . . . . . . 150
5.3. Power setup during Boot . . . . . . . . . . . . . . . . . . 151
Package Information and Contact Assignments . . . . . 152
6.1. 19x19 mm Package Information . . . . . . . . . . . . . 152
6.2. 19 x 19 mm, 0.8 Pitch Ball Map . . . . . . . . . . . . . 171
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Introduction
the application chipset, the i.MX53xA processor provides all the interfaces for connecting peripherals,
such as WLAN, Bluetooth™, GPS, hard drive, camera sensors, and dual displays.
Features of the i.MX53xA processor include the following:
• Multilevel memory system—The multilevel memory system of the i.MX53xA is based on the L1
instruction and data caches, L2 cache, internal and external memory. The i.MX53xA supports
many types of external memory devices, including DDR2, low voltage DDR2, LPDDR2, DDR3,
NOR Flash, PSRAM, cellular RAM, NAND Flash (MLC and SLC), OneNAND™, and managed
NAND including eMMC up to rev 4.4.
• Smart speed technology—The i.MX53xA device has power management throughout the IC that
enables the rich suite of multimedia features and peripherals to consume minimum power in both
active and various low power modes. Smart speed technology enables the designer to deliver a
feature-rich product requiring levels of power far lower than industry expectations.
• Multimedia powerhouse—The multimedia performance of the i.MX53xA processor ARM core is
boosted by a multilevel cache system, Neon (including advanced SIMD, 32-bit single-precision
floating point support) and vector floating point coprocessors. The system is further enhanced by
a multistandard hardware video codec, autonomous image processing unit (IPU), and a
programmable smart DMA (SDMA) controller.
• Powerful graphics acceleration— The i.MX53xA processors provide two independent, integrated
graphics processing units: an OpenGL® ES 2.0 3D graphics accelerator (33 Mtri/s, 200 Mpix/s,
and 800 Mpix/s z-plane performance) and an OpenVG™ 1.1 2D graphics accelerator
(200 Mpix/s).
• Interface flexibility—The i.MX53xA processor supports connection to a variety of interfaces,
including LCD controller for two displays and CMOS sensor interface, high-speed USB on-the-go
with PHY, plus three high-speed USB hosts, multiple expansion card ports (high-speed
MMC/SDIO host and others), 10/100 Ethernet controller, and a variety of other popular interfaces
(PATA, UART, I2C, and I2S serial audio, among others).
• Automotive environment support—Includes interfaces such as two CAN ports, an MLB port, an
ESAI audio interface, and an asynchronous sample rate converter for multichannel/multisource
audio.
• Advanced security—The i.MX53xA processors deliver hardware-enabled security features that
enable secure e-commerce, digital rights management (DRM), information encryption, secure
boot, and secure software downloads. For detailed information about the i.MX53xA security
features contact a Freescale representative.
The i.MX53xA application processor is a follow-on to the i.MX51xA, with improved performance, power
efficiency, and multimedia capabilities.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
2
Freescale Semiconductor
Introduction
1.1
Ordering Information
Table 1 provides ordering information.
Table 1. Ordering Information
Part Number1
Mask Set
Features
Notes
Package2
MCIMX536AVV8C
N78C
800 MHz, full feature set
—
19 x 19 mm, 0.8 mm pitch BGA
Case TEPBGA-2
PCIMX536AVV8C
N78C
800 MHz, full feature set
—
19 x 19 mm, 0.8 mm pitch BGA
Case TEPBGA-2
MCIMX534AVV8C
N78C
800 MHz, no hardware video
codecs
—
19 x 19 mm, 0.8 mm pitch BGA
Case TEPBGA-2
1
2
Part numbers with a PC prefix indicate non production engineering parts.
Case TEPBGA-2 is RoHS compliant, lead-free MSL (moisture sensitivity level) 3.
1.2
Features
The i.MX53xA multimedia applications processor (AP) is based on the ARM Platform, which has the
following features:
• MMU, L1 instruction and L1 data cache
• Unified L2 cache
• Target frequency of the core (including Neon, VFPv3 and L1 cache): 800 MHz
• Neon coprocessor (SIMD media processing architecture) and vector floating point (VFP-Lite)
coprocessor supporting VFPv3
• TrustZone
The memory system consists of the following components:
• Level 1 cache:
— Instruction (32 Kbyte)
— Data (32 Kbyte)
• Level 2 cache:
— Unified instruction and data (256 Kbyte)
• Level 2 (internal) memory:
— Boot ROM, including HAB (64 Kbyte)
— Internal multimedia/shared, fast access RAM (128 Kbyte)
— Secure/non-secure RAM (16 Kbyte)
• External memory interfaces:
— 16/32-bit DDR2-800, LV-DDR2-800 or DDR3-800 up to 2 Gbyte
— 32-bit LPDDR2
— 8/16-bit NAND SLC/MLC Flash, up to 66 MHz, 4/8/14/16-bit ECC
— 8/16-bit NOR Flash, PSRAM, and cellular RAM.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
3
Introduction
— 32-bit multiplexed mode NOR Flash, PSRAM & cellular RAM.
— 8-bit Asynchronous (DTACK mode) EIM interface.
— All EIM pins are muxed on other interfaces (data with NFC pins). I/O muxing logic selects EIM
port, as primary muxing at system boot.
— Samsung OneNAND™ and managed NAND including eMMC up to rev 4.4 (in muxed I/O
mode)
The i.MX53xA system is built around the following system on chip interfaces:
• 64-bit AMBA AXI v1.0 bus—used by ARM platform, multimedia accelerators (such as VPU, IPU,
GPU3D, GPU2D) and the external memory controller (EXTMC) operating at 200 MHz.
• 32-bit AMBA AHB 2.0 bus—used by the rest of the bus master peripherals operating at 133 MHz.
• 32-bit IP bus—peripheral bus used for control (and slow data traffic) of the most system peripheral
devices operating at 66 MHz.
The i.MX53xA makes use of dedicated hardware accelerators to achieve state-of-the-art multimedia
performance. The use of hardware accelerators provides both high performance and low power
consumption while freeing up the CPU core for other tasks.
The i.MX53xA incorporates the following hardware accelerators:
• VPU, version 3—video processing unit
• GPU3D—3D graphics processing unit, OpenGL ES 2.0, version 3, 33 Mtri/s, 200 Mpix/s, and
800 Mpix/s z-plane performance, 256 Kbyte RAM memory
• GPU2D—2D graphics accelerator, OpenVG 1.1, version 1, 200 Mpix/s performance,
• IPU, version 3M—image processing unit
• ASRC—asynchronous sample rate converter
The i.MX53xA includes the following interfaces to external devices:
NOTE
Not all interfaces are available simultaneously, depending on I/O
multiplexer configuration.
•
•
•
Hard disk drives:
— PATA, up to U-DMA mode 5, 100 MByte/s
— SATA I, 1.5 Gbps
Displays:
— Five interfaces available. Total rate of all interfaces is up to 180 Mpixels/s, 24 bpp. Up to two
interfaces may be active at once.
— Two parallel 24-bit display ports. The primary port is up to 165 Mpix/s (for example,
UXGA at 60 Hz).
— LVDS serial ports: one dual channel port up to 165 Mpix/s or two independent single channel
ports up to 85 MP/s (for example, WXGA at 60 Hz) each.
— TV-out/VGA port up to 150 Mpix/s (for example, 1080p60).
Camera sensors:
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
4
Freescale Semiconductor
Introduction
•
•
•
•
— Two parallel 20-bit camera ports. Primary up to 180-MHz peak clock frequency, secondary up
to 120-MHz peak clock frequency.
Expansion cards:
— Four SD/MMC card ports: three supporting 416 Mbps (8-bit i/f) and one enhanced port
supporting 832 Mbps (8-bit, eMMC 4.4).
USB
— High-speed (HS) USB 2.0 OTG (up to 480 Mbps), with integrated HS USB PHY
— Three USB 2.0 (480 Mbps) hosts:
– High-speed host with integrated on-chip high-speed PHY
– Two high-speed hosts for external HS/FS transceivers through ULPI/serial, support IC-USB
Automotive environment interfaces:
— Two controller area network (FlexCAN) interfaces, 1 Mbps each
— Media local bus or MediaLB (MLB) provides interface to most networks (50 Mbps)
— Enhanced serial audio interface (ESAI), up to 1.4 Mbps each channel
Miscellaneous interfaces:
— One-wire (OWIRE) port
— Three I2S/SSI/AC97 ports, supporting up to 1.4 Mbps, each connected to audio multiplexer
(AUDMUX) providing four external ports.
— Five UART RS232 ports, up to 4.0 Mbps each. One supports 8-wire, the other four support
4-wire.
— Two high speed enhanced CSPI (ECSPI) ports plus one CSPI port
— Three I2C ports, supporting 400 kbps
— Fast Ethernet controller, IEEE1588 V1 compliant, 10/100 Mbps
— Sony Phillips Digital Interface (SPDIF), Rx and Tx
— Key pad port (KPP)
— Two pulse-width modulators (PWM)
— GPIO with interrupt capabilities
The system supports efficient and smart power control and clocking:
• Power gating SRPG (State Retention Power Gating) for ARM core and Neon
• Support for various levels of system power modes
• Flexible clock gating control scheme
• On-chip temperature monitor
• On-chip oscillator amplifier supporting 32.768 kHz external crystal
• On-chip LDO voltage regulators for PLLs
Security functions are enabled and accelerated by the following hardware:
• ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, and so
on)
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
5
Introduction
•
•
•
•
•
•
•
Secure JTAG controller (SJC)—Protecting JTAG from debug port attacks by regulating or blocking
the access to the system debug features
Secure real-time clock (SRTC)—Tamper resistant RTC with dedicated power domain and
mechanism to detect voltage and clock glitches
Real-time integrity checker, version 3 (RTICv3)—RTIC type1, enhanced with SHA-256 engine
SAHARAv4 Lite—Cryptographic accelerator that includes true random number generator
(TRNG)
Security controller, version 2 (SCCv2)—Improved SCC with AES engine, secure/non-secure
RAM and support for multiple keys as well as TZ/non-TZ separation
Central security unit (CSU)—Enhancement for the IIM (IC Identification Module). CSU is
configured during boot by e-fuses, and determines the security level operation mode as well as the
TrustZone (TZ) policy
Advanced High Assurance Boot (A-HAB)—HAB with the following embedded enhancements:
SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization
NOTE
The actual feature set depends on the part number as described in Table 1.
Functions such as video hardware acceleration with 2D and 3D hardware
graphics acceleration may not be enabled for specific part numbers.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
6
Freescale Semiconductor
Architectural Overview
2
Architectural Overview
The following subsections provide an architectural overview of the i.MX53xA processor system.
2.1
Block Diagram
Figure 1 shows the functional modules in the i.MX53xA processor system.
NOR/NAND Battery Ctrl
Flash
Device
SATA /
P-ATA
HDD
Internal
RAM
144 KB
TPIU
CTI (2)
Shared Peripherals
GPS
RF/IF
eSDHCv2 (3)
SSI
eSDHCv3
ECSPI
SJC
Security
UART
ESAI
SPDIF Rx/Tx
P-ATA
ASRC
SATA
+ Temp Mon
SAHARAv4
Lite
RF / IF
IC’s
RTICv3
TV-Encoder
SCCv2
CSU
TZIC
Clock and Reset
PLL (4)
CCM
SRC
ARM Cortex A8
Neon, VFPv3
L1 I/D cache
L2 cache 256 KB
ETM, CTI0,1
XTALOSC (2)
CAMP (2)
AP Peripherals
ECSPI
Timers
WDOG (2)
AUDMUX
I2C (3)
OWIRE
PWM (2)
3D Graphics
Proc. Unit
(GPU3D)
IOMUXC
KPP
IIM
G-Memory
256 KB
GPIOx32 (7)
2D Graphics
Proc. Unit
(GPU2D)
FlexCAN (2)
SSI (2)
Bluetooth
WLAN
FEC(IEEE1588)
MLB
USB PHY2
EPIT (2)
Keypad
FIRI
USB PHY1
GPT
IrDA
XVR
CSPI
UART (4)
Video
Proc. Unit
(VPU)
Fuse Box
Ethernet
10/100
Mbps
Temperature
Sensor
GPC
SRTC
Audio,
Power
Mngmnt.
LDB
Composite CVBS/ S-Video
Component RGB, YCC
(HD TV-Out / VGA)
ARM Cortex A8
Platform
Debug
DAP
SPBA
LCD
LCD
Display-1,2
Display (2)
Image Processing
Subsystem
(IPU)
Boot
ROM
64 KB
Smart DMA
(SDMA)
CAN i/f
LVDS
(WSXGA+)
Application Processor
Domain (AP)
External
Memory I/F
(EXTMC)
Digital
Audio
Camera
Camera
(2)
(2)
AXI and AHB Switch Fabric
DDR2/DDR3/
LPDDR2
JTAG
(IEEE1149.1)
MMC/SD
eMMC/eSD
USB OTG
(dev/host)
USB OTG +
3 HS Ports
Access.
Conn.
Figure 1. i.MX53xA System Block Diagram
NOTE
The numbers in brackets indicate number of module instances. For example,
PWM (2) indicates two separate PWM peripherals.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
7
Modules List
3
Modules List
The i.MX53xA processor contains a variety of digital and analog modules. Table 2 describes these
modules in alphabetical order.
Table 2. i.MX53xA Digital and Analog Blocks
Block
Mnemonic
Block Name
Subsystem
Brief Description
ARM
ARM Platform
ARM
The ARM Cortex A8TM Platform consists of the ARM processor version
r2p5 (with TrustZone) and its essential sub-blocks. It contains the 32 Kbyte
L1 instruction cache, 32 Kbyte L1 data cache, Level 2 cache controller and
a 256 Kbyte L2 cache. The platform also contains an event monitor and
debug modules. It also has a NEON coprocessor with SIMD media
processing architecture, a register file with 32/64-bit general-purpose
registers, an integer execute pipeline (ALU, Shift, MAC), dual
single-precision floating point execute pipelines (FADD, FMUL), a
load/store and permute pipeline and a non-pipelined vector floating point
(VFP Lite) coprocessor supporting VFPv3.
ASRC
Asynchronous
Sample Rate
Converter
Multimedia
Peripherals
The asynchronous sample rate converter (ASRC) converts the sampling
rate of a signal associated to an input clock into a signal associated to a
different output clock. The ASRC supports concurrent sample rate
conversion of up to 10 channels of about –120 dB THD+N. The sample rate
conversion of each channel is associated to a pair of incoming and outgoing
sampling rates. The ASRC supports up to three sampling rate pairs.
AUDMUX
Digital Audio
Multiplexer
Multimedia
Peripherals
The AUDMUX is a programmable interconnect for voice, audio, and
synchronous data routing between host serial interfaces (for example,
SSI1, SSI2, and SSI3) and peripheral serial interfaces (audio and voice
codecs). The AUDMUX has seven ports (three internal and four external)
with identical functionality and programming models. A desired connectivity
is achieved by configuring two or more AUDMUX ports.
CAMP-1
CAMP-2
Clock Amplifier
Clocks,
Clock amplifier
Resets, and
Power Control
CCM
Clock Control
Module
Global Power
Controller
System Reset
Controller
Clocks,
These modules are responsible for clock and reset distribution in the
Resets, and
system, as well as for system power management.
Power Control The system includes four PLLs.
CSPI
ECSPI-1
ECSPI-2
Configurable
SPI, Enhanced
CSPI
Connectivity
Peripherals
Full-duplex enhanced synchronous serial interface, with data rates
16-60 Mbit/s. It is configurable to support master/slave modes. In Master
mode it supports four slave selects for multiple peripherals.
CSU
Central Security
Unit
Security
The central security unit (CSU) is responsible for setting comprehensive
security policy within the i.MX53xA platform, and for sharing security
information between the various security modules. The security control
registers (SCR) of the CSU are set during boot time by the high assurance
boot (HAB) code and are locked to prevent further writing.
GPC
SRC
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
8
Freescale Semiconductor
Modules List
Table 2. i.MX53xA Digital and Analog Blocks (continued)
Block
Mnemonic
Block Name
Subsystem
DEBUG
Debug System
EXTMC
External Memory Connectivity
Controller
Peripherals
The EXTMC is an external and internal memory interface. It performs
arbitration between multi-AXI masters to multi-memory controllers, divided
into four major channels, fast memories (DDR2/DDR3/LPDDR2) channel,
slow memories (NOR-FLASH / PSRAM / NAND-FLASH etc.) channel,
internal memory (RAM, ROM) channel and graphical memory (GMEM)
channel.
In order to increase the bandwidth performance, the EXTMC separates the
buffering and the arbitration between different channels so parallel
accesses can occur. By separating the channels, slow accesses do not
interfere with fast accesses.
EXTMC Features:
• 64-bit and 32-bit AXI ports
• Enhanced arbitration scheme for fast channel, including dynamic master
priority, and taking into account which pages are open or closed and
what type (read or write) was the last access
• Flexible bank interleaving
• Support 16/32-bit DDR2-800 or DDR3-800 or LPDDR2.
• Support up to 2 GByte DDR memories.
• Support NFC, EIM signal muxing scheme.
• Support 8/16/32-bit Nor-Flash/PSRAM memories (sync and async
operating modes), at slow frequency. (8-bit is not supported on
D[23]-D[16]).
• Support 4/8/14/16-bit ECC, page sizes of 512-B, 2-KB and 4-KB
Nand-Flash (including MLC)
• Multiple chip selects (up to 4).
• Enhanced DDR memory controller, supporting access latency hiding
• Support watermark for security (internal and external memories)
EPIT-1
EPIT-2
Enhanced
Timer
Periodic Interrupt Peripherals
Timer
Each EPIT is a 32-bit “set and forget” timer that starts counting after the
EPIT is enabled by software. It is capable of providing precise interrupts at
regular intervals with minimal processor intervention. It has a 12-bit
prescaler for division of input clock frequency to get the required time
setting for the interrupts to occur, and counter values can be programmed
on the fly.
Enhanced Serial
Audio Interface
The enhanced serial audio interface (ESAI) provides a full-duplex serial port
for serial communication with a variety of serial devices, including
industry-standard codecs, SPDIF transceivers, and other processors.
The ESAI consists of independent transmitter and receiver sections, each
section with its own clock generator.
The ESAI has 12 pins for data and clocking connection to external devices.
ESAI
System
Control
Brief Description
Connectivity
Peripherals
The debug system provides real-time trace debug capability of both
instructions and data. It supports a trace protocol that is an integral part of
the ARM Real Time Debug solution (RealView).
Real-time tracing is controlled by specifying a set of triggering and filtering
resources, which include address and data comparators, three
cross-system triggers (CTI), counters, and sequencers.
debug access port (DAP) —The DAP provides real-time access for the
debugger without halting the core to system memory, peripheral register,
debug configuration registers and JTAG scan chains.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
9
Modules List
Table 2. i.MX53xA Digital and Analog Blocks (continued)
Block
Mnemonic
Block Name
ESDHCV3-3 Ultra-HighSpeed eMMC /
SD Host
Controller
Subsystem
Connectivity
Peripherals
ESDHCV2-1 Enhanced
ESDHCV2-2 Multi-Media Card
ESDHCv2-4 /
Secure Digital
Host Controller
Brief Description
Ultra high-speed eMMC / SD host controller, enhanced to support eMMC
4.4 standard specification, for 832 MBps.
• Port 3 is specifically enhanced to support eMMC 4.4 specification, for
double data rate (832 Mbps, 8-bit port).
ESDHCV3 is backward compatible to ESDHCV2 and supports all the
features of ESDHCV2 as described below.
Enhanced multimedia card / secure digital host controller
• Ports 1, 2, and 4 are compatible with the “MMC System Specification”
version 4.3, full support and supporting 1, 4 or 8-bit data.
The generic features of the eSDHCv2 module, when serving as SD / MMC
host, include the following:
• Can be configured either as SD / MMC controller
• Supports eSD and eMMC standard, for SD/MMC embedded type cards
• Conforms to SD Host Controller Standard Specification, version 2.0, full
support.
• Compatible with the SD Memory Card Specification, version 1.1
• Compatible with the SDIO Card Specification, version 1.2
• Designed to work with SD memory, miniSD memory, SDIO, miniSDIO,
SD Combo, MMC and MMC RS cards
• Configurable to work in one of the following modes:
- SD/SDIO 1-bit, 4-bit
- MMC 1-bit, 4-bit, 8-bit
• Full/high speed mode.
• Host clock frequency variable between 32 kHz to 52 MHz
• Up to 200 Mbps data transfer for SD/SDIO cards using 4 parallel data
lines
• Up to 416 Mbps data transfer for MMC cards using 8 parallel data lines
FEC
Fast Ethernet
Controller
Connectivity
Peripherals
The Ethernet media access controller (MAC) is designed to support both
10 Mbps and 100 Mbps Ethernet/IEEE Std 802.3™ networks. An external
transceiver interface and transceiver function are required to complete the
interface to the media.
The i.MX53xA also consists of HW assist for IEEE1588™ standard. See,
TSU and CE_RTC (IEEE1588) section for more details.
FIRI
Fast Infrared
Interface
Connectivity
Peripherals
Fast infrared interface
Flexible
Controller Area
Network
Connectivity
Peripherals
The controller area network (CAN) protocol was primarily, but not
exclusively, designed to be used as a vehicle serial data bus. Meets the
following specific requirements of this application: real-time processing,
reliable operation in the EXTMC environment of a vehicle,
cost-effectiveness and required bandwidth. The FLEXCAN is a full
implementation of the CAN protocol specification, Version 2.0 B (ISO
11898), which supports both standard and extended message frames at
1 Mbps.
FLEXCAN-1
FLEXCAN-2
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
10
Freescale Semiconductor
Modules List
Table 2. i.MX53xA Digital and Analog Blocks (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
GPIO-1
GPIO-2
GPIO-3
GPIO-4
GPIO-5
GPIO-6
GPIO-7
General Purpose System
I/O Modules
Control
Peripherals
These modules are used for general purpose input/output to external ICs.
Each GPIO module supports up to 32 bits of I/O.
GPT
General Purpose Timer
Timer
Peripherals
Each GPT is a 32-bit “free-running” or “set and forget” mode timer with a
programmable prescaler and compare and capture register. A timer counter
value can be captured using an external event, and can be configured to
trigger a capture event on either the leading or trailing edges of an input
pulse. When the timer is configured to operate in “set and forget” mode, it is
capable of providing precise interrupts at regular intervals with minimal
processor intervention. The counter has output compare logic to provide the
status and interrupt at comparison. This timer can be configured to run
either on an external clock or on an internal clock.
GPU3D
Graphics
Processing Unit
Multimedia
Peripherals
The GPU, version 3, provides hardware acceleration for 2D and 3D
graphics algorithms with sufficient processor power to run desk-top quality
interactive graphics applications on displays up to HD1080 resolution. It
supports color representation up to 32 bits per pixel. GPU enables
high-performance mobile 3D and 2D vector graphics at rates up to 33
Mtriangles/s, 200 Mpix/s, 800 Mpix/s (z).
GPU2D
Graphics
Processing
Unit-2D
Multimedia
Peripherals
The GPU2D version 1, provides hardware acceleration for 2D graphic
algorithms with sufficient processor power to run desk-top quality
interactive graphics applications on displays up to HD1080 resolution.
I2C Controller
Connectivity
Peripherals
I2C provides serial interface for controlling peripheral devices. Data rates of
up to 400 kbps are supported.
IC Identification
Module
Security
The IC identification module (IIM) provides an interface for reading,
programming, and/or overriding identification and control information stored
in on-chip fuse elements. The module supports electrically programmable
poly fuses (e-Fuses). The IIM also provides a set of volatile
software-accessible signals that can be used for software control of
hardware elements not requiring non-volatility. The IIM provides the primary
user-visible mechanism for interfacing with on-chip fuse elements. Among
the uses for the fuses are unique chip identifiers, mask revision numbers,
cryptographic keys, JTAG secure mode, boot characteristics, and various
control signals requiring permanent non-volatility. The IIM also provides up
to 28 volatile control signals. The IIM consists of a master controller, a
software fuse value shadow cache, and a set of registers to hold the values
of signals visible outside the module.
IIM interfaces to the electrical fuse array (split to banks). Enabled to set up
boot modes, security levels, security keys and many other system
parameters.
i.MX53A consists of 4 x 256-bit + 1x 128-bit fuse-banks (total 1152 bits)
through IIM interface.
I2C-1
I2C-2
I2C-3
IIM
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
11
Modules List
Table 2. i.MX53xA Digital and Analog Blocks (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
IOMUXC
IOMUX Control
System
Control
Peripherals
This module enables flexible I/O multiplexing. Each I/O pad has default as
well as several alternate functions. The alternate functions are software
configurable.
IPU
Image
Processing Unit
Multimedia
Peripherals
Version 3M IPU enables connectivity to displays, relevant processing and
synchronization. It supports two display ports and two camera ports,
through the following interfaces:
• Legacy parallel interfaces
• Single/dual channel LVDS display interface
• Analog TV or VGA interfaces
The processing includes:
• Image enhancement—color adjustment and gamut mapping, gamma
correction and contrast enhancement
• Video/graphics combining
• Support for display backlight reduction
• Image conversion—resizing, rotation, inversion and color space
conversion
• Hardware de-interlacing support
• Synchronization and control capabilities, allowing autonomous
operation.
KPP
Keypad Port
Connectivity
Peripherals
The KPP supports an 8 × 8 external keypad matrix. The KPP features are
as follows:
• Open drain design
• Glitch suppression circuit design
• Multiple keys detection
• Standby key press detection
LDB
LVDS Display
Bridge
Connectivity
Peripherals
LVDS display bridge is used to connect the IPU (image processing unit) to
external LVDS display interface. LDB supports two channels; each channel
has following signals:
• 1 clock pair
• 4 data pairs
On-chip differential drivers are provided for each pair.
MLB
OWIRE
Media local
bus—MediaLB
Connectivity/
Multimedia
Peripherals
The MLB interface module provides a link to a MOST® data network, using
the standardize MediaLB protocol (up to 50 Mbps).
One-Wire
Interface
Connectivity
Peripherals
One-wire support provided for interfacing with an on-board EEPROM, and
smart battery interfaces, for example, Dallas DS2502.
PATA
Parallel ATA
Connectivity
Peripherals
The PATA block is a AT attachment host interface. Its main use is to interface
with hard disk drives and optical disc drives. It interfaces with the ATA-6
compliant device over a number of ATA signals. It is possible to connect a
bus buffer between the host side and the device side.
PWM-1
PWM-2
Pulse Width
Modulation
Connectivity
Peripherals
The pulse-width modulator (PWM) has a 16-bit counter and is optimized to
generate sound from stored sample audio images. It can also generate
tones. The PWM uses 16-bit resolution and a 4 x 16 data FIFO to generate
sound.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
12
Freescale Semiconductor
Modules List
Table 2. i.MX53xA Digital and Analog Blocks (continued)
Block
Mnemonic
INTRAM
BOOTROM
RTIC
Block Name
Subsystem
Brief Description
Internal RAM
Internal
Memory
Internal RAM, shared with VPU.
The on-chip memory controller (OCRAM) module, is an interface between
the system’s AXI bus, to the internal (on-chip) SRAM memory module. It is
used for controlling the 128 KB multimedia RAM, through a 64-bit AXI bus.
Boot ROM
Internal
Memory
Supports secure and regular boot modes.
The ROM controller supports ROM patching.
Run-Time
Security
Integrity Checker
Protecting read only data from modification is one of the basic elements in
trusted platforms. The run-time integrity checker, version 3 (RTIC) block is
a data-monitoring device responsible for ensuring that the memory content
is not corrupted during program execution. The RTIC mechanism
periodically checks the integrity of code or data sections during normal OS
run-time execution without interfering with normal operation. The purpose
of the RTIC is to ensure the integrity of the peripheral memory contents,
protect against unauthorized external memory elements replacement and
assist with boot authentication.
SAHARA
SAHARA
Security
Accelerator
Security
SAHARA (symmetric/asymmetric hashing and random accelerator),
version 4, is a security coprocessor. It implements symmetric encryption
algorithms, (AES, DES, 3DES, RC4 and C2), public key algorithms (RSA
and ECC), hashing algorithms (MD5, SHA-1, SHA-224 and SHA-256), and
a hardware true random number generator. It has a slave IP Bus interface
for the host to write configuration and command information, and to read
status information. It also has a DMA controller, with an AHB bus interface,
to reduce the burden on the host to move the required data to and from
memory.
SATA
Serial ATA
Connectivity
Peripherals
SATA HDD interface, includes the SATA controller and the PHY. It is a
complete mixed-signal IP solution for SATA HDD connectivity.
Security
Controller, ver. 2
Security
The security controller is a security assurance hardware module designed
to safely hold sensitive data, such as encryption keys, digital right
management (DRM) keys, passwords and biometrics reference data. The
SCCv2 monitors the system’s alert signal to determine if the data paths to
and from it are secure, that is, it cannot be accessed from outside of the
defined security perimeter. If not, it erases all sensitive data on its internal
RAM. The SCCv2 also features a key encryption module (KEM) that allows
non-volatile (external memory) storage of any sensitive data that is
temporarily not in use. The KEM utilizes a device-specific hidden secret key
and a symmetric cryptographic algorithm to transform the sensitive data
into encrypted data.
SCCv2
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
13
Modules List
Table 2. i.MX53xA Digital and Analog Blocks (continued)
Block
Mnemonic
SDMA
SECRAM
Block Name
Smart Direct
Memory Access
Subsystem
System
Control
Peripherals
Brief Description
The SDMA is multi-channel flexible DMA engine. It helps in maximizing
system performance by off loading various cores in dynamic data routing.
The SDMA features list is as follows:
• Powered by a 16-bit instruction-set micro-RISC engine
• Multi-channel DMA supports up to 32 time-division multiplexed DMA
channels
• 48 events with total flexibility to trigger any combination of channels
• Memory accesses including linear, FIFO, and 2D addressing
• Shared peripherals between ARM and SDMA
• Very fast context-switching with two-level priority-based preemptive
multi-tasking
• DMA units with auto-flush and prefetch capability
• Flexible address management for DMA transfers (increment, decrement,
and no address changes on source and destination address)
• DMA ports can handle unidirectional and bidirectional flows (copy mode)
• Up to 8-word buffer for configurable burst transfers to / from the EXTMC
• Support of byte swapping and CRC calculations
• A library of scripts and API is available
Secure /
Internal
Non-secure RAM Memory
Secure / non-secure Internal RAM, controlled by SCC.
Secure JTAG
Interface
System
Control
Peripherals
JTAG manipulation is a known hacker’s method of executing unauthorized
program code, getting control over secure applications, and running code in
privileged modes. The JTAG port provides a debug access to several
hardware blocks including the ARM processor and the system bus.
The JTAG port must be accessible during platform initial laboratory
bring-up, manufacturing tests and troubleshooting, as well as for software
debugging by authorized entities. However, in order to properly secure the
system, unauthorized JTAG usage should be strictly forbidden.
In order to prevent JTAG manipulation while allowing access for
manufacturing tests and software debugging, the i.MX53xA processor
incorporates a mechanism for regulating JTAG access. SJC provides four
different JTAG security modes that can be selected through an e-fuse
configuration.
SPBA
Shared
Peripheral Bus
Arbiter
System
Control
Peripherals
SPBA (shared peripheral bus arbiter) is a two-to-one IP bus interface (IP
bus) arbiter.
SPDIF
Sony Philips
Digital Interface
Multimedia
Peripherals
A standard digital audio transmission protocol developed jointly by the Sony
and Philips corporations. Both transmitter and receiver functionalists are
supported.
SJC
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
14
Freescale Semiconductor
Modules List
Table 2. i.MX53xA Digital and Analog Blocks (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
SRTC
Secure Real
Time Clock
Security
The SRTC incorporates a special system state retention register (SSRR)
that stores system parameters during system shutdown modes. This
register and all SRTC counters are powered by dedicated supply rail
NVCC_SRTC_POW. The NVCC_SRTC_POW can be energized
separately even if all other supply rails are shut down. The power for this
block comes from NVCC_SRTC_POW supply. When this supply is driven
by the MC13892 power management controller, this block can be power
backed up through the coin-cell feature of the MC13892. This register is
helpful for storing warm boot parameters. The SSRR also stores the system
security state. In case of a security violation, the SSRR mark the event
(security violation indication).
SSI-1
SSI-2
SSI-3
I2S/SSI/AC97
Interface
Connectivity
Peripherals
The SSI is a full-duplex synchronous interface used on the i.MX53A
processor to provide connectivity with off-chip audio peripherals. The SSI
interfaces connect internally to the AUDMUX for mapping to external ports.
The SSI supports a wide variety of protocols (SSI normal, SSI network, I2S,
and AC-97), bit depths (up to 24 bits per word), and clock/frame sync
options.
Each SSI has two pairs of 8 x 24 FIFOs and hardware support for an
external DMA controller in order to minimize its impact on system
performance. The second pair of FIFOs provides hardware interleaving of
a second audio stream, which reduces CPU overhead in use cases where
two time slots are being used simultaneously.
IPTP
IEEE1588
Precision Time
Protocol
Connectivity
Peripherals
The IEEE 1588-2002 (version 1) standard defines a precision time protocol
(PTP) - which is a time-transfer protocol that enables synchronization of
networks (for example, Ethernet), to a high degree of accuracy and
precision.
The IEEE1588 hardware assist is composed of the two blocks: time stamp
unit and real time clock, which provide the timestamping protocol’s
functionality, generating and reading the needed timestamps.
The hardware-assisted implementation delivers more precise clock
synchronization at significantly lower CPU load compared to purely
software implementations.
System
Control
Peripherals
The temperature sensor is an internal module to the i.MX53xA that monitors
the die temperature. The monitor is capable in generating SW interrupt, or
trigger the CCM, to reduce the core operating frequency.
Multimedia
The TV encoder, version 2.1 is implemented in conjunction with the image
processing unit (IPU) allowing handheld devices to display captured still
images and video directly on a TV or LCD projector. It supports composite
PAL/NTSC, VGA, S-video, and component up to HD1080p analog video
outputs.
Temperature
Monitor
(Part of SATA
Block)
TVE
TV Encoder
TZIC
TrustZone Aware ARM/Control
Interrupt
Controller
The TrustZone interrupt controller (TZIC) collects interrupt requests from all
i.MX53xA sources and routes them to the ARM core. Each interrupt can be
configured as a normal or a secure interrupt. Software Force Registers and
software Priority Masking are also supported.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
15
Modules List
Table 2. i.MX53xA Digital and Analog Blocks (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
UART-1
UART-2
UART-3
UART-4
UART-5
UART Interface
Connectivity
Peripherals
Each of the UART blocks supports the following serial data transmit/receive
protocols and configurations:
• 7 or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd,
or none)
• Programmable bit-rates up to 4 Mbps. This is a higher max baud rate
relative to the 1.875 Mbps, which is specified by the TIA/EIA-232-F
standard.
• 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud
• IrDA 1.0 support (up to SIR speed of 115200 bps)
• Option to operate as 8-pins full UART, DCE, or DTE
USB
USB Controller
Connectivity
Peripherals
USB supports USB2.0 480 MHz, and contains:
• One high-speed OTG sub-block with integrated HS USB PHY
• One high-speed host sub-block with integrated HS USB PHY
• Two identical high-speed Host modules
The high-speed OTG module, which is internally connected to the HS USB
PHY, is equipped with transceiver-less logic to enable on-board USB
connectivity without USB transceivers
All the USB ports are equipped with standard digital interfaces (ULPI, HS
IC-USB) and transceiver-less logic to enable onboard USB connectivity
without USB transceivers.
VPU
Video Processing Multimedia
Unit
Peripherals
A high-performing video processing unit (VPU) version 3, which covers
many SD-level video decoders and SD-level encoders as a multi-standard
video codec engine as well as several important video processing such as
rotation and mirroring.
VPU Features:
• MPEG-2 decode, Mail-High profile, up to 1080i/p resolution, 40 Mbps bit
rate
• MPEG4/XviD decode, SP/ASP profile, up to 1080 i/p resolution, 40 Mbps
bit rate
• H.263 decode, P0/P3 profile, up to 16CIF resolution, 20 Mbps bit rate
• Sorenson H.263 decode, 4CIF resolution, 8 Mbps bit rate
• H.264 decode, BP/MP/HP profile, up to 1080 i/p resolution, 40 Mbps bit
rate
• VC1 decode, SP/MP/AP profile, up to 1080 i/p resolution, 40 Mbps bit
rate
• RV10 decode, 8/9/2010 profile, up to 1080 i/p resolution, 40 Mbps bit rate
• DivX decode, 3/4/5/6 profile, up to 1080 i/p resolution, 40 Mbps bit rate
• MJPEG decode, Baseline profile, up to 8192 x 8192 resolution,
40 Mpixel/s bit rate for 4:4:4 format
• MPEG21 encode, Main-Main profile, up to D1 resolution, 15 Mbps bit
rate
• MPEG4 encode, Simple profile, up to 720p resolution, 12 Mbps bit rate2
• H.263 encode, P0/P3 profile, up to 4CIF resolution, 8 Mbps bit rate2
• H.264 encode, Baseline profile, up to 720p resolution, 14 Mbps bit rate2
• MJPEG encode, Baseline profile, up to 8192 x 8192 resolution,
80 Mpixel/s bit rate for 4:2:2 format
Watch Dog
The watch dog timer supports two comparison points during each counting
period. Each of the comparison points is configurable to evoke an interrupt
to the ARM core, and a second point evokes an external event on the
WDOG line.
WDOG-1
Timer
Peripherals
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
16
Freescale Semiconductor
Electrical Characteristics
Table 2. i.MX53xA Digital and Analog Blocks (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
WDOG-2
(TZ)
Watch Dog
(TrustZone)
Timer
Peripherals
The TrustZone watchdog (TZ WDOG) timer module protects against
TrustZone starvation by providing a method of escaping normal mode and
forcing a switch to the TZ mode. TZ starvation is a situation where the
normal OS prevents switching to the TZ mode. This situation should be
avoided, as it can compromise the system’s security. Once the TZ WDOG
module is activated, it must be serviced by TZ software on a periodic basis.
If servicing does not take place, the timer times out. Upon a time-out, the
TZ WDOG asserts a TZ mapped interrupt that forces switching to the TZ
mode. If it is still not served, the TZ WDOG asserts a security violation
signal to the CSU. The TZ WDOG module cannot be programmed or
deactivated by a normal mode SW.
XTALOSC
24 MHz Crystal
Oscillator
Clocking
Provides a crystal oscillator amplifier that supports a 24-MHz external
crystal
XTALOSC_
32K
Clocking
32.768 KHz
Crystal Oscillator
I/F
1
2
Provides a crystal oscillator amplifier that supports a 32.768-kHz external
crystal.
Video partially performed in hardware accelerator (70%) and partially in software.
VPU can generate higher bit rate than the maximum specified by the corresponding standard.
3.1
Special Signal Considerations
The package contact assignments can be found in Section 6, “Package Information and Contact
Assignments.” Signal descriptions are defined in the i.MX53 Reference Manual. Special signal
considerations information is contained in Chapter 1 of i.MX53 System Development User's Guide.
Document number is MX53UG.
4
Electrical Characteristics
This section provides the device and module-level electrical characteristics for the i.MX53xA processor.
NOTE
This electrical specification is preliminary. These specifications are not fully
tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after thorough characterization and device
qualifications have been completed.
4.1
Chip-Level Conditions
This section provides the device-level electrical characteristics for the IC. See Table 3 for a quick reference
to the individual tables and sections.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
17
Electrical Characteristics
Table 3. i.MX53xA Chip-Level Conditions
For these characteristics, …
Topic appears …
Absolute Maximum Ratings
Table 4 on page 18
TEPBGA-2 Package Thermal Resistance Data
Table 5 on page 19
i.MX53xA Operating Ranges
Table 6 on page 20
External Clock Sources
Table 7 on page 22
Maximal Supply Currents
Table 8 on page 22
USB Interface Current Consumption
Table 9 on page 24
4.1.1
Absolute Maximum Ratings
CAUTION
Stresses beyond those listed under Table 4 may cause permanent damage to
the device. These are stress ratings only. Functional operation of the device
at these or any other conditions beyond those indicated under Table 6 is not
implied. Exposure to absolute-maximum-rated conditions for extended
periods may affect device reliability.
Table 4. Absolute Maximum Ratings
Parameter Description
Symbol
Min
Max
Unit
VCC
–0.3
1.35
V
VDDGP
–0.3
1.35
V
Supply Voltage UHVIO
Supplies denoted as I/O Supply
–0.5
3.6
V
Supply Voltage for non UHVIO
Supplies denoted as I/O Supply
–0.5
3.3
V
VBUS
—
5.25
V
USB_DP/USB_DN
–0.3
3.631
V
Vin/Vout
–0.5
OVDD +0.32
V
—
—
2000
500
V
–40
150
oC
Peripheral Core Supply Voltage
ARM Core Supply Voltage
USB VBUS
Input voltage on USB_OTG_DP, USB_OTG_DN,
USB_H1_DP, USB_H1_DN pins
Input/Output Voltage Range
ESD Damage Immunity:
Vesd
• Human Body Model (HBM)
• Charge Device Model (CDM)
Storage Temperature Range
1
2
TSTORAGE
USB_DN and USB_DP can tolerate 5 V for up to 24 hours.
The term OVDD in this section refers to the associated supply rail of an input or output. The association is described in
Table 113 on page 156. The maximum range can be superseded by the DC tables.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
18
Freescale Semiconductor
Electrical Characteristics
4.1.2
4.1.2.1
Thermal Resistance
TEPBGA-2 Package Thermal Resistance
Table 5 provides the TEPBGA-2 package thermal resistance data.
Table 5. TEPBGA-2 Package Thermal Resistance Data
Rating
Board
Symbol
Value
Unit
Single layer board
(1s)
RθJA
28
°C/W
Four layer board
(2s2p)
RθJA
16
°C/W
Junction to Ambient (at 200 ft/min)1, 3
Single layer board
(1s)
RθJMA
21
°C/W
Junction to Ambient (at 200 ft/min)1, 3
Four layer board
(2s2p)
RθJMA
13
°C/W
Junction to Board4
—
RθJB
6
°C/W
Junction to Case5
—
RθJC
4
°C/W
Junction to Package Top (natural convection)6
—
ΨJT
4
°C/W
Junction to Ambient (natural convection)1, 2
Junction to Ambient (natural convection)1, 2, 3
1
2
3
4
5
6
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
19
Electrical Characteristics
4.1.3
Operating Ranges
Table 6 provides the operating ranges of i.MX53xA processor.
Table 6. i.MX53xA Operating Ranges
Symbol
Parameter
VDDGP
VCC
VDDA3
VDDAL13
Minimum1 Nominal2 Maximum1
Unit
ARM core supply voltage
fARM ≤ 800 MHz
1.05
1.1
1.15
V
ARM core supply voltage
Stop mode
0.8
0.85
1.15
V
Peripheral supply voltage
1.25
1.3
1.35
V
Peripheral supply voltage—Stop mode
0.9
0.95
1.35
V
Memory arrays voltage
1.25
1.30
1.35
V
Memory arrays voltage—Stop mode
0.9
0.95
1.35
V
L1 Cache Memory arrays voltage
1.25
1.30
1.35
V
L1 Cache Memory arrays voltage—Stop mode
0.9
0.95
1.35
V
VDD_DIG_PLL4
PLL Digital supplies—external regulator option
1.25
1.3
1.35
V
VDD_ANA_PLL5
PLL Analog supplies—external regulator option
1.75
1.8
1.95
V
ESD protection of the CKIH pins, FUSE read Supply
and 1.8V bias for the UHVIO pads
1.65
1.8
1.95
V
NVCC_LCD
NVCC_JTAG
GPIO digital power supplies
1.65
1.8 or
2.775
3.1
V
NVCC_LVDS
LVDS interface Supply
2.25
2.5
2.75
V
LVDS Band Gap Supply
2.25
2.5
2.75
V
DDR Supply DDR2 range
1.7
1.8
1.9
DDR Supply LPDDR2 range
1.14
1.2
1.3
1.47
1.55
1.63
1.42
1.5
1.58
DDR Supply DDR3 range
1.42
1.5
1.58
Fusebox Program Supply (Write Only)
3.0
—
3.3
• UHVIO_L
1.65
1.8
1.95
• UHVIO_H
2.5
2.775
3.1
NVCC_CKIH
NVCC_LVDS_BG
NVCC_EMI_DRAM
V
DDR Supply LV-DDR2 range
6
VDD_FUSE
NVCC_NANDF
NVCC_SD1
NVCC_SD2
NVCC_PATA
NVCC_KEYPAD
NVCC_GPIO
NVCC_FEC
NVCC_EIM_MAIN
NVCC_EIM_SEC
NVCC_CSI
V
Ultra High voltage I/O (UHVIO) supplies:
V
• UHVIO_UH
3.0
3.3
3.6
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
20
Freescale Semiconductor
Electrical Characteristics
Table 6. i.MX53xA Operating Ranges (continued)
Symbol
Parameter
Minimum1 Nominal2 Maximum1
Unit
TVE digital and analog power supply, TVE-to-DAC
level shifter supply, cable detector supply, analog
power supply to RGB channel
2.69
2.75
2.91
V
For GPIO use only, when TVE is not in use
1.65
1.8 or
2.775
3.1
V
SRTC Core and slow I/O Supply (GPIO)8
1.25
1.3
1.35
V
LVIO
1.65
1.8 or
2.775
3.1
V
USB_H1_VDDA25
USB_OTG_VDDA25
NVCC_XTAL
USB_PHY analog supply, oscillator amplifier analog
supply9
2.25
2.5
2.75
V
USB_H1_VDDA33
USB_OTG_VDDA33
USB PHY I/O analog supply
3.0
3.3
3.6
V
See Table 4 on page 18 and Table 106 on page 148
for details. Note that this is not a power supply.
—
—
—
—
Power supply input for the integrated linear
regulators
2.37
2.5
2.63
V
VP
SATA PHY core power supply
1.25
1.3
1.35
V
VPH
SATA PHY I/O supply voltage
2.25
2.5
2.75
V
–40
10511
125
oC
TVDAC_DHVDD7
TVDAC_AHVDDRGB7
NVCC_SRTC_POW
NVCC_RESET
VBUS
VDD_REG10
Junction Temperature
TJ
1
Voltage at the package power supply contact must be maintained between the minimum and maximum voltages. The design
must allow for supply tolerances and system voltage drops.
2 The nominal values for the supplies indicate the target setpoint for a tolerance no tighter than ± 50 mV. Use of supplies with a
tighter tolerance allows reduction of the setpoint with commensurate power savings.
3 VDDA and VDDAL1 can be driven by the VDD_DIG_PLL internal regulator using external connections. When operating in this
configuration, the regulator is still operating at the default 1.2 V, as bootup start. During bootup initialization, software should
increase this regulator voltage to match VCC (1.3 V nominal) in order to reduce internal leakage current.
4 By default, VDD_DIG_PLL is driven from internal on-die 1.2 V linear regulator (LDO). In this case, there is no need driving this
supply externally. LDO output to VDD_DIG_PLL should be configured by software after power-up to 1.3 V output. A bypass
capacitor of minimal value 22 μF should be connected to this pad in any case whether it is driven internally or externally. Use
of the on-chip LDO is preferred. See i.MX53 System Development User’s Guide.
5 By default, the VDD_ANA_PLL is driven from internal on-die 1.8 V linear regulator (LDO). In this case there is no need driving
this supply externally. A bypass capacitor of minimal value 22 μF should be connected to this pad in any case whether it is
driven internally or externally. Use of the on-chip LDO is preferred. See i.MX53 System Development User’s Guide.
6 After fuses are programmed, Freescale strongly recommends the best practice of reading the fuses to verify that they are
written correctly. In Read mode, VDD_FUSE should be floated or grounded. Tying VDD_FUSE to a positive supply (3.0 V–3.3
V) increases the possibility of inadvertently blowing fuses and is not recommended in read mode.
7 If not using TVE module or other pads in this power domain for the product, the TVDAC_DHVDD and TVDAC_AHVDDRGB
can remain floating.
8 GPIO pad operational at low frequency
9 The analog supplies should be isolated in the application design. Use of series inductors is recommended.
10
VDD_REG is power supply input for the integrated linear regulators of VDD_ANA_PLL and VDD_DIG_PLL when they are
configured to the internal supply option. VDDR_REG still has to be tied to 2.5 V supply when VDD_ANA_PLL and
VDD_DIG_PLL are configured for external power supply mode although in this case it is not used as supply source.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
21
Electrical Characteristics
11
Lifetime of 43,800 hours based on 105 C junction temperature at nominal supply voltages.
4.1.4
External Clock Sources
The i.MX53xA device has four external input system clocks, a low frequency (CKIL), a high frequency
(XTAL), and two general purpose CKIH1 and CKIH2 clocks.
The CKIL is used for low-frequency functions. It supplies the clock for wake-up circuit, power-down real
time clock operation, and slow system and watch-dog counters. The clock input can be connected to either
external oscillator or a crystal using internal oscillator amplifier.
The system clock input XTAL is used to generate the main system clock. It supplies the PLLs and other
peripherals. The system clock input can be connected to either external oscillator or a crystal using internal
oscillator amplifier.
CKIH1 and CKIH2 provide additional clock source option for peripherals that require specific and
accurate frequencies.
Table 7 shows the interface frequency requirements. Refer to Chapter 1 of the i.MX53 System
Development User's Guide for additional clock and oscillator information. Document number is
MX53UG.
Table 7. External Input Clock Frequency
Parameter Description
CKIL Oscillator1
CKIH1, CKIH2 Operating
Frequency
XTAL Oscillator
1
2
Symbol
Min
Typ
Max
Unit
fckil
—
32.7682/32.0
—
kHz
fckih1,
fckih2
See Table 32, "CAMP Electrical Parameters (CKIH1,
CKIH2)," on page 46
fxtal
22
24
MHz
27
MHz
External oscillator or a crystal with internal oscillator amplifier.
Recommended nominal frequency 32.768 kHz.
4.1.5
Maximal Supply Currents
Table 8 represents the maximal momentary current transients on power lines, and should be used for power
supply selection. Maximal currents higher by far than the average power consumption of typical use cases.
For typical power consumption information, refer to i.MX53xA power consumption application note.
Table 8. Maximal Supply Currents
Power Line
Max Current
Unit
1450
mA
VCC
800
mA
VDDA+VDDAL1
100
mA
VDD_DIG_PLL
10
mA
VP
20
mA
VDD_ANA_PLL
10
mA
VDDGP
Conditions
800 MHz ARM clock.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
22
Freescale Semiconductor
Electrical Characteristics
Table 8. Maximal Supply Currents (continued)
Power Line
Max Current
Unit
MVCC_XTAL
25
mA
VDD_REG
325
mA
Fuse Write Mode
operation
120
mA
1.8v (DDR2)
800
mA
1.5v (DDR3)
650
mA
1.2v (LPDDR2)
250
mA
TVDAC_DHVDD + TVDAC_AHVDDRGB
200
mA
NVCC_SRTC_POW
<1
mA
USB_H1_VDDA25 +
USB_OTG_VDDA25
50
mA
USB_H1_VDDA33 +
USB_OTG_VDDA33
20
mA
VPH
60
VDD_FUSE
NVCC_EMI_DRAM
Conditions
mA
1,
NVCC_CKIH
Use maximal IO Eq N=4
NVCC_CSI
Use maximal IO Eq1, N=20
NVCC_EIM_MAIN
Use maximal IO Eq1, N=39
NVCC_EIM_SEC
Use maximal IO Eq1, N=16
NVCC_EMI_DRAM
Use maximal IO Eq1, N=78
NVCC_FEC
Use maximal IO Eq1, N=11
NVCC_GPIO
Use maximal IO Eq1, N=13
NVCC_JTAG
Use maximal IO Eq1, N=6
NVCC_KPAD
Use maximal IO Eq1, N=11
NVCC_LCD
Use maximal IO Eq1, N=29
NVCC_LVDS
Use maximal IO Eq1, N=20
NVCC_LVDS_BG
Use maximal IO Eq1, N=1
NVCC_NANDF
Use maximal IO Eq1, N=8
NVCC_PATA
Use maximal IO Eq1, N=29
NVCC_REST
Use maximal IO Eq1, N=5
NVCC_SD1
Use maximal IO Eq1, N=6
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
23
Electrical Characteristics
Table 8. Maximal Supply Currents (continued)
Power Line
Conditions
Max Current
NVCC_SD2
Use maximal IO Eq1, N=6
NVCC_XTAL
Use maximal IO Eq1, N=2
Unit
1
General Equation for estimated, maximal power consumption of an IO power supply:
Imax = N * C * V * (0.5 * F)
Where:
N - Number of IO pins supplies by the power line
C - Equivalent external capacitive load
V - IO voltage
(0.5 * F) - Data change rate. Up to 0.5 of the clock rate (F).
4.1.6
USB-OH-3 (OTG + 3 Host ports) Module and the Two USB PHY (OTG
and H1) Current Consumption
Table 9 shows the USB interface current consumption.
Table 9. USB Interface Current Consumption
Parameter
Analog Supply 3.3 V
USB_H1_VDDA33
USB_OTG_VDDA33
Analog Supply 2.5 V
USB_H1_VDDA25
USB_OTG_VDDA25
Conditions
Typical at 25 °C
Max
RX
5.5
6
TX
7
8
RX
5
6
TX
5
6
RX
6.5
7
TX
6.5
7
RX
12
13
TX
21
22
RX
8
—
TX
8
—
RX
8
—
TX
8
—
Unit
Full Speed
mA
High Speed
Full Speed
mA
High Speed
Full Speed
Digital Supply
VCC (1.2 V)
mA
High Speed
4.2
Power Supplies Requirements and Restrictions
The system design must comply with power-up sequence, power-down sequence and steady state
guidelines as described in this section to guarantee the reliable operation of the device. Any deviation from
these sequences may result in the following situations:
• Excessive current during power-up phase
• Prevention of the device from booting
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
24
Freescale Semiconductor
Electrical Characteristics
•
4.2.1
Irreversible damage to the i.MX53xA processor (worst-case scenario)
Power-Up Sequence
The following observations should be considered:
•The consequent steps in power up sequence should not start before the previous step supplies have
been stabilized within 90-110% of their nominal voltage, unless stated otherwise.
•NVCC_SRTC_POW should remain powered ON continuously, to maintain internal real-time
clock status. Otherwise, it has to be powered ON together with VCC, or preceding VCC.
•The VCC should be powered ON together, or any time after NVCC_SRTC_POW.
•NVCC_CKIH should be powered ON after VCC is stable and before other IO supplies
(NVCC_xxx) are powered ON.
•IO Supplies (NVCC_xxx) below or equal to 2.8 V nom./3.1 V max. should not precede
NVCC_CKIH. They can start powering ON during NVCC_CKIH ramp-up, before it is
stabilized. Within this group, the supplies can be powered-up in any order.
•IO Supplies (NVCC_xxx) above 2.8 V nom./3.1 V max. should be powered ON only after
NVCC_CKIH is stable.
•In case VDD_DIG_PLL and VDD_ANA_PLL are powered ON from internal voltage regulator
(default case for i.MX53), there are no related restrictions on VDD_REG, as it is used as their
internal regulators power source.
If VDD_DIG_PLL and VDD_ANA_PLL are powered on externally, to reduce current leakage
during the power-up, it is recommended to activate the VDD_REG before or at the same time
with VDD_DIG_PLL and VDD_ANA_PLL. If this sequencing is not possible, make sure that
the 2.5 V VDD_REG supply shut-off output impedance is higher than 1 kΩ when it is inactive.
•VDD_REG supply is required to be powered ON to enable DDR operation. It must be powered
on after VCC and before NVCC_EMI_DRAM. The sequence should be:
VCC →VDD_REG →NVCC_EMI_DRAM
•VDDA and VDDAL1 can be powered ON anytime before POR_B, regardless of any other power
signal.
•VDDGP can be powered ON anytime before POR_B, regardless of any other power signal.
•VP and VPH can be powered up together, or anytime after, the VCC. VP and VPH should come
before POR.
•TVDAC_DHVDD and TVDAC_AHVDDRGB should be powered from the same regulator. This
is due to ESD diode protection circuit, that may cause current leakage if one of the supplies is
powered ON before the other.
NOTE
The POR_B input must be immediately asserted at power-up and remain
asserted until after the last power rail reaches its working voltage.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
25
Electrical Characteristics
Figure 2 shows the power-up sequence diagram.
NVCC_SRTC_POW
(may remain ON)
90%
VCC
90%
Δt > 0
NVCC_CKIH
90%
Δt > 0
IO Supplies below or equal to
2.8 V nom./3.1 V max.
(in any order, after NVCC_CKIH
ramp up start, if needed)
90%
Δt > 0
IO Supplies above 2.8 V nom./3.1 V max
(in any order, if needed)
90%
Δt > 0
VDD_REG
Δt > 0
90%
Δt > 0
NVCC_EMI_DRAM
90%
Δt > 0
VP, VPH
(in any order)
90%
VDDA,VDDAL1,VDDGP
(in any order)
90%
Δt > 0
Δt > 0
POR_B
Figure 2. Power Up Detailed Sequence 1
NOTE
Need to ensure that there is no back voltage (leakage) from any supply on
the board towards the 3.3 V supply (for example, from the parts that use
both 1.8 V and the 3.3 V supply).
1. If fuse writing is required, VDD_FUSE should be powered ON after NVCC_CKIH is stable.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
26
Freescale Semiconductor
Electrical Characteristics
4.2.2
Power-Down Sequence
Power-down sequence should follow one of the following two options:
Option 1: Switch all supplies down simultaneously with further free discharge. A deviation of few
microseconds of actual power-down of the different power rails is acceptable.
Option 2: Switch down supplies, in any order, keeping the following rules:
• NVCC_CKIH must be powered down at the same time or after the UHVIO IO cell supplies (for
full supply list, refer to Table 6, Ultra High voltage I/O (UHVIO) supplies). A deviation of few
microseconds of actual power-down of the different power rails is acceptable.
• VDD_REG must be powered down at the same time or after NVCC_EMI_DRAM supply. A
deviation of few microseconds of actual power-down of the different power rails is acceptable.
• If all of the following conditions are met:
— 1. VDD_REG is powered down to 0V (Not Hi-Z)
— 2. VDD_DIG_PLL and VDD_ANA_PLL are provided externally,
— 3. VDD_REG is powered down before VDD_DIG_PLL and VDD_ANA_PLL
Then the following rule should be kept: VDD_REG output impedance must be higher than 1 kΩ,
when inactive.
4.2.3
•
•
•
•
4.3
Power Supplies Usage
All IO pins should not be externally driven while the IO power supply for the pin (NVCC_xxx) is
off. This can cause internal latch-up and malfunctions due to reverse current flows. For information
about IO power supply of each pin refer to “Power Rail” columns in pin list tables of Section 6,
“Package Information and Contact Assignments.”
If not using SATA interface and the embedded thermal sensor, the VP and VPH should be
grounded. In particular, keeping VPH turned OFF while the VP is powered ON is not
recommended and might lead to excessive power consumption.
When internal clock source is used for SATA temperature monitor the USB_PHY supplies and
PLL need to be active because they are providing the clock.
If not using TVE the module, the TVDAC_DHVDD and TVDAC_AHVDDRGB can remain
floating. If only the GPIO pads in TVDAC_AHVDDRGB domain are in use, the supplies can be
set to GPIO pad voltage range (1.65 V to 3.1 V).
I/O DC Parameters
This section includes the DC parameters of the following I/O types:
• General Purpose I/O (GPIO)
• Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2 and DDR3 modes
• Low Voltage I/O (LVIO)
• Ultra High Voltage I/O (UHVIO)
• LVDS I/O
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
27
Electrical Characteristics
NOTE
The term ‘OVDD’ in this section refers to the associated supply rail of an
input or output. The association is shown in Table 113.
Figure 3. Circuit for Parameters Voh and Vol for IO Cells
4.3.1
General Purpose I/O (GPIO) DC Parameters
The parameters in Table 10 are guaranteed per the operating ranges in Table 6, unless otherwise noted.
Table 10 shows DC parameters for GPIO pads, operating at two supply ranges:
• 1.1 V to 1.3 V
• 1.65 V to 3.1 V
Table 10. GPIO I/O DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
High-level output voltage1
Voh
Iout = –1 mA
Iout= specified Ioh Drive
OVDD – 0.15
0.8*OVDD
—
—
V
Low-level output voltage1
Vol
Iout = 1 mA
Iout= specified Iol Drive
—
—
0.15
0.2 × OVDD
V
High-level output current
(1.1-1.3V OVDD)
Ioh
—
—
mA
—
—
mA
—
—
mA
Low-level output current
(1.1-1.3V OVDD)
Iol
High-level output current
(1.65-3.1V OVDD)
Ioh
Vout = 0.8×OVDD
Low drive
Medium drive
High drive
Max drive
–0.85
–1.7
–2.5
–3.4
Vout = 0.2×OVDD
Low drive
Medium drive
High drive
Max drive
0.9
1.9
2.9
3.8
Vout = 0.8×OVDD
Low drive
Medium drive
High drive
Max drive
–2.1
–4.2
–6.3
–8.4
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
28
Freescale Semiconductor
Electrical Characteristics
Table 10. GPIO I/O DC Electrical Characteristics (continued)
Parameter
Symbol
Low-level output current
(1.65-3.1V OVDD)
Iol
Test Conditions
Vout = 0.2×OVDD
Low drive
Medium drive
High drive
Max drive
Min
2.1
4.2
6.3
8.4
Typ
Max
Unit
—
—
mA
High-Level DC input voltage1, 2
VIH
—
0.7 × OVDD
—
OVDD
V
Low-Level DC input voltage1, 2
VIL
—
0
—
0.3 × OVDD
V
VHYS
OVDD = 1.875 V
OVDD = 2.775 V
0.25
0.34
0.45
—
V
Schmitt trigger VT+2, 3
VT+
—
0.5 × OVDD
—
—
V
Schmitt trigger VT–2, 3
VT–
—
—
—
0.5 × OVDD
V
Input current (no pull-up/down)
Iin
Vin = OVDD or 0
—
—
2
μA
Input current (22 kΩ Pull-up)
Iin
Vin = 0 V
Vin = OVDD
—
—
161
2
μA
Input current (47 kΩ Pull-up)
Iin
Vin = 0 V
Vin = OVDD
—
—
76
2
μA
Input current (100 kΩ Pull-up)
Iin
Vin = 0 V
Vin= OVDD
—
—
36
2
μA
Input current (100 kΩ Pull-down)
Iin
Vin = 0 V
Vin = OVDD
—
—
2
36
μA
—
1304
—
kΩ
Input Hysteresis
Keeper Circuit Resistance
1
Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,
and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be
controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other
methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.
2 To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC
level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s.
3 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
4 Use an off-chip pull resistor of less than 60 kΩ to override this keeper.
4.3.2
LPDDR2 I/O DC Parameters
The LPDDR2 I/O pads support DDR2/LVDDR2, LPDDR2, and DDR3 operational modes.
4.3.2.1
DDR2 Mode I/O DC Parameters
The DDR2 interface fully complies with JESD79-2E DDR2 JEDEC standard release April, 2008. The
parameters in Table 11 are guaranteed per the operating ranges in Table 6, unless otherwise noted.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
29
Electrical Characteristics
Table 11. DDR2 I/O DC Electrical Parameters1
Parameters
Symbol
Test Conditions
Min
Typ
Max
Unit
High-level output voltage2
Voh
—
0.9*OVDD
—
—
V
Low-level output voltage
Vol
—
—
—
0.1*OVDD
V
Output minimum Source Current3
Ioh
OVDD=1.7 V,
Vout=1.42 V
–13.4
—
—
mA
Output min Sink Current4
Iol
OVDD=1.7 V,
Vout=280 mV
13.4
—
—
mA
Input Reference Voltage
Vref
0.49*OVDD
0.5*OVDD
0.51*OVDD
DC input High Voltage (data pins)
Vihd
(dc)
—
Vref+0.125V
—
OVDD+0.3
V
DC input Low Voltage (data pins)
Vild (dc)
—
–0.3
—
Vref-0.125V
V
DC Input voltage range of each
differential input5
Vin (dc)
—
–0.3
—
OVDD+0.3
V
DC Differential input voltage required for Vid (dc)
switching 6
—
0.25
—
OVDD+0.6
V
Termination Voltage
Vtt
Vtt
Vref – 0.04
Vref
Vref + 0.04
V
Input current (no pull-up/down)
Iin
Vin = 0 V
Vin=OVDD
—
—
—
—
1
1
μA
—
—
1307
—
kΩ
Keeper Circuit Resistance
1
2
3
4
5
6
7
—
Note that the JEDEC SSTL_18 specification (JESD8-15a) for a SSTL interface for class II operation supersedes any
specification in this document.
OVDD is the I/O power supply (1.7 V–1.9 V for DDR2)
(Vout - OVDD) / Ioh must be less than 21 Ω for values of Vout between OVDD and OVDD-0.28 V.
Vout / Iol must be less than 21 Ω for values of Vout between 0 V and 280 mV.
Vin(dc) specifies the allowable DC voltage exertion of each differential input.
Vid(dc) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the “true” input level and Vcp is the
“complementary” input level. The minimum value is equal to Vih(dc) -Vil(dc).
Use an off-chip pull resistor of less than 60 kΩ to override this keeper.
4.3.2.2
LPDDR2 Mode I/O DC Parameters
The LPDDR2 interface fully complies with JESD209-2B LPDDR2 JEDEC standard release June, 2009.
Table 12. LPDDR2 I/O DC Electrical Parameters1
Parameters
Symbol
Test Conditions
Min
Typ
Max
Unit
High-level output voltage
Voh
—
0.9*OVDD
—
—
V
Low-level output voltage
Vol
—
—
—
0.1*OVDD
V
Input Reference Voltage
Vref
0.49*OVDD
0.5*OVDD
0.51*OVDD
DC input High Voltage
Vih(dc)
—
Vref+0.13V
—
OVDD
V
DC input Low Voltage
Vil(dc)
—
OVSS
—
Vref-0.13V
V
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
30
Freescale Semiconductor
Electrical Characteristics
Table 12. LPDDR2 I/O DC Electrical Parameters1 (continued)
Differential Input Logic High
Vih(diff)
0.26
See Note2
Differential Input Logic Low
Vil(diff)
See Note2
-0.26
Input current (no pull-up/down)
Iin
Vin = 0 V
Vin=OVDD
Pull-up/Pull-down impedance Mismatch
—
—
-15
240 Ohm unit calibration resolution
Keeper Circuit Resistance
—
—
1
1
μA
+15
%
10
Ohm
—
kΩ
—
—
1403
—
1
Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.
The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as
the limitations for overshoot and undershoot.
3 Use an off-chip pull resistor of less than 60 kΩ to override this keeper.
2
4.3.2.3
DDR3 Mode I/O DC Parameters
The DDR3 interface fully complies with JESD79-3D DDR3 JEDEC standard release April, 2008. The
parameters in Table 13 are guaranteed per the operating ranges in Table 6, unless otherwise noted.
Table 13. DDR3 I/O DC Electrical Parameters
Parameters
Symbol
Test Conditions
Min
Typ
Max
Unit
High-level output voltage
Voh
—
0.8*OVDD1
—
—
V
Low-level output voltage
Vol
—
—
—
0.2*OVDD
V
2+0.1
—
OVDD
V
—
Vref-0.1
V
DC input Logic High
VIH(dc)
—
DC input Logic Low
VIL(dc)
—
Vref
OVSS
Differential input Logic High
VIH(diff)
—
0.2
—
Differential input Logic Low
VIL(diff)
—
See Note3
—
-0.2
V
Over/undershoot peak
Vpeak
—
—
—
0.4
V
Over/undershoot area
(above OVDD or below OVSS)
Varea
—
—
—
0.67
Vx
nS
Termination Voltage
Vtt
Vtt tracking OVDD/2
0.49*OVDD
Vref
0.51*OVDD
V
Input current (no pull-up/down)
Iin
VI = 0 V
VI=OVDD
—
—
—
—
1
1
μA
Pull-up/Pull-down impedance mismatch
—
Minimum impedance
configuration
—
—
3
Ω
240 Ω unit calibration resolution
—
—
—
—
10
Ω
Keeper Circuit Resistance
—
—
—
1304
—
kΩ
1
2
See
Note3
V
OVDD – I/O power supply (1.425 V–1.575 V for DDR3)
Vref – DDR3 external reference voltage
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
31
Electrical Characteristics
3
The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as
the limitations for overshoot and undershoot.
4
Use an off-chip pull resistor of less than 60 kΩ to override this keeper.
4.3.3
Low Voltage I/O (LVIO) DC Parameters
The parameters in Table 14 are guaranteed per the operating ranges in Table 6, unless otherwise noted.
The LVIO pads operate only as inputs.
Table 14. LVIO DC Electrical Characteristics
DC Electrical Characteristics
Symbol
Test Conditions
Min
Typ
Max
Unit
High-Level DC input voltage1, 2
Vih
—
0.7 × OVDD
—
OVDD
V
1, 2
Vil
—
0
—
0.3 × OVDD
V
Input Hysteresis
Vhys
OVDD = 1.875 V
OVDD = 2.775 V
0.35
0.62
1.27
—
V
Schmitt trigger VT+2, 3
VT+
—
0.5 × OVDD
—
—
V
Schmitt trigger VT–2, 3
VT–
—
—
—
0.5 × OVDD
V
Input current (no pull-up/down)
Iin
Vin = OVDD or 0 V
—
—
1
μA
Input current (22 kΩ Pull-up)
Iin
Vin = 0 V
Vin = OVDD
—
—
161
1
μA
Input current (47 kΩ Pull-up)
Iin
Vin = 0 V
Vin = OVDD
—
—
76
1
μA
Input current (100 kΩ Pull-up)
Iin
Vin = 0 V
Vin = OVDD
—
—
36
1
μA
Input current (100 kΩ Pull-down)
Iin
Vin = 0 V
Vin = OVDD
—
—
1
36
μA
Keeper Circuit Resistance
—
—
1304
—
kΩ
Low-Level DC input voltage
1
Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,
and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must be
controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other
methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.
2
To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC
level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s. VIL and VIH do not apply
when hysteresis is enabled.
3 Hysteresis of 350 mV is guaranteed over all operating conditions when hysteresis is enabled.
4
Use an off-chip pull resistor of less than 60 kΩ to override this keeper.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
32
Freescale Semiconductor
Electrical Characteristics
4.3.4
Ultra-High Voltage I/O (UHVIO) DC Parameters
The parameters in Table 15 are guaranteed per the operating ranges in Table 6, unless otherwise noted.
Table 15. UHVIO DC Electrical Characteristics
DC Electrical Characteristics
Symbol
Test Conditions
Min
Typ
Max
Unit
High-level output voltage1
Voh
Iout = –1mA
Iout= specified Ioh
Drive
OVDD–0.15
0.8 * OVDD
—
—
V
Low-level output voltage1
Vol
Iout = 1mA
Iout= specified Ioh
Drive
—
—
0.15
0.2 * OVDD
V
—
—
mA
—
—
mA
—
—
mA
—
—
mA
Ioh_lv
Vout = 0.8 × OVDD
Low Drive
Medium Drive
High Drive
–2.2
–4.4
–6.6
Ioh_hv
Vout = 0.8 × OVDD
Low Drive
Medium Drive
High Drive
–5.1
–10.2
–15.3
Iol_lv
Vout = 0.2 × OVDD
Low Drive
Medium Drive
High Drive
2.2
4.4
6.6
Iol_hv
Vout = 0.2 × OVDD
Low Drive
Medium Drive
High Drive
5.1
10.2
15.3
High-Level DC input voltage1, 2
VIH
—
0.7 × OVDD
—
OVDD
V
voltage1, 2
VIL
—
0
—
0.3 × OVDD
V
VHYS
low voltage mode
high voltage mode
0.38
0.95
—
0.43
1.33
V
Schmitt trigger VT+2, 3
VT+
—
0.5 × OVDD
—
—
V
Schmitt trigger VT–2, 3
VT–
—
—
—
0.5 × OVDD
V
Input current (no pull-up/down)
Iin
Vin = OVDD or 0 V
—
—
1
μA
Input current (22 kΩ Pull-up)
Iin
Vin = 0
Vin = OVDD
—
—
202
1
μA
Input current (75 kΩ Pull-up)
Iin
Vin = 0
Vin = OVDD
—
—
61
1
μA
Input current (100 kΩ Pull-up)
Iin
Vin = 0
Vin = OVDD
—
—
47
1
μA
Input current (360 kΩ Pull-down)
Iin
Vin = 0
Vin = OVDD
—
—
1
5.7
μA
Keeper Circuit Resistance
—
—
—
1304
—
kΩ
High-level output current, low voltage mode
High-level output current, high voltage
mode
Low-level output current, low voltage mode
Low-level output current, high voltage mode
Low-Level DC input
Input Hysteresis
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
33
Electrical Characteristics
1
Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,
and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must
be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other
methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.
2 To maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current
DC level to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s. VIL and VIH do not apply
when hysteresis is enabled.
3
Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
4
Use an off-chip pull resistor of less than 60 kΩ to override this keeper.
4.3.5
LVDS I/O DC Parameters
The LVDS interface complies with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A,
“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.
Table 16 shows the Low Voltage Differential Signaling (LVDS) DC electrical characteristics.
Table 16. LVDS DC Electrical Characteristics
DC Electrical Characteristics
Symbol
Test Conditions
Min
Typ
Max
Unit
Output Differential Voltage
VOD
250
350
450
mV
Output High Voltage
VOH
Rload=100Ω
padP, –padN
1.25
1.375
1.6
Output Low Voltage
VOL
0.9
1.025
1.25
Offset Voltage
VOS
1.125
1.2
1.375
4.4
V
Output Buffer Impedance Characteristics
This section defines the I/O Impedance parameters of the i.MX53xA processor for the following I/O
types:
• General Purpose I/O (GPIO)
• Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2, and DDR3 modes
• Ultra High Voltage I/O (UHVIO)
• LVDS I/O
NOTE
Output driver impedance is measured with “long” transmission line of
impedance Ztl attached to I/O pad and incident wave launched into
transmission lime. Rpu/Rpd and Ztl form a voltage divider that defines
specific voltage of incident wave relative to OVDD. Output driver
impedance is calculated from this voltage divider (see Figure 4).
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
34
Freescale Semiconductor
Electrical Characteristics
OVDD
PMOS (Rpu)
Ztl Ω, L = 20 inches
ipp_do
pad
predriver
Cload = 1p
NMOS (Rpd)
OVSS
U,(V)
Vin (do)
VDD
t,(ns)
0
U,(V)
Vout (pad)
OVDD
Vref2
Vref1
Vref
t,(ns)
0
Rpu =
Vovdd – Vref1
× Ztl
Vref1
Rpd =
Vref2
× Ztl
Vovdd – Vref2
Figure 4. Impedance Matching Load for Measurement
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
35
Electrical Characteristics
4.4.1
GPIO Output Buffer Impedance
Table 17 shows the GPIO output buffer impedance.
Table 17. GPIO Output Buffer Impedance
Typ
Parameter
Symbol
Output Driver
Impedance
Rpu
Output Driver
Impedance
Rpd
4.4.2
Test Conditions
Min
OVDD 2.775 V
OVDD 1.875 V
Max
Unit
Low Drive Strength, Ztl = 150 Ω
Medium Drive Strength, Ztl = 75 Ω
High Drive Strength, Ztl = 50 Ω
Max Drive Strength, Ztl = 37.5 Ω
80
40
27
20
104
52
35
26
150
75
51
38
250
125
83
62
Ω
Low Drive Strength, Ztl = 150 Ω
Medium Drive Strength, Ztl = 75 Ω
High Drive Strength, Ztl = 50 Ω
Max Drive Strength, Ztl = 37.5 Ω
64
32
21
16
88
44
30
22
134
66
44
34
243
122
81
61
Ω
DDR Output Driver Average Impedance
The DDR2/LVDDR2 interface fully complies with JESD79-2E DDR2 JEDEC standard release April,
2008. The DDR3 interface fully complies with JESD79-3D DDR3 JEDEC standard release April, 2008.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
36
Freescale Semiconductor
Electrical Characteristics
Table 18 shows DDR output driver average impedance of the i.MX53xA processor.
Table 18. DDR Output Driver Average Impedance1
Drive strength (DSE)
Parameter
Output
Driver
Impedance
Symbol
Rdrv2
Test Conditions
Unit
000
001
010
011
100
101
110
111
LPDDR1/DDR2 mode
NVCC_DRAM = 1.8 V
DDR_SEL = 00
Calibration resistance = 300 Ω3
Hi-Z
300
150
100
75
60
50
43
DDR2 mode
NVCC_DRAM = 1.8 V
DDR_SEL = 01
Calibration resistance = 180 Ω3
Hi-Z
180
90
60
45
36
30
26
DDR2 mode
NVCC_DRAM = 1.8 V
DDR_SEL = 10
Calibration resistance = 200 Ω3
Hi-Z
200
100
66
50
40
33
28
DDR2 mode
NVCC_DRAM= 1.8 V
DDR_SEL = 11
Calibration resistance = 140 Ω3
Hi-Z
140
70
46
35
28
23
20
LPDDR2 mode
NVCC_DRAM= 1.2 V
DDR_SEL = 014
Calibration resistance = 160 Ω3
Hi-Z
160
80
53
40
32
27
23
LPDDR2 mode
NVCC_DRAM = 1.2 V
DDR_SEL = 10
Calibration resistance = 240 Ω3
Hi-Z
240
120
80
60
48
40
34
LPDDR2 mode
NVCC_DRAM = 1.2 V
DDR_SEL = 114
Calibration resistance = 160 Ω3
Hi-Z
160
80
53
40
32
27
23
DDR3 mode
NVCC_DRAM = 1.5 V
DDR_SEL = 00
Calibration resistance = 200 Ω3
Hi-Z
240
120
80
60
48
48
34
Ω
1
Output driver impedance is controlled across PVTs (process, voltages, and temperatures) using calibration procedure and
pu_*cal, pd_*cal input pins.
2 Output driver impedance deviation (calibration accuracy) is ±5% (max/min impedance) across PVTs.
3 Calibration is done against external reference resistor. Value of the resistor should be varied depending on DDR mode and
DDR_SEL setting.
4 If DDR_SEL = ‘01’ or DDR_SEL = ‘11’ are selected with NVCC_DRAM = 1.2 V for LPDDR2 operation, the external reference
resistor value must be 160 Ω for a correct ZQ calibration. In any case, reference resistors attached to the DDR memory devices
should be kept to 240 Ω per the JEDEC standard.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
37
Electrical Characteristics
4.4.3
UHVIO Output Buffer Impedance
Table 19 shows the UHVIO output buffer impedance.
Table 19. UHVIO Output Buffer Impedance
Min
Parameter
Symbol
Output Driver
Impedance
Rpu
Output Driver
Impedance
Rpd
4.4.4
Test Conditions
Typ
OVDD OVDD OVDD
1.95 V 3.0 V 1.875 V
Max
OVDD
3.3 V
OVDD
1.65 V
OVDD
3.6 V
Unit
Low Drive Strength, Ztl = 150 Ω
Medium Drive Strength, Ztl = 75 Ω
High Drive Strength, Ztl = 50 Ω
98
49
32
114
57
38
124
62
41
135
67
45
198
99
66
206
103
69
Ω
Low Drive Strength, Ztl = 150 Ω
Medium Drive Strength, Ztl = 75 Ω
High Drive Strength, Ztl = 50 Ω
97
49
32
118
59
40
126
63
42
154
77
51
179
89
60
217
109
72
Ω
LVDS I/O Output Buffer Impedance
The LVDS interface complies with TIA/EIA 644-A standard. See, TIA/EIA STANDARD 644-A,
“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.
4.5
I/O AC Parameters
This section includes the AC parameters of the following I/O types:
• General Purpose I/O (GPIO)
• Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2 and DDR3 modes
• Low Voltage I/O (LVIO)
• Ultra High Voltage I/O (UHVIO)
• LVDS I/O
The load circuit and output transition time waveforms are shown in Figure 5 and Figure 6.
From Output
Under Test
Test Point
CL
CL includes package, probe and fixture capacitance
Figure 5. Load Circuit for Output
OVDD
80%
80%
Output (at pad)
20%
0V
20%
tr
tf
Figure 6. Output Transition Time Waveform
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
38
Freescale Semiconductor
Electrical Characteristics
4.5.1
GPIO I/O AC Electrical Characteristics
AC electrical characteristics for GPIO I/O in slow and fast modes are presented in the Table 20 and
Table 21, respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bit
in the IOMUXC control registers.
Table 20. GPIO I/O AC Parameters Slow Mode
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
Output Pad Transition Times (Max Drive)
tr, tf
15 pF
35 pF
—
—
1.91/1.52
3.07/2.65
ns
Output Pad Transition Times (High Drive)
tr, tf
15 pF
35 pF
—
—
2.22/1.81
3.81/3.42
ns
Output Pad Transition Times (Medium Drive)
tr, tf
15 pF
35 pF
—
—
2.88/2.42
5.43/5.02
ns
Output Pad Transition Times (Low Drive)
tr, tf
15 pF
35 pF
—
—
4.94/4.50
10.55/9.70
ns
Output Pad Slew Rate (Max Drive)1
tps
15 pF
35 pF
0.5/0.65
0.32/0.37
—
—
Output Pad Slew Rate (High Drive)1
tps
15 pF
35 pF
0.43/0.54
0.26/0.41
—
—
Output Pad Slew Rate (Medium Drive)1
tps
15 pF
35 pF
0.34/0.41
0.18/0.2
—
—
Output Pad Slew Rate (Low Drive)1
tps
15 pF
35 pF
0.20/0.22
0.09/0.1
—
—
Output Pad di/dt (Max Drive)
tdit
—
—
—
30
Output Pad di/dt (High Drive)
tdit
—
—
—
23
Output Pad di/dt (Medium drive)
tdit
—
—
—
15
Output Pad di/dt (Low drive)
tdit
—
—
—
7
trm
—
—
—
25
V/ns
mA/ns
2
Input Transition Times
1
2
ns
tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.
Hysteresis mode is recommended for inputs with transition times greater than 25 ns.
Table 21. GPIO I/O AC Parameters Fast Mode
Parameter
Symbol
Test
Condition
Min
Typ
Max
Unit
Output Pad Transition Times (Max Drive)
tr, tf
15 pF
35 pF
—
—
1.45/1.24
2.76/2.54
ns
Output Pad Transition Times (High Drive)
tr, tf
15 pF
35 pF
—
—
1.81/1.59
3.57/3.33
ns
Output Pad Transition Times (Medium
Drive)
tr, tf
15 pF
35 pF
—
—
2.54/2.29
5.25/5.01
ns
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
39
Electrical Characteristics
Table 21. GPIO I/O AC Parameters Fast Mode (continued)
Parameter
Symbol
Test
Condition
Min
Typ
Max
Unit
ns
Output Pad Transition Times (Low Drive)
tr, tf
15 pF
35 pF
—
—
4.82/4.5
10.54/9.95
Output Pad Slew Rate (Max Drive)1
tps
15 pF
35 pF
0.69/0.78
0.36/0.39
—
—
Output Pad Slew Rate (High Drive)1
tps
15 pF
35 pF
0.55/0.62
0.28/0.30
—
—
Output Pad Slew Rate (Medium Drive)1
tps
15 pF
35 pF
0.39/0.44
0.19/0.20
—
—
Output Pad Slew Rate (Low Drive)1
tps
15 pF
35 pF
0.21/0.22
0.09/0.1
—
—
Output Pad di/dt (Max Drive)
tdit
—
—
—
70
mA/ns
Output Pad di/dt (High Drive)
tdit
—
—
—
53
mA/ns
Output Pad di/dt (Medium drive)
tdit
—
—
—
35
mA/ns
Output Pad di/dt (Low drive)
tdit
—
—
—
18
mA/ns
Input Transition Times2
trm
—
—
—
25
ns
1
V/ns
V/ns
V/ns
V/ns
tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.
Hysteresis mode is recommended for inputs with transition time greater than 25 ns.
2
4.5.2
LPDDR2 I/O AC Electrical Characteristics
The DDR2/LVDDR2 interface mode fully complies with JESD79-2E DDR2 JEDEC standard release
April, 2008. The DDR3 interface mode fully complies with JESD79-3D DDR3 JEDEC standard release
April, 2008.
Table 22 shows the AC parameters for LPDDR2 I/O operating in DDR2 mode.
Table 22. LPDDR2 I/O DDR2 mode AC Characteristics1
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
AC input logic high
Vih(ac)
—
Vref+0.25
—
—
V
AC input logic low
Vil(ac)
—
—
—
Vref-0.25
V
Vid(ac)
—
0.5
—
OVDD
V
Vix(ac)
—
Vref – 0.175
—
Vref + 0.175
V
Vox(ac)
—
Vref – 0.125
—
Vref + 0.125
V
tsr
At 25 Ω to Vref
0.4
—
2
V/ns
tSKD
clk=266Mhz
clk=400Mhz
—
—
0.2
0.1
ns
AC differential input voltage2
Input AC differential cross point
voltage3
Output AC differential cross point voltage4
Single output slew rate
Skew between pad rise/fall asymmetry +
skew caused by SSN
1
Note that the JEDEC SSTL_18 specification (JESD8-15a) for class II operation supersedes any specification in this
document.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
40
Freescale Semiconductor
Electrical Characteristics
2
Vid(ac) specifies the input differential voltage |Vtr – Vcp| required for switching, where Vtr is the “true” input signal and Vcp is
the “complementary” input signal. The Minimum value is equal to Vih(ac) – Vil(ac).
3
The typical value of Vix(ac) is expected to be about 0.5 * OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)
indicates the voltage at which differential input signal must cross.
4
The typical value of Vox(ac) is expected to be about 0.5 * OVDD and Vox(ac) is expected to track variation in OVDD. Vox(ac)
indicates the voltage at which differential output signal must cross.
Table 23 shows the AC parameters for LPDDR2 I/O operating in LPDDR2 mode.
Table 23. LPDDR2 I/O LPDDR2 mode AC Characteristics1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
AC input logic high
Vih(ac)
—
Vref + 0.22
—
OVDD
V
AC input logic low
Vil(ac)
—
0
—
Vref – 0.22
V
AC differential input high voltage2
Vidh(ac)
—
0.44
—
—
V
AC differential input low voltage
Vidl(ac)
—
—
—
0.44
V
Input AC differential cross point voltage3
Vix(ac)
Relative to OVDD/2
-0.12
—
0.12
V
Over/undershoot peak
Vpeak
—
—
—
0.35
V
Over/undershoot area (above OVDD
or below OVSS)
Varea
266MHz
—
—
0.6
V*ns
tsr
50Ohm to Vref.
5pF load.
Drive impedance=
40Ohm +-30%
1.5
—
3.5
V/ns
50Ohm to Vref.
5pF load.Drive
impedance= 60Ohm
+-30%
1
—
2.5
clk=266MHz
clk=400MHz
—
—
0.2
0.1
Single output slew rate
Skew between pad rise/fall asymmetry +
skew caused by SSN
tSKD
ns
1
Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.
Vid(ac) specifies the input differential voltage |Vtr – Vcp| required for switching, where Vtr is the “true” input signal and Vcp is
the “complementary” input signal. The Minimum value is equal to Vih(ac) – Vil(ac).
3 The typical value of Vix(ac) is expected to be about 0.5 * OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)
indicates the voltage at which differential input signal must cross.
2
Table 24 shows the AC parameters for LPDDR2 I/O operating in DDR3 mode.
Table 24. LPDDR2 I/O DDR3 mode AC Characteristics1
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
AC input logic high
Vih(ac)
—
Vref + 0.175
—
OVDD
V
AC input logic low
Vil(ac)
—
0
—
Vref – 0.175
V
Vid(ac)
—
0.35
—
—
V
Vix(ac)
—
Vref – 0.15
—
Vref + 0.15
V
AC differential input voltage2
Input AC differential cross point
voltage3
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
41
Electrical Characteristics
Table 24. LPDDR2 I/O DDR3 mode AC Characteristics1 (continued)
Parameter
Symbol Test Condition
Output AC differential cross point voltage4
Single output slew rate
Skew between pad rise/fall asymmetry +
skew caused by SSN
Min
Typ
Max
Unit
Vox(ac)
—
Vref – 0.15
—
Vref + 0.15
V
tsr
At 25 Ω to Vref
2.5
—
5
V/ns
tSKD
clk=266MHz
clk=400MHz
—
—
0.2
0.1
ns
1
Note that the JEDEC JESD79_3C specification supersedes any specification in this document.
Vid(ac) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the “true” input signal and Vcp is
the “complementary” input signal. The Minimum value is equal to Vih(ac) – Vil(ac).
3
The typical value of Vix(ac) is expected to be about 0.5 * OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)
indicates the voltage at which differential input signal must cross.
4
The typical value of Vox(ac) is expected to be about 0.5 * OVDD and Vox(ac) is expected to track variation in OVDD. Vox(ac)
indicates the voltage at which differential output signal must cross.
2
4.5.3
LVIO I/O AC Electrical Characteristics
AC electrical characteristics for LVIO I/O in slow and fast modes are presented in the Table 25 and
Table 26, respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bit
in the IOMUXC control registers.
Table 25. LVIO I/O AC Parameters in Slow Mode
Parameter
Input Transition Times1
1
Symbol Test Condition
trm
—
Min
Typ
Max
Unit
—
—
25
ns
Hysteresis mode is recommended for inputs with transition times greater than 25 ns.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
42
Freescale Semiconductor
Electrical Characteristics
4.5.4
UHVIO I/O AC Electrical Characteristics
Table 26. LVIO I/O AC Parameters in Fast Mode
Parameter
Input Transition Times1
1
Symbol
Test
Condition
Min
Typ
Max
Unit
trm
—
—
—
25
ns
Hysteresis mode is recommended for inputs with transition time greater than 25 ns.
Table 27 shows the AC parameters for UHVIO I/O operating in low output voltage mode. Table 28
shows the AC parameters for UHVIO I/O operating in high output voltage mode.
Table 27. AC Electrical Characteristics of UHVIO Pad (Low Output Voltage Mode)
Parameter
Symbol Test Condition
Min
Typ
Max
Output Pad Transition Times (High Drive)
tr, tf
15 pF
35 pF
—
—
1.59/1.69
3.05/3.30
Output Pad Transition Times (Medium Drive)
tr, tf
15 pF
35 pF
—
—
2.16/2.35
4.45/4.84
Output Pad Transition Times (Low Drive)
tr, tf
15 pF
35 pF
—
—
4.06/4.42
8.79/9.55
Output Pad Slew Rate (High Drive)1
tps
15 pF
35 pF
0.63/0.59
0.33/0.30
—
—
Output Pad Slew Rate (Medium Drive)1
tps
15 pF
35 pF
0.46/0.42
0.22/0.21
—
—
Output Pad Slew Rate (Low Drive)1
tps
15 pF
35 pF
0.25/0.23
0.11/0.11
—
—
Output Pad di/dt (High Drive)
tdit
—
—
—
43.6
Output Pad di/dt (Medium drive)
tdit
—
—
—
32.3
Output Pad di/dt (Low drive)
tdit
—
—
—
18.24
trm
—
—
—
25
Input Transition
1
2
Times2
Unit
ns
V/ns
mA/ns
ns
tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.
Hysteresis mode is recommended for inputs with transition times greater than 25 ns.
Table 28. AC Electrical Characteristics of UHVIO Pad (High Output Voltage Mode)
Parameter
Symbol Test Condition
Min
Typ
Max
Output Pad Transition Times (High Drive)
tr, tf
15 pF
35 pF
—
—
1.72/1.92
3.46/3.70
Output Pad Transition Times (Medium Drive)
tr, tf
15 pF
35 pF
—
—
2.38/2.56
5.07/5.25
Output Pad Transition Times (Low Drive)
tr, tf
15 pF
35 pF
—
—
4.55/4.58
10.04/9.94
Unit
ns
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
43
Electrical Characteristics
Table 28. AC Electrical Characteristics of UHVIO Pad (High Output Voltage Mode) (continued)
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
Output Pad Slew Rate (High Drive)1
tps
15 pF
35 pF
1.05/0.94
0.52/0.49
—
—
Output Pad Slew Rate (Medium Drive)1
tps
15 pF
35 pF
0.76/0.71
0.36/0.34
—
—
Output Pad Slew Rate (Low Drive)1
tps
15 pF
35 pF
0.40/0.93
0.18/0.18
—
—
Output Pad di/dt (High Drive)
tdit
—
—
—
82.8
Output Pad di/dt (Medium drive)
tdit
—
—
—
65.6
Output Pad di/dt (Low drive)
tdit
—
—
—
43.1
Input Transition Times2
trm
—
—
—
25
ns
Unit
1
2
V/ns
mA/ns
tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.
Hysteresis mode is recommended for inputs with transition times greater than 25 ns.
4.5.5
LVDS I/O AC Electrical Characteristics
The differential output transition time waveform is shown in Figure 7.
Figure 7. Differential LVDS Driver Transition Time Waveform
Table 29 shows the AC parameters for LVDS I/O.
Table 29. AC Electrical Characteristics of LVDS Pad
Parameter
Symbol Test Condition
Transition Low to High Time1
tTLH
Transition High to Low Time1
tTHL
Operating Frequency
Offset voltage imbalance
1
Min
Typ
Max
Rload = 100 Ω,
Cload = 2 pF
0.26
—
0.5
0.26
—
0.5
f
—
—
300
—
MHz
Vos
—
—
—
150
mV
ns
Measurement levels are 20-80% from output voltage.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
44
Freescale Semiconductor
Electrical Characteristics
4.6
System Modules Timing
This section contains the timing and electrical parameters for the modules in the i.MX53xA processor.
4.6.1
Reset Timings Parameters
Figure 8 shows the reset timing and Table 30 lists the timing parameters.
RESET_IN
(Input)
CC1
Figure 8. Reset Timing Diagram
Table 30. Reset Timing Parameters
ID
CC1
4.6.2
Parameter
Duration of RESET_IN to be qualified as valid (input slope = 5 ns)
Min
Max
Unit
50
—
ns
WDOG Reset Timing Parameters
Figure 9 shows the WDOG reset timing and Table 31 lists the timing parameters.
WATCHDOG_RST
(Input)
CC5
Figure 9. WATCHDOG_RST Timing Diagram
Table 31. WATCHDOG_RST Timing Parameters
ID
CC5
Parameter
Duration of WATCHDOG_RESET Assertion
Min
Max
Unit
1
—
TCKIL
NOTE
CKIL is approximately 32 kHz. TCKIL is one period or approximately 30 μs.
4.6.3
Clock Amplifier Parameters (CKIH1, CKIH2)
The input to Clock Amplifier (CAMP) is internally ac-coupled allowing direct interface to a square wave
or sinusoidal frequency source. No external series capacitors are required.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
45
Electrical Characteristics
Table 32 shows the electrical parameters of CAMP.
Table 32. CAMP Electrical Parameters (CKIH1, CKIH2)
Parameter
Min
Typ
Max
Unit
Input frequency
8.0
—
40.0
MHz
VIL (for square wave input)
0
—
0.3
V
NVCC_CKIH – 0.25
—
NVCC_CKIH
V
Sinusoidal input amplitude
0.4
—
VDD
Vp-p
Output duty cycle
45
50
55
%
VIH (for square wave input)1
1
NVCC_CKIH is the supply voltage of CAMP.
4.6.4
DPLL Electrical Parameters
Table 33 shows the electrical parameters of digital phase-locked loop (DPLL).
Table 33. DPLL Electrical Parameters
Parameter
Test Conditions/Remarks
Min
Typ
Max
Unit
Reference clock frequency range1
—
10
—
100
MHz
Reference clock frequency range after
pre-divider
—
10
—
40
MHz
Output clock frequency range (dpdck_2)
—
300
—
1025
MHz
—
1
—
16
—
—
5
—
15
—
–67108862
—
67108862
—
Pre-division factor
2
Multiplication factor integer part
Multiplication factor
numerator3
Should be less than denominator
Multiplication factor denominator2
—
1
—
67108863
—
Output Duty Cycle
—
48.5
50
51.5
%
Frequency lock time4
(FOL mode or non-integer MF)
—
—
—
398
Tdpdref
Phase lock time
—
—
—
100
µs
—
—
0.02
0.04
Tdck
Phase jitter (peak value)
FPL mode, integer and fractional MF
—
2.0
3.5
ns
Power dissipation
fdck = 300 MHz at avdd = 1.8 V,
dvdd = 1.2 V
fdck = 650 MHz at avdd = 1.8 V,
dvdd = 1.2 V
—
—
0.65 (avdd)
0.92 (dvdd)
1.98 (avdd)
1.8 (dvdd)
mW
Frequency
jitter5
(peak value)
1
Device input range cannot exceed the electrical specifications of the CAMP, see Table 32.
The values specified here are internal to DPLL. Inside the DPLL, a “1” is added to the value specified by the user. Therefore,
the user has to enter a value “1” less than the desired value at the inputs of DPLL for PDF and MFD.
3
The maximum total multiplication factor (MFI + MFN/MFD) allowed is 15. Therefore, if the MFI value is 15, MFN value must
be zero.
2
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
46
Freescale Semiconductor
Electrical Characteristics
4
Tdpdref is the time period of the reference clock after predivider. According to the specification, the maximum lock time in FOL
mode is 398 cycles of divided reference clock when DPLL starts after full reset.
5
Tdck is the time period of the output clock, dpdck_2.
4.6.5
NAND Flash Controller (NFC) Parameters
This section provides the relative timing requirements among various signals of NFC at the module level,
in each operational mode.
Timing parameters in Figure 10, Figure 11, Figure 12, Figure 13, Figure 15, and Table 35 show the default
NFC mode (asymmetric mode) using two Flash clock cycles per one access of RE_B and WE_B.
Timing parameters in Figure 10, Figure 11, Figure 12, Figure 14, Figure 15, and Table 35 show symmetric
NFC mode using one Flash clock cycle per one access of RE_B and WE_B.
With reference to the timing diagrams, a high is defined as 80% of signal value and low is defined as 20%
of signal value. All parameters are given in nanoseconds. The BGA contact load used in calculations is
20 pF (except for NF16 - 40 pF) and there is maximum drive strength on all contacts.
All timing parameters are a function of T, which is the period of the flash_clk clock (“enfc_clk” at system
level). This clock frequency can be controlled by the user, configuring CCM (SoC clock controller). The
clock is derived from emi_slow_clk after single divider.
Figure 34 demonstrates several examples of clock frequency settings.
Table 34. NFC Clock Settings Examples
emi_slow_clk (MHz)
nfc_podf (Division Factor)
enfc_clk (MHz)
T-Clock Period (ns)
100 (Boot mode)
71
14.29
70
32
33.33
30
4
33.33
30
3
44.33
3
2
663
133
22.5
15
1
Boot value NFC_FREQ_SEL Fuse High (burned)
Boot value NFC_FREQ_SEL Fuse Low
3 For RBB_MODE=1, using NANDF_RB0 signal for ready/busy indication. This mode require setting the delay line. See the
Reference Manual for details.
2
NOTE
A potential limitation for minimum clock frequency may exist for some
devices. When the clock frequency is too low, the data bus capturing might
occur after the specified trhoh (RE_B high to output hold) period. Setting the
clock frequency above 25.6 MHz (that is, T = 39 ns) guaranties a proper
operation for devices having trhoh > 15 ns. It is also recommended that the
NFC_FREQ_SEL Fuse be set accordingly to initiate the boot with
33.33 MHz clock.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
47
Electrical Characteristics
Lower frequency operation can be supported for most available devices in
the market, relying on data lines Bus-Keeper logic. This depends on device
behavior on the data bus in the time interval between data output valid to
data output high-Z state. In NAND device parameters this period is marked
between trhoh and trhz (RE_B high to output high-Z). In most devices, the
data transition from valid value to high-Z occurs without going through
other states. Setting the data bus pads to Bus-Keeper mode in the IOMUXC
registers, keeps the data bus valid internally after the specified hold time,
allowing proper capturing with slower clock.
NFCLE
NF2
NF1
NF3
NF4
NFCE_B
NF5
NFWE_B
NF8
NFIO[7:0]
NF9
command
Figure 10. Command Latch Cycle Timing
NF4
NF3
NFCE_B
NF10
NF11
NF5
NFWE_B
NF7
NF6
NFALE
NF8
NFIO[7:0]
NF9
Address
Figure 11. Address Latch Cycle Timing
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
48
Freescale Semiconductor
Electrical Characteristics
NF3
NFCE_B
NF10
NF11
NF5
NFWE_B
NF8
NFIO[15:0]
NF9
Data to NF
Figure 12. Write Data Latch Timing
NFCE_B
NF14
NF15
NF13
NFRE_B
NF17
NF16
NFRB_B
NF12
NFIO[15:0]
Data from NF
Figure 13. Read Data Latch Timing, Asymmetric Mode
NFCE_B
NF14
NF15
NF13
NFRE_B
NF16
NF18
NFRB_B
NF12
NFIO[15:0]
Data from NF
Figure 14. Read Data Latch Timing, Symmetric Mode
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
49
Electrical Characteristics
NF19
NFCLE
NF20
NFCE_B
NFWE_B
NF21
NF22
NFRE_B
NFRB_B
Figure 15. Other Timing Parameters
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
50
Freescale Semiconductor
Electrical Characteristics
Table 35. NFC—Timing Characteristics
ID
Parameter
Symbol
Asymmetric Mode Min
Symmetric Mode
Min
Max
NF1
NFCLE setup Time
tCLS
2T + 0.1
2T + 0.1
—
NF2
NFCLE Hold Time
tCLH
T – 4.45
T – 4.45
—
NF31
NFCE_B Setup Time
tCS
3T + 0.95
3T+0.95
—
NF4
NFCE_B Hold Time
tCH
2T–5.55
1.5T–5.55
—
NF5
NFWE_B Pulse Width
tWP
T – 1.4
0.5T – 1.4
—
NF6
NFALE Setup Time
tALS
2T + 0.1
2T + 0.1
—
NF7
NFALE Hold Time
tALH
T – 4.45
T – 4.45
—
NF8
Data Setup Time
tDS
T – 0.9
0.5T – 0.9
—
NF9
Data Hold Time
tDH
T – 5.55
0.5T – 5.55
—
NF10
Write Cycle Time
tWC
2T
T–0.5
—
NF11
NFWE_B Hold Time
tWH
T – 1.15
0.5T – 1.15
—
NF12
Ready to NFRE_B Low
tRR
9T + 8.9
9T + 8.9
—
NF13
NFRE_B Pulse Width
tRP
1.5T
0.5T–1
—
NF14
READ Cycle Time
tRC
2T
T
—
NF15
NFRE_B High Hold Time
tREH
0.5T – 1.15
NF162
Data Setup on READ
tDSR
NF174
Data Hold on READ
tDHR
11.2 + 0.5T –
Tdl3
0.5T – 1.15
—
Tdl2
—
11.2 –
0
Tdl2
—
2Taclk + T
– 11.2
2Taclk + T
NF185
Data Hold on READ
tDHR
—
NF19
CLE to RE delay
tCLR
9T
9T
—
NF20
CE to RE delay
tCRE
T – 3.45
T – 3.45
T + 0.3
NF21
WE high to RE low
tWHR
10.5T
10.5T
—
NF22
WE high to busy
tWB
—
—
6T
1
In case of NUM_OF_DEVICES is greater than 0 (for example, interleaved mode), then only during the data phase of
symmetric mode the setup time will equal 1.5T + 0.95.
2 tDSR is calculated by the following formula:
Asymmetric mode: tDSR = tREpd + tDpd + 1/2T – Tdl2
Symmetric mode:
tDSR = tREpd + tDpd – Tdl2
tREpd + tDpd = 11.2 ns (including clock skew)
where tREpd is RE propogation delay in the chip including I/O pad delay, and tDpd is Data propogation delay from I/O pad to
EXTMC including I/O pad delay.
tDSR can be used to determine tREA max parameter with the following formula: tREA = 1.5T – tDSR.
3 Tdl is composed of 4 delay-line units each generates an equal delay with min 1.25 ns and max 1 aclk period (Taclk). Default
is 1/4 aclk period for each delay-line unit, so all 4 delay lines together generates a total of 1 aclk period. Taclk is
“emi_slow_clk” of the system, which default value is 7.5 ns (133 MHz).
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
51
Electrical Characteristics
4
NF17 is defined only in asymmetric operation mode.
NF17 max value is equivalent to max tRHZ value that can be used with NFC.
Taclk is “emi_slow_clk” of the system.
5
NF18 is defined only in Symmetric operation mode.
Tdl2 – (tREpd + tDpd)
tDHR (MIN) is calculated by the following formula:
where tREpd is RE propogation delay in the chip including I/O pad delay, and tDpd is Data propogation delay from I/O pad to
EXTMC including I/O pad delay.
NF18 max value is equivalent to max tRHZ value that can be used with NFC.
Taclk is “emi_slow_clk” of the system.
4.6.6
External Interface Module (EIM)
The following subsections provide information on the EIM.
4.6.6.1
EIM Signal Cross Reference
Table 36 is a guide intended to help the user identify signals in the External Interface Module Chapter of
the Reference Manual which are identical to those mentioned in this data sheet.
Table 36. EIM Signal Cross Reference
Reference Manual
EIM Chapter Nomenclature
BCLK
EIM_BCLK
CSx
EIM_CSx
WE_B
EIM_RW
OE_B
EIM_OE
BEy_B
EIM_EBx
ADV
EIM_LBA
ADDR
EIM_A[25:16], EIM_DA[15:0]
ADDR/M_DATA
DATA
WAIT_B
4.6.6.2
Data Sheet Nomenclature,
Reference Manual External Signals and Pin Multiplexing Chapter,
and IOMUXC Controller Chapter Nomenclature
EIM_DAx (Addr/Data muxed mode)
EIM_NFC_D (Data bus shared with NAND Flash)
EIM_Dx (dedicated data bus)
EIM_WAIT
EIM Interface Pads Allocation
EIM supports16-bit and 8-bit devices operating in address/data separate or multiplexed modes. In some
of the modes the EIM and the NAND FLASH have shared data bus. Table 37 provides EIM interface
pads allocation in different modes.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
52
Freescale Semiconductor
Electrical Characteristics
Table 37. EIM Internal Module Multiplexing
Multiplexed
Address/Data mode
Non Multiplexed Address/Data Mode
Setup
1
2
3
8 Bit
16 Bit
32 Bit
16 Bit
32 Bit
MUM = 0,
DSZ = 111
MUM = 0,
DSZ = 111
MUM = 0,
DSZ = 111
MUM = 0,
DSZ = 001
MUM = 0,
DSZ = 010
MUM = 0,
DSZ = 011
MUM = 1,
DSZ = 001
MUM = 1,
DSZ = 011
A[15:0]
EIM_DA
[15:0]
EIM_DA
[15:0]
EIM_DA
[15:0]
EIM_DA
[15:0]
EIM_DA
[15:0]
EIM_DA
[15:0]
EIM_DA
[15:0]
EIM_DA
[15:0]
A[25:16]
EIM_A
[25:16]
EIM_A
[25:16]
EIM_A
[25:16]
EIM_A
[25:16]
EIM_A
[25:16]
EIM_A
[24:16]1
EIM_A
[25:16]
NANDF_D
[8:0]1
D[7:0],
EIM_EB
0
NANDF_D
[7:0]2
—
—
NANDF_D
[7:0]2
—
NANDF_D
[7:0]
EIM_DA
[7:0]
EIM_DA
[7:0]
D[15:8],
EIM_EB
1
—
NANDF_D
[15:8]3
—
NANDF_D
[15:8]3
—
NANDF_D
[15:8]
EIM_DA
[15:8]
EIM_DA
[15:8]
D[23:16]
,
EIM_EB
2
—
—
—
—
EIM_D
[23:16]
EIM_D
[23:16]
—
NANDF_D
[7:0]
D[31:24]
,
EIM_EB
3
—
—
EIM_D
[31:24]
—
EIM_D
[31:24]
EIM_D
[31:24]
—
NANDF_D
[15:8]
For 32-bit mode, the address range is A[24:0], due to address space allocation in memory map.
NANDF_D[7:0] multiplexed on ALT3 mode of PATA_DATA[7:0]
NANDF_D[15:8] multiplexed on ALT3 mode of PATA_DATA[15:8]
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
53
Electrical Characteristics
4.6.6.3
General EIM Timing-Synchronous Mode
Figure 16, Figure 17, and Table 38 specify the timings related to the EIM module. All EIM output control
signals may be asserted and deasserted by an internal clock synchronized to the BCLK rising edge
according to corresponding assertion/negation control fields.
WE2
,
...
BCLK
WE4
WE3
WE1
WE5
Address
WE6
WE7
WE8
WE9
WE10
WE11
WE12
WE13
WE14
WE15
WE16
WE17
CSx_B
WE_B
OE_B
BEy_B
ADV_B
Output Data
Figure 16. EIM Outputs Timing Diagram
BCLK
WE18
Input Data
WE19
WE20
WAIT_B
WE21
Figure 17. EIM Inputs Timing Diagram
Table 38. EIM Bus Timing Parameters 1
BCD = 0
ID
BCD = 1
BCD = 2
BCD = 3
Parameter
Min
WE1 BCLK Cycle time2
WE2 BCLK Low Level
Width
Max
Min
Max
Min
Max
Min
t
2*t
3*t
4*t
0.4*t
0.8*t
1.2*t
1.6*t
Max
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
54
Freescale Semiconductor
Electrical Characteristics
Table 38. EIM Bus Timing Parameters (continued)1
BCD = 0
ID
BCD = 1
BCD = 2
BCD = 3
Parameter
Min
WE3 BCLK High Level
Width
Max
0.4*t
Min
Max
0.8*t
Min
Max
1.2*t
WE4 Clock rise to
address valid3
-0.5*t-1.25
-0.5*t+1.75
-t-1.25
-t+1.75
-1.5*t-1.2
5
WE5 Clock rise to
address invalid
0.5*t-1.25
0.5*t+1.75
t-1.25
t+1.75
WE6 Clock rise to
CSx_B valid
-0.5*t-1.25
-0.5*t+1.75
-t-1.25
WE7 Clock rise to
CSx_B invalid
0.5*t-1.25
0.5*t+1.75
WE8 Clock rise to
WE_B Valid
-0.5*t-1.25
WE9 Clock rise to
WE_B Invalid
Min
Max
1.6*t
-1.5*t
+1.75
-2*t-1.25
-2*t+1.75
1.5*t-1.2 1.5*t +1.75
5
2*t-1.25
2*t+1.75
-t+1.75
-1.5*t-1.2
5
-2*t-1.25
-2*t+1.75
t-1.25
t+1.75
1.5*t-1.2 1.5*t +1.75
5
2*t-1.25
2*t+1.75
-0.5*t+1.75
-t-1.25
-t+1.75
-1.5*t-1.2
5
-2*t-1.25
-2*t+1.75
0.5*t-1.25
0.5*t+1.75
t-1.25
t+1.75
1.5*t-1.2 1.5*t +1.75
5
2*t-1.25
2*t+1.75
WE10 Clock rise to OE_B -0.5*t-1.25
Valid
-0.5*t+1.75
-t-1.25
-t+1.75
-1.5*t-1.2
5
-2*t-1.25
-2*t+1.75
WE11 Clock rise to OE_B
Invalid
0.5*t-1.25
0.5*t+1.75
t-1.25
t+1.75
1.5*t-1.2 1.5*t +1.75
5
2*t-1.25
2*t+1.75
WE12 Clock rise to
BEy_B Valid
-0.5*t-1.25
-0.5*t+1.75
-t-1.25
-t+1.75
-1.5*t-1.2
5
-2*t-1.25
-2*t+1.75
WE13 Clock rise to
BEy_B Invalid
0.5*t-1.25
0.5*t+1.75
t-1.25
t+1.75
1.5*t-1.2 1.5*t +1.75
5
2*t-1.25
2*t+1.75
WE14 Clock rise to
ADV_B Valid
-0.5*t-1.25
-0.5*t+1.75
-t-1.25
-t+1.75
-1.5*t-1.2
5
-2*t-1.25
-2*t+1.75
WE15 Clock rise to
ADV_B Invalid
0.5*t-1.25
0.5*t+1.75
t-1.25
t+1.75
1.5*t-1.2 1.5*t +1.75
5
2*t-1.25
2*t+1.75
WE16 Clock rise to
Output Data Valid
-0.5*t-1.25
-0.5*t+1.75
-t-1.25
-t+1.75
-1.5*t-1.2
5
-2*t-1.25
-2*t+1.75
WE17 Clock rise to
Output Data
Invalid
0.5*t-1.25
0.5*t+1.75
t-1.25
t+1.75
1.5*t-1.2 1.5*t +1.75
5
2*t-1.25
2*t+1.75
WE18 Input Data setup
time to Clock rise
2
—
4
—
—
—
—
—
WE19 Input Data hold
time from Clock
rise
2
—
2
—
—
—
—
—
WE20 WAIT_B setup
time to Clock rise
2
—
4
—
—
—
—
—
WE21 WAIT_B hold time
from Clock rise
2
—
2
—
—
—
—
—
-1.5*t
+1.75
-1.5*t
+1.75
-1.5*t
+1.75
-1.5*t
+1.75
-1.5*t
+1.75
-1.5*t
+1.75
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
55
Electrical Characteristics
1
t is the maximal EIM logic (axi_clk) cycle time. The maximum allowed axi_clk frequency is 133 MHz, whereas the maximum
allowed BCLK frequency is 104 MHz. As a result, if BCD = 0, axi_clk must be ≤ 104 MHz. If BCD = 1, then 133 MHz is
allowed for axi_clk, resulting in a BCLK of 66.5 MHz. When the clock branch to EIM is decreased to 104 MHz, other busses
are impacted which are clocked from this source. See the CCM chapter of the i.MX53 Reference Manual for a detailed clock
tree description.
2
BCLK parameters are being measured from the 50% point, that is, high is defined as 50% of signal value and low is defined
as 50% as signal value.
3
For signal measurements “High” is defined as 80% of signal value and “Low” is defined as 20% of signal value.
4.6.6.4
Examples of EIM Synchronous Accesses
Figure 18 to Figure 21 provide few examples of basic EIM accesses to external memory devices with the
timing parameters mentioned previously for specific control parameters settings.
BCLK
WE4
ADDR
WE5
Address v1
Last Valid Address
WE6
WE7
CSx_B
WE_B
WE14
ADV_B
WE15
WE10
WE11
WE12
WE13
OE_B
BEy_B
WE18
DATA
D(v1)
WE19
Figure 18. Synchronous Memory Read Access, WSC=1
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
56
Freescale Semiconductor
Electrical Characteristics
BCLK
WE5
WE4
ADDR
Last Valid Address
Address V1
WE6
WE7
WE8
WE9
CSx_B
WE_B
WE14
ADV_B
WE15
OE_B
WE13
WE12
BEy_B
WE16
WE17
DATA
D(V1)
Figure 19. Synchronous Memory, Write Access, WSC=1, WBEA=0, and WADVN=0
BCLK
WE4
ADDR/
M_DATA
Valid
LastAddr
WE6
WE5
WE17
WE16
Write Data
Address V1
WE7
CSx_B
WE8
WE_B
WE14
WE9
WE15
ADV_B
OE_B
WE10
WE11
BEy_B
Figure 20. Muxed Address/Data (A/D) Mode, Synchronous Write Access, WSC=6, ADVA=0, ADVN=1, and
ADH=1
NOTE
In 32-bit muxed address/data (A/D) mode the 16 MSBs are driven on the
data bus.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
57
Electrical Characteristics
BCLK
ADDR/
M_DATA
WE4
Last Valid Addr
WE6
WE19
WE5
Address V1
Data
WE18
CSx_B
WE7
WE_B
WE14
ADV_B
WE15
WE10
WE11
OE_B
WE12
WE13
BEy_B
Figure 21. 16-Bit Muxed A/D Mode, Synchronous Read Access, WSC=7, RADVN=1, ADH=1, and OEA=0
4.6.6.5
General EIM Timing-Asynchronous Mode
Figure 22 through Figure 27, and Table 39 help to determine timing parameters relative to the chip select
(CS) state for asynchronous and DTACK EIM accesses with corresponding EIM bit fields and the timing
parameters mentioned above.
Asynchronous read and write access length in cycles may vary from what is shown in Figure 22 through
Figure 25 as RWSC, OEN, and CSN is configured differently. Refer to i.MX53xA RM for the EIM
programming model.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
58
Freescale Semiconductor
Electrical Characteristics
end of
access
start of
access
INT_CLK
MAXCSO
CSx_B
ADDR/
M_DATA
WE31
Last Valid Address
WE32
Next Address
Address V1
WE_B
ADV_B
WE39
WE40
WE35
WE36
WE37
WE38
OE_B
BEy_B
WE44
MAXCO
DATA[7:0]
D(V1)
WE43
MAXDI
Figure 22. Asynchronous Memory Read Access (RWSC = 5)
end of
access
start of
access
INT_CLK
MAXCSO
CSx_B
MAXDI
WE31
ADDR/
M_DATA
Addr. V1
D(V1)
WE32A
WE_B
WE44
WE40A
WE39
ADV_B
WE35A
WE36
OE_B
WE37
WE38
BEy_B
MAXCO
Figure 23. Asynchronous A/D Muxed Read Access (RWSC = 5)
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
59
Electrical Characteristics
CSx_B
WE31
ADDR
Last Valid Address
WE33
WE32
Next Address
Address V1
WE34
WE_B
WE39
WE40
WE45
WE46
ADV_B
OE_B
BEy_B
WE42
DATA
D(V1)
WE41
Figure 24. Asynchronous Memory Write Access
CSx_B
WE41
WE31
ADDR/
M_DATA
Addr. V1
D(V1)
WE32A
WE33
WE34
WE42
WE_B
WE40A
ADV_B
WE39
OE_B
WE45
WE46
BEy_B
WE42
Figure 25. Asynchronous A/D Muxed Write Access
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
60
Freescale Semiconductor
Electrical Characteristics
CSx_B
WE31
ADDR
Last Valid Address
WE32
Next Address
Address V1
WE_B
WE39
WE40
WE35
WE36
WE37
WE38
ADV_B
OE_B
BEy_B
WE44
DATA[7:0]
D(V1)
WE43
WE48
DTACK
WE47
Figure 26. DTACK Read Access (DAP=0)
CSx_B
WE31
ADDR
Last Valid Address
WE32
Next Address
Address V1
WE33
WE34
WE39
WE40
WE45
WE46
WE_B
ADV_B
OE_B
BEy_B
WE42
DATA
D(V1)
WE41
WE48
DTACK
WE47
Figure 27. DTACK Write Access (DAP=0)
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
61
Electrical Characteristics
Table 39. EIM Asynchronous Timing Parameters Table Relative Chip Select
Min
Max
(If 133 Mhz is
supported by
SOC)
Unit
WE4 - WE6 - CSA3
—
3 - CSA
ns
Address Invalid to CSx_B
invalid
WE7 - WE5 - CSN4
—
3 - CSN
ns
WE32
A(mux
ed A/D
CSx_B valid to Address
Invalid
t5 + WE4 - WE7 + (ADVN +
ADVA + 1 - CSA3)
-3 + (ADVN +
ADVA + 1 - CSA)
—
ns
WE33
CSx_B Valid to WE_B Valid
WE8 - WE6 + (WEA - CSA)
—
3 + (WEA - CSA)
ns
WE34
WE_B Invalid to CSx_B
Invalid
WE7 - WE9 + (WEN - CSN)
—
3 - (WEN_CSN)
ns
WE35
CSx_B Valid to OE_B Valid
WE10 - WE6 + (OEA - CSA)
—
3 + (OEA - CSA)
ns
WE35
A
(muxe
d A/D)
CSx_B Valid to OE_B Valid
WE10 - WE6 + (OEA +
RADVN + RADVA + ADH + 1
- CSA)
-3 + (OEA +
RADVN+RADVA
+ADH+1-CSA)
3 + (OEA +
RADVN+RADVA+A
DH+1-CSA)
ns
WE36
OE_B Invalid to CSx_B
Invalid
WE7 - WE11 + (OEN - CSN)
—
3 - (OEN - CSN)
ns
WE37
CSx_B Valid to BEy_B Valid
(Read access)
WE12 - WE6 + (RBEA - CSA)
—
3 + (RBEA6 - CSA)
ns
WE38
BEy_B Invalid to CSx_B
Invalid (Read access)
WE7 - WE13 + (RBEN - CSN)
—
3 - (RBEN7- CSN)
ns
WE39
CSx_B Valid to ADV_B Valid
WE14 - WE6 + (ADVA - CSA)
—
3 + (ADVA - CSA)
ns
WE40
ADV_B Invalid to CSx_B
Invalid (ADVL is asserted)
WE7 - WE15 - CSN
—
3 - CSN
ns
WE40
A
(muxe
d A/D)
CSx_B Valid to ADV_B Invalid
WE14 - WE6 + (ADVN +
ADVA + 1 - CSA)
-3 + (ADVN +
ADVA + 1 - CSA)
3 + (ADVN + ADVA
+ 1 - CSA)
ns
WE41
CSx_B Valid to Output Data
Valid
WE16 - WE6 - WCSA
—
3 - WCSA
ns
WE41
A
(muxe
d A/D)
CSx_B Valid to Output Data
Valid
WE16 - WE6 + (WADVN +
WADVA + ADH + 1 - WCSA)
—
3 + (WADVN +
WADVA + ADH + 1 WCSA)
ns
WE42
Output Data Invalid to CSx_B
Invalid
WE17 - WE7 - CSN
—
3 - CSN
ns
Parameter
Determination by
Synchronous measured
parameters 12
WE31
CSx_B valid to Address Valid
WE32
Ref
No.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
62
Freescale Semiconductor
Electrical Characteristics
Table 39. EIM Asynchronous Timing Parameters Table Relative Chip Select
Ref
No.
1
2
3
4
5
6
7
Parameter
Determination by
Synchronous measured
parameters 12
Min
Max
(If 133 Mhz is
supported by
SOC)
Unit
ns
MAXC
O
Output max. delay from
internal driving ADDR/control
FFs to chip outputs.
10
—
—
MAXC
SO
Output max. delay from CSx
internal driving FFs to CSx
out.
10
—
—
MAXDI
DATA MAXIMUM delay from
chip input data to its internal
FF
5
—
—
WE43
Input Data Valid to CSx_B
Invalid
MAXCO - MAXCSO + MAXDI
MAXCO MAXCSO +
MAXDI
—
ns
WE44
CSx_B Invalid to Input Data
invalid
0
0
—
ns
WE45
CSx_B Valid to BEy_B Valid
(Write access)
WE12 - WE6 + (WBEA - CSA)
—
3 + (WBEA - CSA)
ns
WE46
BEy_B Invalid to CSx_B
Invalid (Write access)
WE7 - WE13 + (WBEN CSN)
—
-3 + (WBEN - CSN)
ns
MAXD
TI
DTACK MAXIMUM delay from
chip dtack input to its internal
FF + 2 cycles for
synchronization
—
—
—
WE47
Dtack Active to CSx_B Invalid
MAXCO - MAXCSO +
MAXDTI
MAXCO MAXCSO +
MAXDTI
—
ns
WE48
CSx_B Invalid to Dtack
invalid
0
0
—
ns
Parameters WE4... WE21 value see column BCD = 0 in Table 38
All config. parameters (CSA,CSN,WBEA,WBEN,ADVA,ADVN,OEN,OEA,RBEA & RBEN) are in cycle units.
CS Assertion. This bit field determines when CS signal is asserted during read/write cycles.
CS Negation. This bit field determines when CS signal is negated during read/write cycles.
t is axi_clk cycle time.
BE Assertion. This bit field determines when BE signal is asserted during read cycles.
BE Negation. This bit field determines when BE signal is negated during read cycles.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
63
Electrical Characteristics
4.6.7
DDR SDRAM Specific Parameters (DDR2/LVDDR2, LPDDR2, and
DDR3)
The DDR2/LVDDR2 interface fully complies with JESD79-2E – DDR2 JEDEC release April, 2008,
supporting DDR2-800 and LVDDR2-800.
The DDR3 interface fully complies with JESD79-3D – DDR3 JEDEC release April 2008 supporting
DDR3-800.
The LPDDR2 interface fully complies with JESD209-2B, supporting LPDDR2-800.
Figure 28 and Table 40 show the address and control timing parameters for DDR2 and DDR3.
DDR1
SDCLK
SDCLK
DDR2
DDR4
CS
DDR5
RAS
DDR5
DDR4
CAS
DDR4
DDR5
DDR5
WE
ODT/CKE
DDR4
DDR6
DDR7
ADDR
ROW/BA
COL/BA
Figure 28. DDR SDRAM Address and Control Parameters for DDR2 and DDR3
Table 40. DDR SDRAM Timing Parameter Table1 2
SDCLK = 400 MHz
ID
Parameter
Symbol
Units
Min
Max
DDR1
SDRAM clock high-level width
tCH
0.48
0.52
tCK
DDR2
SDRAM clock low-level width
tCL
0.48
0.52
tCK
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
64
Freescale Semiconductor
Electrical Characteristics
Table 40. DDR SDRAM Timing Parameter Table1 2 (continued)
SDCLK = 400 MHz
ID
1
2
Parameter
Symbol
Units
Min
Max
DDR4
CS, RAS, CAS, CKE, WE, ODT setup time
tIS
0.6
—
ns
DDR5
CS, RAS, CAS, CKE, WE, ODT hold time
tIH
0.6
—
ns
DDR6
Address output setup time
tIS
0.6
—
ns
DDR7
Address output hold time
tIH
0.6
—
ns
All timings are refer to Vref level cross point.
Reference load model is 25 ohm resistor from each of the DDR outputs to VDD_REF.
Figure 29 and Table 41 show the address and control timing parameters for LPDDR2.
CK
LP1
LP4
CS
LP2
LP3
CKE
LP3
LP4
LP3
CA
LP3
LP4
Figure 29. DDR SDRAM Address and Control Timing Parameters for LPDDR2
Table 41. DDR SDRAM Timing Parameter Table for LPDDR21 2
SDCLK = 400 MHz
ID
1
2
Parameter
Symbol
Units
Min
Max
LP1
SDRAM clock high-level width
tCH
0.45
0.55
tCK
LP2
SDRAM clock low-level width
tCL
0.45
0.55
tCK
LP3
CS, CKE setup time
tIS
0.3
—
ns
LP4
CS, CKE hold time
tIH
0.3
—
ns
LP3
CA setup time
tIS
0.3
—
ns
LP4
CA hold time
tIH
0.3
—
ns
All timings are refer to Vref level cross point.
Reference load model is 25 ohm resistor from each of the DDR outputs to VDD_REF.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
65
Electrical Characteristics
Figure 30 and Table 42 show the data write timing parameters.
SDCLK
SDCLK_B
DDR21
DDR22
DDR23
DQS (output)
DDR18
DDR17
DQ (output)
DQM (output)
DDR17
DDR17
DDR18
Data
Data
Data
Data
Data
Data
Data
Data
DM
DM
DM
DM
DM
DM
DM
DM
DDR18
DDR17
DDR18
Figure 30. DDR SDRAM Data Write Cycle
Table 42. DDR SDRAM Write Cycle 1 2 3
SDCLK = 400 MHz
ID
Parameter
Symbol
Unit
Min
Max
DDR17
DQ and DQM setup time to DQS (differential strobe)
tDS
0.285
—
ns
DDR18
DQ and DQM hold time to DQS (differential strobe)
tDH
0.285
—
ns
DDR21
DQS latching rising transitions to associated clock edges
tDQSS
-0.25
+0.25
tCK
DDR22
DQS high level width
tDQSH
0.45
0.55
tCK
DDR23
DQS low level width
tDQSL
0.45
0.55
tCK
1
All timings are refer to Vref level cross point.
Reference load model is 25 ohm resistor from each of the DDR outputs to VDD_REF.
3 To receive the reported setup and hold values, write calibration should be performed in order to locate the DQS in the middle
of DQ window.
2
Figure 31 and Table 43 show the data read timing parameters.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
66
Freescale Semiconductor
Electrical Characteristics
SDCLK
SDCLK_B
DQS (input)
DDR27
DQ (input)
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DDR26
Figure 31. DDR SDRAM DQ vs. DQS and SDCLK Read Cycle
Table 43. DDR SDRAM Read Cycle 1
SDCLK = 400 MHz
ID
DDR26
Symbol
Unit
Min
Max
Minimum required DQ valid window width
except from LPDDR2
—
0.6
—
ns
DDR26(LP Minimum required DQ valid window width
DDR2)
for LPDDR2
—
0.425
—
ns
—
0.275
0.475
ns
DDR27
1
Parameter
DQS to DQ valid data
To receive the reported setup and hold values, read calibration should be performed in order to locate the DQS in the middle
of DQ window.
4.7
External Peripheral Interfaces Parameters
The following subsections provide information on external peripheral interfaces.
4.7.1
AUDMUX Timing Parameters
The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between
internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of
AUDMUX external pins is governed by the SSI module. For more information, see the respective SSI
electrical specifications found within this document.
4.7.2
CSPI and ECSPI Timing Parameters
This section describes the timing parameters of the CSPI and ECSPI blocks. The CSPI and ECSPI have
separate timing parameters for master and slave modes. The nomenclature used with the CSPI / ECSPI
modules and the respective routing of these signals is shown in Table 44.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
67
Electrical Characteristics
Table 44. CSPI Nomenclature and Routing
Block Instance
I/O Access
ECSPI-1
GPIO, KPP, DISP0_DAT, CSI0_DAT and EIM_D through IOMUXC
ECSPI-2
DISP0_DAT, CSI0_DAT and EIM through IOMUXC
CSPI
DISP0_DAT, EIM_A/D, SD1 and SD2 through IOMUXC
4.7.2.1
CSPI Master Mode Timing
Figure 32 depicts the timing of CSPI in master mode. Table 45 lists the CSPI master mode timing
characteristics.
RDY
CS10
SSx
CS1
CS5
CS6
CS2
CS3
CS4
SCLK
CS7
CS2
CS3
MOSI
CS9
CS8
MISO
Figure 32. CSPI/ECSPI Master Mode Timing Diagram
Table 45. CSPI Master Mode Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
CS1
SCLK Cycle Time
tclk
60
—
ns
CS2
SCLK High or Low Time
tSW
26
—
ns
CS3
SCLK Rise or Fall1
tRISE/FALL
—
—
ns
CS4
SSx pulse width
tCSLH
26
—
ns
CS5
SSx Lead Time (Slave Select setup
time)
tSCS
26
—
ns
CS6
SSx Lag Time (SS hold time)
tHCS
26
—
ns
CS7
MOSI Propagation Delay
(CLOAD = 20 pF)
tPDmosi
–1
21
ns
CS8
MISO Setup Time
tSmiso
5
—
ns
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
68
Freescale Semiconductor
Electrical Characteristics
Table 45. CSPI Master Mode Timing Parameters (continued)
ID
1
2
Parameter
Symbol
Min
Max
Unit
CS9
MISO Hold Time
tHmiso
5
—
ns
CS10
RDY to SSx Time2
tSDRY
5
—
ns
See specific I/O AC parameters Section 4.5, “I/O AC Parameters”
SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.
4.7.2.2
CSPI Slave Mode Timing
Figure 33 depicts the timing of CSPI in slave mode. Timing characteristics were not available at the time
of publication.
SSx
CS1
CS2
SCLK
CS5
CS6
CS4
CS2
CS9
MISO
CS8
CS7
MOSI
Figure 33. CSPI/ECSPI Slave Mode Timing Diagram
4.7.2.3
ECSPI Master Mode Timing
Figure 32 depicts the timing of ECSPI in master mode. Table 46 lists the ECSPI master mode timing
characteristics.
Table 46. ECSPI Master Mode Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
CS1
SCLK Cycle Time–Read
SCLK Cycle Time–Write
tclk
30
15
—
ns
CS2
SCLK High or Low Time–Read
SCLK High or Low Time–Write
tSW
14
7
—
ns
CS3
SCLK Rise or Fall1
tRISE/FALL
—
—
ns
CS4
SSx pulse width
tCSLH
Half SCLK period
—
ns
CS5
SSx Lead Time (CS setup time)
tSCS
5
—
ns
CS6
SSx Lag Time (CS hold time)
tHCS
5
—
ns
CS7
MOSI Propagation Delay (CLOAD = 20 pF)
tPDmosi
-0.5
2.5
ns
CS8
MISO Setup Time
tSmiso
8.5
—
ns
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
69
Electrical Characteristics
Table 46. ECSPI Master Mode Timing Parameters (continued)
ID
1
Parameter
Symbol
Min
Max
Unit
CS9
MISO Hold Time
tHmiso
0
—
ns
CS10
RDY to SSx Time2
tSDRY
5
—
ns
See specific I/O AC parameters Section 4.5, “I/O AC Parameters”
SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.
2
4.7.2.4
ECSPI Slave Mode Timing
Figure 33 depicts the timing of ECSPI in slave mode. Table 47 lists the ECSPI slave mode timing
characteristics.
Table 47. ECSPI Slave Mode Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
CS1
SCLK Cycle Time–Read
SCLK Cycle Time–Write
tclk
15
40
—
ns
CS2
SCLK High or Low Time–Read
SCLK High or Low Time–Write
tSW
7
20
—
ns
CS4
SSx pulse width
tCSLH
Half SCLK period
—
ns
CS5
SSx Lead Time (CS setup time)
tSCS
5
—
ns
CS6
SSx Lag Time (CS hold time)
tHCS
5
—
ns
CS7
MOSI Setup Time
tSmosi
4
—
ns
CS8
MOSI Hold Time
tHmosi
4
—
ns
CS9
MISO Propagation Delay (CLOAD = 20 pF)
tPDmiso
4
17
ns
4.7.3
Enhanced Serial Audio Interface (ESAI) Timing Parameters
The ESAI consists of independent transmitter and receiver sections, each section with its own clock
generator. Table 48 shows the interface timing values. The number field in the table refers to timing signals
found in Figure 34 and Figure 35.
Table 48. Enhanced Serial Audio Interface (ESAI) Timing
Characteristics1’2,3
No.
Symbol
Expression3
Min
Max
Condition4 Unit
tSSICC
4 × Tc
4 × Tc
30.0
30.0
—
—
i ck
i ck
62
Clock cycle5
63
Clock high period
• For internal clock
—
2 × Tc − 9.0
6
—
—
• For external clock
—
2 × Tc
15
—
—
ns
ns
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
70
Freescale Semiconductor
Electrical Characteristics
Table 48. Enhanced Serial Audio Interface (ESAI) Timing (continued)
Characteristics1’2,3
Symbol
Expression3
Min
Max
Clock low period
• For internal clock
—
2 × Tc − 9.0
6
—
—
• For external clock
—
2 × Tc
15
—
—
65
SCKR rising edge to FSR out (bl) high
—
—
—
—
—
—
17.0
7.0
x ck
i ck a
ns
66
SCKR rising edge to FSR out (bl) low
—
—
—
—
—
—
17.0
7.0
x ck
i ck a
ns
67
SCKR rising edge to FSR out (wr) high6
—
—
—
—
—
—
19.0
9.0
x ck
i ck a
ns
68
SCKR rising edge to FSR out (wr) low6
—
—
—
—
—
—
19.0
9.0
x ck
i ck a
ns
69
SCKR rising edge to FSR out (wl) high
—
—
—
—
—
—
16.0
6.0
x ck
i ck a
ns
70
SCKR rising edge to FSR out (wl) low
—
—
—
—
—
—
17.0
7.0
x ck
i ck a
ns
71
Data in setup time before SCKR (SCK in synchronous
mode) falling edge
—
—
—
—
12.0
19.0
—
—
x ck
i ck
ns
72
Data in hold time after SCKR falling edge
—
—
—
—
3.5
9.0
—
—
x ck
i ck
ns
73
FSR input (bl, wr) high before SCKR falling edge6
—
—
—
—
2.0
12.0
—
—
x ck
i ck a
ns
74
FSR input (wl) high before SCKR falling edge
—
—
—
—
2.0
12.0
—
—
x ck
i ck a
ns
75
FSR input hold time after SCKR falling edge
—
—
—
—
2.5
8.5
—
—
x ck
i ck a
ns
78
SCKT rising edge to FST out (bl) high
—
—
—
—
—
—
18.0
8.0
x ck
i ck
ns
79
SCKT rising edge to FST out (bl) low
—
—
—
—
—
—
20.0
10.0
x ck
i ck
ns
80
SCKT rising edge to FST out (wr) high6
—
—
—
—
—
—
20.0
10.0
x ck
i ck
ns
81
SCKT rising edge to FST out (wr) low6
—
—
—
—
—
—
22.0
12.0
x ck
i ck
ns
82
SCKT rising edge to FST out (wl) high
—
—
—
—
—
—
19.0
9.0
x ck
i ck
ns
83
SCKT rising edge to FST out (wl) low
—
—
—
—
—
—
20.0
10.0
x ck
i ck
ns
84
SCKT rising edge to data out enable from high
impedance
—
—
—
—
—
—
22.0
17.0
x ck
i ck
ns
No.
64
Condition4 Unit
ns
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
71
Electrical Characteristics
Table 48. Enhanced Serial Audio Interface (ESAI) Timing (continued)
No.
Characteristics1’2,3
Symbol
Expression3
Min
Max
Condition4 Unit
86
SCKT rising edge to data out valid
—
—
—
—
—
—
18.0
13.0
x ck
i ck
ns
87
SCKT rising edge to data out high impedance 77
—
—
—
—
—
—
21.0
16.0
x ck
i ck
ns
89
FST input (bl, wr) setup time before SCKT falling edge6
—
—
—
—
2.0
18.0
—
—
x ck
i ck
ns
90
FST input (wl) setup time before SCKT falling edge
—
—
—
—
2.0
18.0
—
—
x ck
i ck
ns
91
FST input hold time after SCKT falling edge
—
—
—
—
4.0
5.0
—
—
x ck
i ck
ns
95
HCKR/HCKT clock cycle
—
2 x TC
15
—
—
ns
96
HCKT input rising edge to SCKT output
—
—
—
18.0
—
ns
97
HCKR input rising edge to SCKR output
—
—
—
18.0
—
ns
1
2
3
4
5
6
7
VCORE_VDD= 1.00 +- 0.10V
Tj = -40C to 125C
CL=50pF
i ck = internal clock
x ck = external clock
i ck a = internal clock, asynchronous mode
(asynchronous implies that SCKT and SCKR are two different clocks)
i ck s = internal clock, synchronous mode
(synchronous implies that SCKT and SCKR are the same clock)
bl = bit length
wl = word length
wr = word length relative
SCKT(SCKT pin) = transmit clock
SCKR(SCKR pin) = receive clock
FST(FST pin) = transmit frame sync
FSR(FSR pin) = receive frame sync
HCKT(HCKT pin) = transmit high frequency clock
HCKR(HCKR pin) = receive high frequency clock
For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync
signal waveform, but it spreads from one serial clock before the first bit clock (like the bit length frame sync signal), until the
second-to-last bit clock of the first word in the frame.
Periodically sampled and not 100% tested.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
72
Freescale Semiconductor
Electrical Characteristics
62
63
64
SCKT
(Input/Output)
78
79
FST (Bit)
Out
82
FST (Word)
Out
83
86
86
84
87
First Bit
Data Out
Last Bit
89
91
FST (Bit) In
90
91
FST (Word) In
Figure 34. ESAI Transmitter Timing
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
73
Electrical Characteristics
62
63
64
SCKR
(Input/Output)
65
66
FSR (Bit)
Out
69
70
FSR (Word)
Out
72
71
Data In
First Bit
Last Bit
75
73
FSR (Bit)
In
74
75
FSR (Word)
In
Figure 35. ESAI Receiver Timing
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
74
Freescale Semiconductor
Electrical Characteristics
4.7.4
Enhanced Secured Digital Host Controller(eSDHCv2/v3) AC timing
This section describes the electrical information of the eSDHCv2/v3, which includes SD/eMMC4.3
(Single Data Rate) timing and eMMC4.4 (Dual Date Rate) timing.
4.7.4.1
SD/eMMC4.3 (Single Data Rate) AC Timing
Figure 36 depicts the timing of SD/eMMC4.3, and Table 49 lists the SD/eMMC4.3 timing characteristics.
SD4
SD2
SD1
SD5
SCK
SD3
CMD
DAT0
DAT1
output from eSDHCv2 to card ......
DAT7
SD6
SD7
SD8
CMD
DAT0
DAT1
input from card to eSDHCv2 ......
DAT7
Figure 36. SD/eMMC4.3 Timing
Table 49. SD/eMMC4.3 Interface Timing Specification
ID
Parameter
Symbols
Min
Max
Unit
Clock Frequency (Low Speed)
fPP1
0
400
kHz
Clock Frequency (SD/SDIO Full Speed/High Speed)
fPP2
0
25/50
MHz
Clock Frequency (MMC Full Speed/High Speed)
fPP3
0
20/52
MHz
Clock Frequency (Identification Mode)
fOD
100
400
kHz
SD2
Clock Low Time
tWL
7
—
ns
SD3
Clock High Time
tWH
7
—
ns
SD4
Clock Rise Time
tTLH
—
3
ns
SD5
Clock Fall Time
tTHL
—
3
ns
5
ns
Card Input Clock
SD1
eSDHC Output/Card Inputs CMD, DAT (Reference to CLK)
SD6
eSDHC Output Delay
tOD
–5
eSDHC Input/Card Outputs CMD, DAT (Reference to CLK)
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
75
Electrical Characteristics
Table 49. SD/eMMC4.3 Interface Timing Specification (continued)
ID
Parameter
Symbols
Min
Max
Unit
SD7
eSDHC Input Setup Time
tISU
2.5
—
ns
SD8
eSDHC Input Hold Time4
tIH
2.5
—
ns
1
In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,
clock frequency can be any value between 0–50 MHz.
3
In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode, clock
frequency can be any value between 0–52 MHz.
4
To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
2
4.7.4.2
eMMC4.4 (Dual Data Rate) eSDHCv3 AC Timing
Figure 37 depicts the timing of eMMC4.4. Table 50 lists the eMMC4.4 timing characteristics. Be aware
that only DATA is sampled on both edges of the clock (not applicable to CMD).
SD1
SCK
DAT0
DAT1
output from eSDHCv3 to card ......
DAT7
SD2
SD2
......
SD3
SD4
DAT0
DAT1
input from card to eSDHCv3 ......
DAT7
......
Figure 37. eMMC4.4 Timing
Table 50. eMMC4.4 Interface Timing Specification
ID
Parameter
Symbols
Min
Max
Unit
0
52
MHz
5
ns
Card Input Clock
SD1
Clock Frequency (MMC Full Speed/High Speed)
fPP
eSDHC Output / Card Inputs CMD, DAT (Reference to CLK)
SD2
eSDHC Output Delay
tOD
–5
eSDHC Input / Card Outputs CMD, DAT (Reference to CLK)
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
76
Freescale Semiconductor
Electrical Characteristics
Table 50. eMMC4.4 Interface Timing Specification (continued)
ID
Parameter
Symbols
Min
Max
Unit
SD3
eSDHC Input Setup Time
tISU
2.5
—
ns
SD4
eSDHC Input Hold Time
tIH
2.5
—
ns
4.7.5
FEC AC Timing Parameters
This section describes the electrical information of the Fast Ethernet Controller (FEC) module. The FEC
is designed to support both 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external transceiver
interface and transceiver function are required to complete the interface to the media. The FEC supports
the 10/100 Mbps MII (18 pins in total) and the 10 Mbps (only 7-wire interface, which uses 7 of the MII
pins), for connection to an external Ethernet transceiver. For the pin list of MII and 7-wire, see the i.MX53
Reference Manual.
This section describes the AC timing specifications of the FEC. The MII signals are compatible with
transceivers operating at a voltage of 3.3 V.
4.7.5.1
MII Receive Signal Timing
The MII receive signal timing involves the FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and
FEC_RX_CLK signals. The receiver functions correctly up to a FEC_RX_CLK maximum frequency of
25 MHz + 1%. There is no minimum frequency requirement but the processor clock frequency must
exceed twice the FEC_RX_CLK frequency. Table 51 lists the MII receive channel signal timing
parameters and Figure 38 shows MII receive signal timings.
.
1
2
Table 51. MII Receive Signal Timing
No.
Characteristics1 2
Min
Max
Unit
M1
FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup
5
—
ns
M2
FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold
5
—
ns
M3
FEC_RX_CLK pulse width high
35%
65%
FEC_RX_CLK period
M4
FEC_RX_CLK pulse width low
35%
65%
FEC_RX_CLK period
FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have same timing in 10 Mbps 7-wire interface mode.
Test conditions: 25pF on each output signal.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
77
Electrical Characteristics
M3
FEC_RX_CLK (input)
M4
FEC_RXD[3:0] (inputs)
FEC_RX_DV
FEC_RX_ER
M1
M2
Figure 38. MII Receive Signal Timing Diagram
4.7.5.2
MII Transmit Signal Timing
The MII transmit signal timing affects the FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and
FEC_TX_CLK signals. The transmitter functions correctly up to a FEC_TX_CLK maximum frequency
of 25 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency
must exceed twice the FEC_TX_CLK frequency.
Table 52 lists MII transmit channel timing parameters. Figure 39 shows MII transmit signal timing
diagram for the values listed in Table 52.
Table 52. MII Transmit Signal Timing
Num
1
2
Characteristic1 2
Min
Max
Unit
M5
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid
5
—
ns
M6
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid
—
20
ns
M7
FEC_TX_CLK pulse width high
35%
65%
FEC_TX_CLK period
M8
FEC_TX_CLK pulse width low
35%
65%
FEC_TX_CLK period
FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10 Mbps 7-wire interface mode.
Test conditions: 25pF on each output signal.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
78
Freescale Semiconductor
Electrical Characteristics
.
M7
FEC_TX_CLK (input)
M5
M8
FEC_TXD[3:0] (outputs)
FEC_TX_EN
FEC_TX_ER
M6
Figure 39. MII Transmit Signal Timing Diagram
4.7.5.3
MII Async Inputs Signal Timing (FEC_CRS and FEC_COL)
Table 53 lists MII asynchronous inputs signal timing information. Figure 40 shows MII asynchronous
input timings listed in Table 53.
Table 53. MII Async Inputs Signal Timing
1
Num
Characteristic 1
Min
Max
Unit
M92
FEC_CRS to FEC_COL minimum pulse width
1.5
—
FEC_TX_CLK period
Test conditions: 25pF on each output signal.
FEC_COL has the same timing in 10 Mbit 7-wire interface mode.
2
.
FEC_CRS, FEC_COL
M9
Figure 40. MII Async Inputs Timing Diagram
4.7.5.4
MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)
Table 54 lists MII serial management channel timings. Figure 41 shows MII serial management channel
timings listed in Table 54. The MDC frequency should be equal to or less than 2.5 MHz to be compliant
with the IEEE 802.3 MII specification. However, the FEC can function correctly with a maximum MDC
frequency of 15 MHz.
Table 54. MII Transmit Signal Timing
Characteristics1
ID
Min Max
Unit
M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay)
0
—
ns
M11 FEC_MDC falling edge to FEC_MDIO output valid (max propagation delay)
—
5
ns
M12 FEC_MDIO (input) to FEC_MDC rising edge setup
18
—
ns
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
79
Electrical Characteristics
Table 54. MII Transmit Signal Timing (continued)
Characteristics1
ID
Min Max
Unit
M13 FEC_MDIO (input) to FEC_MDC rising edge hold
0
M14 FEC_MDC pulse width high
40
%
60% FEC_MDC period
M15 FEC_MDC pulse width low
40
%
60% FEC_MDC period
1
—
ns
Test conditions: 25pF on each output signal.
M14
M15
FEC_MDC (output)
M10
FEC_MDIO (output)
M11
FEC_MDIO (input)
M12
M13
Figure 41. MII Serial Management Channel Timing Diagram
4.7.5.5
RMII Mode Timing
In RMII mode, FEC_TX_CLK is used as the REF_CLK which is a 50 MHz ±50 ppm continuous reference
clock. FEC_RX_DV is used as the CRS_DV in RMII, and other signals under RMII mode include
FEC_TX_EN, FEC_TXD[1:0], FEC_RXD[1:0] and optional FEC_RX_ER.
The RMII mode timings are shown in Table 55 and Figure 42.
Table 55. RMII Signal Timing
No.
Characteristics1
Min
Max
Unit
M16
REF_CLK(FEC_TX_CLK) pulse width high
35%
65%
REF_CLK period
M17
REF_CLK(FEC_TX_CLK) pulse width low
35%
65%
REF_CLK period
M18
REF_CLK to FEC_TXD[1:0], FEC_TX_EN invalid
2
—
ns
M19
REF_CLK to FEC_TXD[1:0], FEC_TX_EN valid
—
16
ns
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
80
Freescale Semiconductor
Electrical Characteristics
Table 55. RMII Signal Timing (continued)
Characteristics1
No.
1
Min
Max
Unit
M20
FEC_RXD[1:0], CRS_DV(FEC_RX_DV), FEC_RX_ER to
REF_CLK setup
4
—
ns
M21
REF_CLK to FEC_RXD[1:0], FEC_RX_DV, FEC_RX_ER
hold
2
—
ns
Test conditions: 25pF on each output signal.
M16
M17
REF_CLK (input)
M18
FEC_TXD[1:0] (output)
FEC_TX_EN
M19
CRS_DV (input)
FEC_RXD[1:0]
FEC_RX_ER
M20
M21
Figure 42. RMII Mode Signal Timing Diagram
4.7.6
Flexible Controller Area Network (FLEXCAN) AC Electrical
Specifications
The electrical characteristics are related to the CAN transceiver external to i.MX53xA such as MC33902
from Freescale.The i.MX53xA has two CAN modules available for systems design. Tx and Rx ports for
both modules are multiplexed with other I/O pins. See the IOMUXC chapter of the i.MX53 Reference
Manual to see which pins expose Tx and Rx pins; these ports are named TXCAN and RXCAN,
respectively.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
81
Electrical Characteristics
4.7.7
I2C Module Timing Parameters
This section describes the timing parameters of the I2C module. Figure 43 depicts the timing of I2C
module, and Table 56 lists the I2C module timing characteristics.
I2CLK
IC11
IC10
I2DAT
IC2
IC10
START
IC7
IC4
IC8
IC11
IC6
IC9
IC3
STOP
START
START
IC5
IC1
Figure 43. I2C Bus Timing
Table 56. I2C Module Timing Parameters
ID
Parameter
Standard Mode
Fast Mode
Supply Voltage =
Supply Voltage =
1.65 V–1.95 V, 2.7 V–3.3 V
2.7 V–3.3 V
Unit
Min
Max
Min
Max
IC1
I2CLK cycle time
10
—
2.5
—
µs
IC2
Hold time (repeated) START condition
4.0
—
0.6
—
µs
IC3
Set-up time for STOP condition
4.0
—
0.6
—
µs
IC4
Data hold time
01
3.452
0
0.92
µs
IC5
HIGH Period of I2CLK Clock
4.0
—
0.6
—
µs
IC6
LOW Period of the I2CLK Clock
4.7
—
1.3
—
µs
IC7
Set-up time for a repeated START condition
4.7
—
0.6
—
µs
—
ns
1
3
IC8
Data set-up time
250
—
100
IC9
Bus free time between a STOP and START condition
4.7
—
1.3
—
µs
4
300
ns
IC10
Rise time of both I2DAT and I2CLK signals
—
1000
20 + 0.1Cb
IC11
Fall time of both I2DAT and I2CLK signals
—
300
20 + 0.1Cb4
300
ns
IC12
Capacitive load for each bus line (Cb)
—
400
—
400
pF
1
A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the
falling edge of I2CLK.
2 The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal.
3 A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7)
of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2CLK signal.
If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line
max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification)
before the I2CLK line is released.
4
Cb = total capacitance of one bus line in pF.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
82
Freescale Semiconductor
Electrical Characteristics
4.7.8
Image Processing Unit (IPU) Module Parameters
The purpose of the IPU is to provide comprehensive support for the flow of data from an image sensor
and/or to a display device. This support covers all aspects of these activities:
• Connectivity to relevant devices—cameras, displays, graphics accelerators, and TV encoders.
• Related image processing and manipulation: sensor image signal processing, display processing,
image conversions, and other related functions.
• Synchronization and control capabilities, such as avoidance of tearing artifacts.
4.7.8.1
IPU Sensor Interface Signal Mapping
The IPU supports a number of sensor input formats. Table 57 defines the mapping of the Sensor Interface
Pins used for various supported interface formats.
Table 57. Camera Input Signal Cross Reference, Format and Bits per Cycle
RGB565
8 bits
2 cycles
RGB5652
8 bits
3 cycles
RGB6663
8 bits
3 cycles
RGB888
8 bits
3 cycles
YCbCr
8 bits
2 cycles
RGB5654
16 bits
2 cycles
YCbCr5
16 bits
1 cycle
YCbCr6
16 bits
1 cycle
YCbCr7
20 bits
1 cycle
CSIx_DAT0
—
—
—
—
—
—
—
0
C[0]
CSIx_DAT1
—
—
—
—
—
—
—
0
C[1]
CSIx_DAT2
—
—
—
—
—
—
—
C[0]
C[2]
CSIx_DAT3
—
—
—
—
—
—
—
C[1]
C[3]
CSIx_DAT4
—
—
—
—
—
B[0]
C[0]
C[2]
C[4]
CSIx_DAT5
—
—
—
—
—
B[1]
C[1]
C[3]
C[5]
CSIx_DAT6
—
—
—
—
—
B[2]
C[2]
C[4]
C[6]
CSIx_DAT7
—
—
—
—
—
B[3]
C[3]
C[5]
C[7]
CSIx_DAT8
—
—
—
—
—
B[4]
C[4]
C[6]
C[8]
CSIx_DAT9
—
—
—
—
—
G[0]
C[5]
C[7]
C[9]
CSIx_DAT10
—
—
—
—
—
G[1]
C[6]
0
Y[0]
CSIx_DAT11
—
—
—
—
—
G[2]
C[7]
0
Y[1]
CSIx_DAT12
B[0], G[3]
R[2],G[4],B[2]
R/G/B[4]
R/G/B[0]
Y/C[0]
G[3]
Y[0]
Y[0]
Y[2]
CSIx_DAT13
B[1], G[4]
R[3],G[5],B[3]
R/G/B[5]
R/G/B[1]
Y/C[1]
G[4]
Y[1]
Y[1]
Y[3]
CSIx_DAT14
B[2], G[5]
R[4],G[0],B[4]
R/G/B[0]
R/G/B[2]
Y/C[2]
G[5]
Y[2]
Y[2]
Y[4]
CSIx_DAT15
B[3], R[0]
R[0],G[1],B[0]
R/G/B[1]
R/G/B[3]
Y/C[3]
R[0]
Y[3]
Y[3]
Y[5]
CSIx_DAT16
B[4], R[1]
R[1],G[2],B[1]
R/G/B[2]
R/G/B[4]
Y/C[4]
R[1]
Y[4]
Y[4]
Y[6]
CSIx_DAT17
G[0], R[2]
R[2],G[3],B[2]
R/G/B[3]
R/G/B[5]
Y/C[5]
R[2]
Y[5]
Y[5]
Y[7]
CSIx_DAT18
G[1], R[3]
R[3],G[4],B[3]
R/G/B[4]
R/G/B[6]
Y/C[6]
R[3]
Y[6]
Y[6]
Y[8]
CSIx_DAT19
G[2], R[4]
R[4],G[5],B[4]
R/G/B[5]
R/G/B[7]
Y/C[7]
R[4]
Y[7]
Y[7]
Y[9]
Signal
Name1
1
CSIx stands for CSI1 or CSI2
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
83
Electrical Characteristics
2
3
4
5
6
7
The MSB bits are duplicated on LSB bits implementing color extension
The two MSB bits are duplicated on LSB bits implementing color extension
RGB 16 bits – supported in two ways: (1) As a “generic data” input – with no on-the-fly processing; (2) With on-the-fly
processing, but only under some restrictions on the control protocol.
YCbCr 16 bits - supported as a “generic-data” input – with no on-the-fly processing.
YCbCr 16 bits - supported as a sub-case of the YCbCr, 20 bits, under the same conditions (BT.1120 protocol).
YCbCr, 20 bits, supported only within the BT.1120 protocol (syncs embedded within the data stream).
4.7.8.2
Sensor Interface Timings
There are three camera timing modes supported by the IPU.
4.7.8.2.1
BT.656 and BT.1120 Video Mode
Smart camera sensors, which include imaging processing, usually support video mode transfer. They use
an embedded timing syntax to replace the SENSB_VSYNC and SENSB_HSYNC signals. The timing
syntax is defined by the BT.656/BT.1120 standards.
This operation mode follows the recommendations of ITU BT.656/ ITU BT.1120 specifications. The only
control signal used is SENSB_PIX_CLK. Start-of-frame and active-line signals are embedded in the data
stream. An active line starts with a SAV code and ends with a EAV code. In some cases, digital blanking
is inserted in between EAV and SAV code. The CSI decodes and filters out the timing-coding from the data
stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use. On BT.656 one
component per cycle is received over the SENSB_DATA bus. On BT.1120 two components per cycle are
received over the SENSB_DATA bus.
4.7.8.2.2
Gated Clock Mode
The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See
Figure 44.
Active Line
Start of Frame
nth frame
n+1th frame
SENSB_VSYNC
SENSB_HSYNC
SENSB_PIX_CLK
SENSB_DATA[19:0]
invalid
invalid
1st byte
1st byte
Figure 44. Gated Clock Mode Timing Diagram
A frame starts with a rising edge on SENSB_VSYNC (all the timings correspond to straight polarity of the
corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. Pixel clock is valid
as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
84
Freescale Semiconductor
Electrical Characteristics
SENSB_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI stops
receiving data from the stream. For next line the SENSB_HSYNC timing repeats. For next frame the
SENSB_VSYNC timing repeats.
4.7.8.2.3
Non-Gated Clock Mode
The timing is the same as the gated-clock mode (described in Section 4.7.8.2.2, “Gated Clock Mode,”)
except for the SENSB_HSYNC signal, which is not used (see Figure 45). All incoming pixel clocks are
valid and cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states
low) until valid data is going to be transmitted over the bus.
Start of Frame
nth frame
n+1th frame
SENSB_VSYNC
SENSB_PIX_CLK
SENSB_DATA[19:0]
invalid
invalid
1st byte
1st byte
Figure 45. Non-Gated Clock Mode Timing Diagram
The timing described in Figure 45 is that of a typical sensor. Some other sensors may have a slightly
different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC;
active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK.
4.7.8.3
Electrical Characteristics
Figure 46 depicts the sensor interface timing. SENSB_MCLK signal described here is not generated by
the IPU. Table 58 lists the sensor interface timing characteristics.
SENSB_PIX_CLK
(Sensor Output)
IP3
IP2
1/IP1
SENSB_DATA,
SENSB_VSYNC,
SENSB_HSYNC
Figure 46. Sensor Interface Timing Diagram
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
85
Electrical Characteristics
Table 58. Sensor Interface Timing Characteristics
ID
Parameter
Symbol
Min
Max
Unit
IP1
Sensor output (pixel) clock frequency
Fpck
0.01
180
IP2
Data and control setup time
Tsu
2
—
ns
IP3
Data and control holdup time
Thd
1
—
ns
4.7.8.4
MHz
IPU Display Interface Signal Mapping
The IPU supports a number of display output video formats. Table 59 defines the mapping of the Display
Interface Pins used during various supported video interface formats.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
86
Freescale Semiconductor
Electrical Characteristics
Table 59. Video Signal Cross-Reference
i.MX53xA
Port Name
(x=0, 1)
LCD
RGB/TV Signal Allocation (Example)
RGB,
Signal
Name
16-bit 18-bit 24 Bit
8-bit
16-bit 20-bit
(General) RGB RGB RGB YCrCb2 YCrCb YCrCb
Comment1
Smart
Signal
Name
DISPx_DAT0
DAT[0]
B[0]
B[0]
B[0]
Y/C[0]
C[0]
C[0]
DAT[0]
DISPx_DAT1
DAT[1]
B[1]
B[1]
B[1]
Y/C[1]
C[1]
C[1]
DAT[1]
DISPx_DAT2
DAT[2]
B[2]
B[2]
B[2]
Y/C[2]
C[2]
C[2]
DAT[2]
The restrictions are as follows:
a) There are maximal three
continuous groups of bits that
could be independently mapped to
the external bus.
DISPx_DAT3
DAT[3]
B[3]
B[3]
B[3]
Y/C[3]
C[3]
C[3]
DAT[3]
Groups should not be overlapped.
DISPx_DAT4
DAT[4]
B[4]
B[4]
B[4]
Y/C[4]
C[4]
C[4]
DAT[4]
DISPx_DAT5
DAT[5]
G[0]
B[5]
B[5]
Y/C[5]
C[5]
C[5]
DAT[5]
b) The bit order is expressed in
each of the bit groups, for example
B[0] = least significant blue pixel
bit
DISPx_DAT6
DAT[6]
G[1]
G[0]
B[6]
Y/C[6]
C[6]
C[6]
DAT[6]
DISPx_DAT7
DAT[7]
G[2]
G[1]
B[7]
Y/C[7]
C[7]
C[7]
DAT[7]
DISPx_DAT8
DAT[8]
G[3]
G[2]
G[0]
—
Y[0]
C[8]
DAT[8]
DISPx_DAT9
DAT[9]
G[4]
G[3]
G[1]
—
Y[1]
C[9]
DAT[9]
DISPx_DAT10
DAT[10]
G[5]
G[4]
G[2]
—
Y[2]
Y[0]
DAT[10]
DISPx_DAT11
DAT[11]
R[0]
G[5]
G[3]
—
Y[3]
Y[1]
DAT[11]
DISPx_DAT12
DAT[12]
R[1]
R[0]
G[4]
—
Y[4]
Y[2]
DAT[12]
DISPx_DAT13
DAT[13]
R[2]
R[1]
G[5]
—
Y[5]
Y[3]
DAT[13]
DISPx_DAT14
DAT[14]
R[3]
R[2]
G[6]
—
Y[6]
Y[4]
DAT[14]
DISPx_DAT15
DAT[15]
R[4]
R[3]
G[7]
—
Y[7]
Y[5]
DAT[15]
DISPx_DAT16
DAT[16]
—
R[4]
R[0]
—
—
Y[6]
—
DISPx_DAT17
DAT[17]
—
R[5]
R[1]
—
—
Y[7]
—
DISPx_DAT18
DAT[18]
—
—
R[2]
—
—
Y[8]
—
DISPx_DAT19
DAT[19]
—
—
R[3]
—
—
Y[9]
—
DISPx_DAT20
DAT[20]
—
—
R[4]
—
—
—
—
DISPx_DAT21
DAT[21]
—
—
R[5]
—
—
—
—
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
87
Electrical Characteristics
Table 59. Video Signal Cross-Reference (continued)
i.MX53xA
Port Name
(x=0, 1)
LCD
RGB/TV Signal Allocation (Example)
RGB,
Signal
16-bit 20-bit
Name
16-bit 18-bit 24 Bit
8-bit
(General) RGB RGB RGB YCrCb2 YCrCb YCrCb
Comment1
Smart
Signal
Name
DISPx_DAT22
DAT[22]
—
—
R[6]
—
—
—
—
—
DISPx_DAT23
DAT[23]
—
—
R[7]
—
—
—
—
—
—
—
DIx_DISP_CLK
PixCLK
DIx_PIN1
—
DIx_PIN2
HSYNC
—
—
DIx_PIN3
VSYNC
—
VSYNC out
DIx_PIN4
—
—
DIx_PIN5
—
—
Additional frame/row synchronous
signals with programmable timing
DIx_PIN6
—
—
DIx_PIN7
—
—
DIx_PIN8
—
—
DIx_D0_CS
—
CS0
—
DIx_D1_CS
—
CS1
Alternate mode of PWM output for
contrast or brightness control
DIx_PIN11
—
WR
—
DIx_PIN12
—
RD
—
DIx_PIN13
—
RS1
Register select signal
DIx_PIN14
—
RS2
Optional RS2
DIx_PIN15
DRDY/DV
DRDY
DIx_PIN16
—
—
DIx_PIN17
Q
—
1
2
VSYNC_IN May be required for anti-tearing
Data validation/blank, data enable
Additional data synchronous
signals with programmable
features/timing
Signal mapping (both data and control/synchronization) is flexible. The table provides examples.
This mode works in compliance with recommendation ITU-R BT.656. The timing reference signals (frame start, frame end, line
start, and line end) are embedded in the 8-bit data bus. Only video data is supported, transmission of non-video related data
during blanking intervals is not supported.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
88
Freescale Semiconductor
Electrical Characteristics
NOTE
Table 59 provides information for both the Disp0 and Disp1 ports. However,
Disp1 port has reduced pinout depending on IOMUXC configuration and
therefore may not support all the above configurations. See the IOMUXC
table for details.
4.7.8.5
IPU Display Interface Timing
The IPU Display Interface supports two kinds of display accesses: synchronous and asynchronous. There
are two groups of external interface pins to provide synchronous and asynchronous controls accordantly.
4.7.8.5.1
Synchronous Controls
The synchronous control changes its value as a function of a system or of an external clock. This control
has a permanent period and a permanent wave form.
There are special physical outputs to provide synchronous controls:
• The ipp_disp_clk is a dedicated base synchronous signal that is used to generate a base display
(component, pixel) clock for a display.
• The ipp_pin_1– ipp_pin_7 are general purpose synchronous pins, that can be used to provide
HSYNC, VSYNC, DRDY or any else independent signal to a display.
The IPU has a system of internal binding counters for internal events (such as HSYNC/VSYCN and so on)
calculation. The internal event (local start point) is synchronized with internal DI_CLK. A suitable control
starts from the local start point with predefined UP and DOWN values to calculate control’s changing
points with half DI_CLK resolution. A full description of the counters system can be found in the IPU
chapter of the i.MX53 Reference Manual.
4.7.8.5.2
Asynchronous Controls
The asynchronous control is a data-oriented signal that changes its value with an output data according to
additional internal flags coming with the data.
There are special physical outputs to provide asynchronous controls, as follows:
• The ipp_d0_cs and ipp_d1_cs pins are dedicated to provide chip select signals to two displays.
• The ipp_pin_11– ipp_pin_17 are general purpose asynchronous pins, that can be used to provide
WR. RD, RS or any other data oriented signal to display.
NOTE
The IPU has independent signal generators for asynchronous signals
toggling. When a DI decides to put a new asynchronous data in the bus, a
new internal start (local start point) is generated. The signals generators
calculate predefined UP and DOWN values to change pins states with half
DI_CLK resolution.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
89
Electrical Characteristics
4.7.8.6
4.7.8.6.1
Synchronous Interfaces to Standard Active Matrix TFT LCD Panels
IPU Display Operating Signals
The IPU uses four control signals and data to operate a standard synchronous interface:
• IPP_DISP_CLK—Clock to display
• HSYNC—Horizontal synchronization
• VSYNC—Vertical synchronization
• DRDY—Active data
All synchronous display controls are generated on the base of an internally generated “local start point”.
The synchronous display controls can be placed on time axis with DI’s offset, up and down parameters.
The display access can be whole number of DI clock (Tdiclk) only. The IPP_DATA can not be moved
relative to the local start point. The data bus of the synchronous interface is output direction only.
4.7.8.6.2
LCD Interface Functional Description
Figure 47 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure
signals are shown with negative polarity. The sequence of events for active matrix interface timing is:
• DI_CLK internal DI clock, used for calculation of other controls.
• IPP_DISP_CLK latches data into the panel on its negative edge (when positive polarity is selected).
In active mode, IPP_DISP_CLK runs continuously.
• HSYNC causes the panel to start a new line. (Usually IPP_PIN_2 is used as HSYNC.)
• VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.
(Usually IPP_PIN_3 is used as VSYNC.)
• DRDY acts like an output enable signal to the CRT display. This output enables the data to be
shifted onto the display. When disabled, the data is invalid and the trace is off.
(DRDY can be used either synchronous or asynchronous generic purpose pin as well.)
VSYNC
HSYNC
LINE 1
LINE 2
LINE 3
LINE 4
LINE n-1
LINE n
HSYNC
DRDY
1
2
3
m–1
m
IPP_DISP_CLK
IPP_DATA
Figure 47. Interface Timing Diagram for TFT (Active Matrix) Panels
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
90
Freescale Semiconductor
Electrical Characteristics
4.7.8.6.3
TFT Panel Sync Pulse Timing Diagrams
Figure 48 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and
the data. All the parameters shown in the figure are programmable. All controls are started by
corresponding internal events—local start points. The timing diagrams correspond to inverse polarity of
the IPP_DISP_CLK signal and active-low polarity of the HSYNC, VSYNC, and DRDY signals.
IP13o
IP7
IP5o
IP8o
IP5
IP8
DI clock
IPP_DISP_CLK
VSYNC
HSYNC
DRDY
IPP_DATA
D0
local start point
local start point
Dn
IP9o
IP9
local start point
D1
IP10
IP6
Figure 48. TFT Panels Timing Diagram—Horizontal Sync Pulse
Figure 49 depicts the vertical timing (timing of one frame). All parameters shown in the figure are
programmable.
Start of frame
IP13
End of frame
VSYNC
HSYNC
DRDY
IP11
IP15
IP14
IP12
Figure 49. TFT Panels Timing Diagram—Vertical Sync Pulse
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
91
Electrical Characteristics
Table 60 shows timing characteristics of signals presented in Figure 48 and Figure 49.
Table 60. Synchronous Display Interface Timing Characteristics (Pixel Level)
ID
Parameter
Symbol
Value
IP5
Display interface clock period
Tdicp
(1)
IP6
Display pixel clock period
Tdpcp
IP7
Screen width time
Tsw
(SCREEN_WIDTH)
× Tdicp
IP8
HSYNC width time
Thsw
(HSYNC_WIDTH)
IP9
Horizontal blank interval 1
Thbi1
BGXP × Tdicp
IP10
Horizontal blank interval 2
Thbi2
IP12
Screen height
IP13
Description
Display interface clock. IPP_DISP_CLK
DISP_CLK_PER_PIXEL Time of translation of one pixel to display,
× Tdicp
DISP_CLK_PER_PIXEL—number of pixel
components in one pixel (1.n). The
DISP_CLK_PER_PIXEL is virtual
parameter to define Display pixel clock
period.
The DISP_CLK_PER_PIXEL is received by
DC/DI one access division to n
components.
Unit
ns
ns
SCREEN_WIDTH—screen width in,
interface clocks. horizontal blanking
included.
The SCREEN_WIDTH should be built by
suitable DI’s counter2.
ns
HSYNC_WIDTH—Hsync width in DI_CLK
with 0.5 DI_CLK resolution. Defined by DI’s
counter.
ns
BGXP—width of a horizontal blanking
before a first active data in a line (in
interface clocks). The BGXP should be built
by suitable DI’s counter.
ns
(SCREEN_WIDTH –
BGXP – FW) × Tdicp
Width a horizontal blanking after a last
active data in a line (in interface clocks)
FW—with of active line in interface clocks.
The FW should be built by suitable DI’s
counter.
ns
Tsh
(SCREEN_HEIGHT)
× Tsw
SCREEN_HEIGHT— screen height in lines
with blanking.
The SCREEN_HEIGHT is a distance
between 2 VSYNCs.
The SCREEN_HEIGHT should be built by
suitable DI’s counter.
ns
VSYNC width
Tvsw
VSYNC_WIDTH
VSYNC_WIDTH—Vsync width in DI_CLK
with 0.5 DI_CLK resolution. Defined by DI’s
counter
ns
IP14
Vertical blank interval 1
Tvbi1
BGYP × Tsw
BGYP—width of first Vertical
blanking interval in line.The BGYP should
be built by suitable DI’s counter.
ns
IP15
Vertical blank interval 2
Tvbi2
Width of second Vertical
blanking interval in line.The FH should be
built by suitable DI’s counter.
ns
(SCREEN_HEIGHT –
BGYP – FH) × Tsw
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
92
Freescale Semiconductor
Electrical Characteristics
Table 60. Synchronous Display Interface Timing Characteristics (Pixel Level) (continued)
ID
Symbol
Value
Todicp
DISP_CLK_OFFSET
× Tdiclk
IP13o Offset of VSYNC
Tovs
IP8o
Offset of HSYNC
IP9o
Offset of DRDY
IP5o
1
Parameter
Offset of IPP_DISP_CLK
Description
Unit
DISP_CLK_OFFSET—offset of
IPP_DISP_CLK edges from local start
point, in DI_CLK×2
(0.5 DI_CLK Resolution)
Defined by DISP_CLK counter
ns
VSYNC_OFFSET
× Tdiclk
VSYNC_OFFSET—offset of Vsync edges
from a local start point, when a Vsync
should be active, in DI_CLK×2
(0.5 DI_CLK Resolution).The
VSYNC_OFFSET should be built by
suitable DI’s counter.
ns
Tohs
HSYNC_OFFSET
× Tdiclk
HSYNC_OFFSET—offset of Hsync edges
from a local start point, when a Hsync
should be active, in DI_CLK×2
(0.5 DI_CLK Resolution).The
HSYNC_OFFSET should be built by
suitable DI’s counter.
ns
Todrdy
DRDY_OFFSET
× Tdiclk
DRDY_OFFSET—offset of DRDY edges
from a suitable local start point, when a
corresponding data has been set on the
bus, in DI_CLK×2
(0.5 DI_CLK Resolution)
The DRDY_OFFSET should be built by
suitable DI’s counter.
ns
Display interface clock period immediate value.
⎧
DISP_CLK_PERIOD
⎪ T diclk × ----------------------------------------------------,
DI_CLK_PERIOD
⎪
Tdicp = ⎨
DISP_CLK_PERIOD
⎪T
⎛
⎞
---------------------------------------------------⎪ diclk ⎝ floor DI_CLK_PERIOD + 0.5 ± 0.5⎠ ,
⎩
for integer DISP_CLK_PERIOD
---------------------------------------------------DI_CLK_PERIOD
for fractional DISP_CLK_PERIOD
---------------------------------------------------DI_CLK_PERIOD
DISP_CLK_PERIOD—number of DI_CLK per one Tdicp. Resolution 1/16 of DI_CLK.
DI_CLK_PERIOD—relation of between programing clock frequency and current system clock frequency
Display interface clock period average value.
DISP_CLK_PERIOD
Tdicp = T diclk × ---------------------------------------------------DI_CLK_PERIOD
2
DI’s counter can define offset, period and UP/DOWN characteristic of output signal according to programed parameters of the
counter. Same of parameters in the table are not defined by DI’s registers directly (by name), but can be generated by
corresponding DI’s counter. The SCREEN_WIDTH is an input value for DI’s HSYNC generation counter. The distance
between HSYNCs is a SCREEN_WIDTH.
The maximal accuracy of UP/DOWN edge of controls is:
Accuracy = ( 0.5 × T diclk ) ± 0.62ns
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
93
Electrical Characteristics
The maximal accuracy of UP/DOWN edge of IPP_DATA is:
Accuracy = T diclk ± 0.62ns
The DISP_CLK_PERIOD, DI_CLK_PERIOD parameters are programmed through the registers.
Figure 50 depicts the synchronous display interface timing for access level. The DISP_CLK_DOWN and
DISP_CLK_UP parameters are set through the Register. Table 61 lists the synchronous display interface
timing characteristics.
IP20o IP20
VSYNC
HSYNC
DRDY
other controls
IPP_DISP_CLK
Tdicu
Tdicd
IPP_DATA
IP16
IP17
IP19
IP18
local start point
Figure 50. Synchronous Display Interface Timing Diagram—Access Level
Table 61. Synchronous Display Interface Timing Characteristics (Access Level)
ID
Parameter
Symbol
Typ1
Min
Max
Unit
IP16
Display interface clock Tckl
low time
Tdicd-Tdicu–1.24
Tdicd2–Tdicu3
Tdicd–Tdicu+1.24
ns
IP17
Display interface clock Tckh
high time
Tdicp–Tdicd+Tdicu–1.24
Tdicp–Tdicd+Tdicu
Tdicp–Tdicd+Tdicu+1.2
ns
IP18
Data setup time
Tdsu
Tdicd–1.24
Tdicu
—
ns
IP19
Data holdup time
Tdhd
Tdicp–Tdicd–1.24
Tdicp–Tdicu
—
ns
IP20o
Control signals offset Tocsu
times (defines for each
pin)
Tocsu–1.24
Tocsu
IP20
Control signals setup
time to display
interface clock
(defines for each pin)
Tdicd–1.24–Tocsu%Tdicp Tdicu
Tcsu
Tocsu+1.24
—
ns
ns
1
The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.
These conditions may be chip specific.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
94
Freescale Semiconductor
Electrical Characteristics
2
Display interface clock down time
2 × DISP_CLK_DOWN
1
Tdicd = --- ⎛⎝ T diclk × ceil ----------------------------------------------------------- ⎞⎠
DI_CLK_PERIOD
2
3
Display interface clock up time where CEIL(X) rounds the elements of X to the nearest integers towards infinity.
2 × DISP_CLK_UP
Tdicu = 1--- ⎛⎝ T diclk × ceil ------------------------------------------------ ⎞⎠
DI_CLK_PERIOD
2
4.7.8.7
Interface to a TV Encoder (TVDAC)
The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The timing of
the interface is described in Figure 51.
•
•
•
•
•
NOTE
The frequency of the clock DISP_CLK is 27 MHz (within 10%)
The HSYNC, VSYNC signals are active low.
The DRDY signal is shown as active high.
The transition to the next row is marked by the negative edge of the
HSYNC signal. It remains low for a single clock cycle.
The transition to the next field/frame is marked by the negative edge of
the VSYNC signal. It remains low for at least one clock cycles.
— At a transition to an odd field (of the next frame), the negative edges
of VSYNC and HSYNC coincide.
At a transition is to an even field (of the same frame), they do not
coincide.
—
•
The active intervals—during which data is transferred—are marked by
the HSYNC signal being high.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
95
Electrical Characteristics
DISP_CLK
HSYNC
VSYNC
DRDY
Cb
IPP_DATA
Y
Cr
Y
Cb
Y
Cr
Pixel Data Timing
HSYNC
523
524
525
1
2
3
4
5
6
10
DRDY
VSYNC
Even Field
HSYNC
261
262
263
Odd Field
264
265
266
267
268
269
273
DRDY
VSYNC
Even Field
Odd Field
Line and Field Timing - NTSC
HSYNC
621
622
623
624
625
1
2
3
4
23
DRDY
VSYNC
Even Field
HSYNC
308
309
Odd Field
310
311
312
313
314
315
316
336
DRDY
VSYNC
Even Field
Odd Field
Line and Field Timing - PAL
Figure 51. TV Encoder Interface Timing Diagram
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
96
Freescale Semiconductor
Electrical Characteristics
4.7.8.7.1
TVEv2 TV Encoder Performance Specifications
The TV encoder output specifications are shown in Table 62. All the parameters in the table are defined
under the following conditions:
• Rset = 1.05 kΩ ±1%, resistor on TVDAC_VREF pin to GND
• Rload = 37.5 Ω ±1%, output load to the GND
Table 62. TV Encoder Video Performance Specifications
Parameter
Conditions
Min
Typ
Max
Unit
—
—
10
—
Bits
—
—
1
2
LSBs
—
—
0.6
1
LSBs
—
—
2
—
%
1.24
1.306
1.37
V
DAC STATIC PERFORMANCE
Resolution1
Integral Nonlinearity (INL)2
Differential Nonlinearity (DNL)
2
Channel-to-channel gain matching2
Full scale output
voltage2
Rset = 1.05 kΩ ±1%
Rload = 37.5 Ω ±1%
DAC DYNAMIC PERFORMANCE
Spurious Free Dynamic Range (SFDR)
Fout = 3.38 MHz
Fsamp = 216 MHz
—
59
—
dBc
Spurious Free Dynamic Range (SFDR)
Fout = 9.28 MHz
Fsamp = 297 MHz
—
54
—
dBc
VIDEO PERFORMANCE IN SD MODE2
Short Term Jitter (Line to Line)
—
—
2.5
—
±ns
Long Term Jitter (Field to Field)
—
—
3.5
—
±ns
0-4.0 MHz
–0.1
—
0.1
dB
5.75 MHz
–0.7
—
0
dB
Frequency Response
Luminance Nonlinearity
—
—
0.5
—
±%
Differential Gain
—
—
0.35
—
%
Differential Phase
—
—
0.6
—
Degrees
—
75
—
dB
Signal-to-Noise Ratio (SNR)
Flat field full bandwidth
Hue Accuracy
—
—
0.8
—
±Degrees
Color Saturation Accuracy
—
—
1.5
—
±%
Chroma AM Noise
—
—
–70
—
dB
Chroma PM Noise
—
—
–47
—
dB
Chroma Nonlinear Phase
—
—
0.5
—
±Degrees
Chroma Nonlinear Gain
—
—
2.5
—
±%
Chroma/Luma Intermodulation
—
—
0.1
—
±%
Chroma/Luma Gain Inequality
—
—
1.0
—
±%
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
97
Electrical Characteristics
Table 62. TV Encoder Video Performance Specifications (continued)
Parameter
Chroma/Luma Delay Inequality
Conditions
Min
Typ
Max
Unit
—
—
1.0
—
±ns
VIDEO PERFORMANCE IN HD MODE2
Luma Frequency Response
0-30 MHz
–0.2
—
0.2
dB
Chroma Frequency Response
0-15 MHz,
YCbCr 422 mode
–0.2
—
0.2
dB
Luma Nonlinearity
—
—
3.2
—
%
Chroma Nonlinearity
—
—
3.4
—
%
Luma Signal-to-Noise Ratio
0-30 MHz
—
62
—
dB
Chroma Signal-to-Noise Ratio
0-15 MHz
—
72
—
dB
1
2
Guaranteed by design.
Guaranteed by characterization.
4.7.8.8
Asynchronous Interfaces
The following sections describes the types of asynchronous interfaces.
4.7.8.8.1
Standard Parallel Interfaces
The IPU has four signal generator machines for asynchronous signal. Each machine generates IPU’s
internal control levels (0 or 1) by UP and DOWN that are defined in registers. Each asynchronous pin has
a dynamic connection with one of the signal generators. This connection is redefined again with a new
display access (pixel/component). The IPU can generate control signals according to system 80/68
requirements. The burst length is received as a result from predefined behavior of the internal signal
generator machines.
The access to a display is realized by the following:
• CS (IPP_CS) chip select
• WR (IPP_PIN_11) write strobe
• RD (IPP_PIN_12) read strobe
• RS (IPP_PIN_13) Register select (A0)
Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 52,
Figure 53, Figure 54, and Figure 55. The timing images correspond to active-low IPP_CS, WR and RD
signals.
Each asynchronous access is defined by an access size parameter. This parameter can be different between
different kinds of accesses. This parameter defines a length of windows, when suitable controls of the
current access are valid. A pause between two different display accesses can be guaranteed by programing
suitable access sizes. There are no minimal/maximal hold/setup times hard defined by DI. Each control
signal can be switched at any time during access size.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
98
Freescale Semiconductor
Electrical Characteristics
IPP_CS
RS
WR
RD
IPP_DATA
Burst access mode with sampling by CS signal
IPP_CS
RS
WR
RD
IPP_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 52. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
99
Electrical Characteristics
IPP_CS
RS
WR
RD
IPP_DATA
Burst access mode with sampling by WR/RD signals
IPP_CS
RS
WR
RD
IPP_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 53. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
100
Freescale Semiconductor
Electrical Characteristics
IPP_CS
RS
WR
(READ/WRITE)
RD
(ENABLE)
IPP_DATA
Burst access mode with sampling by CS signal
IPP_CS
RS
WR
(READ/WRITE)
RD
(ENABLE)
IPP_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 54. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
101
Electrical Characteristics
IPP_CS
RS
WR
(READ/WRITE)
RD
(ENABLE)
IPP_DATA
Burst access mode with sampling by ENABLE signal
IPP_CS
RS
WR
(READ/WRITE)
RD
(ENABLE)
IPP_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 55. Asynchronous Parallel System 68k Interface (Type 2) Timing Diagram
Display operation can be performed with IPP_WAIT signal. The DI reacts to the incoming IPP_WAIT
signal with 2 DI_CLK delay. The DI finishes a current access and a next access is postponed until
IPP_WAIT release. Figure 56 shows timing of the parallel interface with IPP_WAIT control.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
102
Freescale Semiconductor
Electrical Characteristics
DI clock
IPP_CS
IPP_DATA
WR
RD
IPP_WAIT
IPP_DATA_IN
IP39
waiting
waiting
Figure 56. Parallel Interface Timing Diagram—Read Wait States
4.7.8.8.2
Asynchronous Parallel Interface Timing Parameters
Figure 57 depicts timing of asynchronous parallel interfaces based on the system 80 and system 68k
interfaces. Table 64 shows timing characteristics at display access level. All timing diagrams are based
on active low control signals (signals polarity is controlled through the DI_DISP_SIG_POL register).
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
103
Electrical Characteristics
IP29
IP32
IP35
IP36
IP33
IP30
IP47
IP34
IP31
DI clock
IPP_CS
RS
WR
RD
IPP_DATA
A0
D0
D1
D2
PP_DATA_IN
IP27
IP37
IP38
local start point
local start point
local start point
IP28d
local start point
local start point
IP28a
D3
Figure 57. Asynchronous Parallel Interface Timing Diagram
Table 63. Asynchronous Display Interface Timing Parameters (Pixel Level)
ID
Parameter
Symbol
Value
Description
Unit
IP28a
Address Write system cycle time Tcycwa
ACCESS_SIZE_#
predefined value in DI REGISTER
ns
IP28d
Data Write system cycle time
Tcycwd
ACCESS_SIZE_#
predefined value in DI REGISTER
ns
IP29
RS start
Tdcsrr
UP#
RS strobe switch, predefined value
in DI REGISTER
ns
IP30
CS start
Tdcsc
UP#
CS strobe switch, predefined value
in DI REGISTER
ns
IP31
CS hold
Tdchc
DOWN#
CS strobe release, predefined
value in DI REGISTER
—
IP32
RS hold
Tdchrr
DOWN#
RS strobe release, predefined
value in DI REGISTER
—
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
104
Freescale Semiconductor
Electrical Characteristics
Table 63. Asynchronous Display Interface Timing Parameters (Pixel Level) (continued)
ID
Parameter
Symbol
Value
Description
Unit
IP35
Write start
Tdcsw
UP#
write strobe switch, predefined
value in DI REGISTER
ns
IP36
Controls hold time for write
Tdchw
DOWN#
write strobe release, predefined
value in DI REGISTER
ns
Table 64. Asynchronous Parallel Interface Timing Parameters (Access Level)
ID
Parameter
Symbol
Typ1
Min
Max
Unit
IP28 Write system cycle time
Tcycw
Tdicpw – 1.24
Tdicpw2
Tdicpw+1.24
ns
IP29 RS start
Tdcsrr
Tdicurs – 1.24
Tdicurs
Tdicurs+1.24
ns
IP30 CS start
Tdcsc
Tdicucs – 1.24
Tdicur
Tdicucs+1.24
ns
IP31 CS hold
Tdchc
Tdicdcs – Tdicucs – 1.2 Tdicdcs3–Tdicucs4
4
Tdicdcs – Tdicucs+1.24
ns
IP32 RS hold
Tdchrr
Tdicdrs – Tdicurs – 1.24 Tdicdrs5–Tdicurs6
Tdicdrs – Tdicurs+1.24
ns
IP35 Controls setup time for
write
Tdcsw
Tdicuw – 1.24
Tdicuw+1.24
ns
IP36 Controls hold time for
write
Tdchw
Tdicdw – Tdicuw – 1.24 Tdicpw7–Tdicuw8
Tdicdw–Tdicuw+1.24
ns
IP38 Slave device data hold
time8
Troh
Tdrp – Tlbd – Tdicdr+1.
24
Tdicpr – Tdicdr – 1.24
ns
Tdicuw
—
1The
exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.
These conditions may be chip specific.
2Display period value for write
DI_ACCESS_SIZE_#
Tdicpw = T DI_CLK × ceil ----------------------------------------------------DI_CLK_PERIOD
ACCESS_SIZE is predefined in REGISTER.
3Display control down for CS
2 × DISP_DOWN_#
Tdicdcs = 1--- ⎛ T DI_CLK × ceil -------------------------------------------------- ⎞
DI_CLK_PERIOD ⎠
2⎝
DISP_DOWN is predefined in REGISTER.
4Display control up for CS
2 × DISP_UP_#
1
Tdicucs = --- ⎛⎝ T DI_CLK × ceil ---------------------------------------------- ⎞⎠
DI_CLK_PERIOD
2
DISP_UP is predefined in REGISTER.
5Display control down for RS
2 × DISP_DOWN_#
Tdicdrs = 1--- ⎛⎝ T DI_CLK × ceil -------------------------------------------------- ⎞⎠
DI_CLK_PERIOD
2
DISP_DOWN is predefined in REGISTER.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
105
Electrical Characteristics
6
Display control up for RS
2 × DISP_UP_#
1
Tdicurs = --- ⎛⎝ T DI_CLK × ceil ---------------------------------------------- ⎞⎠
DI_CLK_PERIOD
2
DISP_UP is predefined in REGISTER.
7
Display control down for read
2 × DISP_DOWN_#
Tdicdrw = 1--- ⎛⎝ T DI_CLK × ceil -------------------------------------------------- ⎞⎠
DI_CLK_PERIOD
2
DISP_DOWN is predefined in REGISTER.
8
Display control up for write
2 × DISP_UP_#
Tdicuw = 1--- ⎛ T DI_CLK × ceil ---------------------------------------------- ⎞
DI_CLK_PERIOD ⎠
2⎝
DISP_UP is predefined in REGISTER.
4.7.9
LVDS Display Bridge (LDB) Module Parameters
The LVDS interface complies with TIA/EIA 644-A standard. For more details, see TIA/EIA STANDARD
644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits”.
4.7.10
MediaLB (MLB) Controller AC Timing Electrical Specifications
This section describes the timing electrical information of the MediaLB Controller module.
Figure 58 and Figure 59 show the timing of MediaLB Controller, and Table 65 and Table 66 lists the
MediaLB controller timing characteristics.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
106
Freescale Semiconductor
Electrical Characteristics
Figure 58. MediaLB Timing
Figure 59. MediaLB Pulse Width Variation Timing
Ground = 0.0 V; Load Capacitance = 60 pF; MediaLB speed = 256/512 Fs; Fs = 48 kHz; all timing
parameters specified from the valid voltage threshold as listed below; unless otherwise noted.
Table 65. MLB 256/512 Fs Timing Parameters
Parameter
Symbol
Min
MLBCLK operating frequency1
fmck
11.264
Typ
Max
Units
MHz
12.288
24.576
24.6272
25.600
Comment
Min: 256*fs at 44.0 kHz
Typ: 256*fs at 48.0 kHz
Typ: 512*fs at 48.0 kHz
Max: 512*fs at 48.1 kHz
Max: 512*fs PLL unlocked
MLBCLK rise time
tmckr
—
—
3
ns
VIL TO VIH
MLB fall time
tmckf
—
—
3
ns
VIH TO VIL
MLBCLK cycle time
tmckc
—
—
81
40
—
—
ns
256*Fs
512*Fs
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
107
Electrical Characteristics
Table 65. MLB 256/512 Fs Timing Parameters (continued)
Parameter
MLBCLK low time
MLBCLK high time
Symbol
Min
Typ
Max
Units
Comment
tmckl
31.5
30
37
35.5
—
—
ns
256*Fs
256*Fs PLL unlocked
14.5
14
17
16.5
—
—
ns
512*Fs
512*Fs PLL unlocked
31.5
30
38
36.5
—
—
ns
256*Fs
256*Fs PLL unlocked
14.5
14
17
16.5
—
—
ns
512*Fs
512*Fs PLL unlocked
tmckh
MLBCLK pulse width variation
tmpwv
—
—
2
ns pp
Note2
MLBSIG/MLBDAT input valid to
MLBCLK falling
tdsmcf
1
—
—
ns
—
MLBSIG/MLBDAT input hold
from MLBCLK low
tdhmcf
0
—
—
ns
—
MLBSIG/MLBDAT output high
impedance from MLBCLK low
tmcfdz
0
—
tmckl
ns
—
Bus Hold Time
tmdzh
4
—
—
ns
Note3
1
The MLB controller can shut off MLBCLK to place MediaLB in a low-power state.
Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other
edge, measured in ns peak-to-peak (pp)
3 The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this
time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
2
Ground = 0.0 V; load capacitance = 40 pF; MediaLB speed = 1024 Fs; Fs = 48 kHz; all timing parameters
specified from the valid voltage threshold as listed in Table 66; unless otherwise noted.
Table 66. MLB Device 1024 Fs Timing Parameters
Parameter
Symbol
Min
MLBCLK Operating
Frequency1
fmck
45.056
Typ
Max
Units
Comment
MHz
Min: 1024*fs at 44.0 kHz
Typ: 1024*fs at 48.0 kHz
Max: 1024fs*fs at 48.1 kHz
Max: 1024*fs PLL unlocked
49.152
49.2544
51.200
MLBCLK rise time
tmckr
—
—
1
ns
VIL TO VIH
MLB fall time
tmckf
—
—
1
ns
VIH TO VIL
MLBCLK cycle time
tmckc
—
20.3
—
ns
—
MLBCLK low time
tmckl
6.5
6.1
7.7
7.3
—
ns
9.7
9.3
10.6
10.2
—
—
ns
—
—
0.7
ns pp
MLBCLK high time
MLBCLK pulse width variation
tmckh
tmpwv
PLL unlocked
PLL unlocked
Note2
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
108
Freescale Semiconductor
Electrical Characteristics
Table 66. MLB Device 1024 Fs Timing Parameters (continued)
Parameter
Symbol
Min
Typ
Max
Units
Comment
MLBSIG/MLBDAT input valid
to MLBCLK falling
tdsmcf
1
—
—
ns
—
MLBSIG/MLBDAT input hold
from MLBCLK low
tdhmcf
0
—
—
ns
—
MLBSIG/MLBDAT output high
impedance from MLBCLK low
tmcfdz
0
—
tmckl
ns
—
Bus Hold Time
tmdzh
2
—
—
ns
Note3
1
The MLB Controller can shut off MLBCLK to place MediaLB in a low-power state.
Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other
edge, measured in ns peak-to-peak (pp).
3 The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this
time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
2
4.7.11
One-Wire (OWIRE) Timing Parameters
Figure 60 depicts the RPP timing, and Table 67 lists the RPP timing parameters.
One-WIRE Tx
“Reset Pulse”
One Wire Device Tx
“Presence Pulse”
OW2
One-Wire bus
(BATT_LINE)
OW3
OW1
OW4
tR
Figure 60. Reset and Presence Pulses (RPP) Timing Diagram
Table 67. RPP Sequence Delay Comparisons Timing Parameters
ID
Parameters
Symbol
Min
Typ
Max
Unit
OW1
Reset Time Low
tRSTL
480
511
—1
µs
OW2
Presence Detect High
tPDH
15
—
60
µs
OW3
Presence Detect Low
tPDL
60
—
240
µs
OW4
Reset Time High
(includes recovery time)
tRSTH
480
512
—
µs
1
In order not to mask signaling by other devices on the 1-Wire bus, tRSTL + tR should always be less than 960 µs.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
109
Electrical Characteristics
Figure 61 depicts Write 0 Sequence timing, and Table 68 lists the timing parameters.
OW6
tREC
One-Wire bus
(BATT_LINE)
OW5
Figure 61. Write 0 Sequence Timing Diagram
Table 68. WR0 Sequence Timing Parameters
ID
Parameter
Symbol
Min
Typ
Max
Unit
OW5
Write 0 Low Time
tLOW0
60
100
120
µs
OW6
Transmission Time Slot
tSLOT
OW5
117
120
µs
Recovery time
tREC
1
—
—
µs
Figure 62 depicts Write 1 Sequence timing, Figure 63 depicts the Read Sequence timing, and Table 69
lists the timing parameters.
OW8
One-Wire bus
(BATT_LINE)
OW7
Figure 62. Write 1 Sequence Timing Diagram
OW8
One-Wire bus
(BATT_LINE)
tSU
OW11
OW9
OW10
Figure 63. Read Sequence Timing Diagram
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
110
Freescale Semiconductor
Electrical Characteristics
Table 69. WR1 /RD Timing Parameters
ID
Parameter
Symbol
Min
Typ
Max
Unit
OW7
Write 1 Low Time
tLOW1
1
5
15
µs
OW8
Transmission Time Slot
tSLOT
60
117
120
µs
tSU
—
—
1
µs
Read Data Setup
OW9
Read Low Time
tLOWR
1
5
15
µs
OW10
Read Data Valid
tRDV
—
15
—
µs
OW11
Release Time
tRELEASE
0
—
45
µs
4.7.12
Pulse Width Modulator (PWM) Timing Parameters
This section describes the electrical information of the PWM. The PWM can be programmed to select one
of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before
being input to the counter. The output is available at the pulse-width modulator output (PWMO) external
pin.
Figure 64 depicts the timing of the PWM, and Table 70 lists the PWM timing parameters.
1
2a
3b
System Clock
2b
3a
4b
4a
PWM Output
Figure 64. PWM Timing
Table 70. PWM Output Timing Parameter
Ref. No.
1
Parameter
Min
Max
Unit
0
ipg_clk
MHz
1
System CLK frequency1
2a
Clock high time
12.29
—
ns
2b
Clock low time
9.91
—
ns
3a
Clock fall time
—
0.5
ns
3b
Clock rise time
—
0.5
ns
4a
Output delay time
—
9.37
ns
4b
Output setup time
8.71
—
ns
CL of PWMO = 30 pF
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
111
Electrical Characteristics
4.7.13
PATA Timing Parameters
This section describes the timing parameters of the Parallel ATA module which are compliant with
ATA/ATAPI-6 specification.
Parallel ATA module can work on PIO/Multi-Word DMA/Ultra DMA transfer modes. Each transfer mode
has different data transfer rate, Ultra DMA mode 4 data transfer rate is up to 100MB/s. Parallel ATA
module interface consist of a total of 29 pins. Some pins act on different function in different transfer
mode. There are different requirements of timing relationships among the function pins conform with
ATA/ATAPI-6 specification and these requirements are configurable by the ATA module registers.
Table 71 and Figure 65 define the AC characteristics of all the PATA interface signals in all data transfer
modes.
ATA Interface Signals
SI2
SI1
Figure 65. PATA Interface Signals Timing Diagram
Table 71. AC Characteristics of All Interface Signals
ID
1
Parameter
Symbol
Min
Max
Unit
SI1
Rising edge slew rate for any signal on ATA interface1
Srise
—
1.25
V/ns
SI2
Falling edge slew rate for any signal on ATA interface1
Sfall
—
1.25
V/ns
SI3
Host interface signal capacitance at the host connector
Chost
—
20
pF
SRISE and SFALL shall meet this requirement when measured at the sender’s connector from 10–90% of full signal
amplitude with all capacitive loads from 15–40 pF where all signals have the same capacitive load value.
The user must use level shifters for 5.0 V compatibility on the ATA interface. The i.MX53xA PATA
interface is 3.3 V compatible.
The use of bus buffers introduces delay on the bus and skew between signal lines. These factors make it
difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. If fast UDMA mode
operation is needed, this may not be compatible with bus buffers.
Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus.
According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns with
a 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals.
When bus buffers are used, the ata_data bus buffer is special. This is a bidirectional bus buffer, so a
direction control signal is needed. This direction control signal is ata_buffer_en. When its high, the bus
should drive from host to device. When its low, the bus should drive from device to host. Steering of the
signal is such that contention on the host and device tri-state busses is always avoided.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
112
Freescale Semiconductor
Electrical Characteristics
In the timing equations, some timing parameters are used. These parameters depend on the
implementation of the i.MX53xA PATA interface on silicon, the bus buffer used, the cable delay and
cable skew. Table 72 shows ATA timing parameters.
Table 72. PATA Timing Parameters
Name
T
ti_ds
ti_dh
Bus clock period (AHB_CLK_ROOT)
Peripheral clock frequency
(7.5 ns for 133 MHz clock)
Set-up time ata_data to ata_iordy edge (UDMA-in only)
UDMA0
UDMA1
UDMA2, UDMA3
UDMA4
UDMA5
15 ns
10 ns
7 ns
5 ns
4 ns
Hold time ata_iordy edge to ata_data (UDMA-in only)
UDMA0, UDMA1, UDMA2, UDMA3, UDMA4
UDMA5
5.0 ns
4.6 ns
tco
Propagation delay bus clock L-to-H to
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,
ata_data, ata_buffer_en
12.0 ns
tsu
Set-up time ata_data to bus clock L-to-H
8.5 ns
tsui
Set-up time ata_iordy to bus clock H-to-L
8.5 ns
thi
Hold time ata_iordy to bus clock H to L
2.5 ns
tskew1
Max difference in propagation delay bus clock L-to-H to any of following signals
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,
ata_data (write), ata_buffer_en
7 ns
tskew2
Max difference in buffer propagation delay for any of following signals:
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,
ata_data (write), ata_buffer_en
Transceiver
tskew3
Max difference in buffer propagation delay for any of following signals ata_iordy,
ata_data (read)
Transceiver
Max buffer propagation delay
Transceiver
tbuf
1
Value/
Contributing Factor1
Description
tcable1
Cable propagation delay for ata_data
Cable
tcable2
Cable propagation delay for control signals ata_dior, ata_diow, ata_iordy,
ata_dmack
Cable
tskew4
Max difference in cable propagation delay between ata_iordy and ata_data (read)
Cable
tskew5
Max difference in cable propagation delay between (ata_dior, ata_diow,
ata_dmack) and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write)
Cable
tskew6
Max difference in cable propagation delay without accounting for ground bounce
Cable
Values provided where applicable.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
113
Electrical Characteristics
4.7.13.1
PIO Mode Read Timing
Figure 66 shows timing for PIO read. Table 73 lists the timing parameters for PIO read.
Figure 66. PIO Read Timing Diagram
Table 73. PIO Read Timing Parameters
ATA
Parameter
Parameter from Figure 66
Controlling
Variable
Value
t1
t1
t1(min) = time_1 * T – (tskew1 + tskew2 + tskew5)
time_1
t2 (read)
t2r
t2(min) = time_2r * T – (tskew1 + tskew2 + tskew5)
time_2r
t9
t9
t9(min) = time_9 * T – (tskew1 + tskew2 + tskew6)
time_9
t5
t5
t5(min) = tco + tsu + tbuf + tbuf+ tcable1 + tcable2
time_2 (affects tsu and
tco)
t6
t6
0
tA
tA
tA(min) = (1.5 + time_ax) * T – (tco + tsui + tcable2 + tcable2 + 2*tbuf)
trd
trd1
t0
—
—
time_ax
time_pio_rdx
trd1(max) = (–trd)+ (tskew3 + tskew4)
trd1(min) = (time_pio_rdx – 0.5)*T – (tsu + thi)
(time_pio_rdx – 0.5) * T > tsu + thi + tskew3 + tskew4
t0(min) = (time_1 + time_2r+ time_9) * T
time_1, time_2r, time_9
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
114
Freescale Semiconductor
Electrical Characteristics
Figure 67 shows timing for PIO write. Table 74 lists the timing parameters for PIO write.
Figure 67. Multi-word DMA (MDMA) Timing
Table 74. PIO Write Timing Parameters
ATA
Parameter
Paramete
from Figure 67
r
Value
t1(min) = time_1 * T – (tskew1 + tskew2 + tskew5)
Controlling
Variable
t1
t1
t2 (write)
t2w
t9
t9
t9(min) = time_9 * T – (tskew1 + tskew2 + tskew6)
t3
—
t3(min) = (time_2w – time_on)* T – (tskew1 + tskew2 +tskew5)
t4
t4
t4(min) = time_4 * T – tskew1
time_4
tA
tA
tA = (1.5 + time_ax) * T – (tco + tsui + tcable2 + tcable2 + 2*tbuf)
time_ax
t0
—
t0(min) = (time_1 + time_2 + time_9) * T
—
—
Avoid bus contention when switching buffer on by making ton long enough
—
—
—
Avoid bus contention when switching buffer off by making toff long enough
—
t2(min) = time_2w * T – (tskew1 + tskew2 + tskew5)
time_1
time_2w
time_9
If not met, increase
time_2w
time_1, time_2r,
time_9
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
115
Electrical Characteristics
Figure 68 shows timing for MDMA read, Figure 69 shows timing for MDMA write, and Table 75 lists
the timing parameters for MDMA read and write.
Figure 68. MDMA Read Timing Diagram
Figure 69. MDMA Write Timing Diagram
Table 75. MDMA Read and Write Timing Parameters
ATA
Parameter
Parameter from
Figure 68 (Read),
Figure 69 (Write)
tm, ti
tm
tm(min) = ti(min) = time_m * T – (tskew1 + tskew2 + tskew5)
time_m
td
td, td1
td1(min) = td(min) = time_d * T – (tskew1 + tskew2 + tskew6)
time_d
tk
tk1
tk(min) = time_k * T – (tskew1 + tskew2 + tskew6)
time_k
t0
—
t0(min) = (time_d + time_k) * T
tg(read)
tgr
tgr(min-read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2
tgr(min-drive) = td – te(drive)
tf(read)
tfr
tfr(min) = 5 ns
tg(write)
—
tg(min-write) = time_d * T – (tskew1 + tskew2 + tskew5)
time_d
tf(write)
—
tf(min-write) = time_k * T – (tskew1 + tskew2 + tskew6)
time_k
tL
—
tL (max) = (time_d + time_k – 2)×T – (tsu + tco + 2×tbuf + 2×tcable2)
Controlling
Variable
Value
time_d, time_k
time_d
—
time_d,
time_k2
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
116
Freescale Semiconductor
Electrical Characteristics
Table 75. MDMA Read and Write Timing Parameters (continued)
ATA
Parameter
Parameter from
Figure 68 (Read),
Figure 69 (Write)
tn, tj
tkjn
tn= tj= tkjn = time_jn * T – (tskew1 + tskew2 + tskew6)
—
ton
toff
ton = time_on × T – tskew1
toff = time_off × T – tskew1
1
2
Value
Controlling
Variable
time_jn
—
tk1 in the MDMA figures (Figure 68 and Figure 69) equals (tk – 2*T).
tk1 in the MDMA figures equals (tk – 2*T).
4.7.13.2
Ultra DMA (UDMA) Input Timing
Figure 70 shows timing when the UDMA in transfer starts, Figure 71 shows timing when the UDMA in
host terminates transfer, Figure 72 shows timing when the UDMA in device terminates transfer, and
Table 76 lists the timing parameters for UDMA in burst.
Figure 70. UDMA in Transfer Starts Timing Diagram
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
117
Electrical Characteristics
Figure 71. UDMA in Host Terminates Transfer Timing Diagram
Figure 72. UDMA in Device Terminates Transfer Timing Diagram
Table 76. UDMA in Burst Timing Parameters
ATA
Parameter
Parameter
from
Figure 70,
Figure 71,
Figure 72
tack
tack
tack (min) = (time_ack × T) – (tskew1 + tskew2)
time_ack
tenv
tenv
tenv (min) = (time_env × T) – (tskew1 + tskew2)
tenv (max) = (time_env × T) + (tskew1 + tskew2)
time_env
tds
tds1
tds – (tskew3) – ti_ds > 0
tdh
tdh1
tdh – (tskew3) – ti_dh > 0
Description
Controlling Variable
tskew3, ti_ds, ti_dh
should be low enough
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
118
Freescale Semiconductor
Electrical Characteristics
Table 76. UDMA in Burst Timing Parameters (continued)
ATA
Parameter
Parameter
from
Figure 70,
Figure 71,
Figure 72
tcyc
tc1
(tcyc – tskew) > T
trp
trp
trp (min) = time_rp × T – (tskew1 + tskew2 + tskew6)
time_rp
—
tx11
(time_rp × T) – (tco + tsu + 3T + 2 ×tbuf + 2×tcable2) > trfs (drive)
time_rp
tmli
tmli1
tmli1 (min) = (time_mlix + 0.4) × T
time_mlix
tzah
tzah
tzah (min) = (time_zah + 0.4) × T
time_zah
tdzfs
tdzfs
tdzfs = (time_dzfs × T) – (tskew1 + tskew2)
time_dzfs
tcvh
tcvh
tcvh = (time_cvh ×T) – (tskew1 + tskew2)
time_cvh
—
ton
toff2
ton = time_on × T – tskew1
toff = time_off × T – tskew1
Description
Controlling Variable
T big enough
—
1
There is a special timing requirement in the ATA host that requires the internal DIOW to go only high 3 clocks after the last
active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.
2 Make ton and toff big enough to avoid bus contention.
4.7.13.3
UDMA Output Timing
Figure 73 shows timing when the UDMA out transfer starts, Figure 74 shows timing when the UDMA out
host terminates transfer, Figure 75 shows timing when the UDMA out device terminates transfer, and
Table 77 lists the timing parameters for UDMA out burst.
Figure 73. UDMA Out Transfer Starts Timing Diagram
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
119
Electrical Characteristics
Figure 74. UDMA Out Host Terminates Transfer Timing Diagram
Figure 75. UDMA Out Device Terminates Transfer Timing Diagram
Table 77. UDMA Out Burst Timing Parameters
ATA
Parameter
Parameter
from
Figure 73,
Figure 74,
Figure 75
tack
tack
tack (min) = (time_ack × T) – (tskew1 + tskew2)
time_ack
tenv
tenv
tenv (min) = (time_env × T) – (tskew1 + tskew2)
tenv (max) = (time_env × T) + (tskew1 + tskew2)
time_env
tdvs
tdvs
tdvs = (time_dvs × T) – (tskew1 + tskew2)
time_dvs
tdvh
tdvh
tdvs = (time_dvh × T) – (tskew1 + tskew2)
time_dvh
tcyc
tcyc
tcyc = time_cyc × T – (tskew1 + tskew2)
time_cyc
t2cyc
—
t2cyc = time_cyc × 2 × T
time_cyc
Controlling
Variable
Value
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
120
Freescale Semiconductor
Electrical Characteristics
Table 77. UDMA Out Burst Timing Parameters (continued)
ATA
Parameter
Parameter
from
Figure 73,
Figure 74,
Figure 75
trfs1
trfs
—
tdzfs
tss
tss
tmli
tdzfs_mli
tli
Controlling
Variable
Value
trfs = 1.6 × T + tsui + tco + tbuf + tbuf
—
tdzfs = time_dzfs × T – (tskew1)
time_dzfs
tss = time_ss × T – (tskew1 + tskew2)
time_ss
tdzfs_mli =max (time_dzfs, time_mli) × T – (tskew1 + tskew2)
—
tli1
tli1 > 0
—
tli
tli2
tli2 > 0
—
tli
tli3
tli3 > 0
—
tcvh
tcvh
tcvh = (time_cvh ×T) – (tskew1 + tskew2)
—
ton
toff
ton = time_on × T – tskew1
toff = time_off × T – tskew1
4.7.14
time_cvh
—
SATA PHY Parameters
This section describes SATA PHY electrical specifications.
4.7.14.1
Reference Clock Electrical and Jitter Specifications
The refclk signal is differential and supports frequencies of 25 MHz or 50-156.25 MHz (100 MHz and
125 MHz are common frequencies). The frequency is pin-selectable (for more information about the
signal, see “Per-Transceiver Control and Status Signals” in the SATA PHY chapter in the Reference
Manual).
Table 78 provides the SATA PHY reference clock specifications.
Table 78. Reference Clock Specifications
Parameters
Test Conditions
Min
Max
Differential peak voltage (typically 0.71 V)
—
350
850
mV
Common mode voltage
(refclk_p + refclk_m) / 2
—
175
2,000
mV
For information about total
phase jitter, see following
section
—
3
ps RMS
Minimum/maximum duty cycle
—
40
60
% UI
Frequency range
—
25
Total phase jitter
156.25
Unit
MHz
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
121
Electrical Characteristics
4.7.14.1.1
Reference Clock Jitter Measurement
The total phase jitter on the reference clock is specified at 3 ps RMS. There are numerous ways to measure
the reference clock jitter, one of which is as follows.
Using a high-speed sampling scope (20 GSamples/s), 1 million samples of the differential reference clock
are taken, and the zero-crossing times of each rising edge are calculated. From the zero-crossing data, an
average reference clock period is calculated. This average reference clock period is subtracted from each
sequential, instantaneous period to find the difference between each reference clock rising edge and the
ideal placement to produce the phase jitter sequence. The power spectral density (PSD) of the phase jitter
is calculated and integrated after being weighted with the transfer function shown in Figure 76. The square
root of the resultant integral is the RMS total phase jitter.
Figure 76. Weighting Function for RMS Phase Jitter Calculation
4.7.14.2
Transmitter and Receiver Characteristics
The SATA PHY meets or exceeds the electrical compliance requirements defined in the SATA
specification. The following subsections provide values obtained from a combination of simulations and
silicon characterization.
NOTE
The tables in the following sections indicate any exceptions to the SATA
specification or aspects of the SATA PHY that exceed the standard, as well
as provide information about parameters not defined in the standard.
4.7.14.2.1
SATA PHY Transmitter Characteristics
Table 79 provides specifications for SATA PHY transmitter characteristics.
Table 79. SATA2 PHY Transmitter Characteristics
Parameters
Symbol
Min
Typ
Max
Unit
V
Transmit common mode voltage
VCTM
0.4
—
0.6
Transmitter pre-emphasis accuracy (measured
change in de-emphasized bit)
—
–0.5
—
0.5
dB
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
122
Freescale Semiconductor
Electrical Characteristics
4.7.14.2.2
SATA PHY Receiver Characteristics
Table 80 provides specifications for SATA PHY receiver characteristics.
Table 80. SATA PHY Receiver Characteristics
Parameters
Symbol
Minimum Rx eye height (differential peak-to-peak) VMIN_RX_EYE_HEIGHT
Tolerance
4.7.14.3
PPM
Min
Typ
Max
Unit
—
—
175
mV
–400
—
400
ppm
SATA_REXT Reference Resistor Connection
The impedance calibration process requires connection of reference resistor 191 Ω. 1% precision resistor
on SATA_REXT pad to ground.
Resistor calibration consists of learning which state of the internal Resistor Calibration register causes an
internal, digitally trimmed calibration resistor to best match the impedance applied to the SATA_REXT
pin. The calibration register value is then supplied to all Tx and Rx termination resistors.
During the calibration process (for a few tens of microseconds), up to 0.3 mW can be dissipated in the
external SATA_REXT resistor. At other times, no power is dissipated by the SATA_REXT resistor.
4.7.14.4
SATA Connectivity When Not in Use
NOTE
The Temperature Sensor is part of the SATA module. If SATA IP is disabled,
the Temperature Sensor will not work as well. Temperature Sensor
functionality is important in supporting high performance applications
without overheating the device (at high ambient temp).
When both SATA and thermal sensor are not required, connect VP and VPH supplies to ground. The rest
of the ports, both inputs and outputs (SATA_REFCLKM, SATA_REFCLKP, SATA_REXT, SATA_RXM,
SATA_RXP, SATA_TXM) can be left floating. It is not recommended to turn off the VPH while the VP is
active.
When SATA is not in use but thermal sensor is still required, both VP and VPH supplies must be powered
on according to their nominal voltage levels. The reference clock input frequency must fall within the
specified range of 25 MHz to 156.25 MHz. SATA_REXT does not need to be connected, as the
termination impedance is not of consequence.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
123
Electrical Characteristics
4.7.15
SCAN JTAG Controller (SJC) Timing Parameters
Figure 77 depicts the SJC test clock input timing. Figure 78 depicts the SJC boundary scan timing.
Figure 79 depicts the SJC test access port. Signal parameters are listed in Table 81.
SJ1
SJ2
TCK
(Input)
SJ2
VM
VIH
VM
VIL
SJ3
SJ3
Figure 77. Test Clock Input Timing Diagram
TCK
(Input)
VIH
VIL
SJ4
Data
Inputs
SJ5
Input Data Valid
SJ6
Data
Outputs
Output Data Valid
SJ7
Data
Outputs
SJ6
Data
Outputs
Output Data Valid
Figure 78. Boundary Scan (JTAG) Timing Diagram
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
124
Freescale Semiconductor
Electrical Characteristics
TCK
(Input)
VIH
VIL
SJ8
TDI
TMS
(Input)
SJ9
Input Data Valid
SJ10
TDO
(Output)
Output Data Valid
SJ11
TDO
(Output)
SJ10
TDO
(Output)
Output Data Valid
Figure 79. Test Access Port Timing Diagram
TCK
(Input)
SJ13
TRST
(Input)
SJ12
Figure 80. TRST Timing Diagram
Table 81. JTAG Timing
All Frequencies
Parameter1,2
ID
Unit
Min
Max
0.001
22
MHz
45
—
ns
22.5
—
ns
SJ0
TCK frequency of operation 1/(3•TDC)1
SJ1
TCK cycle time in crystal mode
SJ2
TCK clock pulse width measured at VM2
SJ3
TCK rise and fall times
—
3
ns
SJ4
Boundary scan input data set-up time
5
—
ns
SJ5
Boundary scan input data hold time
24
—
ns
SJ6
TCK low to output data valid
—
40
ns
SJ7
TCK low to output high impedance
—
40
ns
SJ8
TMS, TDI data set-up time
5
—
ns
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
125
Electrical Characteristics
Table 81. JTAG Timing (continued)
All Frequencies
Parameter1,2
ID
Unit
Min
Max
SJ9
TMS, TDI data hold time
25
—
ns
SJ10
TCK low to TDO data valid
—
44
ns
SJ11
TCK low to TDO high impedance
—
44
ns
SJ12
TRST assert time
100
—
ns
SJ13
TRST set-up time to TCK low
40
—
ns
1
2
TDC = target frequency of SJC
VM = mid-point voltage
4.7.16
SPDIF Timing Parameters
The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When
encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.
Table 82 and Figures , show SPDIF timing parameters for the Sony/Philips Digital Interconnect Format
(SPDIF), including the timing of the modulating Rx clock (SRCK) for SPDIF in Rx mode and the timing
of the modulating Tx clock (STCLK) for SPDIF in Tx mode.
Table 82. SPDIF Timing Parameters
Timing Parameter Range
Characteristics
Symbol
Units
Min
Max
SPDIFIN Skew: asynchronous inputs, no specs apply
—
—
0.7
ns
SPDIFOUT output (Load = 50pf)
• Skew
• Transition rising
• Transition falling
—
—
—
—
—
—
1.5
24.2
31.3
ns
SPDIFOUT1 output (Load = 30pf)
• Skew
• Transition rising
• Transition falling
—
—
—
—
—
—
1.5
13.6
18.0
ns
Modulating Rx clock (SRCK) period
srckp
40.0
—
ns
SRCK high period
srckph
16.0
—
ns
SRCK low period
srckpl
16.0
—
ns
Modulating Tx clock (STCLK) period
stclkp
40.0
—
ns
STCLK high period
stclkph
16.0
—
ns
STCLK low period
stclkpl
16.0
—
ns
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
126
Freescale Semiconductor
Electrical Characteristics
srckp
srckpl
srckph
VM
SRCK
(Output)
VM
Figure 81. SPDIF Timing Diagram
stclkp
stclkpl
stclkph
VM
STCLK
(Input)
VM
Figure 82. STCLK Timing
4.7.17
SSI Timing Parameters
This section describes the timing parameters of the SSI module. The connectivity of the serial
synchronous interfaces are summarized in Table 83.
Table 83. AUDMUX Port Allocation
Port
Signal Nomenclature
AUDMUX port 1
SSI 1
Internal
AUDMUX port 2
SSI 2
Internal
AUDMUX port 3
AUD3
External – AUD3 I/O
AUDMUX port 4
AUD4
External – EIM or CSPI1 I/O through IOMUXC
AUDMUX port 5
AUD5
External – EIM or SD1 I/O through IOMUXC
AUDMUX port 6
AUD6
External – EIM or DISP2 through IOMUXC
AUDMUX port 7
SSI 3
Internal
•
•
Type and Access
NOTE
The terms WL and BL used in the timing diagrams and tables refer to
Word Length (WL) and Bit Length (BL).
The SSI timing diagrams use generic signal names wherein the names
used in the i.MX53 Reference Manual are channel specific signal
names. For example, a channel clock referenced in the IOMUXC
chapter as AUD3_TXC appears in the timing diagram as TXC.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
127
Electrical Characteristics
4.7.17.1
SSI Transmitter Timing with Internal Clock
Figure 83 depicts the SSI transmitter internal clock timing and Table 84 lists the timing parameters for the
SSI transmitter internal clock.
.
SS1
SS3
SS5
SS2
SS4
TXC
SS8
SS6
TXFS (bl)
(Output)
SS10
SS12
SS14
TXFS (wl)
(Output)
SS15
SS16
SS18
SS17
TXD
(Output)
SS43
SS42
SS19
RXD
(Input)
Note: SRXD input in synchronous mode only
: SRXD input in synchronous mode only
Figure 83. SSI Transmitter Internal Clock Timing Diagram
Table 84. SSI Transmitter Timing with Internal Clock
ID
Parameter
Min
Max
Unit
Internal Clock Operation
SS1
(Tx/Rx) CK clock period
81.4
—
ns
SS2
(Tx/Rx) CK clock high period
36.0
—
ns
SS3
(Tx/Rx) CK clock rise time
—
6.0
ns
SS4
(Tx/Rx) CK clock low period
36.0
—
ns
SS5
(Tx/Rx) CK clock fall time
—
6.0
ns
SS6
(Tx) CK high to FS (bl) high
—
15.0
ns
SS8
(Tx) CK high to FS (bl) low
—
15.0
ns
SS10
(Tx) CK high to FS (wl) high
—
15.0
ns
SS12
(Tx) CK high to FS (wl) low
—
15.0
ns
SS14
(Tx/Rx) Internal FS rise time
—
6.0
ns
SS15
(Tx/Rx) Internal FS fall time
—
6.0
ns
SS16
(Tx) CK high to STXD valid from high impedance
—
15.0
ns
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
128
Freescale Semiconductor
Electrical Characteristics
Table 84. SSI Transmitter Timing with Internal Clock (continued)
ID
Parameter
Min
Max
Unit
SS17
(Tx) CK high to STXD high/low
—
15.0
ns
SS18
(Tx) CK high to STXD high impedance
—
15.0
ns
SS19
STXD rise/fall time
—
6.0
ns
Synchronous Internal Clock Operation
SS42
SRXD setup before (Tx) CK falling
10.0
—
ns
SS43
SRXD hold after (Tx) CK falling
0.0
—
ns
SS52
Loading
—
25.0
pF
•
•
•
•
•
NOTE
All the timings for the SSI are given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables
and in the figures.
All timings are on Audiomux Pads when SSI is being used for data
transfer.
The terms WL and BL refer to Word Length (WL) and Bit Length (BL).
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
For internal Frame Sync operation using external clock, the FS timing is
same as that of Tx Data (for example, during AC97 mode of operation).
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
129
Electrical Characteristics
4.7.17.2
SSI Receiver Timing with Internal Clock
Figure 84 depicts the SSI receiver internal clock timing and Table 85 lists the timing parameters for the
receiver timing with the internal clock
SS1
SS3
SS5
SS4
SS2
TXC
(Output)
SS9
SS7
TXFS (bl)
(Output)
SS11
TXFS (wl)
(Output)
SS13
SS20
SS21
RXD
(Input)
SS47
SS48
SS51
SS49
SS50
RXC
(Output)
Figure 84. SSI Receiver Internal Clock Timing Diagram
Table 85. SSI Receiver Timing with Internal Clock
ID
Parameter
Min
Max
Unit
Internal Clock Operation
SS1
(Tx/Rx) CK clock period
81.4
—
ns
SS2
(Tx/Rx) CK clock high period
36.0
—
ns
SS3
(Tx/Rx) CK clock rise time
—
6.0
ns
SS4
(Tx/Rx) CK clock low period
36.0
—
ns
SS5
(Tx/Rx) CK clock fall time
—
6.0
ns
SS7
(Rx) CK high to FS (bl) high
—
15.0
ns
SS9
(Rx) CK high to FS (bl) low
—
15.0
ns
SS11
(Rx) CK high to FS (wl) high
—
15.0
ns
SS13
(Rx) CK high to FS (wl) low
—
15.0
ns
SS20
SRXD setup time before (Rx) CK low
10.0
—
ns
SS21
SRXD hold time after (Rx) CK low
0.0
—
ns
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
130
Freescale Semiconductor
Electrical Characteristics
Table 85. SSI Receiver Timing with Internal Clock (continued)
ID
Parameter
Min
Max
Unit
15.04
—
ns
Oversampling Clock Operation
SS47
Oversampling clock period
SS48
Oversampling clock high period
6.0
—
ns
SS49
Oversampling clock rise time
—
3.0
ns
SS50
Oversampling clock low period
6.0
—
ns
SS51
Oversampling clock fall time
—
3.0
ns
•
•
•
•
•
NOTE
All the timings for the SSI are given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables
and in the figures.
All timings are on Audiomux Pads when SSI is being used for data
transfer.
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
The terms WL and BL refer to Word Length (WL) and Bit Length (BL).
For internal Frame Sync operation using external clock, the FS timing is
same as that of Tx Data (for example, during AC97 mode of operation).
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
131
Electrical Characteristics
4.7.17.3
SSI Transmitter Timing with External Clock
Figure 85 depicts the SSI transmitter external clock timing and Table 86 lists the timing parameters for
the transmitter timing with the external clock
SS22
SS23
SS25
SS26
SS24
TXC
(Input)
SS27
SS29
TXFS (bl)
(Input)
SS33
SS31
TXFS (wl)
(Input)
SS37
SS39
SS38
TXD
(Output)
SS45
SS44
RXD
(Input)
SS46
Note: SRXD Input in Synchronous mode only
Figure 85. SSI Transmitter External Clock Timing Diagram
Table 86. SSI Transmitter Timing with External Clock
ID
Parameter
Min
Max
Unit
External Clock Operation
SS22
(Tx/Rx) CK clock period
81.4
—
ns
SS23
(Tx/Rx) CK clock high period
36.0
—
ns
SS24
(Tx/Rx) CK clock rise time
—
6.0
ns
SS25
(Tx/Rx) CK clock low period
36.0
—
ns
SS26
(Tx/Rx) CK clock fall time
—
6.0
ns
SS27
(Tx) CK high to FS (bl) high
–10.0
15.0
ns
SS29
(Tx) CK high to FS (bl) low
10.0
—
ns
SS31
(Tx) CK high to FS (wl) high
–10.0
15.0
ns
SS33
(Tx) CK high to FS (wl) low
10.0
—
ns
SS37
(Tx) CK high to STXD valid from high impedance
—
15.0
ns
SS38
(Tx) CK high to STXD high/low
—
15.0
ns
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
132
Freescale Semiconductor
Electrical Characteristics
Table 86. SSI Transmitter Timing with External Clock (continued)
ID
SS39
Parameter
(Tx) CK high to STXD high impedance
Min
Max
Unit
—
15.0
ns
Synchronous External Clock Operation
SS44
SRXD setup before (Tx) CK falling
10.0
—
ns
SS45
SRXD hold after (Tx) CK falling
2.0
—
ns
SS46
SRXD rise/fall time
—
6.0
ns
•
•
•
•
•
NOTE
All the timings for the SSI are given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables
and in the figures.
All timings are on Audiomux Pads when SSI is being used for data
transfer.
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
The terms WL and BL refer to Word Length (WL) and Bit Length (BL).
For internal Frame Sync operation using external clock, the FS timing is
same as that of Tx Data (for example, during AC97 mode of operation).
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
133
Electrical Characteristics
4.7.17.4
SSI Receiver Timing with External Clock
Figure 86 depicts the SSI receiver external clock timing and Table 87 lists the timing parameters for the
receiver timing with the external clock.
SS22
SS26
SS24
SS25
SS23
TXC
SS30
SS28
TXFS (bl)
SS32
SS34
SS35
TXFS (wl)
SS41
SS40
SS36
RXD
(Input)
Figure 86. SSI Receiver External Clock Timing Diagram
Table 87. SSI Receiver Timing with External Clock
ID
Parameter
Min
Max
Unit
81.4
—
ns
External Clock Operation
SS22
(Tx/Rx) CK clock period
SS23
(Tx/Rx) CK clock high period
36
—
ns
SS24
(Tx/Rx) CK clock rise time
—
6.0
ns
SS25
(Tx/Rx) CK clock low period
36
—
ns
SS26
(Tx/Rx) CK clock fall time
—
6.0
ns
SS28
(Rx) CK high to FS (bl) high
–10
15.0
ns
SS30
(Rx) CK high to FS (bl) low
10
—
ns
SS32
(Rx) CK high to FS (wl) high
–10
15.0
ns
SS34
(Rx) CK high to FS (wl) low
10
—
ns
SS35
(Tx/Rx) External FS rise time
—
6.0
ns
SS36
(Tx/Rx) External FS fall time
—
6.0
ns
SS40
SRXD setup time before (Rx) CK low
10
—
ns
SS41
SRXD hold time after (Rx) CK low
2
—
ns
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
134
Freescale Semiconductor
Electrical Characteristics
•
•
•
•
•
4.7.18
NOTE
All the timings for the SSI are given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables
and in the figures.
All timings are on Audiomux Pads when SSI is being used for data
transfer.
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
The terms WL and BL refer to Word Length (WL) and Bit Length (BL).
For internal Frame Sync operation using external clock, the FS timing is
same as that of Tx Data (for example, during AC97 mode of operation).
UART I/O Configuration and Timing Parameters
4.7.18.1
UART RS-232 I/O Configuration in Different Modes
The i.MX53xA UART interfaces can serve both as DTE or DCE device. This can be configured by the
DCEDTE control bit (default 0 – DCE mode). Table 88 shows the UART I/O configuration based on the
enabled mode.
Table 88. UART I/O Configuration vs. Mode
DTE Mode
DCE Mode
Port
Direction
Description
Direction
Description
RTS
Output
RTS from DTE to DCE
Input
RTS from DTE to DCE
CTS
Input
CTS from DCE to DTE
Output
CTS from DCE to DTE
DTR
Output
DTR from DTE to DCE
Input
DTR from DTE to DCE
DSR
Input
DSR from DCE to DTE
Output
DSR from DCE to DTE
DCD
Input
DCD from DCE to DTE
Output
DCD from DCE to DTE
RI
Input
RING from DCE to DTE
Output
RING from DCE to DTE
TXD_MUX
Input
Serial data from DCE to DTE
Output
Serial data from DCE to DTE
RXD_MUX
Output
Serial data from DTE to DCE
Input
Serial data from DTE to DCE
4.7.18.2
UART RS-232 Serial Mode Timing
The following sections describe the electrical information of the UART module in the RS-232 mode.
4.7.18.2.1
UART Transmitter
Figure 87 depicts the transmit timing of UART in the RS-232 serial mode, with 8 data bit/1 stop bit format.
Table 89 lists the UART RS-232 serial mode transmit timing characteristics.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
135
Electrical Characteristics
UA1
TXD
(output)
Start
Bit
Possible
Parity
Bit
UA1
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Par Bit STOP
BIT
Next
Start
Bit
UA1
UA1
Figure 87. UART RS-232 Serial Mode Transmit Timing Diagram
Table 89. RS-232 Serial Mode Transmit Timing Parameters
ID
UA1
1
2
Parameter
Transmit Bit Time
Symbol
Min
Max
Units
tTbit
1/Fbaud_rate1 –
Tref_clk2
1/Fbaud_rate +
Tref_clk
—
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
4.7.18.2.2
UART Receiver
Figure 88 depicts the RS-232 serial mode receive timing with 8 data bit/1 stop bit format. Table 90 lists
serial mode receive timing characteristics.
UA2
RXD
(input)
Start
Bit
Possible
Parity
Bit
UA2
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Par Bit STOP
BIT
Next
Start
Bit
UA2
UA2
Figure 88. UART RS-232 Serial Mode Receive Timing Diagram
Table 90. RS-232 Serial Mode Receive Timing Parameters
ID
Parameter
Symbol
Min
Max
Units
UA2
Receive Bit Time1
tRbit
1/Fbaud_rate2 –
1/(16*Fbaud_rate)
1/Fbaud_rate +
1/(16*Fbaud_rate)
—
1
The UART receiver can tolerate 1/(16*Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not
exceed 3/(16*Fbaud_rate).
2 F
baud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
4.7.18.3
UART IrDA Mode Timing
The following subsections give the UART transmit and receive timings in IrDA mode.
4.7.18.3.3
UART IrDA Mode Transmitter
Figure 89 depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 91 lists
the transmit timing characteristics.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
136
Freescale Semiconductor
Electrical Characteristics
UA3
UA4
UA3
UA3
UA3
TXD
(output)
Start
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Possible
Parity
Bit
Bit 7
STOP
BIT
Figure 89. UART IrDA Mode Transmit Timing Diagram
Table 91. IrDA Mode Transmit Timing Parameters
1
2
ID
Parameter
Symbol
Min
Max
Units
UA3
Transmit Bit Time in IrDA mode
tTIRbit
1/Fbaud_rate1 –
Tref_clk2
1/Fbaud_rate + Tref_clk
—
UA4
Transmit IR Pulse Duration
tTIRpulse
(3/16)*(1/Fbaud_rate)
– Tref_clk
(3/16)*(1/Fbaud_rate) +
Tref_clk
—
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
4.7.18.3.4
UART IrDA Mode Receiver
Figure 90 depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 92 lists the
receive timing characteristics.
UA5
UA6
UA5
UA5
UA5
RXD
(input)
Start
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Possible
Parity
Bit
Bit 7
STOP
BIT
Figure 90. UART IrDA Mode Receive Timing Diagram
Table 92. IrDA Mode Receive Timing Parameters
ID
Parameter
UA5
Receive Bit Time1 in IrDA mode
UA6
Receive IR Pulse Duration
Symbol
Min
Max
Units
tRIRbit
1/Fbaud_rate2 –
1/(16*Fbaud_rate)
1/Fbaud_rate +
1/(16*Fbaud_rate)
—
tRIRpulse
1.41 us
(5/16)*(1/Fbaud_rate)
—
1
The UART receiver can tolerate 1/(16*Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not
exceed 3/(16*Fbaud_rate).
2
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
137
Electrical Characteristics
4.7.19
USB-OH-3 Parameters
This section describes the electrical parameters of the USB OTG port and USB HOST ports. For on-chip
USB PHY parameters see Section 4.7.20, “USB PHY Parameters.”
4.7.19.1
Serial Interface
In order to support four serial different interfaces, the USB serial transceiver can be configured to operate
in one of four modes:
•
DAT_SE0 bidirectional, 3-wire mode
•
DAT_SE0 unidirectional, 6-wire mode
•
VP_VM bidirectional, 4-wire mode
•
VP_VM unidirectional, 6-wire mode
4.7.19.1.1
DAT_SE0 Bidirectional Mode
Table 93. Signal Definitions - DAT_SE0 Bidirectional Mode
Name
Direction
Signal Description
USB_TXOE_B
Out
Transmit enable, active low
USB_DAT_VP
Out
In
TX data when USB_TXOE_B is low
Differential RX data when USB_TXOE_B is high
USB_SE0_VM
Out
In
SE0 drive when USB_TXOE_B is low
SE0 RX indicator when USB_TXOE_B is high
Transmit
US3
USB_TXOE_B
USB_DAT_VP
US1
USB_SE0_VM
US2
US4
Figure 91. USB Transmit Waveform in DAT_SE0 Bidirectional Mode
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
138
Freescale Semiconductor
Electrical Characteristics
Receive
USB_TXOE_B
USB_DAT_VP
USB_SE0_VM
US7
US8
USB_SE0_VM
Figure 92. USB Receive Waveform in DAT_SE0 Bidirectional Mode
Table 94. Definitions of USB Waveform in DAT_SE0 Bi-Directional Mode
No.
Parameter
Signal Name
Direction
Min
Max
Unit
Conditions /
Reference Signal
US1
TX Rise/Fall Time
USB_DAT_VP
Out
-—
5.0
ns
50 pF
US2
TX Rise/Fall Time
USB_SE0_VM
Out
—
5.0
ns
50 pF
US3
TX Rise/Fall Time
USB_TXOE_B
Out
—
5.0
ns
50 pF
US4
TX Duty Cycle
USB_DAT_VP
Out
49.0
51.0
%
—
US7
RX Rise/Fall Time
USB_DAT_VP
In
—
3.0
ns
35 pF
US8
RX Rise/Fall Time
USB_SE0_VM
In
—
3.0
ns
35 pF
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
139
Electrical Characteristics
4.7.19.1.2
DAT_SE0 Unidirectional Mode
Table 95. Signal Definitions - DAT_SE0 Unidirectional Mode
Name
Direction
Signal Description
USB_TXOE_B
Out
Transmit enable, active low
USB_DAT_VP
Out
TX data when USB_TXOE_B is low
USB_SE0_VM
Out
SE0 drive when USB_TXOE_B is low
USB_VP1
In
Buffered data on DP when USB_TXOE_B is high
USB_VM1
In
Buffered data on DM when USB_TXOE_B is high
Transmit
US11
USB_TXOE_B
USB_DAT_VP
US9
USB_SE0_VM
US10
US12
Figure 93. USB Transmit Waveform in DAT_SE0 Unidirectional Mode
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
140
Freescale Semiconductor
Electrical Characteristics
Receive
USB_TXOE_B
USB_DAT_VP
US15
US16
USB_SE0_VM
Figure 94. USB Receive Waveform in DAT_SE0 Unidirectional Mode
Table 96. USB Port Timing Specification in DAT_SE0 Unidirectional Mode
Parameter
Signal Name
Signal
Source
Min
Max
Unit
Condition /
Reference Signal
US9
TX Rise/Fall Time
USB_DAT_VP
Out
—
5.0
ns
50 pF
US10
TX Rise/Fall Time
USB_SE0_VM
Out
—
5.0
ns
50 pF
US11
TX Rise/Fall Time
USB_TXOE_B
Out
—
5.0
ns
50 pF
US12
TX Duty Cycle
USB_DAT_VP
Out
49.0
51.0
%
—
US15
RX Rise/Fall Time
USB_VP1
In
—
3.0
ns
35 pF
US16
RX Rise/Fall Time
USB_VM1
In
—
3.0
ns
35 pF
No.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
141
Electrical Characteristics
4.7.19.1.3
VP_VM Bidirectional Mode
Table 97. Signal Definitions - VP_VM Bidirectional mode
Name
Direction
Signal Description
USB_TXOE_B
Out
Transmit enable, active low
USB_DAT_VP
Out (Tx)
In (Rx)
TX VP data when USB_TXOE_B is low
RX VP data when USB_TXOE_B is high
USB_SE0_VM
Out (Tx)
In (Rx)
TX VM data when USB_TXOE_B low
RX VM data when USB_TXOE_B high
Transmit
US20
USB_TXOE_B
USB_DAT_VP
USB_SE0_VM
US18
US19
US21
US22
US22
Figure 95. USB Transmit Waveform in VP_VM Bidirectional Mode
Receive
US26
USB_DAT_VP
USB_SE0_VM
US27
US28
Figure 96. USB Receive Waveform in VP_VM Bidirectional Mode
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
142
Freescale Semiconductor
Electrical Characteristics
Table 98. USB Port Timing Specification in VP_VM Bidirectional Mode
No.
Parameter
Signal Name
Direction
Min
Max
Unit
Condition /
Reference Signal
US18
TX Rise/Fall Time
USB_DAT_V
P
Out
—
5.0
ns
50 pF
US19
TX Rise/Fall Time
USB_SE0_V
M
Out
—
5.0
ns
50 pF
US20
TX Rise/Fall Time
USB_TXOE
_B
Out
—
5.0
ns
50 pF
US21
TX Duty Cycle
USB_DAT_V
P
Out
49.0
51.0
%
—
US22
TX Overlap
USB_SE0_V
M
Out
-3.0
+3.0
ns
USB_DAT_VP
US26
RX Rise/Fall Time
USB_DAT_V
P
In
—
3.0
ns
35 pF
US27
RX Rise/Fall Time
USB_SE0_V
M
In
—
3.0
ns
35 pF
US28
RX Skew
USB_DAT_V
P
In
-4.0
+4.0
ns
USB_SE0_VM
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
143
Electrical Characteristics
4.7.19.1.4
VP_VM Unidirectional Mode
Table 99. Signal Definitions - VP_VM Unidirectional mode
Name
Direction
Signal Description
USB_TXOE_B
Out
Transmit enable, active low
USB_DAT_VP
Out
TX VP data when USB_TXOE_B is low
USB_SE0_VM
Out
TX VM data when USB_TXOE_B is low
USB_VP1
In
RX VP data when USB_TXOE_B is high
USB_VM1
In
RX VM data when USB_TXOE_B is high
Transmit
US32
USB_TXOE_B
USB_DAT_VP
USB_SE0_VM
US30
US33
US31
US34
Figure 97. USB Transmit Waveform in VP_VM Unidirectional Mode
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
144
Freescale Semiconductor
Electrical Characteristics
Receive
USB_TXOE_B
USB_VP1
US38
USB_VM1
US40
US39
Figure 98. USB Receive Waveform in VP_VM Unidirectional Mode
Table 100. USB Timing Specification in VP_VM Unidirectional Mode
No.
Parameter
Signal
Direction
Min
Max
Unit
Conditions /
Reference Signal
US30
TX Rise/Fall Time
USB_DAT_VP
Out
—
5.0
ns
50 pF
US31
TX Rise/Fall Time
USB_SE0_V
M
Out
—
5.0
ns
50 pF
US32
TX Rise/Fall Time
USB_TXOE_
B
Out
—
5.0
ns
50 pF
US33
TX Duty Cycle
USB_DAT_VP
Out
49.0
51.0
%
—
US34
TX Overlap
USB_SE0_V
M
Out
-3.0
3.0
ns
USB_DAT_VP
US38
RX Rise/Fall Time
USB_VP1
In
—
3.0
ns
35 pF
US39
RX Rise/Fall Time
USB_VM1
In
—
3.0
ns
35 pF
US40
RX Skew
USB_VP1
In
-4.0
+4.0
ns
USB_VM1
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
145
Electrical Characteristics
4.7.19.2
Parallel Interface (Normal ULPI) Timing
Electrical and timing specifications of Parallel Interface (Normal ULPI) for Host Port2 and Port3 are
presented in the subsequent sections.
Table 101. Signal Definitions - Parallel Interface (Normal ULPI)
Name
USB_Clk
USB_Data[7:0]
USB_Dir
USB_Stp
Direction
Signal Description
In
Interface clock. All interface signals are synchronous to Clock.
I/O
Bi-directional data bus, driven low by the link during idle. Bus
ownership is determined by Dir.
In
Direction. Control the direction of the Data bus.
Stop. The link asserts this signal for 1 clock cycle to stop the
data stream currently on the bus.
Out
In
USB_Nxt
Next. The PHY asserts this signal to throttle the data.
USB_Clk
US15
US16
USB_Dir/Nxt
US15
US16
USB_Data
US17
US17
USB_Stp
Figure 99. USB Transmit/Receive Waveform in Parallel Mode
Table 102. USB Timing Specification for Normal ULPI Mode
ID
Parameter
Min
Max
Unit
Conditions /
Reference Signal
US15
Setup Time (Dir&Nxt in, Data in)
6.0
—
ns
10 pF
US16
Hold Time (Dir&Nxt in, Data in)
0.0
—
ns
10 pF
US17
Output Delay Time (Stp out, Data out
—
9.0
ns
10 pF
4.7.20
USB PHY Parameters
This section describes the USB-OTG PHY and the USB Host port PHY parameters.
4.7.20.1
USB PHY AC Parameters
Table 103 lists the AC timing parameters for USB PHY.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
146
Freescale Semiconductor
Electrical Characteristics
Table 103. USB PHY AC Timing Parameters
Parameter
Conditions
Min
Typ
Max
Unit
trise
1.5 Mbps
12 Mbps
480 Mbps
75
4
0.5
—
300
20
ns
tfall
1.5 Mbps
12 Mbps
480 Mbps
75
4
0.5
—
300
20
ns
Jitter
1.5 Mbps
12 Mbps
480 Mbps
—
—
10
1
0.2
ns
4.7.20.2
USB PHY Additional Electrical Parameters
Table 104 lists the parameters for additional electrical characteristics for USB PHY.
Table 104. Additional Electrical Characteristics for USB PHY
Parameter
Conditions
Min
Typ
Max
Unit
–0.05
0.8
—
0.5
2.5
V
Vcm DC
(dc level measured at receiver connector)
HS Mode
LS/FS Mode
Crossover Voltage
LS Mode
FS Mode
1.3
1.3
—
2
2
V
Power supply ripple noise
(analog 3.3 V)
< 160 MHz
–50
0
50
mV
Power supply ripple noise
(analog 2.5 V)
< 1.2 MHz
> 1.2 MHz
–10
–50
0
0
10
50
mV
Power supply ripple noise
(Digital 1.2 V)
All conditions
–50
0
50
mV
4.7.20.3
USB PHY System Clocking (SYSCLK)
Table 105 lists the USB PHY system clocking parameters.
Table 105. USB PHY System Clocking Parameters
Parameter
Conditions
Min
Typ
Max
Unit
Reference Clock
frequency 24 MHz
–150
—
150
ppm
—
—
—
200
ps
Jitter (peak-peak)
< 1.2 MHz
0
—
50
ps
Jitter (peak-peak)
> 1.2 MHz
0
—
100
ps
Reference Clock
frequency 24 MHz
40
—
60
%
Clock deviation
Rise/fall time
Duty-cycle
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
147
Electrical Characteristics
4.7.20.4
USB PHY Voltage Thresholds
Table 106 lists the USB PHY voltage thresholds.
Table 106. VBUS Comparators Thresholds
Parameter
Conditions
Min
Typ
Max
Unit
A-Device Session Valid
—
0.8
1.4
2.0
V
B-Device Session Valid
—
0.8
1.4
4.0
V
B-Device Session End
—
0.2
0.45
0.8
V
VBUS Valid Comparator Threshold1
—
4.4
4.6
4.75
V
1
For VBUS maximum rating, see Table 4 on page 18
4.7.20.5
USB PHY Termination
USB driver impedance in FS and HS modes is 45 Ω ±10% (steady state). No external resistors required.
4.8
XTAL Electrical Specifications
Table 107 shows the XTALOSC electrical specifications.
Table 108 shows the XTALOSC_32K electrical specifications.
Table 107. XTALOSC Electrical Specifications
Parameter
Frequency
Min
Typ
Max
Units
22
24
27
MHz
Table 108. XTALOSC_32K Electrical Specifications
Parameter
Frequency
1
Min
Typ
Max
Units
--
32.768/32.01
--
kHz
Recommended nominal frequency 32.768 kHz.
4.9
Integrated LDO Voltage Regulators Parameters
The PLL supplies VDD_DIG_PLL and VDD_ANA_PLL can be powered ON from internal LDO voltage
regulator (default case). In this case VDD_REG is used as internal regulator’s power source. The
regulator’s output can be used as a supply for other domains such as VDDA and VDDAL1.
Table 109 shows the VDD_DIG_PLL and VDD_ANA_PLL Integrated Voltage Regulators Parameters.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
148
Freescale Semiconductor
Boot Mode Configuration
Table 109. LDO Voltage Regulators Electrical Specifications
Parameter
Symbol
Min
Typ
Max
Units
VDD_DIG_PLL functional Voltage
Range1
VVID_DIG_PLL
1.15
1.2
1.3
V
VDD_ANA_PLL functional Voltage
Range1
VVDD_ANA_PLL
1.7
1.8
1.95
V
VDD_DIG_PLL and VDD_ANA_PLL
accuracy
—
—
—
+/–3
%
VDD_DIG_PLL power-supply rejection
ratio2
—
—
–18
—
dB
VDD_ANA_PLL power-supply rejection
ratio2
—
—
–15
—
dB
IVID_DIG_PLL+
IVDD_ANA_PLL
—
—
125
mA
Output current3
1
VDD_DIG_PLL and VDD_ANA_PLL voltages are programmable, but should not be set outside the target functional range
for proper PLL operation.
2 The gain or attenuation from the input supply variation to the output of the LDO (by design).
3 The limitation is for sum of the VDD_DIG_PLL and VDD_ANA_PLL current.
5
Boot Mode Configuration
This section provides information on boot mode configuration pins allocation and boot devices interfaces
allocation.
5.1
Boot Mode Configuration Pins
Table 110 provides boot options, functionality, fuse values, and associated pins. Several input pins are also
sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse.
The boot option pins are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared, which is the case for an
unblown fuse). For detailed boot mode options configured by the boot mode pins, please refer to the
i.MX53 Fuse Map document and Boot chapter in i.MX53 Reference Manual.
Table 110. Fuses and Associated Pins Used for Boot
Pin
Direction at
Reset
E-Fuse Name
Details
BOOT_MODE[1]
Input
N/A
Boot Mode selection
BOOT_MODE[0]
Input
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
149
Boot Mode Configuration
Table 110. Fuses and Associated Pins Used for Boot (continued)
Pin
Direction at
Reset
E-Fuse Name
EIM_A22
Input
BOOT_CFG1[7]/Test Mode Selection
EIM_A21
Input
EIM_A20
Input
EIM_A19
Input
EIM_A18
Input
EIM_A17
Input
EIM_A16
Input
BOOT_CFG1[1]
EIM_LBA
Input
BOOT_CFG1[0]
EIM_EB0
Input
BOOT_CFG2[7]
EIM_EB1
Input
BOOT_CFG2[6]
EIM_DA0
Input
BOOT_CFG2[5]
EIM_DA1
Input
BOOT_CFG2[4]
EIM_DA2
Input
BOOT_CFG2[3]
EIM_DA3
Input
BOOT_CFG2[2]
EIM_DA4
Input
BOOT_CFG3[7]
EIM_DA5
Input
BOOT_CFG3[6]
EIM_DA6
Input
BOOT_CFG3[5]
EIM_DA7
Input
BOOT_CFG3[4]
EIM_DA8
Input
BOOT_CFG3[3]
EIM_DA9
Input
BOOT_CFG3[2]
EIM_DA10
Input
BOOT_CFG3[1]
5.2
Details
Boot Options, Pin value overrides fuse
settings for BT_FUSE_SEL = ‘0’.
BOOT_CFG1[6]/Test Mode Selection
Signal Configuration as Fuse Override
BOOT_CFG1[5]/Test Mode Selection Input at Power Up. These are special I/O
lines that control the boot up configuration
BOOT_CFG1[4]
during product development. In production,
the boot configuration can be controlled by
BOOT_CFG1[3]
fuses.
BOOT_CFG1[2]
Boot Devices Interfaces Allocation
Table 111 lists the interfaces that can be used by the boot process in accordance with the specific boot
mode configuration. The table also describes the interface’s specific modes and IOMUXC allocation,
which are configured during boot when appropriate.
Table 111. Interfaces Allocation During Boot
Interface
IP Instance
SPI
CSPI
SPI
SPI
Allocated Pads During Boot
Comment
EIM_A25, EIM_D21, EIM_D22, EIM_D28
Only SS1 is supported
ECSPI-1
EIM_D[19:16]
Only SS1 is supported
ECSPI-2
CSI_DAT[10:8], EIM_LBA
Only SS1 is supported
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
150
Freescale Semiconductor
Boot Mode Configuration
Table 111. Interfaces Allocation During Boot (continued)
Interface
IP Instance
EIM
EIM
NAND Flash
EXTMC
SD/MMC
Allocated Pads During Boot
Comment
EIM
• Lower 16 bit data bus A/D
multiplexed or upper 16 bit data bus
non multiplexed
• Only CS0 is supported.
NAND
• 8/16 bit
• NAND data can be muxed either over
EIM data or PATA data
• Only CS0 is supported
eSDHCv2-1
PATA_DATA[11:8], SD1_DATA[3:0], SD1_CMD,
SD1_CLK
1, 4 or 8 bit
SD/MMC
eSDHCv2-2
PATA_DATA[15:12], SD2_CLK, SD2_CMD,
SD2_DATA[3:0]
1, 4 or 8 bit
SD/MMC
eSDHCv3-3
PATA_RESET_B, PATA_IORDY, PATA_DA_0,
PATA_DATA[3:0], PATA_DATA[11:8]
1, 4 or 8 bit
SD/MMC
eSDHCv2-4
PATA_DA1, PATA_DA_2, PATA_DATA[7:4],
PATA_DATA[15:12]
1, 4 or 8 bit
I2C
I2C-1
EIM_D21, EIM_D28
—
I2C
I2C-2
EIM_D16, EIM_EB2
—
I2C
I2C-3
EIM_D[18:17]
—
PATA
PATA
PATA_DIOW, PATA_DMACK, PATA_DMARQ,
PATA_BUFFER_EN, PATA_INTRQ, PATA_DIOR,
PATA_RESET_B, PATA_IORDY, PATA_DA_[2:0],
PATA_CS_[1:0], PATA_DATA[15:0]
—
SATA
SATA_PHY
SATA_TXM, SATA_TXP, SATA_RXP, SATA_RXM,
SATA_REXT, SATA_REFCLKM, SATA_REFCLKP
—
UART
UARTv2-1
CSI0_DAT[11:10]
RXD/TXD only
UART
UARTv2-2
PATA_DMARQ, PATA_BUFFER_EN
RXD/TXD only
UART
UARTv2-3
EIM_D24, EIM_D25
RXD/TXD only
UART
UARTv2-4
CSI0_DAT[13:12]
RXD/TXD only
UART
UARTv2-5
CSI0_DAT[15:14]
RXD/TXD only
USB
USB-OTG
PHY
USB_H1_GPANAIO
USB_H1_RREFEXT
USB_H1_DP
USB_H1_DN
USB_H1_VBUS
5.3
—
Power setup during Boot
By default, VDD_DIG_PLL is driven from internal on-die 1.2 V linear regulator (LDO). In order to
achieve the standard operating mode (see VDD_DIG_PLL on Table 6), LDO output to VDD_DIG_PLL
should be configured by software by boot code after power-up to 1.3 V output. This is done by
programming the PLL1P2_VREG bits.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
151
Package Information and Contact Assignments
6
Package Information and Contact Assignments
This section includes the contact assignment information and mechanical package drawing.
6.1
19x19 mm Package Information
This section contains the outline drawing, signal assignment map, ground/power reference ID (by ball grid
location) for the 19 × 19 mm, 0.8 mm pitch package.
6.1.1
Case TEPBGA-2, 19 x 19 mm, 0.8 mm Pitch, 23 x 23 Ball Matrix
Figure 100 shows the top view of the 19×19 mm package, Figure 101 shows the bottom view and the ball
location (529 solder balls) of the 19×19 mm package, and Figure 102 shows the side view of the 19×19
mm package.
Figure 100. 19 x 19 mm Package Top View
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
152
Freescale Semiconductor
Package Information and Contact Assignments
Figure 101. 19 x 19 mm Package, 529 Solder Balls, Bottom View
Figure 102. 19 x 19 mm Package Side View
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
153
Package Information and Contact Assignments
The following notes apply to Figure 100, Figure 101, and Figure 102.
1. All dimensions are in millimeters.
2. Dimensions and tolerancing per ASME Y14.5M1–994.
6.1.2
19 x 19 mm Signal Assignments, Power Rails, and I/O
Table 112 shows the device connection list for ground, power, sense, and reference contact signals.
Table 113 displays an alpha-sorted list of the signal assignments including associated power supplies. The
table also includes out of reset pad state. Table 114 shows the package ball map.
6.1.2.1
19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments
Table 112 shows the device connection list for ground, power, sense, and reference contact signals
alpha-sorted by name.
Table 112. 19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments
Contact Name
Package Contact Assignment(s)
DDR_VREF
L17
GND
A1, A11, A13, A18, A2, A22, A23, AA11, AA15, AA20, AA21, AB1, AB18, AB2, AB22, AB23,
AC1, AC18, AC2, AC22, AC23, B1, B11, B13, B18, B23, C12, C20, C21, D19, E19, F19, F20,
F21, F22, G19, G7, H10, H12, H8, J11, J13, J15, J17, J20, J9, K10, K12, K14, K16, K21, K8,
L11, L13, L15, L7, L9, M10, M12, M14, M16, M8, N11, N13, N15, N9, P10, P12, P14, P16,
P21, P7, P8, R11, R13, R15, R17, R20, R9, T10, T14, T16, T8, U15, U19, V15, V18, V19,
V20, V21, V22, W19, Y14, Y15, Y19
NVCC_CKIH
G17
NVCC_CSI
R7
NVCC_EIM_MAIN
U10, U9
NVCC_EIM_SEC
U7
NVCC_EMI_DRAM
H18, K17, N17, P17, T18
NVCC_FEC
F11
NVCC_GPIO
F8
NVCC_JTAG
G9
NVCC_KEYPAD
F7
NVCC_LCD
J6, J7
NVCC_LVDS
U13
NVCC_LVDS_BG
U14
NVCC_NANDF
T12
NVCC_PATA
N7
NVCC_RESET
H16
NVCC_SD1
H15
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
154
Freescale Semiconductor
Package Information and Contact Assignments
Table 112. 19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments (continued)
Contact Name
Package Contact Assignment(s)
NVCC_SD2
H14
NVCC_SRTC_POW
V11
NVCC_XTAL
V12
SVCC
B22
SVDDGP
B2
TVDAC_AHVDDRGB
U17, V16
TVDAC_DHVDD
U16
USB_H1_VDDA25
F13
USB_H1_VDDA33
G13
USB_OTG_VDDA25
F14
USB_OTG_VDDA33
G14
VCC
H13, J14, J16, K13, K15, L14, L16, M11, M13, M15, M9, N10, N12, N14, N16, N8, P11, P13,
P15, P9, R10, R12, R14, R16, R8, T11, T13, T15, T17, T7, T9, U18, U8
VDDA
G12, M17, M7, U12
VDDAL1
F9
VDD_ANA_PLL
G16
VDD_DIG_PLL
H17
VDD_FUSE
G15
VDDGP
G10, G11, G8, H11, H7, H9, J10, J12, J8, K11, K7, K9, L10, L12, L8
VDD_REG
G18
VP
A15, B15
VPH
A9, B9
Table 113 displays an alpha-sorted list of the signal assignments including power rails. The table also
includes out of reset pad state.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
155
Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O
Package
Contact
Contact Name
Assign
ment
Power Rail
I/O Buffer
Type
Alt.
Mode
Block Instance
Out of Reset Condition1
Block I/O
Direction
Config./
Value
BOOT_MODE C18
0
NVCC_RESET
LVIO
ALT0
SRC
src_BOOT_MOD
E[0]
Input
100 KΩ PD
BOOT_MODE B20
1
NVCC_RESET
LVIO
ALT0
SRC
src_BOOT_MOD
E[1]
Input
100 KΩ PD
CKIH1
B21
NVCC_CKIH
ANALOG
ALT0
CAMP1
camp1_CKIH
Input
Analog
CKIH2
D18
NVCC_CKIH
ANALOG
ALT0
CAMP2
camp2_CKIH
Input
Analog
CKIL
AB10
NVCC_SRTC_POW
ANALOG
—
SRCT
CKIL
—
—
CSI0_DAT10
R5
NVCC_CSI
UHVIO
ALT1
GPIO-5 gpio5_GPIO[28]
Input
100 KΩ PU
CSI0_DAT11
T2
NVCC_CSI
UHVIO
ALT1
GPIO-5 gpio5_GPIO[29]
Input
100 KΩ PU
CSI0_DAT12
T3
NVCC_CSI
UHVIO
ALT1
GPIO-5 gpio5_GPIO[30]
Input
360 KΩ PD
CSI0_DAT13
T6
NVCC_CSI
UHVIO
ALT1
GPIO-5 gpio5_GPIO[31]
Input
360 KΩ PD
CSI0_DAT14
U1
NVCC_CSI
UHVIO
ALT1
GPIO-6 gpio6_GPIO[0]
Input
360 KΩ PD
CSI0_DAT15
U2
NVCC_CSI
UHVIO
ALT1
GPIO-6 gpio6_GPIO[1]
Input
360 KΩ PD
CSI0_DAT16
T4
NVCC_CSI
UHVIO
ALT1
GPIO-6 gpio6_GPIO[2]
Input
360 KΩ PD
CSI0_DAT17
T5
NVCC_CSI
UHVIO
ALT1
GPIO-6 gpio6_GPIO[3]
Input
360 KΩ PD
CSI0_DAT18
U3
NVCC_CSI
UHVIO
ALT1
GPIO-6 gpio6_GPIO[4]
Input
360 KΩ PD
CSI0_DAT19
U4
NVCC_CSI
UHVIO
ALT1
GPIO-6 gpio6_GPIO[5]
Input
360 KΩ PD
CSI0_DAT4
R1
NVCC_CSI
UHVIO
ALT1
GPIO-5 gpio5_GPIO[22]
Input
100 KΩ PU
CSI0_DAT5
R2
NVCC_CSI
UHVIO
ALT1
GPIO-5 gpio5_GPIO[23]
Input
360 KΩ PD
CSI0_DAT6
R6
NVCC_CSI
UHVIO
ALT1
GPIO-5 gpio5_GPIO[24]
Input
100 KΩ PU
CSI0_DAT7
R3
NVCC_CSI
UHVIO
ALT1
GPIO-5 gpio5_GPIO[25]
Input
100 KΩ PU
CSI0_DAT8
T1
NVCC_CSI
UHVIO
ALT1
GPIO-5 gpio5_GPIO[26]
Input
100 KΩ PU
CSI0_DAT9
R4
NVCC_CSI
UHVIO
ALT1
GPIO-5 gpio5_GPIO[27]
Input
360 KΩ PD
CSI0_DATA_E P3
N
NVCC_CSI
UHVIO
ALT1
GPIO-5 gpio5_GPIO[20]
Input
100 KΩ PU
CSI0_MCLK
P2
NVCC_CSI
UHVIO
ALT1
GPIO-5 gpio5_GPIO[19]
Input
100 KΩ PU
CSI0_PIXCLK
P1
NVCC_CSI
UHVIO
ALT1
GPIO-5 gpio5_GPIO[18]
Input
100 KΩ PU
CSI0_VSYNC
P4
NVCC_CSI
UHVIO
ALT1
GPIO-5 gpio5_GPIO[21]
Input
100 KΩ PU
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
156
Freescale Semiconductor
Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Package
Contact
Contact Name
Assign
ment
Power Rail
I/O Buffer
Type
Alt.
Mode
Block Instance
Out of Reset Condition1
Block I/O
Direction
Config./
Value
DI0_DISP_CL
K
H4
NVCC_LCD
GPIO
ALT1
GPIO-4 gpio4_GPIO[16]
Input
100 KΩ PU
DI0_PIN15
E4
NVCC_LCD
GPIO
ALT1
GPIO-4 gpio4_GPIO[17]
Input
100 KΩ PU
DI0_PIN2
D3
NVCC_LCD
GPIO
ALT1
GPIO-4 gpio4_GPIO[18]
Input
100 KΩ PU
DI0_PIN3
C2
NVCC_LCD
GPIO
ALT1
GPIO-4 gpio4_GPIO[19]
Input
100 KΩ PU
DI0_PIN4
D2
NVCC_LCD
GPIO
ALT1
GPIO-4 gpio4_GPIO[20]
Input
100 KΩ PU
DISP0_DAT0
J5
NVCC_LCD
GPIO
ALT1
GPIO-4 gpio4_GPIO[21]
Input
100 KΩ PD
DISP0_DAT1
J4
NVCC_LCD
GPIO
ALT1
GPIO-4 gpio4_GPIO[22]
Input
100 KΩ PD
DISP0_DAT10 G3
NVCC_LCD
GPIO
ALT1
GPIO-4 gpio4_GPIO[31]
Input
100 KΩ PU
DISP0_DAT11 H5
NVCC_LCD
GPIO
ALT1
GPIO-5 gpio5_GPIO[5]
Input
100 KΩ PD
DISP0_DAT12 H1
NVCC_LCD
GPIO
ALT1
GPIO-5 gpio5_GPIO[6]
Input
100 KΩ PU
DISP0_DAT13 E1
NVCC_LCD
GPIO
ALT1
GPIO-5 gpio5_GPIO[7]
Input
100 KΩ PU
DISP0_DAT14 F2
NVCC_LCD
GPIO
ALT1
GPIO-5 gpio5_GPIO[8]
Input
100 KΩ PU
DISP0_DAT15 F3
NVCC_LCD
GPIO
ALT1
GPIO-5 gpio5_GPIO[9]
Input
100 KΩ PU
DISP0_DAT16 D1
NVCC_LCD
GPIO
ALT1
GPIO-5 gpio5_GPIO[10]
Input
100 KΩ PU
DISP0_DAT17 F5
NVCC_LCD
GPIO
ALT1
GPIO-5 gpio5_GPIO[11]
Input
100 KΩ PU
DISP0_DAT18 G4
NVCC_LCD
GPIO
ALT1
GPIO-5 gpio5_GPIO[12]
Input
100 KΩ PU
DISP0_DAT19 G5
NVCC_LCD
GPIO
ALT1
GPIO-5 gpio5_GPIO[13]
Input
100 KΩ PU
DISP0_DAT2
H2
NVCC_LCD
GPIO
ALT1
GPIO-4 gpio4_GPIO[23]
Input
100 KΩ PD
DISP0_DAT20 F4
NVCC_LCD
GPIO
ALT1
GPIO-5 gpio5_GPIO[14]
Input
100 KΩ PU
DISP0_DAT21 C1
NVCC_LCD
GPIO
ALT1
GPIO-5 gpio5_GPIO[15]
Input
100 KΩ PU
DISP0_DAT22 E3
NVCC_LCD
GPIO
ALT1
GPIO-5 gpio5_GPIO[16]
Input
100 KΩ PU
DISP0_DAT23 C3
NVCC_LCD
GPIO
ALT1
GPIO-5 gpio5_GPIO[17]
Input
100 KΩ PU
DISP0_DAT3
F1
NVCC_LCD
GPIO
ALT1
GPIO-4 gpio4_GPIO[24]
Input
100 KΩ PD
DISP0_DAT4
G2
NVCC_LCD
GPIO
ALT1
GPIO-4 gpio4_GPIO[25]
Input
100 KΩ PD
DISP0_DAT5
H3
NVCC_LCD
GPIO
ALT1
GPIO-4 gpio4_GPIO[26]
Input
100 KΩ PD
DISP0_DAT6
G1
NVCC_LCD
GPIO
ALT1
GPIO-4 gpio4_GPIO[27]
Input
100 KΩ PD
DISP0_DAT7
H6
NVCC_LCD
GPIO
ALT1
GPIO-4 gpio4_GPIO[28]
Input
100 KΩ PD
DISP0_DAT8
G6
NVCC_LCD
GPIO
ALT1
GPIO-4 gpio4_GPIO[29]
Input
100 KΩ PU
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
157
Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Package
Contact
Contact Name
Assign
ment
Power Rail
I/O Buffer
Type
Block Instance
Out of Reset Condition1
Alt.
Mode
Block I/O
Direction
Config./
Value
DISP0_DAT9
E2
NVCC_LCD
GPIO
ALT1
GPIO-4 gpio4_GPIO[30]
Input
100 KΩ PU
DRAM_A0
M19
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_A[0]
Output
Low
DRAM_A1
L21
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_A[1]
Output
Low
DRAM_A10
K19
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_A[10
]
Output
Low
DRAM_A11
L22
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_A[11
]
Output
Low
DRAM_A12
L20
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_A[12
]
Output
Low
DRAM_A13
L23
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_A[13
]
Output
Low
DRAM_A14
N18
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_A[14
]
Output
Low
DRAM_A15
M18
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_A[15
]
Output
Low
DRAM_A2
M20
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_A[2]
Output
Low
DRAM_A3
N20
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_A[3]
Output
Low
DRAM_A4
K20
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_A[4]
Output
Low
DRAM_A5
N21
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_A[5]
Output
Low
DRAM_A6
M22
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_A[6]
Output
Low
DRAM_A7
N22
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_A[7]
Output
Low
DRAM_A8
N23
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_A[8]
Output
Low
DRAM_A9
M21
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_A[9]
Output
Low
DRAM_CALIB M23
RATION
NVCC_EMI_DRAM
special
—
—
Input
—
DRAM_CAS
L18
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_CAS
Output
High
DRAM_CS0
K18
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_CS[
0]
Output
High
DRAM_CS1
P19
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_CS[
1]
Output
High
(used in DRAM
driver calibration.
See Special
Signal
Considerations
{add xref} above)
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
158
Freescale Semiconductor
Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Package
Contact
Contact Name
Assign
ment
Power Rail
I/O Buffer
Type
Alt.
Mode
Block Instance
Out of Reset Condition1
Block I/O
Direction
Config./
Value
DRAM_D0
H20
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[0]
Output
High
DRAM_D1
G21
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[1]
Output
High
DRAM_D10
E22
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[10
]
Output
High
DRAM_D11
D20
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[11
]
Output
High
DRAM_D12
E23
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[12
]
Output
High
DRAM_D13
C23
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[13
]
Output
High
DRAM_D14
F23
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[14
]
Output
High
DRAM_D15
C22
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[15
]
Output
High
DRAM_D16
U20
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[16
]
Output
High
DRAM_D17
T21
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[17
]
Output
High
DRAM_D18
U21
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[18
]
Output
High
DRAM_D19
R21
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[19
]
Output
High
DRAM_D2
J21
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[2]
Output
High
DRAM_D20
U23
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[20
]
Output
High
DRAM_D21
R22
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[21
]
Output
High
DRAM_D22
U22
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[22
]
Output
High
DRAM_D23
R23
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[23
]
Output
High
DRAM_D24
Y20
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[24
]
Output
High
DRAM_D25
W21
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[25
]
Output
High
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
159
Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Package
Contact
Contact Name
Assign
ment
Power Rail
I/O Buffer
Type
Alt.
Mode
Block Instance
Out of Reset Condition1
Block I/O
Direction
Config./
Value
DRAM_D26
Y21
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[26
]
Output
High
DRAM_D27
W22
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[27
]
Output
High
DRAM_D28
AA23
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[28
]
Output
High
DRAM_D29
V23
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[29
]
Output
High
DRAM_D3
G20
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[3]
Output
High
DRAM_D30
AA22
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[30
]
Output
High
DRAM_D31
W23
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[31
]
Output
High
DRAM_D4
J23
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[4]
Output
High
DRAM_D5
G23
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[5]
Output
High
DRAM_D6
J22
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[6]
Output
High
DRAM_D7
G22
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[7]
Output
High
DRAM_D8
E21
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[8]
Output
High
DRAM_D9
D21
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_D[9]
Output
High
DRAM_DQM0 H21
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_DQ
M[0]
Output
Low
DRAM_DQM1 E20
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_DQ
M[1]
Output
Low
DRAM_DQM2 T20
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_DQ
M[2]
Output
Low
DRAM_DQM3 W20
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_DQ
M[3]
Output
Low
DRAM_RAS
J19
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_RAS
Output
High
DRAM_RESE
T
P18
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_RES
ET
Output
Low
DRAM_SDBA
0
R19
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_SDB
A[0]
Output
Low
DRAM_SDBA
1
P20
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_SDB
A[1]
Output
Low
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
160
Freescale Semiconductor
Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Package
Contact
Contact Name
Assign
ment
Power Rail
I/O Buffer
Type
Alt.
Mode
Block Instance
Out of Reset Condition1
Block I/O
Direction
Config./
Value
DRAM_SDBA
2
N19
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_SDB
A[2]
Output
Low
DRAM_SDCK
E0
H19
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_SDC
KE[0]
Output
Low
DRAM_SDCK
E1
T19
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_SDC
KE[1]
Output
Low
DRAM_SDCL
K_0
K23
NVCC_EMI_DRAM
DDR3CLK
ALT0
EXTMC emi_DRAM_SDC
LK0
Output
Floating
DRAM_SDCL
K_0_B
K22
NVCC_EMI_DRAM
DDR3CLK
ALT0
EXTMC emi_DRAM_SDC
LK0_B
Output
Floating
DRAM_SDCL
K_1
P22
NVCC_EMI_DRAM
DDR3CLK
ALT0
EXTMC emi_DRAM_SDC
LK1
Output
Floating
DRAM_SDCL
K_1_B
P23
NVCC_EMI_DRAM
DDR3CLK
ALT0
EXTMC emi_DRAM_SDC
LK1_B
Output
Floating
DRAM_SDOD J18
T0
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_ODT
[0]
Output
Low
DRAM_SDOD R18
T1
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_ODT
[1]
Output
Low
DRAM_SDQS
0
H23
NVCC_EMI_DRAM
DDR3CLK
ALT0
EXTMC emi_DRAM_SDQ
S[0]
Input
Low
DRAM_SDQS
0_B
H22
NVCC_EMI_DRAM
DDR3CLK
ALT0
EXTMC emi_DRAM_SDQ
S_B[0]
Input
High
DRAM_SDQS
1
D23
NVCC_EMI_DRAM
DDR3CLK
ALT0
EXTMC emi_DRAM_SDQ
S[1]
Input
Low
DRAM_SDQS
1_B
D22
NVCC_EMI_DRAM
DDR3CLK
ALT0
EXTMC emi_DRAM_SDQ
S_B[1]
Input
High
DRAM_SDQS
2
T22
NVCC_EMI_DRAM
DDR3CLK
ALT0
EXTMC emi_DRAM_SDQ
S[2]
Input
Low
DRAM_SDQS
2_B
T23
NVCC_EMI_DRAM
DDR3CLK
ALT0
EXTMC emi_DRAM_SDQ
S_B[2]
Input
High
DRAM_SDQS
3
Y22
NVCC_EMI_DRAM
DDR3CLK
ALT0
EXTMC emi_DRAM_SDQ
S[3]
Input
Low
DRAM_SDQS
3_B
Y23
NVCC_EMI_DRAM
DDR3CLK
ALT0
EXTMC emi_DRAM_SDQ
S_B[3]
Input
High
DRAM_SDWE L19
NVCC_EMI_DRAM
DDR3
ALT0
EXTMC emi_DRAM_SD
WE
Output
High
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
161
Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Package
Contact
Contact Name
Assign
ment
Power Rail
I/O Buffer
Type
Alt.
Mode
Block Instance
Out of Reset Condition1
Block I/O
Direction
Config./
Value
ECKIL {no block
I/O by this name
in RM}
—
—
ECKIL
AC10
NVCC_SRTC_POW
ANALOG
—
SRTC
EIM_A16
AA5
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_EIM_A[16]
Output2
—
EIM_A17
V7
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_EIM_A[17]
Output2
—
EIM_A18
AB3
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_EIM_A[18]
Output2
—
EIM_A19
W7
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_EIM_A[19]
Output2
—
EIM_A20
Y6
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_EIM_A[20]
Output2
—
EIM_A21
AA4
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_EIM_A[21]
Output2
—
EIM_A22
AA3
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_EIM_A[22]
Output2
—
EIM_A23
V6
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_EIM_A[23]
Output
—
EIM_A24
Y5
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_EIM_A[24]
Output
—
EIM_A25
W6
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_EIM_A[25]
Output
—
EIM_BCLK
W11
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_EIM_BCLK
Output
—
EIM_CS0
W8
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_EIM_CS[0]
Output
—
EIM_CS1
Y7
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_EIM_CS[1]
Output
—
EIM_D16
U6
NVCC_EIM_SEC
UHVIO
ALT1
GPIO-3 gpio3_GPIO[16]
Input
100 KΩ PU
EIM_D17
U5
NVCC_EIM_SEC
UHVIO
ALT1
GPIO-3 gpio3_GPIO[17]
Input
100 KΩ PU
EIM_D18
V1
NVCC_EIM_SEC
UHVIO
ALT1
GPIO-3 gpio3_GPIO[18]
Input
100 KΩ PU
EIM_D19
V2
NVCC_EIM_SEC
UHVIO
ALT1
GPIO-3 gpio3_GPIO[19]
Input
100 KΩ PU
EIM_D20
W1
NVCC_EIM_SEC
UHVIO
ALT1
GPIO-3 gpio3_GPIO[20]
Input
100 KΩ PU
EIM_D21
V3
NVCC_EIM_SEC
UHVIO
ALT1
GPIO-3 gpio3_GPIO[21]
Input
100 KΩ PU
EIM_D22
W2
NVCC_EIM_SEC
UHVIO
ALT1
GPIO-3 gpio3_GPIO[22]
Input
360 KΩ PD
EIM_D23
Y1
NVCC_EIM_SEC
UHVIO
ALT1
GPIO-3 gpio3_GPIO[23]
Input
100 KΩ PU
EIM_D24
Y2
NVCC_EIM_SEC
UHVIO
ALT1
GPIO-3 gpio3_GPIO[24]
Input
100 KΩ PU
EIM_D25
W3
NVCC_EIM_SEC
UHVIO
ALT1
GPIO-3 gpio3_GPIO[25]
Input
100 KΩ PU
EIM_D26
V5
NVCC_EIM_SEC
UHVIO
ALT1
GPIO-3 gpio3_GPIO[26]
Input
100 KΩ PU
EIM_D27
V4
NVCC_EIM_SEC
UHVIO
ALT1
GPIO-3 gpio3_GPIO[27]
Input
100 KΩ PU
EIM_D28
AA1
NVCC_EIM_SEC
UHVIO
ALT1
GPIO-3 gpio3_GPIO[28]
Input
100 KΩ PU
EIM_D29
AA2
NVCC_EIM_SEC
UHVIO
ALT1
GPIO-3 gpio3_GPIO[29]
Input
100 KΩ PU
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
162
Freescale Semiconductor
Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Package
Contact
Contact Name
Assign
ment
Power Rail
I/O Buffer
Type
Alt.
Mode
Block Instance
Out of Reset Condition1
Block I/O
Direction
Config./
Value
EIM_D30
W4
NVCC_EIM_SEC
UHVIO
ALT1
GPIO-3 gpio3_GPIO[30]
Input
100 KΩ PU
EIM_D31
W5
NVCC_EIM_SEC
UHVIO
ALT1
GPIO-3 gpio3_GPIO[31]
Input
360 KΩ PD
EIM_DA0
Y8
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_NAND_EIM
_DA[0]
Input2
100 KΩ PU
EIM_DA1
AC4
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_NAND_EIM
_DA[1]
Input2
100 KΩ PU
EIM_DA10
AB7
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_NAND_EIM
_DA[10]
Input2
100 KΩ PU
EIM_DA11
AC6
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_NAND_EIM
_DA[11]
Input
100 KΩ PU
EIM_DA12
V10
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_NAND_EIM
_DA[12]
Input
100 KΩ PU
EIM_DA13
AC7
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_NAND_EIM
_DA[13]
Input
100 KΩ PU
EIM_DA14
Y10
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_NAND_EIM
_DA[14]
Input
100 KΩ PU
EIM_DA15
AA9
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_NAND_EIM
_DA[15]
Input
100 KΩ PU
EIM_DA2
AA7
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_NAND_EIM
_DA[2]
Input2
100 KΩ PU
EIM_DA3
W9
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_NAND_EIM
_DA[3]
Input2
100 KΩ PU
EIM_DA4
AB6
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_NAND_EIM
_DA[4]
Input2
100 KΩ PU
EIM_DA5
V9
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_NAND_EIM
_DA[5]
Input2
100 KΩ PU
EIM_DA6
Y9
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_NAND_EIM
_DA[6]
Input2
100 KΩ PU
EIM_DA7
AC5
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_NAND_EIM
_DA[7]
Input2
100 KΩ PU
EIM_DA8
AA8
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_NAND_EIM
_DA[8]
Input2
100 KΩ PU
EIM_DA9
W10
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_NAND_EIM
_DA[9]
Input2
100 KΩ PU
EIM_EB0
AC3
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_EIM_EB[0]
Output2
—
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
163
Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Package
Contact
Contact Name
Assign
ment
Power Rail
I/O Buffer
Type
Block Instance
Out of Reset Condition1
Alt.
Mode
Block I/O
Direction
Config./
Value
EIM_EB1
AB5
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_EIM_EB[1]
Output2
—
EIM_EB2
Y3
NVCC_EIM_MAIN
UHVIO
ALT1
GPIO-2 gpio2_GPIO[30]
Input
100 KΩ PU
EIM_EB3
Y4
NVCC_EIM_MAIN
UHVIO
ALT1
GPIO-2 gpio2_GPIO[31]
Input
100 KΩ PU
2
—
EIM_LBA
AA6
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_EIM_LBA
Output
EIM_OE
V8
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_EIM_OE
Output
—
EIM_RW
AB4
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_EIM_RW
Output
—
EIM_WAIT
AB9
NVCC_EIM_MAIN
UHVIO
ALT0
EXTMC emi_EIM_WAIT
Output
—
EXTAL
AB11
NVCC_XTAL
ANALOG
—
EXTAL
OSC
EXTAL
—
—
FASTR_ANA
E18
NVCC_CKIH
ANALOG
—
—
(reserved, tie to
ground)
—
—
FASTR_DIG
E17
NVCC_CKIH
ANALOG
—
—
(reserved, tie to
ground)
—
—
FEC_CRS_DV D11
NVCC_FEC
UHVIO
ALT1
GPIO-1 gpio1_GPIO[25]
Input
100 KΩ PU
FEC_MDC
E10
NVCC_FEC
UHVIO
ALT1
GPIO-1 gpio1_GPIO[31]
Input
100 KΩ PU
FEC_MDIO
D12
NVCC_FEC
UHVIO
ALT1
GPIO-1 gpio1_GPIO[22]
Input
100 KΩ PU
FEC_REF_CL E12
K
NVCC_FEC
UHVIO
ALT1
GPIO-1 gpio1_GPIO[23]
Input
100 KΩ PU
FEC_RX_ER
F12
NVCC_FEC
UHVIO
ALT1
GPIO-1 gpio1_GPIO[24]
Input
100 KΩ PU
FEC_RXD0
C11
NVCC_FEC
UHVIO
ALT1
GPIO-1 gpio1_GPIO[27]
Input
100 KΩ PU
FEC_RXD1
E11
NVCC_FEC
UHVIO
ALT1
GPIO-1 gpio1_GPIO[26]
Input
100 KΩ PU
FEC_TX_EN
C10
NVCC_FEC
UHVIO
ALT1
GPIO-1 gpio1_GPIO[28]
Input
360 KΩ PD
FEC_TXD0
F10
NVCC_FEC
UHVIO
ALT1
GPIO-1 gpio1_GPIO[30]
Input
100 KΩ PU
FEC_TXD1
D10
NVCC_FEC
UHVIO
ALT1
GPIO-1 gpio1_GPIO[29]
Input
100 KΩ PU
GPIO_0
C8
NVCC_GPIO
UHVIO
ALT1
GPIO-1 gpio1_GPIO[0]
Input
360 KΩ PD
GPIO_1
B7
NVCC_GPIO
UHVIO
ALT1
GPIO-1 gpio1_GPIO[1]
Input
360 KΩ PD
GPIO_10
W16
TVDAC_AHVDDRG
B
GPIO
ALT0
GPIO-4 gpio4_GPIO[0]
Input
100 KΩ PU
GPIO_11
V17
TVDAC_AHVDDRG
B
GPIO
ALT0
GPIO-4 gpio4_GPIO[1]
Input
100 KΩ PU
GPIO_12
W17
TVDAC_AHVDDRG
B
GPIO
ALT0
GPIO-4 gpio4_GPIO[2]
Input
100 KΩ PU
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
164
Freescale Semiconductor
Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Package
Contact
Contact Name
Assign
ment
Power Rail
I/O Buffer
Type
Alt.
Mode
Block Instance
Out of Reset Condition1
Block I/O
Direction
Config./
Value
GPIO_13
AA18
TVDAC_AHVDDRG
B
GPIO
ALT0
GPIO-4 gpio4_GPIO[3]
Input
100 KΩ PU
GPIO_14
W18
TVDAC_AHVDDRG
B
GPIO
ALT0
GPIO-4 gpio4_GPIO[4]
Input
100 KΩ PU
GPIO_16
C6
NVCC_GPIO
UHVIO
ALT1
GPIO-7 gpio7_GPIO[11]
Input
360 KΩ PD
GPIO_17
A3
NVCC_GPIO
UHVIO
ALT1
GPIO-7 gpio7_GPIO[12]
Input
360 KΩ PD
GPIO_18
D7
NVCC_GPIO
UHVIO
ALT1
GPIO-7 gpio7_GPIO[13]
Input
360 KΩ PD
GPIO_19
B4
NVCC_KEYPAD
UHVIO
ALT1
GPIO-4 gpio4_GPIO[5]
Input3
100 KΩ PU
GPIO_2
C7
NVCC_GPIO
UHVIO
ALT1
GPIO-1 gpio1_GPIO[2]
Input
360 KΩ PD
GPIO_3
A6
NVCC_GPIO
UHVIO
ALT1
GPIO-1 gpio1_GPIO[3]
Input
360 KΩ PD
GPIO_4
D8
NVCC_GPIO
UHVIO
ALT1
GPIO-1 gpio1_GPIO[4]
Input
100 KΩ PU
GPIO_5
A5
NVCC_GPIO
UHVIO
ALT1
GPIO-1 gpio1_GPIO[5]
Input
360 KΩ PD
GPIO_6
B6
NVCC_GPIO
UHVIO
ALT1
GPIO-1 gpio1_GPIO[6]
Input
360 KΩ PD
GPIO_7
A4
NVCC_GPIO
UHVIO
ALT1
GPIO-1 gpio1_GPIO[7]
Input
360 KΩ PD
GPIO_8
B5
NVCC_GPIO
UHVIO
ALT1
GPIO-1 gpio1_GPIO[8]
Input
360 KΩ PD
GPIO_9
E8
NVCC_GPIO
UHVIO
ALT1
GPIO-1 gpio1_GPIO[9]
Input
100 KΩ PU
JTAG_MOD
C9
NVCC_JTAG
GPIO
ALT0
SJC
sjc_MOD
Input
100 KΩ PU
JTAG_TCK
D9
NVCC_JTAG
GPIO
ALT0
SJC
sjc_TCK
Input
100 KΩ PD
JTAG_TDI
B8
NVCC_JTAG
GPIO
ALT0
SJC
sjc_TDI
Input
47 KΩ PU
JTAG_TDO
A7
NVCC_JTAG
GPIO
ALT0
SJC
sjc_TDO
Input
Keeper
JTAG_TMS
A8
NVCC_JTAG
GPIO
ALT0
SJC
sjc_TMS
Input
47 KΩ PU
JTAG_TRSTB
E9
NVCC_JTAG
GPIO
ALT0
SJC
sjc_TRSTB
Input
47 KΩ PU
KEY_COL0
C5
NVCC_KEYPAD
UHVIO
ALT1
GPIO-4 gpio4_GPIO[6]
Input4
100 KΩ PU
KEY_COL1
E7
NVCC_KEYPAD
UHVIO
ALT1
GPIO-4 gpio4_GPIO[8]
Input
100 KΩ PU
KEY_COL2
C4
NVCC_KEYPAD
UHVIO
ALT1
GPIO-4 gpio4_GPIO[10]
Input
100 KΩ PU
KEY_COL3
F6
NVCC_KEYPAD
UHVIO
ALT1
GPIO-4 gpio4_GPIO[12]
Input
100 KΩ PU
KEY_COL4
E5
NVCC_KEYPAD
UHVIO
ALT1
GPIO-4 gpio4_GPIO[14]
Input
100 KΩ PU
KEY_ROW0
B3
NVCC_KEYPAD
UHVIO
ALT1
GPIO-4 gpio4_GPIO[7]
Input
360 KΩ PD
KEY_ROW1
D6
NVCC_KEYPAD
UHVIO
ALT1
GPIO-4 gpio4_GPIO[9]
Input
100 KΩ PU
KEY_ROW2
D5
NVCC_KEYPAD
UHVIO
ALT1
GPIO-4 gpio4_GPIO[11]
Input
100 KΩ PU
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
165
Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Package
Contact
Contact Name
Assign
ment
Power Rail
I/O Buffer
Type
Alt.
Mode
Block Instance
Out of Reset Condition1
Block I/O
Direction
Config./
Value
KEY_ROW3
D4
NVCC_KEYPAD
UHVIO
ALT1
GPIO-4 gpio4_GPIO[13]
Input
100 KΩ PU
KEY_ROW4
E6
NVCC_KEYPAD
UHVIO
ALT1
GPIO-4 gpio4_GPIO[15]
Input
360 KΩ PD
LVDS_BG_RE AA14
S
NVCC_LVDS_BG
ANALOG
—
LDB
—
—
LVDS0_CLK_
N
AB16
NVCC_LVDS
LVDS
ALT0
GPIO-7 gpio7_GPI[25]
Input
Floating
LVDS0_CLK_
P
AC16
NVCC_LVDS
LVDS
ALT0
GPIO-7 gpio7_GPI[24]
Input
Floating
LVDS0_TX0_
N
Y17
NVCC_LVDS
LVDS
ALT0
GPIO-7 gpio7_GPI[31]
Input
Floating
LVDS0_TX0_P AA17
NVCC_LVDS
LVDS
ALT0
GPIO-7 gpio7_GPI[30]
Input
Floating
LVDS0_TX1_
N
AB17
NVCC_LVDS
LVDS
ALT0
GPIO-7 gpio7_GPI[29]
Input
Floating
LVDS0_TX1_P AC17
NVCC_LVDS
LVDS
ALT0
GPIO-7 gpio7_GPI[28]
Input
Floating
LVDS0_TX2_
N
NVCC_LVDS
LVDS
ALT0
GPIO-7 gpio7_GPI[27]
Input
Floating
LVDS0_TX2_P AA16
NVCC_LVDS
LVDS
ALT0
GPIO-7 gpio7_GPI[26]
Input
Floating
LVDS0_TX3_
N
AB15
NVCC_LVDS
LVDS
ALT0
GPIO-7 gpio7_GPI[23]
Input
Floating
LVDS0_TX3_P AC15
NVCC_LVDS
LVDS
ALT0
GPIO-7 gpio7_GPI[22]
Input
Floating
LVDS1_CLK_
N
AA13
NVCC_LVDS
LVDS
ALT0
GPIO-6 gpio6_GPI[27]
Input
Floating
LVDS1_CLK_
P
Y13
NVCC_LVDS
LVDS
ALT0
GPIO-6 gpio6_GPI[26]
Input
Floating
LVDS1_TX0_
N
AC14
NVCC_LVDS
LVDS
ALT0
GPIO-6 gpio6_GPI[31]
Input
Floating
LVDS1_TX0_P AB14
NVCC_LVDS
LVDS
ALT0
GPIO-6 gpio6_GPI[30]
Input
Floating
LVDS1_TX1_
N
AC13
NVCC_LVDS
LVDS
ALT0
GPIO-6 gpio6_GPI[29]
Input
Floating
LVDS1_TX1_P AB13
NVCC_LVDS
LVDS
ALT0
GPIO-6 gpio6_GPI[28]
Input
Floating
LVDS1_TX2_
N
AC12
NVCC_LVDS
LVDS
ALT0
GPIO-6 gpio6_GPI[25]
Input
Floating
LVDS1_TX2_P AB12
NVCC_LVDS
LVDS
ALT0
GPIO-6 gpio6_GPI[24]
Input
Floating
Y16
LVDS_BG_RES
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
166
Freescale Semiconductor
Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Package
Contact
Contact Name
Assign
ment
LVDS1_TX3_
N
AA12
Power Rail
I/O Buffer
Type
Alt.
Mode
Block Instance
Out of Reset Condition1
Block I/O
Direction
Config./
Value
NVCC_LVDS
LVDS
ALT0
GPIO-6 gpio6_GPI[23]
Input
Floating
LVDS1_TX3_P Y12
NVCC_LVDS
LVDS
ALT0
GPIO-6 gpio6_GPI[22]
Input
Floating
NANDF_ALE
Y11
NVCC_NANDF
UHVIO
ALT1
GPIO-6 gpio6_GPIO[8]
Input
100 KΩ PU
NANDF_CLE
AA10
NVCC_NANDF
UHVIO
ALT1
GPIO-6 gpio6_GPIO[7]
Input
100 KΩ PU
NANDF_CS0
W12
NVCC_NANDF
UHVIO
ALT1
GPIO-6 gpio6_GPIO[11]
Input
100 KΩ PU
NANDF_CS1
V13
NVCC_NANDF
UHVIO
ALT1
GPIO-6 gpio6_GPIO[14]
Input
100 KΩ PU
NANDF_CS2
V14
NVCC_NANDF
UHVIO
ALT1
GPIO-6 gpio6_GPIO[15]
Input
100 KΩ PU
NANDF_CS3
W13
NVCC_NANDF
UHVIO
ALT1
GPIO-6 gpio6_GPIO[16]
Input
100 KΩ PU
NANDF_RB0
U11
NVCC_NANDF
UHVIO
ALT1
GPIO-6 gpio6_GPIO[10]
Input
100 KΩ PU
NANDF_RE_B AC8
NVCC_EIM_MAIN
UHVIO
ALT1
GPIO-6 gpio6_GPIO[13]
Input
100 KΩ PU
NANDF_WE_
B
AB8
NVCC_EIM_MAIN
UHVIO
ALT1
GPIO-6 gpio6_GPIO[12]
Input
100 KΩ PU
NANDF_WP_
B
AC9
NVCC_NANDF
UHVIO
ALT1
GPIO-6 gpio6_GPIO[9]
Input
100 KΩ PU
PATA_BUFFE
R_EN
K4
NVCC_PATA
UHVIO
ALT1
GPIO-7 gpio7_GPIO[1]
Input
100 KΩ PU
PATA_CS_0
L5
NVCC_PATA
UHVIO
ALT1
GPIO-7 gpio7_GPIO[9]
Input
100 KΩ PU
PATA_CS_1
L2
NVCC_PATA
UHVIO
ALT1
GPIO-7 gpio7_GPIO[10]
Input
100 KΩ PU
PATA_DA_0
K6
NVCC_PATA
UHVIO
ALT1
GPIO-7 gpio7_GPIO[6]
Input
100 KΩ PU
PATA_DA_1
L3
NVCC_PATA
UHVIO
ALT1
GPIO-7 gpio7_GPIO[7]
Input
100 KΩ PU
PATA_DA_2
L4
NVCC_PATA
UHVIO
ALT1
GPIO-7 gpio7_GPIO[8]
Input
100 KΩ PU
PATA_DATA0
L1
NVCC_PATA
UHVIO
ALT1
GPIO-2 gpio2_GPIO[0]
Input
100 KΩ PU
PATA_DATA1
M1
NVCC_PATA
UHVIO
ALT1
GPIO-2 gpio2_GPIO[1]
Input
100 KΩ PU
PATA_DATA10
N4
NVCC_PATA
UHVIO
ALT1
GPIO-2 gpio2_GPIO[10]
Input
100 KΩ PU
PATA_DATA11
M6
NVCC_PATA
UHVIO
ALT1
GPIO-2 gpio2_GPIO[11]
Input
100 KΩ PU
PATA_DATA12
N5
NVCC_PATA
UHVIO
ALT1
GPIO-2 gpio2_GPIO[12]
Input
100 KΩ PU
PATA_DATA13
N6
NVCC_PATA
UHVIO
ALT1
GPIO-2 gpio2_GPIO[13]
Input
100 KΩ PU
PATA_DATA14
P6
NVCC_PATA
UHVIO
ALT1
GPIO-2 gpio2_GPIO[14]
Input
100 KΩ PU
PATA_DATA15
P5
NVCC_PATA
UHVIO
ALT1
GPIO-2 gpio2_GPIO[15]
Input
100 KΩ PU
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
167
Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Package
Contact
Contact Name
Assign
ment
Power Rail
I/O Buffer
Type
Alt.
Mode
Block Instance
Out of Reset Condition1
Block I/O
Direction
Config./
Value
PATA_DATA2
L6
NVCC_PATA
UHVIO
ALT1
GPIO-2 gpio2_GPIO[2]
Input
100 KΩ PU
PATA_DATA3
M2
NVCC_PATA
UHVIO
ALT1
GPIO-2 gpio2_GPIO[3]
Input
100 KΩ PU
PATA_DATA4
M3
NVCC_PATA
UHVIO
ALT1
GPIO-2 gpio2_GPIO[4]
Input
100 KΩ PU
PATA_DATA5
M4
NVCC_PATA
UHVIO
ALT1
GPIO-2 gpio2_GPIO[5]
Input
100 KΩ PU
PATA_DATA6
N1
NVCC_PATA
UHVIO
ALT1
GPIO-2 gpio2_GPIO[6]
Input
100 KΩ PU
PATA_DATA7
M5
NVCC_PATA
UHVIO
ALT1
GPIO-2 gpio2_GPIO[7]
Input
100 KΩ PU
PATA_DATA8
N2
NVCC_PATA
UHVIO
ALT1
GPIO-2 gpio2_GPIO[8]
Input
100 KΩ PU
PATA_DATA9
N3
NVCC_PATA
UHVIO
ALT1
GPIO-2 gpio2_GPIO[9]
Input
100 KΩ PU
PATA_DIOR
K3
NVCC_PATA
UHVIO
ALT1
GPIO-7 gpio7_GPIO[3]
Input
100 KΩ PU
PATA_DIOW
J3
NVCC_PATA
UHVIO
ALT1
GPIO-6 gpio6_GPIO[17]
Input
100 KΩ PU
PATA_DMACK J2
NVCC_PATA
UHVIO
ALT1
GPIO-6 gpio6_GPIO[18]
Input
100 KΩ PU
PATA_DMARQ J1
NVCC_PATA
UHVIO
ALT1
GPIO-7 gpio7_GPIO[0]
Input
100 KΩ PU
PATA_INTRQ
K5
NVCC_PATA
UHVIO
ALT1
GPIO-7 gpio7_GPIO[2]
Input
100 KΩ PU
PATA_IORDY
K1
NVCC_PATA
UHVIO
ALT1
GPIO-7 gpio7_GPIO[5]
Input
100 KΩ PU
PATA_RESET
_B
K2
NVCC_PATA
UHVIO
ALT1
GPIO-7 gpio7_GPIO[4]
Input
100 KΩ PU
PMIC_ON_RE W14
Q
NVCC_SRTC_POW
GPIO
ALT0
SRTC
srtc_SRTCALAR
M
Output
—
PMIC_STBY_
REQ
W15
NVCC_SRTC_POW
GPIO
ALT0
CCM
ccm_PMIC_VST
BY_REQ
Output
—
POR_B
C19
NVCC_RESET
LVIO
ALT0
SRC
src_POR_B
Input
100 KΩ PU
RESET_IN_B
A21
NVCC_RESET
LVIO
ALT0
SRC
src_RESET_B
Input
100 KΩ PU
SATA_REFCL
KM
A14
VPH
ANALOG
—
SATA
SATA_REFCLKM
—
—
SATA_REFCL
KP
B14
VPH
ANALOG
—
SATA
SATA_REFCLKP
—
—
SATA_REXT
C13
VPH
ANALOG
—
SATA
SATA_REXT
—
—
SATA_RXM
A12
VPH
ANALOG
—
SATA
SATA_RXM
—
—
SATA_RXP
B12
VPH
ANALOG
—
SATA
SATA_RXP
—
—
SATA_TXM
B10
VPH
ANALOG
—
SATA
SATA_TXM
—
—
SATA_TXP
A10
VPH
ANALOG
—
SATA
SATA_TXP
—
—
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
168
Freescale Semiconductor
Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Package
Contact
Contact Name
Assign
ment
Power Rail
I/O Buffer
Type
Alt.
Mode
Block Instance
Out of Reset Condition1
Block I/O
Direction
Config./
Value
SD1_CLK
E16
NVCC_SD1
UHVIO
ALT1
GPIO-1 gpio1_GPIO[20]
Input
100 KΩ PU
SD1_CMD
F18
NVCC_SD1
UHVIO
ALT1
GPIO-1 gpio1_GPIO[18]
Input
100 KΩ PU
SD1_DATA0
A20
NVCC_SD1
UHVIO
ALT1
GPIO-1 gpio1_GPIO[16]
Input
100 KΩ PU
SD1_DATA1
C17
NVCC_SD1
UHVIO
ALT1
GPIO-1 gpio1_GPIO[17]
Input
100 KΩ PU
SD1_DATA2
F17
NVCC_SD1
UHVIO
ALT1
GPIO-1 gpio1_GPIO[19]
Input
100 KΩ PU
SD1_DATA3
F16
NVCC_SD1
UHVIO
ALT1
GPIO-1 gpio1_GPIO[21]
Input
100 KΩ PU
SD2_CLK
E14
NVCC_SD2
UHVIO
ALT1
GPIO-1 gpio1_GPIO[10]
Input
100 KΩ PU
SD2_CMD
C15
NVCC_SD2
UHVIO
ALT1
GPIO-1 gpio1_GPIO[11]
Input
100 KΩ PU
SD2_DATA0
D13
NVCC_SD2
UHVIO
ALT1
GPIO-1 gpio1_GPIO[15]
Input
100 KΩ PU
SD2_DATA1
C14
NVCC_SD2
UHVIO
ALT1
GPIO-1 gpio1_GPIO[14]
Input
100 KΩ PU
SD2_DATA2
D14
NVCC_SD2
UHVIO
ALT1
GPIO-1 gpio1_GPIO[13]
Input
100 KΩ PU
SD2_DATA3
E13
NVCC_SD2
UHVIO
ALT1
GPIO-1 gpio1_GPIO[12]
Input
100 KΩ PU
TEST_MODE
D17
NVCC_RESET
LVIO
ALT0
tcu_TEST_MOD
E
Input
100 KΩ PD
TVCDC_IOB_
BACK
AB19
TVDAC_AHVDDRG
B
ANALOG
—
TVE
TVCDC_IOB_BA
CK
—
—
TVCDC_IOG_ AC20
BACK
TVDAC_AHVDDRG
B
ANALOG
—
TVE
TVCDC_IOG_BA
CK
—
—
TVCDC_IOR_
BACK
AB21
TVDAC_AHVDDRG
B
ANALOG
—
TVE
TVCDC_IOR_BA
CK
—
—
TVDAC_COM
P
AA19
TVDAC_AHVDDRG
B
ANALOG
—
TVE
TVDAC_COMP
—
—
TVDAC_IOB
AC19
TVDAC_AHVDDRG
B
ANALOG
—
TVE
TVDAC_IOB
—
—
TVDAC_IOG
AB20
TVDAC_AHVDDRG
B
ANALOG
—
TVE
TVDAC_IOG
—
—
TVDAC_IOR
AC21
TVDAC_AHVDDRG
B
ANALOG
—
TVE
TVDAC_IOR
—
—
TVDAC_VREF Y18
TVDAC_AHVDDRG
B
ANALOG
—
TVE
TVDAC_VREF
—
—
USB_H1_DN
USB_H1_VDDA25,
USB_H1_VDDA33
ANALOG50 —
USB
USB_H1_DN
—
—
B17
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
169
Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Out of Reset Condition1
Block Instance
Package
Contact
Contact Name
Assign
ment
Block I/O
A17
USB_H1_VDDA25,
USB_H1_VDDA33
ANALOG50 —
USB
USB_H1_DP
—
—
USB_H1_GPA A16
NAIO
USB_H1_VDDA25,
USB_H1_VDDA33
ANALOG25 —
USB
USB_H1_GPANA
IO
—
—
USB_H1_RRE B16
FEXT
USB_H1_VDDA25,
USB_H1_VDDA33
ANALOG25 —
USB
USB_H1_RREFE
XT
—
—
USB_H1_VBU D15
S
USB_H1_VDDA25,
USB_H1_VDDA33
ANALOG50 —
USB
USB_H1_VBUS
—
—
USB_OTG_D
N
A19
USB_OTG_VDDA25, ANALOG50 —
USB_OTG_VDDA33
USB
USB_OTG_DN
—
—
USB_OTG_DP B19
USB_OTG_VDDA25, ANALOG50 —
USB_OTG_VDDA33
USB
USB_OTG_DP
—
—
USB_OTG_G
PANAIO
F15
USB_OTG_VDDA25, ANALOG25 —
USB_OTG_VDDA33
USB
USB_OTG_GPA
NAIO
—
—
USB_OTG_ID
C16
USB_OTG_VDDA25, ANALOG25 —
USB_OTG_VDDA33
USB
USB_OTG_ID
—
—
USB_OTG_R
REFEXT
D16
USB_OTG_VDDA25, ANALOG25 —
USB_OTG_VDDA33
USB
USB_OTG_RRE
FEXT
—
—
USB_OTG_VB E15
US
USB_OTG_VDDA25, ANALOG50 —
USB_OTG_VDDA33
USB
USB_OTG_VBU
S
—
—
XTAL
NVCC_XTAL
XTALO
SC
XTAL
—
—
USB_H1_DP
AC11
Power Rail
I/O Buffer
Type
ANALOG
Alt.
Mode
—
Direction
Config./
Value
1
The state immediately after reset and before ROM firmware or software has executed.
During power-on reset, this port acts as input for fuse override. See Section 5.1, “Boot Mode Configuration Pins” for details.
For appropriate resistor values, see Chapter 1 of i.MX53 System Development User's Guide, document number MX53UG.
3 During power-on reset this port acts as output for diagnostic signal INT_BOOT
4 During power-on reset this port acts as output for diagnostic signal ANY_PU_RST
2
NOTE
KEY_COL0 and GPIO_19 act as output for diagnostic signals during
power-on reset.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
170
Freescale Semiconductor
Freescale Semiconductor
11
GND
GND
FEC_RXD0
FEC_CRS_DV
FEC_MDIO
SD2_DATA0
SD2_DATA2
USB_H1_VBUS
USB_OTG_RREFEXT
TEST_MODE
CKIH2
GND
DRAM_D11
DRAM_D9
DRAM_SDQS1_B
DRAM_SDQS1
FEC_RXD1
FEC_REF_CLK
SD2_DATA3
SD2_CLK
USB_OTG_VBUS
SD1_CLK
FASTR_DIG
FASTR_ANA
GND
DRAM_DQM1
DRAM_D8
DRAM_D10
DRAM_D12
11
12
13
14
15
16
17
18
19
20
21
22
23
D
10
SATA_TXP
SATA_TXM
FEC_TX_EN
FEC_TXD1
FEC_MDC
10
E
9
VPH
VPH
JTAG_MOD
JTAG_TCK
JTAG_TRSTB
9
C
DRAM_D13
DRAM_D15
GND
GND
POR_B
BOOT_MODE0
SD1_DATA1
USB_OTG_ID
SD2_CMD
SD2_DATA1
SATA_REXT
B
GND
SVCC
CKIH1
BOOT_MODE1
USB_OTG_DP
GND
USB_H1_DN
USB_H1_RREFEXT
VP
SATA_REFCLKP
GND
A
GND
GND
RESET_IN_B
SD1_DATA0
USB_OTG_DN
GND
USB_H1_DP
USB_H1_GPANAIO
VP
SATA_REFCLKM
GND
23
22
21
20
19
18
17
16
15
14
13
12
8
JTAG_TMS
JTAG_TDI
GPIO_0
GPIO_4
GPIO_9
8
SATA_RXM
7
JTAG_TDO
GPIO_1
GPIO_2
GPIO_18
KEY_COL1
7
SATA_RXP
6
GPIO_3
GPIO_6
GPIO_16
KEY_ROW1
KEY_ROW4
6
GND
5
GPIO_5
GPIO_8
GPIO_7
GPIO_19
KEY_COL2
KEY_ROW3
DI0_PIN15
4
KEY_COL0
4
GPIO_17
KEY_ROW0
DISP0_DAT23
DI0_PIN2
DISP0_DAT22
3
KEY_ROW2
3
GND
SVDDGP
DI0_PIN3
DI0_PIN4
DISP0_DAT9
2
KEY_COL4
2
GND
GND
DISP0_DAT21
DISP0_DAT16
DISP0_DAT13
1
6.2
5
1
A
B
C
D
E
Package Information and Contact Assignments
19 x 19 mm, 0.8 Pitch Ball Map
Table 114 shows the 19 × 19 mm, 0.8 pitch ball map.
Table 114. 19 x 19 mm, 0.8 Pitch Ball Map
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
171
172
DRAM_D4
J
DRAM_SDCLK_0
K
L
DRAM_RAS
DRAM_A13
DRAM_A10
DRAM_SDWE
19
DRAM_SDODT0
23
DRAM_CS0
DRAM_CAS
18
GND
DRAM_D6
NVCC_EMI_DRAM
DDR_VREF
17
VCC
DRAM_SDCLK_0_B
GND
VCC
16
GND
DRAM_A11
VCC
GND
15
VCC
22
GND
VCC
14
GND
DRAM_D2
VCC
GND
13
VDDGP
GND
GND
VDDGP
12
GND
DRAM_A1
VDDGP
GND
11
VDDGP
21
GND
VDDGP
10
GND
GND
VDDGP
GND
9
VDDGP
DRAM_A4
GND
VDDGP
8
NVCC_LCD
DRAM_A12
VDDGP
GND
7
NVCC_LCD
DISP0_DAT0
DISP0_DAT1
PATA_DIOW
PATA_DMACK
PATA_DMARQ
J
20
PATA_DA_0
PATA_DATA2
PATA_BUFFER_EN
PATA_DA_2
4
6
PATA_DIOR
PATA_DA_1
3
PATA_INTRQ
PATA_RESET_B
PATA_CS_1
2
PATA_CS_0
PATA_IORDY
PATA_DATA0
1
5
K
L
H
DRAM_SDQS0
DRAM_SDQS0_B
DRAM_DQM0
DRAM_D0
DRAM_SDCKE0
NVCC_EMI_DRAM
VDD_DIG_PLL
NVCC_RESET
NVCC_SD1
NVCC_SD2
VCC
GND
VDDGP
GND
VDDGP
GND
VDDGP
DISP0_DAT7
DISP0_DAT11
DI0_DISP_CLK
DISP0_DAT5
DISP0_DAT2
DISP0_DAT12
H
G
DRAM_D5
DRAM_D7
DRAM_D1
DRAM_D3
GND
VDD_REG
NVCC_CKIH
VDD_ANA_PLL
VDD_FUSE
USB_OTG_VDDA33
USB_H1_VDDA33
VDDA
VDDGP
VDDGP
NVCC_JTAG
VDDGP
GND
DISP0_DAT8
DISP0_DAT19
DISP0_DAT18
DISP0_DAT10
DISP0_DAT4
DISP0_DAT6
G
12
FEC_RX_ER
F
DRAM_D14
GND
GND
GND
GND
SD1_CMD
SD1_DATA2
SD1_DATA3
23
22
21
20
19
18
17
16
15
11
NVCC_FEC
USB_OTG_GPANAIO
10
FEC_TXD0
14
9
VDDAL1
USB_OTG_VDDA25
8
NVCC_GPIO
13
7
NVCC_KEYPAD
USB_H1_VDDA25
6
KEY_COL3
4
DISP0_DAT20
5
3
DISP0_DAT15
DISP0_DAT17
2
1
DISP0_DAT14
DISP0_DAT3
F
Package Information and Contact Assignments
Table 114. 19 x 19 mm, 0.8 Pitch Ball Map
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
Freescale Semiconductor
VCC
GND
VCC
NVCC_NANDF
VCC
GND
VCC
GND
VCC
NVCC_EMI_DRAM
DRAM_SDCKE1
DRAM_DQM2
DRAM_D17
DRAM_SDQS2
DRAM_SDQS2_B
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NANDF_RB0
VDDA
NVCC_LVDS
NVCC_LVDS_BG
GND
TVDAC_DHVDD
TVDAC_AHVDDRGB
VCC
GND
DRAM_D16
DRAM_D18
DRAM_D22
DRAM_D20
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
T
DRAM_D23
GND
VCC
8
U
DRAM_D21
VCC
NVCC_EIM_SEC
7
R
DRAM_D19
GND
DRAM_SDBA0
DRAM_SDODT1
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
NVCC_CSI
CSI0_DAT6
CSI0_DAT13
CSI0_DAT10
CSI0_DAT9
EIM_D16
CSI0_DAT16
CSI0_DAT19
4
CSI0_DAT7
6
CSI0_DAT12
CSI0_DAT18
3
CSI0_DAT5
CSI0_DAT17
CSI0_DAT11
CSI0_DAT15
2
CSI0_DAT4
EIM_D17
CSI0_DAT8
CSI0_DAT14
1
R
5
T
U
P
DRAM_SDCLK_1_B
DRAM_SDCLK_1
GND
DRAM_SDBA1
DRAM_CS1
DRAM_RESET
NVCC_EMI_DRAM
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
GND
PATA_DATA14
PATA_DATA15
CSI0_VSYNC
CSI0_DATA_EN
CSI0_MCLK
CSI0_PIXCLK
P
N
DRAM_A8
DRAM_A7
DRAM_A5
DRAM_A3
DRAM_SDBA2
DRAM_A14
NVCC_EMI_DRAM
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
NVCC_PATA
PATA_DATA13
PATA_DATA12
PATA_DATA10
PATA_DATA9
PATA_DATA8
PATA_DATA6
N
M
DRAM_CALIBRATION
DRAM_A6
DRAM_A9
DRAM_A2
DRAM_A0
DRAM_A15
VDDA
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VDDA
PATA_DATA11
PATA_DATA7
PATA_DATA5
PATA_DATA4
PATA_DATA3
PATA_DATA1
M
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Package Information and Contact Assignments
Table 114. 19 x 19 mm, 0.8 Pitch Ball Map
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
173
174
GND
AB
GND
AC
23
TVCDC_IOB_BACK
TVDAC_IOB
19
GND
GND
GND
18
GND
LVDS0_TX1_N
LVDS0_TX1_P
17
22
LVDS0_CLK_N
LVDS0_CLK_P
16
TVCDC_IOR_BACK
LVDS0_TX3_N
LVDS0_TX3_P
15
TVDAC_IOR
LVDS1_TX0_P
LVDS1_TX0_N
14
21
LVDS1_TX1_P
LVDS1_TX1_N
13
TVDAC_IOG
LVDS1_TX2_P
LVDS1_TX2_N
12
TVCDC_IOG_BACK
11
NVCC_SRTC_POW
EIM_BCLK
NANDF_ALE
GND
EXTAL
XTAL
11
20
10
EIM_DA12
EIM_DA9
EIM_DA14
NANDF_CLE
CKIL
ECKIL
10
AA
DRAM_D28
DRAM_D30
GND
GND
TVDAC_COMP
GPIO_13
LVDS0_TX0_P
LVDS0_TX2_P
GND
LVDS_BG_RES
LVDS1_CLK_N
Y
DRAM_SDQS3_B
DRAM_SDQS3
DRAM_D26
DRAM_D24
GND
TVDAC_VREF
LVDS0_TX0_N
LVDS0_TX2_N
GND
GND
LVDS1_CLK_P
W
DRAM_D31
DRAM_D27
DRAM_D25
DRAM_DQM3
GND
GPIO_14
GPIO_12
GPIO_10
PMIC_STBY_REQ
PMIC_ON_REQ
NANDF_CS3
V
DRAM_D29
GND
GND
GND
GND
GND
GPIO_11
TVDAC_AHVDDRGB
GND
NANDF_CS2
NANDF_CS1
23
22
21
20
19
18
17
16
15
14
13
12
9
EIM_DA5
EIM_DA3
EIM_DA6
EIM_DA15
EIM_WAIT
NANDF_WP_B
9
NVCC_XTAL
8
EIM_OE
EIM_CS0
EIM_DA0
EIM_DA8
NANDF_WE_B
NANDF_RE_B
8
NANDF_CS0
7
EIM_A17
EIM_A19
EIM_CS1
EIM_DA2
EIM_DA10
EIM_DA13
7
LVDS1_TX3_P
6
EIM_A23
EIM_A25
EIM_A20
EIM_LBA
EIM_DA4
EIM_DA11
6
LVDS1_TX3_N
5
EIM_D26
EIM_D31
EIM_A24
EIM_D27
EIM_D30
EIM_EB3
EIM_A21
EIM_RW
EIM_DA1
4
EIM_A16
4
EIM_D21
EIM_D25
EIM_EB2
EIM_A22
EIM_A18
EIM_EB0
3
EIM_EB1
3
EIM_D19
EIM_D22
EIM_D24
EIM_D29
GND
GND
2
EIM_DA7
2
EIM_D18
EIM_D20
EIM_D23
EIM_D28
GND
GND
1
5
1
V
W
Y
AA
AB
AC
Package Information and Contact Assignments
Table 114. 19 x 19 mm, 0.8 Pitch Ball Map
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
Revision History
7
Revision History
Table 115 provides a revision history for this data sheet.
Table 115. i.MX53xA Data Sheet Document Revision History
Rev.
Number
Rev 2
Date
Substantive Change(s)
05/2011 • Updated Table 1, "Ordering Information," on page 3.
• Updated the note on page 6 in Section 1.2, “Features.”
• Modified VDD_FUSE design best practice footnote on Table 6, "i.MX53xA Operating Ranges," on
page 20.
• Changed VDD_FUSE max current to 120 mA in Table 8, "Maximal Supply Currents," on page 22.
• In Table 9, "USB Interface Current Consumption," on page 24, removed the row for Suspend
specification.
• Made changes related to text, tables, and figures in Section 4.6.7, “DDR SDRAM Specific
Parameters (DDR2/LVDDR2, LPDDR2, and DDR3). Changes include adding LPDDR2 waves,
updating timings by ACCZ test results, and changing note about DDR load model.
• Removed the Standard Serial Interfaces section.
• In Table 10, "GPIO I/O DC Electrical Characteristics," on page 28, changed input current with no
pull-up/down from 250/120 nA to 2 μA, all input currents with pull-up from 0.12 μΑ to 2 μA when
Vin = OVDD, and input current with pull-down from 0.25 μA to 2 μA when Vin = 0.
• In Table 11, Table 12, and Table 13, changed input current from the nA range to 1 μA.
• In Table 14, "LVIO DC Electrical Characteristics," on page 32, changed input current with no
pull-up/down from 250/120 nA to 1 μA, all input currents with pull-up from 0.12 μΑ to 1 μA when
Vin = OVDD, and input current with pull-down from 0.25 μA to 1 μA when Vin = 0.
• In Table 15, "UHVIO DC Electrical Characteristics," on page 33, changed input current with no
pull-up/down from 300/63 nA to 1 μA, all input currents with pull-up from 0.06 μΑ to 1 μA when Vin
= OVDD, and input current with pull-down from 0.3 μA to 1 μA when Vin = 0.
• Updated keeper values in Table 10 through Table 15.
• Fixed titles of Figure 18 through Figure 26, to fit original EIM AC spec.
• Updated Figure 2, "Power Up Detailed Sequence," on page 26.
• Added Figure 27, "DTACK Write Access (DAP=0)," on page 61.
• Added Table 18, "DDR Output Driver Average Impedance," on page 37.
• Deleted the second footnote of Table 32, "CAMP Electrical Parameters (CKIH1, CKIH2)," on page
46.
• Deleted the Revision 1.0 EIM Internal Module Multiplexing table.
• Deleted the CKIL Electrical Specifications table.
• Deleted the CSPI Slave Mode Timing Parameters table .
• Changed the title of Section 4.4.2, “DDR Output Driver Average Impedance,” from “LPDDR2 I/O
Output Buffer Impedance.”
• Updated the last paragragh of Section 4.7.8.6.1, “IPU Display Operating Signals.”
• Updated Table 35, " NFC—Timing Characteristics," on page 51.
• Removed the “Differential pulse skew” row from Table 29, "AC Electrical Characteristics of LVDS
Pad," on page 44.
• Updated Table 63, "Asynchronous Display Interface Timing Parameters (Pixel Level)," on page
104.
• Updated Table 64, "Asynchronous Parallel Interface Timing Parameters (Access Level)," on page
105.
• Updated Table 102, "USB Timing Specification for Normal ULPI Mode," on page 146.
• Updated the second footnote on Table 113, "19 x 19 mm Signal Assignments, Power Rails, and
I/O," on page 156.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
175
Revision History
Table 115. i.MX53xA Data Sheet Document Revision History (continued)
Rev.
Number
Date
Substantive Change(s)
Rev 1
03/2011 • Updated the first sentence of Section 3.1, “Special Signal Considerations.”
• Deleted two tables, “Special Signal Considerations” and “JTAG Controller Interface Summary,” in
Section 3.1, “Special Signal Considerations.”
• Updated Table 6, "i.MX53xA Operating Ranges," on page 20.
•
Changed VDDGP voltages as follows:
— 800 MHz from 1.0/1.05/1.1 to 1.05/1.1/1.15 V minimum/nominal/maximum.
— Stop mode from 0.9/0.95/1.1 to 0.8/0.85/1.15 V minimum/nominal/maximum.
•
Added statements to footnotes 4 and 5.
Rev 0
02/2011 Initial release.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
176
Freescale Semiconductor
THIS PAGE INTENTIONALLY LEFT BLANK
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
177
How to Reach Us:
Home Page:
www.freescale.com
Web Support:
http://www.freescale.com/support
USA/Europe or Locations Not Listed:
Freescale Semiconductor, Inc.
Technical Information Center, EL516
2100 East Elliot Road
Tempe, Arizona 85284
1-800-521-6274 or
+1-480-768-2130
www.freescale.com/support
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
www.freescale.com/support
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku
Tokyo 153-0064
Japan
0120 191014 or
+81 3 5437 9125
[email protected]
Asia/Pacific:
Freescale Semiconductor China Ltd.
Exchange Building 23F
No. 118 Jianguo Road
Chaoyang District
Beijing 100022
China
+86 10 5879 8000
[email protected]
For Literature Requests Only:
Freescale Semiconductor
Literature Distribution Center
1-800 441-2447 or
+1-303-675-2140
Fax: +1-303-675-2150
LDCForFreescaleSemiconductor
@hibbertgroup.com
Document Number: IMX53AEC
Rev. 2
5/2011
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters that may be
provided in Freescale Semiconductor data sheets and/or specifications can and do vary
in different applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Semiconductor was negligent regarding the design or manufacture of the part.
RoHS-compliant and/or Pb-free versions of Freescale products have the functionality
and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free
counterparts. For further information, see http://www.freescale.com or contact your
Freescale sales representative.
For information on Freescale’s Environmental Products program, go to
http://www.freescale.com/epp.
Freescale and the Freescale logo are trademarks or registered trademarks of Freescale
Semiconductor, Inc. in the U.S. and other countries. All other product or service names
are the property of their respective owners. ARM is the registered trademark of ARM
Limited. ARM Cortex A8 is a trademark of ARM Limited.
© Freescale Semiconductor, Inc., 2011. All rights reserved.