TECHNICAL DATA IN74HC21A Dual 4-Input AND Gate The IN74HC21A is high-speed Si-gate CMOS device and is pin compatible with pullup resistors with low power Schottky TTL (LSTTL). The device provide the Dual 4-input AND function. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION IN74HC21AN Plastic IN74HC21AD SOIC IZ74HC21A Chip TA = -55° to 125° C for all packages LOGIC DIAGRAM PIN ASSIGNMENT A1 B1 Y1 A1 1 14 V CC B1 2 13 D2 3 12 C2 C1 4 11 D1 5 10 B2 Y1 6 9 A2 GND 7 8 Y2 C1 A2 B2 Y2 C2 FUNCTION TABLE D2 Inputs PIN 14 =VCC PIN 7 = GND Output A B Ñ D Y L X X X L X L X X L X X L X L X X X L L H H H H H X = don’t care INTEGRAL 1 IN74HC21A MAXIMUM RATINGS * Symbol Parameter Value Unit -0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin ±20 mA DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air, Plastic DIP** SOIC Package** 750 500 mW -65 to +150 °C 260 °C VOUT IIN IOUT Tstg Storage Temperature TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. **Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, t f Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min Max Unit 2.0 6.0 V 0 VCC V -55 +125 °C 0 0 0 1000 500 400 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. INTEGRAL 2 IN74HC21A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Test Conditions VCC Guaranteed Limit Unit V 25 °C to -55°C ≤85 °C ≤125 °C VIH Minimum High-Level Input Voltage 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 V VIL Maximum Low -Level Input Voltage 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 V VOH Minimum High-Level Output Voltage VIN=VIH or VIL IOUT = -50 µA 2.0 3.0 4.5 6.0 1.92 2.92 4.42 5.92 1.9 2.9 4.4 5.9 1.9 2.9 4.4 5.9 V VIN=VIH or VIL IOUT = -2.4 mÀ 3.0 2.48 2.34 2.2 VIN=VIH or VIL IOUT = -4 mÀ 4.5 3.98 3.84 3.7 VIN=VIH or VIL IOUT = -5.2 mÀ 6.0 5.48 5.34 5.2 VIN= VIH or VIL IOUT = 50 µA 2.0 3.0 4.5 6.0 0.09 0.09 0.09 0.09 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 VIN=VIH or VIL IOUT = 2.4 mÀ 3.0 0.26 0.33 0.4 VIN=VIH or VIL IOUT = 4 mÀ 4.5 0.26 0.33 0.4 VIN=VIH or VIL IOUT = 5.2 mÀ 6.0 0.26 0.33 0.4 VOL Maximum Low-Level Output Voltage V IIL Maximum Low-Level Input Leakage Current VIN= 0 V 6.0 -0.1 -1.0 -1.0 µA IIH Maximum High-Level Input Leakage Current VIN= VCC 6.0 0.1 1.0 1.0 µA ICC Maximum Quiescent Supply Current VIN=VCC or 0 V 6.0 4.0 40 160 µA INTEGRAL 3 IN74HC21A AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input t r=t f=6.0 ns) VCC Symbol Parameter Guaranteed Limit V 25 °C to -55°C ≤85°C ≤125°C Unit tPHL, t PLH Maximum Propagation Delay (Figure 1) 2.0 4.5 6.0 110 22 19 140 28 24 165 33 28 ns tTHL, t TLH Maximum Output Transition Time (Figure 1) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns Maximum Input Capacitance 5.0 10 10 10 pF CIN Power Dissipation Capacitance (Per Gate) CPD TA=25°C,VCC=5.0 V Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC 50 tLH pF tHL V1 0.9 0.9 Input V2 V2 0.1 GND 0.1 tPLH tPHL VCC 0.9 0.9 V2 Output V2 0.1 0.1 0V tTHL tTLH V1 = 0.5 VCC Figure 1. Switching Waveforms VCC VI VO PULSE GENERATOR RT Termination resistance RT – should be equal to ZOUT of pulse generators DEVICE UNDER TEST CL 50 pF Figure 2. Test Circuit INTEGRAL 4 IN74HC21A CHIP PAD DIAGRAM IZ74HC21A Chip marking IN74HC21 (x=1.009; y=0.727) 12 11 10 08 13 1.12 ±0.03 09 14 07 01 06 02 03 04 05 1.22 ±0.03 Pad size 0.108 x 0.108 mm (Pad size is given as per passivation layer) Thickness of chip 0.46 ± 0,02 mm PAD LOCATION Pad No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 INTEGRAL Symbol À1 B1 C1 D1 Y1 GND Y2 A2 B2 C2 D2 Vcc X 1.1165 0.2405 0.5105 0.6925 1.0065 1.0065 1.0065 1.0065 1.0065 0.6925 0.5105 0.2405 0.1165 0.1165 Y 0.3160 0.1150 0.1020 0.1150 0.1400 0.3160 0.4840 0.7040 0.8800 0.9050 0.9180 0.9050 0.6960 0.5360 5