Integral IN74HCU04D Hex unbuffered inverter high-performance silicon-gate cmo Datasheet

TECHNICAL DATA
IN74HCU04
Hex Unbuffered Inverter
High-Performance Silicon-Gate CMOS
The IN74HCU04A is identical in pinout to the LS/ALS04. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device consists of six single-stage inverters. These inverters
are well suited for use as oscillators, pulse shapers, and in many other
applications requiring a high-input impedance amplifier. For digital
applications, the HC04 is recommended.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V; 2.5 to 6 V in Oscillator
Configurations.
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
LOGIC DIAGRAM
ORDERING INFORMATION
IN74HCU04N
Plastic
IN74HCU04D
SOIC
IZ74HCU04 Chip
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
A1
1
14
V CC
Y1
2
13
A6
A2
3
12
Y6
Y2
4
11
A5
A3
5
10
Y5
Y3
6
9
A4
GND
7
8
Y4
FUNCTION TABLE
Inputs
Output
A
Y
L
H
H
L
PIN 14 =VCC
PIN 7 = GND
1
IN74HCU04
MAXIMUM RATINGS *
Symbol
Parameter
Value
Unit
-0.5 to +7.0
V
VCC
DC Supply Voltage (Referenced to GND)
VIN
DC Input Voltage (Referenced to GND)
-1.5 to VCC +1.5
V
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
DC Input Current, per Pin
±20
mA
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VCC and GND Pins
±50
mA
PD
Power Dissipation in Still Air, Plastic DIP **
SOIC Package **
750
500
mW
-65 to +150
°C
260
°C
VOUT
IIN
IOUT
Tstg
TL
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
** Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, t f
Input Rise and Fall Time (Figure 1)
VCC =2.0 Â
VCC =4.5 Â
VCC =6.0 Â
Min
Max
Unit
2.0
6.0
V
0
VCC
V
-55
+125
°C
-
1000
500
400
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
2
IN74HCU04
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
V
25 °C to
-55°C
≤85
°C
≤125
°C
Unit
VOUT=0.1 V *
IOUT≤ 20 µA
2.0
4.5
6.0
1.7
3.6
4.8
1.7
3.6
4.8
1.7
3.6
4.8
V
Maximum Low Level Input Voltage
VOUT= VCC-0.1 V *
IOUT ≤ 20 µA
2.0
4.5
6.0
0.3
0.8
1.1
0.3
0.8
1.1
0.3
0.8
1.1
V
Minimum HighLevel Output
Voltage
VIN=VIL
IOUT ≤ 20 µA
2.0
4.5
6.0
1.8
4.0
5.5
1.8
4.0
5.5
1.8
4.0
5.5
V
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
2.0
4.5
6.0
0.2
0.5
0.5
0.2
0.5
0.5
0.2
0.5
0.5
VIN=VIH
IOUT ≤ 4.0 mA
IOUT ≤ 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
Symbol
Parameter
VIH
Minimum HighLevel Input Voltage
VIL
VOH
Test Conditions
VIN=VIL
IOUT ≤ 4.0 mA
IOUT ≤ 5.2 mA
VOL
Guaranteed Limit
Maximum LowLevel Output
Voltage
VIN=VIH
IOUT ≤ 20 µA
V
IIN
Maximum Input
Leakage Current
VIN=VCC or GND
6.0
±0.1
±1.0
±1.0
µA
ICC
Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
IOUT=0µA
6.0
2.0
20
40
µA
* For VCC = 2.0 V, VOUT = 0.2 V or VCC – 0.2 V.
3
IN74HCU04
AC ELECTRICAL CHARACTERISTICS (CL=50pF, Input t r=t f=6.0 ns)
VCC
Symbol
Parameter
Guaranteed Limit
V
25 °C to
-55°C
≤85°C
≤125°C
Unit
tPLH, t PHL
Maximum Propagation Delay, Input A to
Output Y (Figures 1 and 2)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
tTLH, t THL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
4.5
6.0
70
15
13
85
18
16
100
22
19
ns
-
10
10
10
pF
CIN
Maximum Input Capacitance
CPD
Power Dissipation Capacitance (Per Inverter)
TA=25?Ñ, VCC=5.0 V
Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
15
pF
For load considerations, see Chepter 4.
TEST POINT
tr
tf
VCC
90%
50%
10%
INPUT A
OUTPUT
DEVICE
UNDER
TEST
GND
tPLH
tPHL
CL*
90%
50%
10%
OUTPUT Y
tTHL
tTLH
* Includes all probe and jig capacitance
Figure 1. Switching Waveforms.
Figure 2. Test Circuit
LOGIC DETAIL
(1/6 of Device Show)
VCC
A
Y
4
IN74HCU04
TYPICAL APPLICATIONS
Crystal Oscillator
Stable RC Oscillator
1/6HCU04 1/6HCU04 1/6HCU04
R2
Vout
1/6HCU04
R2 > > R1
C1 < C2
C
R1
R2
C1
R1
C2
Vout
Schmitt Trigger
High Input Single -Stage Amplifier
with a 2 to 6 V Supply Range
R2
VCC
1 M 1/6HCU04
R2 > 6R1
R1
1/6HCU04 1/6HCU04
INPUT
Vin
OUTPUT
Vout
1M
Multi-Stage Amplifier
LED Driver
VCC
+V
1/6HCU04 1/6HCU04 1/6HCU04
INPUT
1/6HCU04
OUTPUT
For reduced power suplly current, use high-efficiency LEDs
such as the Hewlett-Packard HLMP series or equivalent
5
IN74HCU04
CHIP PAD DIAGRAM IZ74HCU04
1.19 + 0.003
1.17 + 0.003
(0,0)
Chip marking
25HCU04A
(x=0.992, y=0.092)
Thickness of chip 0.46 ± 0,02 mm
PAD LOCATION
Pad No
Symbol
01
A1
02
Y1
03
A2
04
Y2
05
A3
06
Y3
07
GND
08
Y4
09
A4
10
Y5
11
A5
12
Y6
13
A6
14
VCC
* Pad size is given as per metallization layer
X
0.110
0.170
0.350
0.610
0.850
0.950
0.950
0.950
0.850
0.610
0.350
0.170
0.110
0.110
Y
0.280
0.110
0.110
0.110
0.110
0.320
0.510
0.760
0.970
0.970
0.970
0.970
0.800
0.550
Pad size* , mm
0.105x0.105
0.105x0.105
0.105x0.105
0.105x0.105
0.105x0.105
0.105x0.105
0.105x0.105
0.105x0.105
0.105x0.105
0.105x0.105
0.105x0.105
0.105x0.105
0.105x0.105
0.105x0.105
6
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