Vishay IRF840LCL Power mosfet Datasheet

IRF840LCS, IRF840LCL, SiHF840LCS, SiHF840LCL
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Halogen-free According to IEC 61249-2-21
Definition
• Ultra Low Gate Charge
• Reduced Gate Drive Requirement
• Enhanced 30 V VGS Rating
• Reduced Ciss, Coss, Crss
• Extremely High Frequency Operation
• Repetitive Avalanche Rated
• Compliant to RoHS Directive 2002/95/EC
500
RDS(on) ()
VGS = 10 V
Qg (Max.) (nC)
0.85
39
Qgs (nC)
10
Qgd (nC)
19
Configuration
Single
DESCRIPTION
D
G
G
This new series of low charge Power MOSFETs achieve
significantly lower gate charge then conventional Power
MOSFETs. Utilizing the new LCDMOS (low charge device
Power MOSFETs) technology, the device improvements are
achieved without added product cost, allowing for reduced
gate drive requirements and total system savings. In
addition, reduced switching losses and improved efficiency
are achievable in a variety of high frequency applications.
Frequencies of a few MHz at high current are possible using
the new low charge Power MOSFETs.
These device improvements combined with the proven
ruggedness and reliability that characterize Power
MOSFETs offer the designer a new power transistor
standard for switching applications.
D2PAK (TO-263)
I2PAK (TO-262)
D
S
G
D
S
S
N-Channel MOSFET
ORDERING INFORMATION
Package
Lead (Pb)-free and Halogen-free
Lead (Pb)-free
D2PAK (TO-263)
SiHF840LCS-GE3
IRF840LCSPbF
SiHF840LCS-E3
I2PAK (TO-262)
SiHF840LCL-GE3
IRF840LCLPbF
SiHF840LCL-E3
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
VDS
VGS
500
± 30
8.0
5.1
28
1.0
510
8.0
13
125
3.1
3.5
- 55 to + 150
300d
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Currenta, e
Linear Derating Factor
Single Pulse Avalanche Energyb, e
Avalanche Currenta
Repetiitive Avalanche Energya
Maximum Power Dissipation
Peak Diode Recovery dV/dtc, e
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
ID
IDM
EAS
IAR
EAR
TC = 25 °C
TA = 25 °C
PD
dV/dt
TJ, Tstg
for 10 s
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting TJ = 25 °C, L = 14 mH, Rg = 25 , IAS = 8.0 A (see fig. 12).
c. ISD  8.0 A, dI/dt  100 A/μs, VDD  VDS, TJ  150 °C.
d. 1.6 mm from case.
e. Uses IRF840LC, SiHF840LC data and test conditions.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91068
S11-1050-Rev. C, 30-May-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF840LCS, IRF840LCL, SiHF840LCS, SiHF840LCL
Vishay Siliconix
THERMAL RESISTANCE RATINGS
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
(PCB Mounted, Steady-State)a
PARAMETER
RthJA
-
40
Maximum Junction-to-Case (Drain)
RthJC
-
1.0
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
VDS
VGS = 0, ID = 250 μA
500
-
-
V
VDS/TJ
Reference to 25 °C, ID = 1 mAc
-
0.63
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.0
V
Gate-Source Leakage
IGSS
VGS = ± 20 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 500 V, VGS = 0 V
-
-
25
VDS = 400 V, VGS = 0 V, TJ = 125 °C
-
-
250
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
gfs
ID = 4.8 Ab
VGS = 10 V
VDS = 50 V, ID = 4.8 Ab
μA
-
-
0.85

4.0
-
-
S
-
1100
-
-
170
-
-
18
-
-
-
39
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5c
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
-
-
10
Gate-Drain Charge
Qgd
-
-
19
Turn-On Delay Time
td(on)
-
12
-
tr
-
25
-
-
27
-
-
19
-
-
-
8.0
-
-
28
Rise Time
Turn-Off Delay Time
Fall Time
td(off)
VGS = 10 V
ID = 8.0 A, VDS = 400 V,
see fig. 6 and 13b, c
VDD = 250 V, ID = 8.0 A,
Rg = 9.1 , RD = 30 , see fig. 10b, c
tf
pF
nC
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulsed Diode Forward Currenta
Body Diode Voltage
IS
ISM
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IS = 8.0 A, VGS = 0
S
Vb
TJ = 25 °C, IF = 8.0 A, dI/dt = 100 A/μsb, c
-
-
2.0
V
-
490
740
ns
-
3.0
4.5
μC
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 μs; duty cycle  2 %.
c. Uses SiHF840LC data and test conditions.
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Document Number: 91068
S11-1050-Rev. C, 30-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF840LCS, IRF840LCL, SiHF840LCS, SiHF840LCL
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
VGS
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
Bottom 4.5 V
Top
100
4.5 V
101
ID, Drain Current (A)
ID, Drain Current (A)
101
150 °C
25 °C
100
20 µs Pulse Width
VDS = 50 V
20 µs Pulse Width
TC = 25 °C
10-1
10-1
100
4
101
VDS, Drain-to-Source Voltage (V)
91068_01
ID, Drain Current (A)
101
100
VGS
Top
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
Bottom 4.5 V
4.5 V
10-1
20 µs Pulse Width
TC = 150 °C
10-1
91068_02
100
101
VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
Document Number: 91068
S11-1050-Rev. C, 30-May-11
6
7
8
9
10
Fig. 3 - Typical Transfer Characteristics
RDS(on), Drain-to-Source On Resistance
(Normalized)
Fig. 1 - Typical Output Characteristics
5
VGS, Gate-to-Source Voltage (V)
91068_03
91068_04
3.0
2.5
ID = 8.0 A
VGS = 10 V
2.0
1.5
1.0
0.5
0.0
- 60 - 40 - 20 0
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 4 - Normalized On-Resistance vs. Temperature
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF840LCS, IRF840LCL, SiHF840LCS, SiHF840LCL
2400
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
Capacitance (pF)
2000
1600
Ciss
1200
800
Coss
400
Crss
ISD, Reverse Drain Current (A)
Vishay Siliconix
100
101
VDS = 250 V
VDS = 100 V
8
4
102
5
10 µs
2
10
100 µs
5
1 ms
2
1
For test circuit
see figure 13
16
24
32
40
2
0.1
1
48
QG, Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
91068_08
10 ms
TC = 25 °C
TJ = 150 °C
Single Pulse
5
8
1.6
2
ID, Drain Current (A)
VGS, Gate-to-Source Voltage (V)
VDS = 400 V
0
1.4
Operation in this area limited
by RDS(on)
5
0
1.2
VSD, Source-to-Drain Voltage (V)
103
16
1.0
Fig. 7 - Typical Source-Drain Diode Forward Voltage
ID = 8.0 A
12
0.8
91068_07
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
20
VGS = 0 V
0.6
VDS, Drain-to-Source Voltage (V)
91068_05
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4
25 °C
100
0
91068_06
150 °C
101
2
5
10
2
5
102
2
5
103
VDS, Drain-to-Source Voltage (V)
Fig. 8 - Maximum Safe Operating Area
Document Number: 91068
S11-1050-Rev. C, 30-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF840LCS, IRF840LCL, SiHF840LCS, SiHF840LCL
Vishay Siliconix
RD
VDS
VGS
8.0
D.U.T.
ID, Drain Current (A)
Rg
6.0
+
- VDD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
4.0
Fig. 10a - Switching Time Test Circuit
2.0
VDS
90 %
0.0
25
50
75
100
125
150
TC, Case Temperature (°C)
91068_09
10 %
VGS
td(on)
Fig. 9 - Maximum Drain Current vs. Case Temperature
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
Thermal Response (ZthJC)
10
1
D = 0.5
PDM
0.2
0.1
0.1
t1
0.05
0.02
0.01
t2
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
Single Pulse
(Thermal Response)
10-2
10-5
91068_11
10-4
10-3
10-2
0.1
1
10
t1, Rectangular Pulse Duration (s)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
Document Number: 91068
S11-1050-Rev. C, 30-May-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF840LCS, IRF840LCL, SiHF840LCS, SiHF840LCL
Vishay Siliconix
VDS
15 V
tp
Driver
L
VDS
Rg
D.U.T
+
A
- VDD
IAS
20 V
tp
IAS
0.01 Ω
Fig. 12a - Unclamped Inductive Test Circuit
Fig. 12b - Unclamped Inductive Waveforms
EAS, Single Pulse Energy (mJ)
1200
ID
3.6 A
5.1 A
Bottom 8.0 A
Top
1000
800
600
400
200
0
VDD = 50 V
25
91068_12c
50
75
100
125
150
Starting TJ, Junction Temperature (°C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
10 V
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
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Fig. 13b - Gate Charge Test Circuit
Document Number: 91068
S11-1050-Rev. C, 30-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF840LCS, IRF840LCL, SiHF840LCS, SiHF840LCL
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91068.
Document Number: 91068
S11-1050-Rev. C, 30-May-11
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Package Information
Vishay Siliconix
TO-263AB (HIGH VOLTAGE)
A
(Datum A)
3
A
4
4
L1
B
A
E
c2
H
Gauge
plane
4
0° to 8°
5
D
B
Detail A
Seating plane
H
1
2
C
3
C
L
L3
L4
Detail “A”
Rotated 90° CW
scale 8:1
L2
B
A1
B
A
2 x b2
c
2xb
E
0.010 M A M B
± 0.004 M B
2xe
Plating
5
b1, b3
Base
metal
c1
(c)
D1
4
5
(b, b2)
Lead tip
MILLIMETERS
DIM.
MIN.
MAX.
View A - A
INCHES
MIN.
4
E1
Section B - B and C - C
Scale: none
MILLIMETERS
MAX.
DIM.
MIN.
INCHES
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D1
6.86
-
0.270
-
A1
0.00
0.25
0.000
0.010
E
9.65
10.67
0.380
0.420
6.22
-
0.245
-
b
0.51
0.99
0.020
0.039
E1
b1
0.51
0.89
0.020
0.035
e
b2
1.14
1.78
0.045
0.070
H
14.61
15.88
0.575
0.625
b3
1.14
1.73
0.045
0.068
L
1.78
2.79
0.070
0.110
2.54 BSC
0.100 BSC
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.066
c1
0.38
0.58
0.015
0.023
L2
-
1.78
-
0.070
c2
1.14
1.65
0.045
0.065
L3
D
8.38
9.65
0.330
0.380
L4
0.25 BSC
4.78
5.28
0.010 BSC
0.188
0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
Document Number: 91364
Revision: 15-Sep-08
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Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.
Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free
requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
conform to JEDEC JS709A standards.
Revision: 02-Oct-12
1
Document Number: 91000
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