PD - 95936C
IRFB4610PbF
IRFS4610PbF
IRFSL4610PbF
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
HEXFET® Power MOSFET
D
G
S
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
VDSS
RDS(on) typ.
max.
ID
S
GD
S
D
G
D2Pak
IRFS4610PbF
TO-262
IRFSL4610PbF
S
D
G
TO-220AB
IRFB4610PbF
100V
11m:
14m:
73A
Absolute Maximum Ratings
Symbol
Parameter
Max.
Units
73
A
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V
52
IDM
Pulsed Drain Current
290
PD @TC = 25°C
Maximum Power Dissipation
VGS
dV/dt
TJ
Peak Diode Recovery
7.6
TSTG
Storage Temperature Range
f
190
W
Linear Derating Factor
1.3
Gate-to-Source Voltage
± 20
W/°C
V
e
-55 to + 175
Operating Junction and
300
Soldering Temperature, for 10 seconds
(1.6mm from case)
x
Avalanche Characteristics
EAS (Thermally limited)
Single Pulse Avalanche Energy
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
x
10lb in (1.1N m)
Mounting torque, 6-32 or M3 screw
c
V/ns
°C
d
mJ
370
See Fig. 14, 15, 16a, 16b,
f
A
mJ
Thermal Resistance
Symbol
Parameter
Typ.
Max.
–––
0.77
Case-to-Sink, Flat Greased Surface , TO-220
0.50
–––
Junction-to-Ambient, TO-220
–––
62
–––
40
j
RθJC
Junction-to-Case
RθCS
RθJA
RθJA
Junction-to-Ambient (PCB Mount) , D2Pak
www.irf.com
j
ij
Units
°C/W
1
09/16/10
IRF/B/S/SL4610PbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
∆V(BR)DSS/∆TJ
RDS(on)
VGS(th)
IDSS
IGSS
RG
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Gate Input Resistance
Min. Typ. Max. Units
100
–––
–––
2.0
–––
–––
–––
–––
–––
––– –––
0.085 –––
11
14
–––
4.0
–––
20
––– 250
––– 200
––– -200
1.5
–––
Conditions
V VGS = 0V, ID = 250µA
V/°C Reference to 25°C, ID = 1mA
mΩ VGS = 10V, ID = 44A
V VDS = VGS, ID = 100µA
µA VDS = 100V, VGS = 0V
VDS = 100V, VGS = 0V, TJ = 125°C
nA VGS = 20V
VGS = -20V
Ω f = 1MHz, open drain
c
f
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss eff. (ER)
Coss eff. (TR)
Parameter
Min. Typ. Max. Units
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
73
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Effective Output Capacitance (Energy Related) –––
–––
Effective Output Capacitance (Time Related)
–––
90
20
36
18
87
53
70
3550
260
150
330
380
–––
140
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
S
nC
ns
pF
Conditions
VDS = 50V, ID = 44A
ID = 44A
VDS = 80V
VGS = 10V
VDD = 65V
ID = 44A
RG = 5.6Ω
VGS = 10V
VGS = 0V
VDS = 50V
ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 80V
VGS = 0V, VDS = 0V to 80V
f
f
h, See Fig.11
g, See Fig. 5
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
73
ISM
(Body Diode)
Pulsed Source Current
–––
–––
290
VSD
trr
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
c
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.39mH
RG = 25Ω, IAS = 44A, VGS =10V. Part not recommended for use
above this value.
ISD ≤ 44A, di/dt ≤ 660A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
2
A
Conditions
MOSFET symbol
showing the
integral reverse
D
G
p-n junction diode.
––– –––
1.3
V TJ = 25°C, IS = 44A, VGS = 0V
VR = 85V,
–––
35
53
ns TJ = 25°C
IF = 44A
TJ = 125°C
–––
42
63
di/dt = 100A/µs
–––
44
66
nC TJ = 25°C
TJ = 125°C
–––
65
98
–––
2.1
–––
A TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
f
S
f
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS .
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C
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IRF/B/S/SL4610PbF
1000
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
100
BOTTOM
10
4.5V
≤ 60µs PULSE WIDTH
Tj = 25°C
BOTTOM
100
4.5V
≤ 60µs PULSE WIDTH
Tj = 25°C
1
10
0.1
1
10
100
0.1
VDS, Drain-to-Source Voltage (V)
10
100
Fig 2. Typical Output Characteristics
1000.0
3.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current(Α)
1
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
100.0
TJ = 175°C
10.0
TJ = 25°C
1.0
VDS = 25V
≤ 60µs PULSE WIDTH
0.1
2.0
3.0
4.0
5.0
6.0
7.0
2.0
1.5
1.0
0.5
8.0
-60 -40 -20 0
VGS, Gate-to-Source Voltage (V)
Coss = Cds + Cgd
4000
Ciss
3000
2000
1000
Coss
Crss
10
100
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
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ID= 44A
VDS = 80V
VDS= 50V
VDS= 20V
16
12
8
4
0
0
1
Fig 4. Normalized On-Resistance vs. Temperature
20
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
5000
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
Fig 3. Typical Transfer Characteristics
6000
ID = 73A
VGS = 10V
2.5
VGS, Gate-to-Source Voltage (V)
C, Capacitance (pF)
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
0
20
40
60
80
100
120
140
QG Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
3
IRF/B/S/SL4610PbF
1000
100.0
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000.0
TJ = 175°C
10.0
TJ = 25°C
1.0
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µsec
100
10
1msec
10msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
1
2.0
V(BR)DSS , Drain-to-Source Breakdown Voltage
ID , Drain Current (A)
80
60
40
20
0
50
75
100
125
150
1000
125
120
115
110
105
100
175
-60 -40 -20 0
TJ , Junction Temperature (°C)
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Drain-to-Source Breakdown Voltage
EAS, Single Pulse Avalanche Energy (mJ)
2.0
1.5
Energy (µJ)
100
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
25
10
VDS , Drain-toSource Voltage (V)
VSD, Source-to-Drain Voltage (V)
1.0
0.5
1600
I D
4.6A
6.3A
BOTTOM 44A
TOP
1200
800
400
0
0.0
0
20
40
60
80
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy
4
DC
0.1
0.1
100
25
50
75
100
125
150
175
Starting TJ, Junction Temperature (°C)
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
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IRF/B/S/SL4610PbF
1
Thermal Response ( ZthJC )
D = 0.50
0.20
0.10
0.1
0.05
R1
R1
0.02
0.01
τJ
0.01
τJ
τ1
R2
R2
τC
τ2
τ1
τ
Ri (°C/W) τi (sec)
0.4367 0.001016
0.3337
τ2
0.009383
Ci= τi/Ri
Ci i/Ri
0.001
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)
Avalanche Current (A)
Duty Cycle = Single Pulse
0.01
10
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
EAR , Avalanche Energy (mJ)
400
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as neither Tjmax nor Iav (max)
is exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 44A
300
200
100
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
Fig 15. Maximum Avalanche Energy vs. Temperature
www.irf.com
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
5
IRF/B/S/SL4610PbF
16
ID = 1.0A
ID = 1.0mA
ID = 250µA
4.0
12
ID = 100µA
IRRM - (A)
VGS(th) Gate threshold Voltage (V)
5.0
3.0
8
IF = 29A
VR = 85V
4
2.0
TJ = 125°C
TJ = 25°C
0
1.0
-75 -50 -25
0
25
50
75
100 200 300 400 500 600 700 800 900 1000
100 125 150 175
dif / dt - (A / µs)
TJ , Temperature ( °C )
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage Vs. Temperature
16
300
12
QRR - (nC)
IRRM - (A)
200
8
100
4
IF = 44A
VR = 85V
IF = 29A
VR = 85V
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
0
0
100 200 300 400 500 600 700 800 900 1000
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / µs)
dif / dt - (A / µs)
Fig. 19 - Typical Stored Charge vs. dif/dt
Fig. 18 - Typical Recovery Current vs. dif/dt
300
QRR - (nC)
200
100
0
IF = 44A
VR = 85V
TJ = 125°C
TJ = 25°C
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / µs)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRF/B/S/SL4610PbF
D.U.T
Driver Gate Drive
-
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D=
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V(BR)DSS
15V
D.U.T
RG
VGS
20V
DRIVER
L
VDS
tp
+
V
- DD
IAS
tp
A
0.01Ω
I AS
Fig 22a. Unclamped Inductive Test Circuit
LD
Fig 22b. Unclamped Inductive Waveforms
VDS
VDS
90%
+
VDD -
10%
D.U.T
VGS
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
td(on)
Fig 23a. Switching Time Test Circuit
tr
td(off)
tf
Fig 23b. Switching Time Waveforms
Id
Vds
Vgs
L
DUT
0
VCC
Vgs(th)
1K
Qgs1 Qgs2
Fig 24a. Gate Charge Test Circuit
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Qgd
Qgodr
Fig 24b. Gate Charge Waveform
7
IRF/B/S/SL4610PbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
EXAMPLE: T HIS IS AN IRF1010
LOT CODE 1789
AS S EMBLED ON WW 19, 2000
IN T HE AS S EMBLY LINE "C"
Note: "P" in ass embly line position
indicates "Lead - Free"
INT ERNAT IONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
PART NUMBER
DAT E CODE
YEAR 0 = 2000
WEEK 19
LINE C
TO-220AB packages are not recommended for Surface Mount Application.
Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
8
www.irf.com
IRF/B/S/SL4610PbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
EXAMPLE: T HIS IS AN IRL3103L
LOT CODE 1789
ASS EMBLED ON WW 19, 1997
IN THE ASSEMBLY LINE "C"
INTERNATIONAL
RECT IF IER
LOGO
ASS EMBLY
LOT CODE
PART NUMBER
DAT E CODE
YEAR 7 = 1997
WEEK 19
LINE C
OR
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLY
LOT CODE
PART NUMBER
DATE CODE
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 7 = 1997
WEEK 19
A = ASSEMBLY SITE CODE
Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
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9
IRF/B/S/SL4610PbF
D2Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
D2Pak (TO-263AB) Part Marking Information
T HIS IS AN IRF530S WIT H
LOT CODE 8024
AS S EMBLED ON WW 02, 2000
IN T HE AS S EMBLY LINE "L"
INT ERNAT IONAL
RECT IFIER
LOGO
PART NUMBER
F530S
DAT E CODE
YEAR 0 = 2000
WEEK 02
LINE L
AS S EMBLY
LOT CODE
OR
INT ERNATIONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
PART NUMBER
F530S
DAT E CODE
P = DES IGNAT ES LEAD - FREE
PRODUCT (OPT IONAL)
YEAR 0 = 2000
WEEK 02
A = AS S EMBLY S ITE CODE
Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
10
www.irf.com
IRF/B/S/SL4610PbF
D2Pak (TO-263AB) Tape & Reel Information
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
11.60 (.457)
11.40 (.449)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
10.90 (.429)
10.70 (.421)
1.75 (.069)
1.25 (.049)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
60.00 (2.362)
MIN.
26.40 (1.039)
24.40 (.961)
3
30.40 (1.197)
MAX.
4
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 09/2010
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11