IS41C85125 IS41LV85125 ISSI 512K x 8 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE ® PRELIMINARY INFORMATION AUGUST 2001 FEATURES DESCRIPTION • • • • Fast access and cycle time TTL compatible inputs and outputs Refresh Interval: 1024 cycles/16 ms Refresh Mode: RAS-Only, CAS-before-RAS (CBR), and Hidden • JEDEC standard pinout • Single power supply: -- 5V ± 10% (IS41C85125) -- 3.3V ± 10% (IS41LV85125) • Industrial temperature available The ISSI IS41C85125 and IS41LV85125 are 512,288 x 8-bit high-performance CMOS Dynamic Random Access Memories. Fast Page Mode allows 1024 random accesses within a single row with access cycle time as short as 12 ns per 8-bit word. KEY TIMING PARAMETERS PIN CONFIGURATION 28-Pin SOJ Parameter Max. RAS Access Time (tRAC) Max. CAS Access Time (tCAC) Max. Column Address Access Time (tAA) Min. Fast Page Mode Cycle Time (tPC) Min. Read/Write Cycle Time (tRC) -35 35 10 18 12 60 -60 60 15 30 25 110 These features make the IS41C85125 and the IS41LV85125 ideally suited for high band-width graphics, digital signal processing, high-performance computing systems, and peripheral applications. The IS41C85125 and IS41LV85125 are available in a 28-pin, 400-mil SOJ package. Unit ns ns ns ns ns PIN DESCRIPTIONS VCC 1 28 GND I/O0 2 27 I/O7 I/O1 3 26 I/O6 I/O2 4 25 I/O5 I/O3 5 24 I/O4 NC 6 23 CAS WE 7 22 OE RAS 8 21 NC A0-A9 Address Inputs I/O0-I/O7 Data Inputs/Outputs A9 9 20 A8 WE Write Enable A0 10 19 A7 OE Output Enable A1 11 18 A6 RAS Row Address Strobe A2 12 17 A5 CAS Column Address Strobe A3 13 16 A4 VCC Power VCC 14 15 GND GND Ground NC No Connection This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION 09/25/01 Rev. 00A 1 IS41C85125 IS41LV85125 ISSI ® FUNCTIONAL BLOCK DIAGRAM OE WE CAS CAS CLOCK GENERATOR WE CONTROL LOGICS CAS WE OE CONTROL LOGIC OE RAS CLOCK GENERATOR RAS DATA I/O BUS COLUMN DECODERS SENSE AMPLIFIERS ROW DECODER REFRESH COUNTER ADDRESS BUFFERS A0-A9 DATA I/O BUFFERS RAS I/O0-I/O7 MEMORY ARRAY 512,288 x 8 TRUTH TABLE Function Standby Read Write: Word (Early Write) Read-Write Hidden Refresh Read Write(1) RAS-Only Refresh CBR Refresh RAS H L L L L→H→L L→H→L L H→L CAS H L L L L L H L WE X H L H→L H L X X OE X L X L→H L X X X Address tR/tC X ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/NA X I/O High-Z DOUT DIN DOUT, DIN DOUT DOUT High-Z High-Z Notes: 1. EARLY WRITE only. 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 09/25/01 IS41C85125 IS41LV85125 ISSI ® FUNCTIONAL DESCRIPTION The IS41C85125 and IS41LV85125 are CMOS DRAMs optimized for high-speed bandwidth, low-power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 19 address bits. The first ten address bits (A0-A9) are entered as row address and latter nine address bits (A0-A8) are entered as column address. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first ten bits of row address and CAS is used to latch the latter nine bits of column address. Memory Cycle A memory cycle is initiated by bringing RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensure proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. A new cycle must not be initiated until the minimum precharge time tRP, tCP has elapsed. Read Cycle A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA, tCAC and tOEA are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters. at or before the falling edge of CAS or WE, whichever occurs last. Refresh Cycle To retain data, 1024 refresh cycles are required in each 16 ms period. There are two ways to refresh the memory: 1. By clocking each of the 1024 row addresses (A0 through A9) with RAS at least once every 16 ms. Any read, write, read-modify-write or RAS-only cycle refreshes the addressed row. 2. Using a CAS-before-RAS refresh cycle. CAS-beforeRAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 10-bit counter provides the row addresses and the external address inputs are ignored. CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle. Power-On After application of the VCC supply, an initial pause of 200 µs is required followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS signal). During power-on, it is recommended that RAS track with VCC or be held at a valid VIH to avoid current surges. Write Cycle A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION 09/25/01 Rev. 00A 3 IS41C85125 IS41LV85125 ISSI ® ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameters VT Voltage on Any Pin Relative to GND VCC Supply Voltage IOUT PD TA Output Current Power Dissipation Operation Temperature TSTG Storage Temperature 5V 3.3V 5V 3.3V Com. Ind. Rating Unit –1.0 to +7.0 –0.5 t0 +4.6 –1.0 to +7.0 –0.5 t0 +4.6 50 1 0 to 70 –40 to +85 –55 to +125 V V mA W °C °C Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND) Symbol VCC VCC VIH VIH VIL VIL TA Parameter Supply Voltage Supply Voltage Input High Voltage Input High Voltage Input Low Voltage Input Low Voltage Ambient Temperature Voltage Min. Typ. Max. Unit 5V 3.3V 5V 3.3V 5V 3.3 Com. Ind. 4.5 3.0 2.4 2.0 –1.0 –0.3 0 –40 5.0 3.3 — — — — — — 5.5 3.6 VCC + 1.0 VCC + 0.3 0.8 0.8 70 85 V V V V V V °C Max. Unit 5 7 7 pF pF pF CAPACITANCE(1,2) Symbol Parameter CIN1 CIN2 CIO Input Capacitance: A0-A9 Input Capacitance: RAS, UCAS, LCAS, WE, OE Data Input/Output Capacitance: I/O0-I/O7 Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz. 4 Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 09/25/01 IS41C85125 IS41LV85125 ISSI ® ELECTRICAL CHARACTERISTICS(1) (Recommended Operation Conditions unless otherwise noted.) Symbol Parameter Test Condition IIL Input Leakage Current IIO Output Leakage Current VOH VOL Output High Voltage Level Output Low Voltage Level Any input 0V ≤ VIN ≤ Vcc Other inputs not under test = 0V Output is disabled (Hi-Z) 0V ≤ VOUT ≤ Vcc IOH = –2.5 mA IOL = 2.1 mA ICC1 Stand-by Current: TTL RAS, CAS ≥ VIH ICC2 Stand-by Current: CMOS RAS, CAS ≥ VCC – 0.2V ICC3 Operating Current: Random Read/Write(2,3,4) Average Power Supply Current Operating Current: Fast Page Mode(2,3,4) Average Power Supply Current Refresh Current: RAS-Only(2,3) Average Power Supply Current Refresh Current: CBR (2,3,5) Average Power Supply Current RAS, CAS, Address Cycling, tRC = tRC (min.) ICC4 ICC5 ICC6 Speed Min. Max. Unit –10 10 µA –10 10 µA 2.4 — — 0.4 V V 2 3 1 2 2 1 230 170 mA -35 -60 — — — — — — — — RAS = VIL, CAS, Cycling tPC = tPC (min.) -35 -60 — — 220 160 mA RAS Cycling, CAS ≥ VIH tRC = tRC (min.) -35 -60 — — 230 170 mA RAS, CAS Cycling tRC = tRC (min.) -35 -60 — — 230 170 mA 5V 5V 3.3V 3.3V 5V 3.3V Com. Ind. Com. Ind. mA mA Notes: 1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured.The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. Dependent on cycle rates. 3. Specified values are obtained with minimum cycle time and the output open. 4. Column-address is changed once each fast page cycle. 5. Enables on-chip refresh and address counters. Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION 09/25/01 Rev. 00A 5 IS41C85125 IS41LV85125 ISSI ® AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) -35 Symbol t RC t RAC t CAC t AA t RAS t RP t CAS t CP t CSH t RCD t ASR t RAH t ASC t CAH t AR t RAD t RAL t RPC t RSH t CLZ t CRP t OD tOE t OEHC tOEP tOES t RCS t RRH t RCH t WCH t WCR Parameter Random READ or WRITE Cycle Time Access Time from RAS(6, 7) Access Time from CAS(6, 8, 15) Access Time from Column-Address(6) RAS Pulse Width RAS Precharge Time CAS Pulse Width(26) CAS Precharge Time(9, 25) CAS Hold Time (21) RAS to CAS Delay Time(10, 20) Row-Address Setup Time Row-Address Hold Time Column-Address Setup Time(20) Column-Address Hold Time(20) Column-Address Hold Time (referenced to RAS) RAS to Column-Address Delay Time(11) Column-Address to RAS Lead Time RAS to CAS Precharge Time RAS Hold Time(27) CAS to Output in Low-Z(15, 29) CAS to RAS Precharge Time(21) Output Disable Time(19, 28, 29) Output Enable Time(15, 16) OE HIGH Hold Time from CAS HIGH OE HIGH Pulse Width OE LOW to CAS HIGH Setup Time Read Command Setup Time(17, 20) Read Command Hold Time (referenced to RAS)(12) Read Command Hold Time (referenced to CAS)(12, 17, 21) Write Command Hold Time(17, 27) Write Command Hold Time (referenced to RAS)(17) -60 Min. 60 — — — 35 20 6 5 35 11 0 6 0 6 30 Max. — 35 10 18 10K — 10K — — 28 — — — — — Min. 110 — — — 60 40 10 10 60 20 0 10 0 10 40 Max. — 60 15 30 10K — 10K — — 45 — — — — — Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 12 18 0 8 3 5 3 — 10 10 5 0 0 20 — — — — — 15 10 — — — — — 15 30 0 15 3 5 3 — 10 10 5 0 0 30 — — — — — 15 15 — — — — — ns ns ns ns ns ns ns ns ns ns ns ns ns 0 — 0 — ns 5 30 — — 10 50 — — ns ns (Continued) 6 Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 09/25/01 IS41C85125 IS41LV85125 ISSI ® AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) -35 Symbol tWP tWPZ tRWL tCWL tWCS t DHR t ACH tOEH t DS t DH t RWC t RWD t CWD tAWD t PC tRASP tCPA tPRWC tOFF tWHZ t CLCH t CSR t CHR tORD tREF tT Parameter Write Command Pulse Width(17) WE Pulse Widths to Disable Outputs Write Command to RAS Lead Time(17) Write Command to CAS Lead Time(17, 21) Write Command Setup Time(14, 17, 20) Data-in Hold Time (referenced to RAS) Column-Address Setup Time to CAS Precharge during WRITE Cycle OE Hold Time from WE during READ-MODIFY-WRITE cycle(18) Data-In Setup Time(15, 22) Data-In Hold Time(15, 22) READ-MODIFY-WRITE Cycle Time RAS to WE Delay Time during READ-MODIFY-WRITE Cycle(14) CAS to WE Delay Time(14, 20) Column-Address to WE Delay Time(14) Fast Page Mode READ or WRITE Cycle Time(24) RAS Pulse Width Access Time from CAS Precharge(15) READ-WRITE Cycle Time(24) Output Buffer Turn-Off Delay from CAS or RAS(13,15,19, 29) Output Disable Delay from WE Last CAS going LOW to First CAS returning HIGH(23) CAS Setup Time (CBR REFRESH)(30, 20) CAS Hold Time (CBR REFRESH)(30, 21) OE Setup Time prior to RAS during HIDDEN REFRESH Cycle Refresh Period (1024 Cycles) Transition Time (Rise or Fall)(2, 3) Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION 09/25/01 Rev. 00A -60 Min. 5 10 8 8 0 30 15 Max. — — — — — — — Min. 10 10 15 15 0 40 15 Max. — — — — — — — Units ns ns ns ns ns ns ns 8 — 15 — ns 0 6 80 45 — — — — 0 10 140 80 — — — — ns ns ns ns 25 30 12 — — — 36 49 25 — — — ns ns ns 35 — 40 3 100K 21 — 15 60 — 56 3 100K 34 — 15 ns ns ns ns 3 10 15 — 3 10 15 — ns ns 8 8 0 — — — 10 10 0 — — — ns ns ns — 1 16 50 — 1 16 50 ms ns 7 IS41C85125 IS41LV85125 ISSI ® Notes: 1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs. 3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. If CAS and RAS = VIH, data output is High-Z. 5. If CAS = VIL, data output may contain data from the last valid READ cycle. 6. Measured with a load equivalent to one TTL gate and 50 pF. 7. Assumes that tRCD - tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 8. Assumes that tRCD • tRCD (MAX). 9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data output buffer, CAS and RAS must be pulsed for tCP. 10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC. 11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA. 12. Either tRCH or tRRH must be satisfied for a READ cycle. 13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. 14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS • tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD • tRWD (MIN), tAWD • tAWD (MIN) and tCWD • tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle. 15. Output parameter (I/O) is referenced to corresponding CAS input, 16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE WRITE or READ-MODIFY-WRITE is not possible. 17. Write command is defined as WE going low. 18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and OE is taken back to LOW after tOEH is met. 19. The I/Os are in open during READ cycles once tOD or tOFF occur. 20. The first χCAS edge to transition LOW. 21. The last χCAS edge to transition HIGH. 22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles. 23. Last falling χCAS edge to first rising χCAS edge. 24. Last rising χCAS edge to next cycle’s last rising χCAS edge. 25. Last rising χCAS edge to first falling χCAS edge. 26. Each χCAS must meet minimum pulse width. 27. Last χCAS to go LOW. 28. I/Os controlled, regardless of CAS. 29. The 3 ns minimum is a parameter guaranteed by design. 30. Enables on-chip refresh and address counters. 8 Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 09/25/01 IS41C85125 IS41LV85125 ISSI ® AC WAVEFORMS FAST-PAGE-MODE READ CYCLE tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD tRRH CAS tAR tRAD tASR ADDRESS tRAH tRAL tCAH tASC Row Column Row tRCS tRCH WE tAA tRAC tCAC tCLC tOFF(1) Open I/O Open Valid Data tOE tOD OE tOES Don't Care Note: 1. tOFF is referenced from rising edge of CAS. Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION 09/25/01 Rev. 00A 9 IS41C85125 IS41LV85125 ISSI ® FAST PAGE MODE READ-MODIFY-WRITE CYCLE tRASP tRP RAS tPRWC tCAS tCSH tCAS tCRP tRCD tRSH tCAS tCP tCRP tCP CAS tAR tRAH tRAD tASC tASR ADDRESS tCPWD tRAL tCAH tCPWD Row tCAH tAR Column tASC Column tCWL tRWD tAWD tCWD tRCS tCAH tASC Column tCWL tRWL tCWL tAWD tCWD tWP tAWD tCWD tWP tWP WE tAA tAA tCAC tCAC tOEA OE tCAC tOEA tOEZ tOED tRAC tOEA tOEZ tOED OUT IN tOEZ tOED tDH tDH tDS tCLZ tCLZ I/O tAA tDS OUT IN tDH tCLZ OUT tDS IN Don't Care 10 Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 09/25/01 IS41C85125 IS41LV85125 ISSI ® FAST-PAGE-MODE EARLY WRITE CYCLE (OE = DON'T CARE) tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD CAS tAR tRAD tRAH tASR ADDRESS tRAL tCAH tACH tASC Row Column Row tCWL tRWL tWCR tWCS tWCH tWP WE tDHR tDS I/O tDH Valid Data Don't Care Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION 09/25/01 Rev. 00A 11 IS41C85125 IS41LV85125 ISSI ® FAST-PAGE-MODE READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles) tRWC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD CAS tAR tRAD tASR tRAH tRAL tCAH tASC tACH ADDRESS Row Column Row tRWD tCWL tRWL tCWD tRCS tAWD tWP WE tAA tRAC tCAC tCLZ I/O tDS Open Valid DOUT tOE tOD tDH Valid DIN Open tOEH OE Don't Care 12 Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 09/25/01 IS41C85125 IS41LV85125 ISSI ® FAST PAGE MODE EARLY WRITE CYCLE tRASP tRP RAS tCAS tCRP tRHCP tRSH tCAS tPC tCAS tCSH tRCD tCP tCRP tCP CAS tAR tRAL tRAD tRAH tASC tASR ADDRESS Row tCAH tCAH tAR Column tASC Column Column tCWL tWCS tWCH tCAH tASC tCWL tWP tCWL tWCH tWCS tWCS tWP tWCH tWP WE tWCR OE tDHR tDS tDH Valid DIN I/O tDS tDH Valid DIN tDS tDH Valid DIN Don't Care Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION 09/25/01 Rev. 00A 13 IS41C85125 IS41LV85125 ISSI ® READ CYCLE (With WE-Controlled Disable) RAS tCSH tCRP tRCD tCP tCAS CAS tAR tRAD tRAH tASR ADDRESS tCAH tASC Row tASC Column Column tRCS tRCH tRCS WE tAA tRAC tCAC tCLZ Open I/O tWHZ tCLZ Valid Data Open tOE tOD OE Don't Care RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE) tRC tRAS tRP RAS tCRP tRPC CAS tASR ADDRESS I/O tRAH Row Row Open Don't Care 14 Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 09/25/01 IS41C85125 IS41LV85125 ISSI ® CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE) tRP tRAS tRP tRAS RAS tRPC tCP tCHR tCHR tRPC tCSR tCSR CAS Open I/O HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW) tRAS tRP tRAS RAS tCRP tRCD tASR tRAD tRAH tASC tRSH tCHR CAS tAR ADDRESS Row tRAL tCAH Column tAA tRAC tOFF(2) tCAC tCLZ Open I/O Valid Data tOE Open tOD tORD OE Don't Care Notes: 1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH. 2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last. Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION 09/25/01 Rev. 00A 15 IS41C85125 IS41LV85125 ISSI ORDERING INFORMATION IS41C85125 Commercial Range: 0⋅⋅ C to 70⋅⋅ C Speed (ns) Order Part No. 35 60 IS41C85125-35K IS41C85125-60K Package 28-pin, 400-mil SOJ 28-pin, 400-mil SOJ IS41LV85125 Commercial Range: 0⋅⋅ C to 70⋅⋅ C Speed (ns) Order Part No. 35 60 Package IS41LV85125-35K IS41LV85125-60K 28-pin, 400-mil SOJ 28-pin, 400-mil SOJ Industrial Range: –40⋅⋅C to 85⋅⋅ C Industrial Range: –40⋅⋅C to 85⋅⋅ C Speed (ns) Order Part No. Speed (ns) Order Part No. 35 60 IS41C85125-35KI IS41C85125-60KI Package 28-pin, 400-mil SOJ 28-pin, 400-mil SOJ ® 60 Package IS41LV85125-60KI 28-pin, 400-mil SOJ ISSI ® Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: [email protected] www.issi.com 16 Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 09/25/01