ISSI IS42S16400J-6TL

IS42S16400J
IS45S16400J
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
FEATURES
• Clock frequency: 200, 166, 143, 133 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Self refresh modes
• Auto refresh (CBR)
• 4096 refresh cycles every 64 ms (Com, Ind, A1
grade) or 16ms (A2 grade)
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
OPTIONS
• Package:
54-pin TSOP II
54-ball TF-BGA (8mm x 8mm)
60-ball TF-BGA (10.1mm x 6.4mm)
• Operating Temperature Range
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
Automotive Grade A1 (-40oC to +85oC)
Automotive Grade A2 (-40oC to +105oC)
MAY 2013
OVERVIEW
ISSI's 64Mb Synchronous DRAM is organized as 1,048,576
bits x 16-bit x 4-bank for improved performance. The
synchronous DRAMs achieve high-speed data transfer
using pipeline architecture. All inputs and outputs signals
refer to the rising edge of the clock input.
KEY TIMING PARAMETERS
Parameter
Clk Cycle Time
CAS Latency = 3
CAS Latency = 2
Clk Frequency
CAS Latency = 3
CAS Latency = 2
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
-5
5
7.5
200
133
4.8
5.4
-6
6
7.5
166
133
5.4
5.4
-7Unit
7
ns
7.5
ns
143 Mhz
133 Mhz
5.4
ns
5.4
ns
ADDRESS TABLE
Parameter
4M x 16
Configuration
1M x 16 x 4
banks
Refresh Count
Com./Ind. 4K/64ms
A1 4K/64ms
A2 4K/16ms
Row Addresses
A0-A11
Column Addresses
A0-A7
Bank Address Pins
BA0, BA1
Auto Precharge Pins
A10/AP
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
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Rev. D
5/28/2013
IS42S16400J
IS45S16400J
GENERAL DESCRIPTION
The 64Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V
memory systems containing 67,108,864 bits. Internally
configured as a quad-bank DRAM with a synchronous
interface. Each 16,777,216-bit bank is organized as 4,096
rows by 256 columns by 16 bits.
The 64Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible.
The 64Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE function
enabled. Precharge one bank while accessing one of the
other three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
SDRAM read and write accesses are burst oriented starting
at a selected location and continuing for a programmed
number of locations in a programmed sequence. The
registration of an ACTIVE command begins accesses,
followed by a READ or WRITE command. The ACTIVE
command in conjunction with address bits registered are
used to select the bank and row to be accessed (BA0,
BA1 select the bank; A0-A11 select the row). The READ
or WRITE commands in conjunction with address bits
registered are used to select the starting column location
for the burst access.
Programmable READ or WRITE burst lengths consist of
1, 2, 4 and 8 locations, or full page, with a burst terminate
option.
FUNCTIONAL BLOCK DIAGRAM
DQM
DATA IN
BUFFER
COMMAND
DECODER
&
CLOCK
GENERATOR
16
MODE
REGISTER
12
DQ 0-15
SELF
REFRESH
A11
CONTROLLER
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
16
REFRESH
CONTROLLER
16
VDD/VDDQ
DATA OUT
BUFFER
GND/GNDQ
16
12
MULTIPLEXER
REFRESH
COUNTER
ROW
ADDRESS
LATCH
12
12
COLUMN
ADDRESS LATCH
ROW
ADDRESS
BUFFER
ROW DECODER
CLK
CKE
CS
RAS
CAS
WE
A10
4096
4096
4096
4096
MEMORY CELL
ARRAY
BANK 0
SENSE AMP I/O GATE
256K
(x 16)
BANK CONTROL LOGIC
8
BURST COUNTER
COLUMN
ADDRESS BUFFER
2
COLUMN DECODER
8
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IS45S16400J
PIN CONFIGURATION
PACKAGE CODE: B 54 BALL TF-BGA (Top View) (8 mm x 8 mm Body, 0.8 mm Ball Pitch)
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
GND DQ15 GNDQ
VDDQ DQ0
VDD
DQ14 DQ13 VDDQ
GNDQ DQ2
DQ1
DQ12 DQ11 GNDQ
VDDQ DQ4
DQ3
DQ10 DQ9 VDDQ
GNDQ DQ6
DQ5
DQ8
NC
GND
VDD DQML DQ7
DQMH CLK
CKE
CAS
RAS
WE
NC
A11
A9
BA0
BA1
CS
A8
A7
A6
A0
A1
A10
GND
A5
A4
A3
A2
VDD
PIN DESCRIPTIONS
A0-A11
A0-A7
BA0, BA1
DQ0 to DQ15
CLK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Addresses
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
LDQM, UDQM
Vdd
GND
Vddq
GNDQ
NC
Write Enable
x16 Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
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PIN CONFIGURATION
PACKAGE CODE: B2 60 BALL TF-BGA (Top View) (10.1 mm x 6.4 mm Body, 0.65 mm Ball Pitch)
1 2 3 4 5 6 7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
GND DQ15
DQ0
VDD
DQ14 GNDQ
VDDQ DQ1
DQ13 VDDQ
GNDQ DQ2
DQ12 DQ11
DQ4
DQ3
DQ10 GNDQ
VDDQ DQ5
DQ9 VDDQ
GNDQ DQ6
DQ8
NC
NC
DQ7
NC
NC
VDD
NC
LDQM
WE
NC UDQM
NC
CLK
RAS
CAS
CKE
NC
NC
CS
A11
A9
BA1
BA0
A8
A7
A0
A10
A6
A5
A2
A1
GND
A4
A3
VDD
PIN DESCRIPTIONS
A0-A11 A0-A7
BA0, BA1
DQ0 to DQ15
CLK
CKE
CS
RAS
CAS
4
Row Address Input
Column Address Input
Bank Select Addresses
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
LDQM, UDQM
Vdd
GND
Vddq
GNDq NC
Write Enable
x16 Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
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Rev. D
5/28/2013
IS42S16400J
IS45S16400J
PIN CONFIGURATIONS
54 pin TSOP - Type II
VDD
1
54
GND
DQ0
2
53
DQ15
VDDQ
3
52
GNDQ
DQ1
4
51
DQ14
DQ2
5
50
DQ13
GNDQ
6
49
VDDQ
DQ3
7
48
DQ12
DQ4
8
47
DQ11
VDDQ
9
46
GNDQ
DQ5
10
45
DQ10
DQ6
11
44
DQ9
GNDQ
12
43
VDDQ
DQ7
13
42
DQ8
VDD
14
41
GND
LDQM
15
40
NC
WE
16
39
UDQM
CAS
17
38
CLK
RAS
18
37
CKE
CS
19
36
NC
BA0
20
35
A11
BA1
21
34
A9
A10
22
33
A8
A0
23
32
A7
A1
24
31
A6
A2
25
30
A5
A3
26
29
A4
VDD
27
28
GND
PIN DESCRIPTIONS
A0-A11 A0-A7
BA0, BA1
DQ0 to DQ15
CLK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
Write Enable
LDQM x16 Lower Byte, Input/Output Mask
UDQM x16 Upper Byte, Input/Output Mask
VddPower
GND
Ground
Vddq
Power Supply for I/O Pin
GNDq Ground for I/O Pin
NC
No Connection
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Rev. D
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PIN FUNCTIONS
Symbol
A0-A11
BA0, BA1
TSOP Pin No.
Type
23 to 26
Input Pin
29 to 34
22, 35
20, 21
Input Pin
CAS
17
Input Pin
CKE
37
Input Pin
CLK
38
Input Pin
CS
19
Input Pin
DQ0 to
DQ15
LDQM,
UDQM
2, 4, 5, 7, 8, 10,
11,13, 42, 44, 45,
47, 48, 50, 51, 53
15, 39
DQ Pin
Input Pin
RAS
18
Input Pin
WE
16
Input Pin
3, 9, 43, 49
1, 14, 27
6, 12, 46, 52
28, 41, 54
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Vddq
Vdd
GNDq
GND
6
Function
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE command (A0-A7
with A10 defining auto precharge) to select one location out of the memory array
in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE
or PRECHARGE command is being applied.
CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" for details on device commands.
The CKE input determines whether the CLK input is enabled. The next rising edge
of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE
is LOW, the device will be in either power-down mode, clock suspend mode, or self
refresh mode. CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH.
DQ0 to DQ15 are I/O pins. I/O through these pins can be controlled in byte units
using the LDQM and UDQM pins.
LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read
mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW,
the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs
go to the HIGH impedance state when LDQM/UDQM is HIGH. This function corresponds to OE in conventional DRAMs. In write mode, LDQM and UDQM control
the input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can be written to the device. When LDQM or UDQM is HIGH, input
data is masked and cannot be written to the device.
RAS, in conjunction with CAS and WE, forms the device command. See the "Command Truth Table" item for details on device commands.
WE, in conjunction with RAS and CAS, forms the device command. See the "Command Truth Table" item for details on device commands.
Vddq is the output buffer power supply.
Vdd is the device internal power supply.
GNDq is the output buffer ground.
GND is the device internal ground.
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IS42S16400J
IS45S16400J
READ
The READ command selects the bank from BA0, BA1 inputs
and starts a burst read access to an active row. Inputs
A0-A7 provides the starting column location. When A10 is
HIGH, this command functions as an AUTO PRECHARGE
command. When the auto precharge is selected, the row
being accessed will be precharged at the end of the READ
burst. The row will remain open for subsequent accesses
when AUTO PRECHARGE is not selected. DQ’s read
data is subject to the logic level on the DQM inputs two
clocks earlier. When a given DQM signal was registered
HIGH, the corresponding DQ’s will be High-Z two clocks
later. DQ’s will provide valid data when the DQM signal
was registered LOW.
WRITE
A burst write access to an active row is initiated with the
WRITE command. BA0, BA1 inputs selects the bank,
and the starting column location is provided by inputs
A0-A7. Whether or not AUTO-PRECHARGE is used is
determined by A10.
The row being accessed will be precharged at the end of
the WRITE burst, if AUTO PRECHARGE is selected. If
AUTO PRECHARGE is not selected, the row will remain
open for subsequent accesses.
A memory array is written with corresponding input data
on DQ’s and DQM input logic level appearing at the same
time. Data will be written to memory when DQM signal is
LOW. When DQM is HIGH, the corresponding data inputs
will be ignored, and a WRITE will not be executed to that
byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open
row in a particular bank or the open row in all banks. BA0,
BA1 can be used to select which bank is precharged or they
are treated as “Don’t Care”. A10 determines whether one
or all banks are precharged. After executing this command,
the next command for the selected bank(s) is executed after
passage of the period tRP, which is the period required for
bank precharging. Once a bank has been precharged, it
is in the idle state and must be activated prior to any READ
or WRITE commands being issued to that bank.
AUTO PRECHARGE
The AUTO PRECHARGE function ensures that the
precharge is initiated at the earliest valid stage within a
burst. This function allows for individual-bank precharge
without requiring an explicit command. A10 can be used
to enable the AUTO PRECHARGE function in conjunction with a specific READ or WRITE command. For each
individual READ or WRITE command, auto precharge is
either enabled or disabled. AUTO PRECHARGE does not
apply except in full-page burst mode. Upon completion of
the READ or WRITE burst, a precharge of the bank/row
that is addressed is automatically performed.
AUTO REFRESH COMMAND
This command executes the AUTO REFRESH operation. The row address and bank to be refreshed are automatically
generated during this operation. The stipulated period (trc) is
required for a single refresh operation, and no other commands can be executed during this period. This command
is executed at least 4096 times every Tref. During an AUTO
REFRESH command, address bits are “Don’t Care”. This
command corresponds to CBR Auto-refresh.
SELF REFRESH
During the SELF REFRESH operation, the row address to
be refreshed, the bank, and the refresh interval are generated automatically internally. SELF REFRESH can be
used to retain data in the SDRAM without external clocking,
even if the rest of the system is powered down. The SELF
REFRESH operation is started by dropping the CKE pin
from HIGH to LOW. During the SELF REFRESH operation
all other inputs to the SDRAM become “Don’t Care”. The
device must remain in self refresh mode for a minimum
period equal to tras or may remain in self refresh mode
for an indefinite period beyond that. The SELF-REFRESH
operation continues as long as the CKE pin remains LOW
and there is no need for external control of any other pins.
The next command cannot be executed until the device
internal recovery period (trc) has elapsed. Once CKE
goes HIGH, the NOP command must be issued (minimum
of two clocks) to provide time for the completion of any
internal refresh in progress. After the self-refresh, since it
is impossible to determine the address of the last row to
be refreshed, an AUTO-REFRESH should immediately be
performed for all addresses.
BURST TERMINATE
The BURST TERMINATE command forcibly terminates
the burst read and write operations by truncating either
fixed-length or full-page bursts and the most recently
registered READ or WRITE command prior to the BURST
TERMINATE.
COMMAND INHIBIT
COMMAND INHIBIT prevents new commands from being
executed. Operations in progress are not affected, apart
from whether the CLK signal is enabled
NO OPERATION
When CS is low, the NOP command prevents unwanted
commands from being registered during idle or wait
states.
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LOAD MODE REGISTER
During the LOAD MODE REGISTER command the mode
register is loaded from A0-A11. This command can only
be issued when all banks are idle.
ACTIVE COMMAND
When the ACTIVE COMMAND is activated, BA0, BA1
inputs selects a bank to be accessed, and the address
inputs on A0-A11 selects the row. Until a PRECHARGE
command is issued to the bank, the row remains open
for accesses.
8
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TRUTH TABLE – COMMANDS AND DQM OPERATION(1)
FUNCTION
CS
COMMAND INHIBIT (NOP)
H
NO OPERATION (NOP)
L
(3)
ACTIVE (Select bank and activate row) L
(4)
READ (Select bank/column, start READ burst) L
WRITE (Select bank/column, start WRITE burst)(4) L
BURST TERMINATE
L
(5)
PRECHARGE (Deactivate row in bank or banks) L
AUTO REFRESH or SELF REFRESH(6,7)
L
(Enter self refresh mode)
LOAD MODE REGISTER(2)
L
(8)
Write Enable/Output Enable ­—
Write Inhibit/Output High-Z(8)
­—
RAS
X
H
L
H
H
H
L
L
CAS
X
H
H
L
L
H
H
L
L
­—
L
­—
L
­—
­—
­—
­—
ADDR
X
X
Bank/Row
Bank/Col
Bank/Col
X
Code
X
DQs
X
X
X
X
Valid
Active
X
X
X
L
Op-Code
­—
X
Active
H
­—
High-Z
WEDQM
X
X
H
X
H
X
H
L/H(8)
L
L/H(8)
L
X
L
X
H
X
NOTES:
1. CKE is HIGH for all commands except SELF REFRESH.
2. A0-A11 define the op-code written to the mode register.
3. A0-A11 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-A7 (x16) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables
auto precharge; BA0, BA1 determine which bank is being read from or written to.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.”
6. AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
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TRUTH TABLE – CKE (1-4)
CURRENT STATE
Power-Down
Self Refresh
Clock Suspend
Power-Down(5)
Self Refresh(6)
Clock Suspend(7)
All Banks Idle
All Banks Idle
Reading or Writing
COMMANDn
X
X
X
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
X
COMMAND INHIBIT or NOP
AUTO REFRESH
VALID
ACTIONn
Maintain Power-Down
Maintain Self Refresh
Maintain Clock Suspend
Exit Power-Down
Exit Self Refresh
Exit Clock Suspend
Power-Down Entry
Self Refresh Entry
Clock Suspend Entry
CKEn-1
L
L
L
L
L
L
H
H
H
See TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK n H
CKEn
L
L
L
H
H
H
L
L
L
H
NOTES:
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTONn is a result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n+1 (provided that tcks is
met).
6. Exiting self refresh at clock edge n will put the device in all banks idle state once txsr is met. COMMAND INHIBIT or NOP
commands should be issued on clock edges occurring during the txsr period. A minimum of two NOP commands must be sent
during txsr period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge
n+1.
TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK n (1-6)
CURRENT STATE
Any
Idle
Row Active
Read
(Auto
Precharge
Disabled)
Write
(Auto
Precharge
Disabled)
COMMAND (ACTION)
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
ACTIVE (Select and activate row)
AUTO REFRESH(7)
LOAD MODE REGISTER(7)
PRECHARGE(11)
READ (Select column and start READ burst)(10)
WRITE (Select column and start WRITE burst)(10)
PRECHARGE (Deactivate row in bank or banks)(8)
READ (Select column and start new READ burst)(10)
WRITE (Select column and start WRITE burst)(10)
PRECHARGE (Truncate READ burst, start PRECHARGE)(8)
BURST TERMINATE(9)
READ (Select column and start READ burst)(10)
WRITE (Select column and start new WRITE burst)(10)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)(8)
BURST TERMINATE(9)
CS RASCASWE
H
X
X
X
L
H
H
H
L
L
H
H
L
L
L
H
L
L
L
L
L
L
H
L
L
H
L
H
L
H
L
L
L
L
H
L
L
H
L
H
L
H
L
L
L
L
H
L
L
H
H
L
L
H
L
H
L
H
L
L
L
L
H
L
L
H
H
L
NOTE:
1.This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table - CKE) and after txsr has been met (if the
previous state was SELF REFRESH).
2.This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those
allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
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3.Current state definitions:
Idle:The bank has been precharged, and trp has been met.
Row Active:A row in the bank has been activated, and trcd has been met. No data bursts/accesses and no register
accesses are in progress.
Read:A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
Write:A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
4.The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands,
or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and CURRENT STATE BANK n truth tables.
Precharging:Starts with registration of a PRECHARGE command and ends when trp is met. Once trp is met, the bank
will be in the idle state.
Row Activating:Starts with registration of an ACTIVE command and ends when trcd is met. Once trcd is met, the bank will
be in the row active state.
Read w/Auto
Precharge Enabled:Starts with registration of a READ command with auto precharge enabled and ends when trp has been
met. Once trp is met, the bank will be in the idle state.
Write w/Auto
Precharge Enabled:Starts with registration of a WRITE command with auto precharge enabled and ends when trp has been
met. Once trp is met, the bank will be in the idle state.
5.The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be
applied on each positive clock edge during these states.
Refreshing:Starts with registration of an AUTO REFRESH command and ends when trc is met. Once trc is met, the
SDRAM will be in the all banks idle state.
Accessing Mode
Register:Starts with registration of a LOAD MODE REGISTER command and ends when tmrd has been met. Once
tmrd is met, the SDRAM will be in the all banks idle state.
Precharging All:Starts with registration of a PRECHARGE ALL command and ends when trp is met. Once trp is met, all
banks will be in the idle state.
6.All states and sequences not shown are illegal or reserved.
7.Not bank-specific; requires that all banks are idle.
8.May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
9.Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
10.READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and
READs or WRITEs with auto precharge disabled.
11.Does not affect the state of the bank and acts as a NOP to that bank.
Integrated Silicon Solution, Inc. — www.issi.com11
Rev. D
5/28/2013
IS42S16400J
IS45S16400J
TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK m (1-6)
CURRENT STATE
Any
Idle
Row
Activating,
Active, or
Precharging
Read
(Auto
Precharge
Disabled)
COMMAND (ACTION)
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
Any Command Otherwise Allowed to Bank m
ACTIVE (Select and activate row)
READ (Select column and start READ burst)(7)
WRITE (Select column and start WRITE burst)(7)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)(7,10)
WRITE (Select column and start WRITE burst)(7,11)
PRECHARGE(9)
Write
(Auto
Precharge
Disabled)
Read
(With Auto
Precharge)
Write
(With Auto
Precharge)
ACTIVE (Select and activate row)
READ (Select column and start READ burst)(7,12)
WRITE (Select column and start new WRITE burst)(7,13)
PRECHARGE(9)
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)(7,8,14)
WRITE (Select column and start WRITE burst)(7,8,15)
PRECHARGE(9)
ACTIVE (Select and activate row)
READ (Select column and start READ burst)(7,8,16)
WRITE (Select column and start new WRITE burst)(7,8,17)
PRECHARGE(9)
CS RASCASWE
H
X
X
X
L
H
H
H
X
X
X
X
L
L
H
H
L
H
L
H
L
H
L
L
L
L
H
L
L
L
H
H
L
H
L
H
L
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
L
H
H
L
L
H
H
L
L
H
H
H
L
L
H
H
L
L
H
H
L
L
NOTE:
1.This table applies when CKE n-1 was HIGH and CKE n is HIGH (Truth Table - CKE) and after txsr has been met (if the previous state was self refresh).
2.This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands
shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below.
3.Current state definitions:
Idle:The bank has been precharged, and trp has been met.
Row Active:A row in the bank has been activated, and trcd has been met. No data bursts/accesses and no register
accesses are in progress.
Read:A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
Write:A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
Read w/Auto
Precharge Enabled:Starts with registration of a READ command with auto precharge enabled, and ends when trp has been
met. Once trp is met, the bank will be in the idle state.
Write w/Auto
Precharge Enabled:Starts with registration of a WRITE command with auto precharge enabled, and ends when trp has been
met. Once trp is met, the bank will be in the idle state.
4.AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5.A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state
only.
6.All states and sequences not shown are illegal or reserved.
7.READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled
and READs or WRITEs with auto precharge disabled.
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
5/28/2013
IS42S16400J
IS45S16400J
8.CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command when its burst has been interrupted by bank m’s burst.
9.Burst in bank n continues as initiated.
10.For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt
the READ on bank n, CAS latency later (Consecutive READ Bursts).
11.For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered (READ to WRITE). DQM should be used one clock prior to the WRITE command to
prevent bus contention.
12.For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt
the WRITE on bank n when registered (WRITE to READ), with the data-out appearing CAS latency later. The last valid WRITE
to bank n will be data-in registered one clock prior to the READ to bank m.
13.For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered (WRITE to WRITE). The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m.
14.For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the
READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Fig CAP
1).
15.For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt
the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention.
The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Fig CAP 2).
16.For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt
the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin
after tWR is met, where twr begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (Fig CAP 3).
17.For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt
the WRITE on bank n when registered. The PRECHARGE to bank n will begin after twr is met, where t WR begins when the
WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m
(Fig CAP 4).
Integrated Silicon Solution, Inc. — www.issi.com13
Rev. D
5/28/2013
IS42S16400J
IS45S16400J
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Parameters
VDD max
Maximum Supply Voltage
VDDq max
Maximum Supply Voltage for Output Buffer
Vin
Input Voltage
Vout
Output Voltage
Pd max
Allowable Power Dissipation
IcsOutput Shorted Current
Topr
Operating Temperature
Com.
Ind.
A1
A2
Tstg
Storage Temperature
Rating
–1.0 to +4.6
–1.0 to +4.6
–1.0 to Vddq + 0.5
–1.0 to Vddq + 0.5
1
50
0 to +70
-40 to +85
-40 to +85
-40 to +105
–65 to +150
Unit
V
V
V
V
W
mA
°C
°C
°C
°C
°C
DC RECOMMENDED OPERATING CONDITIONS(2)
(At Ta = 0 to +70°C for commercial grade. Ta = -40 to +85°C for industrial and A1 grade. Ta = -40 to +105°C for A2 grade)
Symbol
VDD, VDDq
Vih
Vil
Parameter
Supply Voltage
Input High Voltage(3)
Input Low Voltage(4)
Min.
3.0
2.0
-0.3
Typ. Max.
3.3
3.6
—
Vdd + 0.3
—
+0.8
Unit
V
V
V
CAPACITANCE CHARACTERISTICS(1,2) (At Ta = 0 to +25°C, Vdd = Vddq = 3.3 ± 0.3V, f = 1 MHz)
Symbol
Cin
Cclk
CI/O
Parameter
Input Capacitance: Address and Control
Input Capacitance: (CLK)
Data Input/Output Capacitance: I/O0-I/O15
Typ. Max. Unit
—
3.8
pF
—
3.5
pF
—
6.5
pF
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2. All voltages are referenced to GND.
3. Vih(max) = Vddq + 1.2V with a pulse width < 3ns.
4. Vil(min) = GND - 1.2V with a pulse width < 3ns.
THERMAL RESISTANCE
Package
Substrate
Theta-ja
(Airflow = 0m/s)
Theta-ja
(Airflow = 1m/s)
Theta-ja
(Airflow = 2m/s)
Theta-jc
Units
Alloy42 TSOP2(54)
4-layer
88.0
81
77.4
16.1
C/W
Copper TSOP2(54)
4-layer
51.7
49.0
47.7
11.9
C/W
BGA(54)
4-layer
50.5
44.6
41.7
11.3
C/W
BGA(60)
4-layer
48.3
42.3
41
7.5
C/W
14
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
5/28/2013
IS42S16400J
IS45S16400J
DC ELECTRICAL CHARACTERISTICS 1 (Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
-5 -6
(1)
Idd1 Operating Current
One bank active, CL = 3, BL = 1, 90 80
tclk = tclk (min), trc = trc (min)
Idd2p
Precharge Standby Current CKE ≤ Vil (max), tck = 15ns 2 2
(In Power-Down Mode)
CS ≥ Vdd - 0.2V
Idd2ps
Precharge Standby Current CKE ≤ Vil (max), CLK ≤ Vil (max)
2 2
with clock stop
CS ≥ Vdd - 0.2V
(In Power-Down Mode)
(2)
Idd2n Precharge Standby Current CS ≥ Vdd - 0.2V, CKE ≥ Vih (min)
20 20
(In Non Power-Down Mode) tck = 15ns
Idd2ns
Precharge Standby Current CS ≥ Vdd - 0.2V, CKE ≥ Vih (min)
10 10
with clock stop
(In Non Power-Down Mode) All inputs stable
(2)
Idd3p Active Standby Current
CKE ≤ Vil (max), CS ≥ Vdd - 0.2V
6 6
(In Power-Down Mode)
tck = 15ns
Idd3ps
Active Standby Current
CKE ≤ Vil (max), CLK ≤ Vil (max),
6 6
with clock stop
CS ≥ Vdd - 0.2V
(In Power-Down Mode)
(2)
Idd3n Active Standby Current
CS ≥ Vdd - 0.2V, CKE ≥ Vih (min)
25 25
(In Non Power-Down Mode) tck = 15ns
Idd3ns
Active Standby Current
CS ≥ Vdd - 0.2V, CKE ≥ Vih (min)
20 20
with clock stop
All inputs stable
(In Non Power-Down Mode) Idd4
Operating Current
All banks active, BL = 4, CL = 3, 110 100
tck = tck (min)
Idd5
Auto-Refresh Current
trc = trc (min), tclk = tclk (min) 110 100
Idd6
Self-Refresh Current
CKE ≤ 0.2V
2 2
-7
70
Unit
mA
2
mA
2
mA
20
mA
10
mA
6
mA
6
mA
25
mA
20
mA
90
mA
90
2
mA
mA
Notes:
1. Idd (max) is specified at the output open condition.
2. Input signals are changed one time during 30ns.
DC ELECTRICAL CHARACTERISTICS 2 (Recommended Operation Conditions unless otherwise noted.)
Symbol
Iil
Iol
Voh
Vol
Parameter
Input Leakage Current
Output Leakage Current
Output High Voltage Level
Output Low Voltage Level
Test Condition
0V ≤ Vin ≤ Vdd, with pins other than
the tested pin at 0V
Output is disabled, 0V ≤ Vout ≤ Vdd,
Ioh = -2mA Iol = 2mA Min
-5
-5
2.4
—
MaxUnit
5
µA
5
—
0.4
µA
V
V
Integrated Silicon Solution, Inc. — www.issi.com15
Rev. D
5/28/2013
IS42S16400J
IS45S16400J
AC ELECTRICAL CHARACTERISTICS (1,2,3)
-5-6-7
Symbol
Parameter
Min.Max. Min.Max. Min.Max. Units
tck3
Clock Cycle Time
CAS Latency = 3
5
—
6
—
7
—
ns
tck2
CAS Latency = 2
7.5
—
7.5
—
7.5
—
ns
tac3
Access Time From CLK(4,6)
CAS Latency = 3
—
4.8
—
5.4
—
5.4
ns
tac2
CAS Latency = 2
—
5.4
—
5.4
—
5.4
ns
tch
CLK HIGH Level Width
2
—
2
—
2.5
—
ns
tcl
CLK LOW Level Width
2
—
2
—
2.5
—
ns
(6)
toh3
Output Data Hold Time CAS Latency = 3
2.5
—
2.5
—
2.7
—
ns
toh2
CAS Latency = 2
2.5
—
2.5
—
2.7
—
ns
tlz
Output LOW Impedance Time
0
—
0
—
0
—
ns
thz3
Output HIGH Impedance Time(5) CAS Latency = 3
—
4.8
—
5.4
—
5.4
ns
thz2
CAS Latency = 2
—
5.4
—
5.4
—
5.4
ns
tds
Input Data Setup Time
1.5
—
1.5
—
1.5
—
ns
tdh
Input Data Hold Time
0.8
—
0.8
—
0.8
—
ns
tas
Address Setup Time
1.5
—
1.5
—
1.5
—
ns
tah
Address Hold Time
0.8
—
0.8
—
0.8
—
ns
tcks
CKE Setup Time
1.5
—
1.5
—
1.5
—
ns
tckh
CKE Hold Time
0.8
—
0.8
—
0.8
—
ns
tcka
CKE to CLK Recovery Delay Time
1CLK+3— 1CLK+3— 1CLK+3 —ns
tcms
Command Setup Time (CS, RAS, CAS, WE, DQM)
1.5— 1.5— 1.5— ns
tcmh
Command Hold Time (CS, RAS, CAS, WE, DQM)
0.8— 0.8— 0.8— ns
trc
Command Period (REF to REF / ACT to ACT)
55
—
60
—
63
—
ns
tras
Command Period (ACT to PRE)
40 100,00042
100,00042
100,000ns
trp
Command Period (PRE to ACT)
15
—
15
—
15
—
ns
trcd
Active Command To Read / Write Command Delay Time
15
—
15
—
15
—
ns
trrd
Command Period (ACT [0] to ACT[1])
10
—
12
—
14
—
ns
tdpl or Input Data To Precharge
CAS Latency = 3
2CLK
—
2CLK
—
2CLK
—
ns
twr
Command Delay time
CAS Latency = 2
2CLK
—
2CLK
—
2CLK
—
ns
tdal
Input Data To Active / Refresh
CAS Latency = 3
2CLK+trp —
2CLK+trp —
2CLK+trp —ns
Command Delay time
(During Auto-Precharge)
CAS Latency = 2
2CLK+trp —
2CLK+trp —
2CLK+trp —ns
tt
Transition Time
0.3
1.2
0.3
1.2
0.3
1.2
ns
txsr
Exit Self-Refresh to Active Time
60
—
66
—
70
—
ns
tref
Refresh Cycle Time (4096)
Ta ≤ 70oC Com., Ind., A1, A2
—
64
—
64
—
64
ms
Ta ≤ 85oC Ind., A1, A2
—
—
—
64
—
64
ms
Ta > 85oC A2
—
—
—
—
—
16
ms
Notes:
1. When power is first applied, memory operation should be started 200 µs after Vdd and Vddq reach their stipulated voltages. Also
note that the power-on sequence must be executed before starting memory operation.
2. Measured with tt = 1 ns.
3. The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between Vih (min.) and Vil
(max.).
4. Access time is measured at 1.4V with the load shown in the figure below.
5. The time thz (max.) is defined as the time required for the output voltage to transition by ± 200 mV from Voh (min.) or Vol (max.)
when the output is in the high impedance state.
6. If clock rising time is longer than 1ns, tt/2 - 0.5ns should be added to the parameter.
16
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
5/28/2013
IS42S16400J
IS45S16400J
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SYMBOL
PARAMETER
tck
Clock Cycle Time
CL=3
CL=2
Freq.
Operating Frequency
CL=3
CL=2
tccd
READ/WRITE command to READ/WRITE command
tcked
CKE to clock disable or power-down entry mode
tped
CKE to clock enable or power-down exit setup mode
tdqd
DQM to input data delay
tdqm
DQM to data mask during WRITEs
tdqz
DQM to data high-impedance during READs tdwd
WRITE command to input data delay
tdal
tdpl
tbdl
tcdl
trdl
tmrd
troh
Data-in to ACTIVE command
Data-in to PRECHARGE command
Last data-in to burst STOP command
Last data-in to new READ/WRITE command
Last data-in to PRECHARGE command
LOAD MODE REGISTER command
to ACTIVE or REFRESH command
Data-out to high-impedance from
PRECHARGE command
-5-6-7
UNITS
5
6
7
ns
7.5
7.5
7.5
ns
200
166
143
MHz
133
133
133
MHz
1
1
1
cycle
1
1
1
cycle
1
1
1
cycle
0
0
0
cycle
0
0
0
cycle
2
2
2
cycle
0
0
0
cycle
CL=3
CL=2
5
4
2
1
1
2
2
5
4
2
1
1
2
2
5
4
2
1
1
2
2
cycle
cycle
cycle
cycle
cycle
cycle
cycle
CL=3
CL=2
3
2
3
2
3
2
cycle
cycle
AC TEST CONDITIONS (Input/Output Reference Level: 1.4V)
Input Load
Output Load
tCK
tCL
tCH
3.0V
50 Ω
CLK 1.4V
0V
I/O
tCMS
tCMH
+1.4V
50 pF
3.0V
INPUT 1.4V
0V
tAC
tOH
OUTPUT
1.4V
1.4V
Integrated Silicon Solution, Inc. — www.issi.com17
Rev. D
5/28/2013
IS42S16400J
IS45S16400J
FUNCTIONAL DESCRIPTION
Initialization
The 64Mb SDRAMs (1 Meg x 16 x 4 banks) are quad-bank
DRAMs which operate at 3.3V and include a synchronous
interface (all signals are registered on the positive edge of
the clock signal, CLK). Each of the 16,777,216-bit banks is
organized as 4,096 rows by 256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to
be accessed (BA0 and BA1 select the bank, A0-A11 select the
row).The address bits (A0-A7) registered coincident with the
READ or WRITE command are used to select the starting
column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information
covering device initialization, register definition, command
descriptions and device operation.
SDRAMs must be powered up and initialized in a
predefined manner.
The 64Mb SDRAM is initialized after the power is applied
to Vdd and Vddq (simultaneously), and the clock is stable
with DQM High and CKE High.
A 100µs delay is required prior to issuing any command
other than a COMMAND INHIBIT or a NOP. The COMMAND
INHIBIT or NOP may be applied during the 100µs period and
continue should at least through the end of the period.
With at least one COMMAND INHIBIT or NOP command
having been applied, a PRECHARGE command should
be applied once the 100µs delay has been satisfied. All
banks must be precharged. This will leave all banks in
an idle state, after which at least two AUTO REFRESH cycles
must be performed. After the AUTO REFRESH cycles are
complete, the SDRAM is then ready for mode register
programming.
The mode register should be loaded prior to applying
any operational command because it will power up in an
unknown state. After the Load Mode Register command,
at least one NOP command must be asserted prior to
any command.
18
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Rev. D
5/28/2013
IS42S16400J
IS45S16400J
REGISTER DEFINITION
Mode Register
Mode register bits M0-M2 specify the burst length, M3
specifies the type of burst (sequential or interleaved), M4- M6
specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifies the WRITE burst mode, and M10 and
M11 are reserved for future use.
The mode register must be loaded when all banks are
idle, and the controller must wait the specified time before
initiating the subsequent operation.Violating either of these
requirements will result in unspecified operation.
The mode register is used to define the specific mode
of operation of the SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency,
an operating mode and a write burst mode, as shown in
MODE REGISTER DEFINITION.
The mode register is programmed via the LOAD MODE
REGISTER command and will retain the stored information
until it is programmed again or the device loses power.
MODE REGISTER DEFINITION
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
Mode Register (Mx)
Burst Length
(1)
Reserved
M2
M1
M0
M3=0
M3=1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
Reserved
Reserved
Reserved
Full Page
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Burst Type
M3
Type
0
1
Sequential
Interleaved
Latency Mode
M6 M5 M4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Operating Mode
M8 M7
M6-M0
Mode
0 0
— —
Defined
—
Standard Operation
All Other States Reserved
Write Burst Mode
M9
0
1
Mode
Programmed Burst Length
Single Location Access
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
5/28/2013
1. To ensure compatibility with future devices,
should program M11, M10 = "0, 0"
19
IS42S16400J
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Burst Length
Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown in
MODE REGISTER DEFINITION. The burst length determines the maximum number of column locations that can
be accessed for a given READ or WRITE command. Burst
lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a full-page
burst is available for the sequential type. The full-page
burst is used in conjunction with the BURST TERMINATE
command to generate arbitrary burst lengths.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, mean-
ing that the burst will wrap within the block if a boundary
is reached. The block is uniquely selected by A1-A7 (x16)
when the burst length is set to two; by A2-A7 (x16) when
the burst length is set to four; and by A3-A7 (x16) when the
burst length is set to eight. The remaining (least significant)
address bit(s) is (are) used to select the starting location
within the block. Full-page bursts wrap within the page if
the boundary is reached.
Burst Type
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in BURST DEFINITION table.
BURST DEFINITION
BurstStarting Column
Order of Accesses Within a Burst
Length
Address
Type = Sequential
Type = Interleaved
A0
2
0
0-1 0-1
1
1-0
1-0
A1 A0
0 0
0-1-2-3
0-1-2-3
4
0
1 1-2-3-0 1-0-3-2
1 0
2-3-0-1
2-3-0-1
1 1
3-0-1-2
3-2-1-0
A2A1A0
000 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
001 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
8
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
100 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
101 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
110 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
111 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Full
n = A0-A7 Cn, Cn + 1, Cn + 2
Not Supported
Page
Cn + 3, Cn + 4...
(y)
(location 0-y)
…Cn - 1,
Cn…
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CAS Latency
Operating Mode
The CAS latency is the delay, in clock cycles, between
the registration of a READ command and the availability of
the first piece of output data. The latency can be set to two or
three clocks.
If a READ command is registered at clock edge n, and
the latency is m clocks, the data will be available by clock
edge n + m. The DQs will start driving as a result of the
clock edge one cycle earlier (n + m - 1), and provided that
the relevant access times are met, the data will be valid by
clock edge n + m. For example, assuming that the clock
cycle time is such that all relevant access times are met,
if a READ command is registered at T0 and the latency
is programmed to two clocks, the DQs will start driving
after T1 and the data will be valid by T2, as shown in CAS
Latency diagrams. The Allowable Operating Frequency
table indicates the operating frequencies at which each
CAS latency setting can be used.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
The normal operating mode is selected by setting M7 and M8
to zero; the other combinations of values for M7 and M8 are
reserved for future use and/or test modes. The programmed
burst length applies to both READ and WRITE bursts.
Test modes and reserved states should not be used because unknown operation or incompatibility with future
versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1,
the programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses.
CAS Latency
Allowable Operating Frequency (MHz)
Speed
CAS Latency = 2
-5
133
-6­133
-7
133
CAS Latency = 3
200
166
143
CAS Latency
T0
T1
T2
T3
READ
NOP
NOP
CLK
COMMAND
tAC
DOUT
DQ
tOH
tLZ
CAS Latency - 2
T0
T1
T2
T3
T4
READ
NOP
NOP
NOP
CLK
COMMAND
tAC
DOUT
DQ
tLZ
tOH
CAS Latency - 3
DON'T CARE
UNDEFINED
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OPERATION
Activating Specific Row Within Specific Bank
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued
to a bank within the SDRAM, a row in that bank must be
“opened.” This is accomplished via the ACTIVE command,
which selects both the bank and the row to be activated
(see Activating Specific Row Within Specific Bank).
After opening a row (issuing an ACTIVE command), a READ
or WRITE command may be issued to that row, subject to
the trcd specification. Minimum trcd should be divided by
the clock period and rounded up to the next whole number
to determine the earliest clock edge after the ACTIVE
command on which a READ or WRITE command can be
entered. For example, a trcd specification of 20ns with a
125 MHz clock (8ns period) results in 2.5 clocks, rounded
to 3. This is reflected in the following example, which covers any case where 2 < [trcd (MIN)/tck] ≤ 3. (The same
procedure is used to convert other specification limits from
time units to clock cycles).
A subsequent ACTIVE command to a different row in the
same bank can only be issued after the previous active
row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the
same bank is defined by trc.
CLK
CKE
HIGH - Z
CS
RAS
CAS
WE
A0-A11
ROW ADDRESS
BA0, BA1
BANK ADDRESS
A subsequent ACTIVE command to another bank can be
issued while the first bank is being accessed, which results
in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to
different banks is defined by trrd.
Example: Meeting trcd (MIN) when 2 < [trcd (min)/tck] ≤ 3
T0
T1
T2
ACTIVE
NOP
NOP
T3
T4
CLK
COMMAND
READ or
WRITE
tRCD
DON'T CARE
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READS
READ bursts are initiated with a READ command, as
shown in the READ COMMAND diagram.
The starting column and bank addresses are provided with
the READ command, and auto precharge is either enabled or
disabled for that burst access. If auto precharge is enabled,
the row being accessed is precharged at the completion of
the burst. For the generic READ commands used in the following illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from the
starting column address will be available following the
CAS latency after the READ command. Each subsequent
data-out element will be valid by the next positive clock
edge. The CAS Latency diagram shows general timing
for each possible CAS latency setting.
Upon completion of a burst, assuming no other commands
have been initiated, the DQs will go High-Z. A full-page burst
will continue until terminated. (At the end of the page, it will
wrap to column 0 and continue.)
Data from any READ burst may be truncated with a subsequent READ command, and data from a fixed-length
READ burst may be immediately followed by data from a
READ command. In either case, a continuous flow of data
can be maintained. The first data element from the new
burst follows either the last element of a completed burst
or the last desired data element of a longer burst which
is being truncated.
The new READ command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This is
shown in Consecutive READ Bursts for CAS latencies of
two and three; data element n + 3 is either the last of a
burst of four or the last desired of a longer burst. The 64Mb
SDRAM uses a pipelined architecture and therefore does
not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle
following a previous READ command. Full-speed random
read accesses can be performed to the same bank, as
shown in Random READ Accesses, or each subsequent
READ may be performed to a different bank.
Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length
READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations).
The WRITE burst may be initiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be
avoided. In a given system design, there may be a possibility that the device driving the input data will go Low-Z
before the SDRAM DQs go High-Z. In this case, at least
a single-cycle delay should occur between the last read
data and the WRITE command.
READ COMMAND
CLK
CKE
HIGH-Z
CS
RAS
CAS
WE
A0-A7
COLUMN ADDRESS
A8, A9, A11
AUTO PRECHARGE
A10
NO PRECHARGE
BA0, BA1
BANK ADDRESS
The DQM input is used to avoid I/O contention, as shown
in Figures RW1 and RW2. The DQM signal must be asserted (HIGH) at least three clocks prior to the WRITE
command (DQM latency is two clocks for output buffers)
to suppress data-out from the READ. Once the WRITE
command is registered, the DQs will go High-Z (or remain
High-Z), regardless of the state of the DQM signal, provided
the DQM was active on the clock just prior to the WRITE
command that truncated the READ command. If not, the
second WRITE will be an invalid WRITE. For example, if
DQM was LOW during T4 in Figure RW2, then the WRITEs
at T5 and T7 would be valid, while the WRITE at T6 would
be invalid.
The DQM signal must be de-asserted prior to the WRITE
command (DQM latency is zero clocks for input buffers)
to ensure that the written data is not masked.
A fixed-length READ burst may be followed by, or truncated
with, a PRECHARGE command to the same bank (provided
that auto precharge was not activated), and a full-page burst
may be truncated with a PRECHARGE command to the
same bank.The PRECHARGE command should be issued
x cycles before the clock edge at which the last desired
data element is valid, where x equals the CAS latency
minus one. This is shown in the READ to PRECHARGE
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diagram for each possible CAS latency; data element n +
3 is either the last of a burst of four or the last desired of
a longer burst. Following the PRECHARGE command, a
subsequent command to the same bank cannot be issued
until trp is met. Note that part of the row precharge time is
hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command
and address buses be available at the appropriate time to
issue the command; the advantage of the PRECHARGE
command is that it can be used to truncate fixed-length
or full-page bursts.
Full-page READ bursts can be truncated with the BURST
TERMINATE command, and fixed-length READ bursts
may be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated.The BURST
TERMINATE command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This is
shown in the READ Burst Termination diagram for each
possible CAS latency; data element n + 3 is the last desired
data element of a longer burst.
CAS Latency
T0
T1
T2
T3
READ
NOP
NOP
CLK
COMMAND
tAC
DOUT
DQ
tOH
tLZ
CAS Latency - 2
T0
T1
T2
T3
T4
READ
NOP
NOP
NOP
CLK
COMMAND
tAC
DOUT
DQ
tLZ
tOH
CAS Latency - 3
DON'T CARE
UNDEFINED
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Consecutive READ Bursts
T0
T1
T2
T3
T4
T5
T6
READ
NOP
NOP
NOP
READ
NOP
NOP
DOUT n+3
DOUT b
CLK
COMMAND
x =1 cycle
BANK,
COL n
ADDRESS
BANK,
COL b
DQ
DOUT n
DOUT n+1
DOUT n+2
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
READ
NOP
NOP
NOP
READ
T5
T6
T7
NOP
NOP
NOP
DOUT n+3
DOUT b
CLK
COMMAND
x = 2 cycles
ADDRESS
BANK,
COL n
BANK,
COL b
DQ
DOUT n
DOUT n+1
DOUT n+2
CAS Latency - 3
DON'T CARE
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Random READ Accesses
T0
T1
T2
T3
T4
T5
COMMAND
READ
READ
READ
READ
NOP
NOP
ADDRESS
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
CLK
DQ
DOUT n
DOUT b
DOUT m
DOUT x
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
COMMAND
READ
READ
READ
READ
NOP
NOP
NOP
ADDRESS
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
CLK
DQ
DOUT n
DOUT b
DOUT m
DOUT x
CAS Latency - 3
DON'T CARE
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RW1 - READ to WRITE
T0
T1
T2
T3
T4
T5
T6
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
WRITE
ADDRESS
BANK,
COL n
CLK
DQM
BANK,
COL b
tHZ
DOUT n
DQ
DOUT n+1
DIN b
DOUT n+2
CAS Latency - 2
tDS
DON'T CARE
RW2 - READ to WRITE
T0
T1
T2
T3
T4
T5
COMMAND
READ
NOP
NOP
NOP
NOP
WRITE
ADDRESS
BANK,
COL n
CLK
DQM
BANK,
COL b
tHZ
DOUT n
DQ
CAS Latency - 3
DIN b
tDS
DON'T CARE
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READ to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
tRP
COMMAND
READ
NOP
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
x = 1 cycle
ADDRESS
BANK a,
COL n
BANK
(a or all)
DQ
DOUT n
DOUT n+1
BANK a,
ROW
DOUT n+2
DOUT n+3
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
tRP
COMMAND
READ
NOP
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
x = 2 cycles
ADDRESS
BANK,
COL n
BANK,
COL b
DQ
DOUT n
DOUT n+1
BANK a,
ROW
DOUT n+2
DOUT n+3
CAS Latency - 3
DON'T CARE
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READ Burst Termination
T0
T1
T2
T3
T4
READ
NOP
NOP
NOP
T5
T6
NOP
NOP
CLK
COMMAND
BURST
TERMINATE
x = 1 cycle
BANK a,
COL n
ADDRESS
DQ
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
READ
NOP
NOP
NOP
T4
T5
T6
T7
NOP
NOP
NOP
CLK
COMMAND
BURST
TERMINATE
x = 2 cycles
ADDRESS
BANK,
COL n
DQ
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 3
DON'T CARE
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WRITEs
WRITE bursts are initiated with a WRITE command, as
shown in WRITE Command diagram.
WRITE Command
CLK
CKE
HIGH - Z
CS
RAS
CAS
WE
A0-A7
COLUMN ADDRESS
A8, A9, A11
AUTO PRECHARGE
A10
NO PRECHARGE
BA0, BA1
BANK ADDRESS
The starting column and bank addresses are provided with
the WRITE command, and auto precharge is either enabled
or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of
the burst. For the generic WRITE commands used in the
following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be
registered coincident with the WRITE command. Subsequent
data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst,
assuming no other commands have been initiated, the
DQs will remain High-Z and any additional input data will
be ignored (see WRITE Burst). A full-page burst will continue until terminated. (At the end of the page, it will wrap
to column 0 and continue.)
Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE
burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on
any clock following the previous WRITE command, and the
data provided coincident with the new command applies to
the new command.
30
An example is shown in WRITE to WRITE diagram. Data
n + 1 is either the last of a burst of two or the last desired
of a longer burst. The 64Mb SDRAM uses a pipelined
architecture and therefore does not require the 2n rule associated with a prefetch architecture. A WRITE command
can be initiated on any clock cycle following a previous
WRITE command. Full-speed random write accesses within
a page can be performed to the same bank, as shown in
Random WRITE Cycles, or each subsequent WRITE may
be performed to a different bank.
Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed-length WRITE
burst may be immediately followed by a subsequent READ
command. Once the READ command is registered, the
data inputs will be ignored, and WRITEs will not be executed. An example is shown in WRITE to READ. Data n
+ 1 is either the last of a burst of two or the last desired
of a longer burst.
Data for a fixed-length WRITE burst may be followed
by, or truncated with, a PRECHARGE command to the
same bank (provided that auto precharge was not activated), and a full-page WRITE burst may be truncated
with a PRECHARGE command to the same bank. The
PRECHARGE command should be issued twr after the
clock edge at which the last desired input data element
is registered. The auto precharge mode requires a twr of
at least one clock plus time, regardless of frequency. In
addition, when truncating a WRITE burst, the DQM signal
must be used to mask input data for the clock edge prior
to, and the clock edge coincident with, the PRECHARGE
command. An example is shown in the WRITE to PRECHARGE diagram. Data n+1 is either the last of a burst
of two or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to the
same bank cannot be issued until trp is met.
In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum
time (as described above) provides the same operation that
would result from the same fixed-length burst with auto
precharge.The disadvantage of the PRECHARGE command
is that it requires that the command and address buses be
available at the appropriate time to issue the command; the
advantage of the PRECHARGE command is that it can be
used to truncate fixed-length or full-page bursts.
Fixed-length or full-page WRITE bursts can be truncated
with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with
the BURST TERMINATE command will be ignored. The
last data written (provided that DQM is LOW at that time)
will be the input data applied one clock previous to the
BURST TERMINATE command. This is shown in WRITE
Burst Termination, where data n is the last desired data
element of a longer burst.
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WRITE Burst
T0
T1
T2
T3
COMMAND
WRITE
NOP
NOP
NOP
ADDRESS
BANK,
COL n
CLK
DQ
DIN n
DIN n+1
DON'T CARE
WRITE to WRITE
T0
T1
T2
COMMAND
WRITE
NOP
WRITE
ADDRESS
BANK,
COL n
CLK
DQ
BANK,
COL b
DIN n
DIN n+1
DIN b
DON'T CARE
Random WRITE Cycles
T0
T1
T2
T3
COMMAND
WRITE
WRITE
WRITE
WRITE
ADDRESS
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
DIN b
DIN m
DIN x
CLK
DQ
DIN n
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WRITE to READ
T0
T1
T2
T3
T4
T5
COMMAND
WRITE
NOP
READ
NOP
NOP
NOP
ADDRESS
BANK,
COL n
DOUT b
DOUT b+1
CLK
DQ
BANK,
COL b
DIN n
DIN n+1
CAS Latency - 2
DON'T CARE
WP1 - WRITE to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
NOP
NOP
CLK
DQM
tRP
COMMAND
WRITE
ADDRESS
BANK a,
COL n
NOP
PRECHARGE
NOP
ACTIVE
BANK
(a or all)
BANK a,
ROW
tWR
DQ
DIN n
DIN n+1
CAS Latency - 2
32
DON'T CARE
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WP2 - WRITE to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
tRP
COMMAND
WRITE
ADDRESS
BANK a,
COL n
NOP
PRECHARGE
NOP
NOP
BANK
(a or all)
ACTIVE
NOP
BANK a,
ROW
tWR
DQ
DIN n
DIN n+1
CAS Latency - 3
DON'T CARE
WRITE Burst Termination
T0
T1
T2
COMMAND
WRITE
BURST
TERMINATE
NEXT
COMMAND
ADDRESS
BANK,
COL n
CLK
DQ
DIN n
(ADDRESS)
(DATA)
DON'T CARE
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PRECHARGE
PRECHARGE Command
The PRECHARGE command (see figure) is used to deactivate the open row in a particular bank or the open row in
all banks.The bank(s) will be available for a subsequent row
access some specified time (trp) after the PRECHARGE
command is issued. Input A10 determines whether one or
all banks are to be precharged, and in the case where only
one bank is to be precharged, inputs BA0, BA1 select the
bank. When all banks are to be precharged, inputs BA0,
BA1 are treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to
that bank.
CLK
CKE
HIGH - Z
CS
RAS
CAS
WE
POWER-DOWN
A0-A9, A11
Power-down occurs if CKE is registered LOW coincident
with a NOP or COMMAND INHIBIT when no accesses
are in progress. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down;
if power-down occurs when there is a row active in either
bank, this mode is referred to as active power-down.
Entering power-down deactivates the input and output
buffers, excluding CKE, for maximum power savings while
in standby. The device may not remain in the power-down
state longer than the refresh period (64ms) since no refresh
operations are performed in this mode.
The power-down state is exited by registering a NOP or
COMMAND INHIBIT and CKE HIGH at the desired clock
edge (meeting tcks). See figure below.
ALL BANKS
A10
BANK SELECT
BA0, BA1
BANK ADDRESS
POWER-DOWN
CLK
≥ tCKS
tCKS
CKE
COMMAND
NOP
All banks idle
NOP
Input buffers gated off
Enter power-down mode
Exit power-down mode
ACTIVE
tRCD
tRAS
tRC
DON'T CARE
34
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
5/28/2013
IS42S16400J
IS45S16400J
CLOCK SUSPEND
Clock suspend mode occurs when a column access/burst
is in progress and CKE is registered LOW. In the clock
suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled
LOW, the next internal positive clock edge is suspended.
Any command or data present on the input pins at the time
of a suspended internal clock edge is ignored; any data
present on the DQ pins remains driven; and burst counters
are not incremented, as long as the clock is suspended.
(See following examples.)
Clock suspend mode is exited by registering CKE HIGH;
the internal clock and related operation will resume on the
subsequent positive clock edge.
Clock Suspend During WRITE Burst
T0
T1
NOP
WRITE
T2
T3
T4
T5
NOP
NOP
DIN n+1
DIN n+2
CLK
CKE
INTERNAL
CLOCK
COMMAND
BANK a,
COL n
ADDRESS
DQ
DIN n
DON'T CARE
Clock Suspend During READ Burst
T0
T1
T2
COMMAND
READ
NOP
NOP
ADDRESS
BANK a,
COL n
T3
T4
T5
T6
NOP
NOP
NOP
CLK
CKE
INTERNAL
CLOCK
DQ
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com35
Rev. D
5/28/2013
IS42S16400J
IS45S16400J
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by programming
the write burst mode bit (M9) in the mode register to a logic
1. In this mode, all WRITE commands result in the access
of a single column location (burst of one), regardless of
the programmed burst length. READ commands access
columns according to the programmed burst length and
sequence, just as in the normal mode of operation (M9
= 0).
SDRAMs support CONCURRENT AUTO PRECHARGE.
Four cases where CONCURRENT AUTO PRECHARGE
occurs are defined below.
READ with Auto Precharge
1. Interrupted by a READ (with or without auto precharge):
A READ to bank m will interrupt a READ on bank n,
CAS latency later. The PRECHARGE to bank n will
begin when the READ to bank m is registered.
2. Interrupted by a WRITE (with or without auto precharge):
A WRITE to bank m will interrupt a READ on bank n
when registered. DQM should be used two clocks prior
to the WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to
bank m is registered.
CONCURRENT AUTO PRECHARGE
An access command (READ or WRITE) to another bank
while an access command with auto precharge enabled is
executing is not allowed by SDRAMs, unless the SDRAM
supports CONCURRENT AUTO PRECHARGE. ISSI
Fig CAP 1 - READ With Auto Precharge interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
NOP
NOP
NOP
NOP
CLK
NOP
COMMAND
BANK n
READ - AP
BANK n
Page Active
NOP
READ - AP
BANK m
READ with Burst of 4
Interrupt Burst, Precharge
Internal States
BANK m
ADDRESS
Idle
tRP - BANK n
Page Active
tRP - BANK m
READ with Burst of 4
BANK n,
COL a
Precharge
BANK m,
COL b
DQ
DOUT a
DOUT a+1
DOUT b
DOUT b+1
CAS Latency - 3 (BANK n)
DON'T CARE
CAS Latency - 3 (BANK m)
Fig CAP 2 - READ With Auto Precharge interrupted by a WRITE
T0
T1
T2
T3
NOP
NOP
NOP
T4
T5
T6
T7
NOP
NOP
NOP
CLK
COMMAND
WRITE - AP
BANK n
BANK n
READ with Burst of 4
Internal States
Interrupt Burst, Precharge
Page Active
BANK m
ADDRESS
WRITE - AP
BANK m
tRP - BANK n
Page Active
WRITE with Burst of 4
BANK n,
COL a
Idle
tRP - BANK m
Write-Back
BANK m,
COL b
DQM
DOUT a
DQ
CAS Latency - 3 (BANK n)
36
DIN b
DIN b+1
DIN b+2
DIN b+3
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
5/28/2013
IS42S16400J
IS45S16400J
WRITE with Auto Precharge
4. Interrupted by a WRITE (with or without auto precharge):
AWRITE to bank m will interrupt a WRITE on bank n when
registered. The PRECHARGE to bank n will begin after
twr is met, where twr begins when the WRITE to bank
m is registered. The last valid data WRITE to bank n
will be data registered one clock prior to a WRITE to
bank m.
3. Interrupted by a READ (with or without auto precharge):
A READ to bank m will interrupt a WRITE on bank n
when registered, with the data-out appearing CAS latency
later. The PRECHARGE to bank n will begin after twr
is met, where twr begins when the READ to bank m is
registered. The last valid WRITE to bank n will be data-in
registered one clock prior to the READ to bank m.
Fig CAP 3 - WRITE With Auto Precharge interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
NOP
NOP
NOP
NOP
CLK
NOP
COMMAND
BANK n
WRITE - AP
BANK n
Page Active
NOP
READ - AP
BANK m
WRITE with Burst of 4
Interrupt Burst, Write-Back
Precharge
tWR - BANK n
tRP - BANK n
Internal States
BANK m
Page Active
READ with Burst of 4
BANK n,
COL a
ADDRESS
DQ
tRP - BANK m
Precharge
BANK m,
COL b
DIN a
DIN a+1
DOUT b
DOUT b+1
CAS Latency - 3 (BANK m)
DON'T CARE
Fig CAP 4 - WRITE With Auto Precharge interrupted by a WRITE
T0
T1
T2
T3
NOP
NOP
T4
T5
T6
T7
NOP
NOP
NOP
CLK
NOP
COMMAND
BANK n
WRITE - AP
BANK n
Page Active
WRITE with Burst of 4
WRITE - AP
BANK m
Interrupt Burst, Write-Back
tWR - BANK n
Internal States
BANK m
ADDRESS
DQ
Page Active
DIN a
tRP - BANK n
tRP - BANK m
WRITE with Burst of 4
BANK n,
COL a
Precharge
Write-Back
BANK m,
COL b
DIN a+1
DIN a+2
DIN b
DIN b+1
DIN b+2
DIN b+3
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com37
Rev. D
5/28/2013
IS42S16400J
IS45S16400J
INITIALIZE AND LOAD MODE REGISTER(1)
T0
CLK
T1
tCK
Tn+1
tCH
To+1
tCL
Tp+1
Tp+2
Tp+3
tCKS tCKH
CKE
COMMAND
tCMS tCMH
tCMS tCMH
tCMS tCMH
NOP
PRECHARGE
AUTO
REFRESH
NOP
AUTO
REFRESH
NOP
Load MODE
REGISTER
NOP
ACTIVE
DQM/
DQML, DQMH
tAS tAH
A0-A9, A11
ALL BANKS
A10
CODE
tAS tAH
ROW
CODE
ROW
SINGLE BANK
BA0, BA1
BANK
ALL BANKS
DQ
T
Power-up: VCC
and CLK stable
T = 100µs Min.
tRP
Precharge
all banks
tRC
AUTO REFRESH
tRC
AUTO REFRESH
At least 2 Auto-Refresh Commands
tMRD
Program MODE REGISTER (2, 3, 4)
DON'T CARE
Notes:
1. If CS is High at clock High time, all commands applied are NOP.
2. The Mode register may be loaded prior to the Auto-Refresh cycles if desired.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after the command is issued.
38
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
5/28/2013
IS42S16400J
IS45S16400J
POWER-DOWN MODE CYCLE
T0
T1
tCK
CLK
tCKS tCKH
T2
tCL
Tn+1
Tn+2
tCH
tCKS
tCKS
CKE
tCMS tCMH
COMMAND
PRECHARGE
NOP
NOP
NOP
ACTIVE
DQM/
DQML, DQMH
ROW
A0-A9, A11
ALL BANKS
A10
ROW
SINGLE BANK
tAS tAH
BA0, BA1
BANK
BANK
DQ High-Z
Two clock cycles
Precharge all
active banks
All banks idle, enter
power-down mode
Input buffers gated
off while in
power-down mode
All banks idle
Exit power-down mode
DON'T CARE
CAS latency = 2, 3
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
5/28/2013
39
IS42S16400J
IS45S16400J
CLOCK SUSPEND MODE
T0
CLK
tCK
T1
tCKS tCKH
tCL
T2
tCH
T3
T4
T5
T6
NOP
NOP
NOP
T7
T8
T9
tCKS tCKH
CKE
tCMS tCMH
COMMAND
READ
NOP
NOP
WRITE
NOP
tCMS tCMH
DQM/
DQML, DQMH
tAS tAH
A0-A9, A11
COLUMN m(2)
tAS tAH
COLUMN n(2)
A10
tAS tAH
BA0, BA1
BANK
BANK
tAC
tAC
DOUT m
DQ
tLZ
tHZ
DOUT m+1
tDS
tDH
DOUT e
DOUT e+1
tOH
DON'T CARE
UNDEFINED
Notes:
1. CAS latency = 3, burst length = 2
2. A8, A9, and A11 = "Don't Care"
40
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
5/28/2013
IS42S16400J
IS45S16400J
AUTO-REFRESH CYCLE
T0
CLK
tCK
T1
tCL
T2
Tn+1
tCH
To+1
tCKS tCKH
CKE
tCMS tCMH
COMMAND
PRECHARGE
NOP
Auto
Refresh
NOP
Auto
Refresh
NOP
ACTIVE
DQM/
DQML, DQMH
A0-A9, A11
ROW
ALL BANKS
A10
ROW
SINGLE BANK
BA0, BA1
DQ
BANK
BANK(s)
tAS tAH
High-Z
tRP
tRC
tRC
DON'T CARE
CAS latency = 2, 3
Integrated Silicon Solution, Inc. — www.issi.com41
Rev. D
5/28/2013
IS42S16400J
IS45S16400J
SELF-REFRESH CYCLE
T0
T1
tCK
CLK
T2
tCH
tCKS tCKH
Tn+1
To+1
To+2
tCL
tCKS
≥ tRAS
CKE
tCKS
tCMS tCMH
COMMAND
PRECHARGE
NOP
Auto
Refresh
NOP
NOP
Auto
Refresh
DQM/
DQML, DQMH
A0-A9, A11
ALL BANKS
A10
SINGLE BANK
tAS tAH
BA0, BA1
BANK
DQ High-Z
Precharge all
active banks
tXSR
tRP
Enter self
refresh mode
CLK stable prior to exiting
Exit self refresh mode
self refresh mode
(Restart refresh time base)
DON'T CARE
Note:
1. Self-Refresh Mode is not supported for A2 grade with Ta > 85oC.
42
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Rev. D
5/28/2013
IS42S16400J
IS45S16400J
READ WITHOUT AUTO PRECHARGE
T0
CLK
tCK
T1
tCL
T2
tCH
T3
T4
T5
T6
T7
T8
NOP
ACTIVE
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
PRECHARGE
tCMS tCMH
DQM/
DQML, DQMH
tAS tAH
A0-A9, A11
ROW
tAS tAH
A10
ROW
tAS tAH
DISABLE AUTO PRECHARGE
BANK
BANK
BA0, BA1
COLUMN m(2)
ROW
ALL BANKS
ROW
SINGLE BANK
DQ
tRCD
tRAS
tRC
BANK
BANK
tAC
tLZ
CAS Latency
tAC
DOUT m
tAC
DOUT m+1
tAC
DOUT m+2
tHZ
DOUT m+3
tOH
tOH
tOH
tOH
DON'T CARE
tRP
UNDEFINED
Notes:
1. CAS latency = 2, burst length = 4
2. A8, A9, and A11 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.com43
Rev. D
5/28/2013
IS42S16400J
IS45S16400J
READ WITH AUTO PRECHARGE
T0
CLK
tCK
T1
tCL
T2
T3
tCH
T4
T5
T6
T7
T8
NOP
ACTIVE
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
tCMS tCMH
DQM/
DQML, DQMH
tAS tAH
A0-A9, A11
ROW
tAS tAH
A10
ROW
tAS tAH
BA0, BA1
BANK
COLUMN m(2)
ROW
ENABLE AUTO PRECHARGE
ROW
BANK
BANK
tAC
DQ
tRCD
tRAS
tRC
tLZ
CAS Latency
tAC
DOUT m
tAC
DOUT m+1
tAC
DOUT m+2
tHZ
DOUT m+3
tOH
tOH
tOH
tOH
tRP
DON'T CARE
UNDEFINED
Notes:
1. CAS latency = 2, burst length = 4
2. A8, A9, and A11 = "Don't Care"
44
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
5/28/2013
IS42S16400J
IS45S16400J
SINGLE READ WITHOUT AUTO PRECHARGE
T0
CLK
tCK
T1
tCL
T2
tCH
T3
T4
T5
T6
T7
T8
ACTIVE
NOP
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
PRECHARGE
NOP
tCMS tCMH
DQM/
DQML, DQMH
tAS tAH
A0-A9, A11
ROW
tAS tAH
A10
ROW
tAS tAH
DISABLE AUTO PRECHARGE
BANK
BANK
BA0, BA1
COLUMN m(2)
ROW
ALL BANKS
ROW
SINGLE BANK
BANK
tAC
BANK
tOH
DOUT m
DQ
tRCD
tRAS
tRC
tLZ
CAS Latency
tHZ
DON'T CARE
tRP
UNDEFINED
Notes:
1. CAS latency = 2, burst length = 1
2. A8, A9, and A11 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.com45
Rev. D
5/28/2013
IS42S16400J
IS45S16400J
SINGLE READ WITH AUTO PRECHARGE
T0
CLK
tCK
T1
tCL
T2
tCH
T3
T4
T5
T6
T7
NOP
NOP
T8
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
NOP
NOP
READ
ACTIVE
NOP
tCMS tCMH
DQM/
DQML, DQMH
tAS tAH
A0-A9, A11
ROW
tAS tAH
A10
ROW
tAS tAH
BA0, BA1
BANK
COLUMN m(2)
ROW
ENABLE AUTO PRECHARGE
ROW
BANK
BANK
tOH
tAC
DOUT m
DQ
tRCD
tRAS
tRC
tHZ
CAS Latency
tRP
DON'T CARE
UNDEFINED
Notes:
1. CAS latency = 2, burst length = 1
2. A8, A9, and A11 = "Don't Care"
46
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
5/28/2013
IS42S16400J
IS45S16400J
ALTERNATING BANK READ ACCESSES
T0
CLK
tCK
T1
tCL
T2
tCH
T3
T4
T5
T6
T7
T8
NOP
READ
NOP
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
ACTIVE
ACTIVE
tCMS tCMH
DQM/
DQML, DQMH
tAS tAH
A0-A9, A11
COLUMN m(2)
ROW
tAS tAH
A10
ROW
tAS tAH
BA0, BA1
BANK 0
COLUMN b(2)
ROW
ENABLE AUTO PRECHARGE
ROW
ENABLE AUTO PRECHARGE
ROW
BANK 0
ROW
BANK 3
tLZ
BANK 3
tOH
tOH
DQ
DOUT m
tAC
tRCD - BANK 0
tRRD
tOH
DOUT m+1
tAC
BANK 0
tAC
tOH
DOUT m+2
tOH
DOUT m+3
tAC
tAC
tRP - BANK 0
CAS Latency - BANK 0
tRCD - BANK 3
DOUT b
tAC
tRCD - BANK 0
CAS Latency - BANK 3
tRAS - BANK 0
tRC - BANK 0
DON'T CARE
Notes:
1. CAS latency = 2, burst length = 4
2. A8, A9, and A11 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.com47
Rev. D
5/28/2013
IS42S16400J
IS45S16400J
READ - FULL-PAGE BURST
T0
CLK
tCK
T1
tCL
T2
T3
tCH
T4
T5
T6
Tn+1
NOP
NOP
NOP
Tn+2
Tn+3
Tn+4
NOP
NOP
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
BURST TERM
tCMS tCMH
DQM/
DQML, DQMH
tAS tAH
A0-A9, A11
ROW
tAS tAH
A10
ROW
tAS tAH
BA0, BA1
BANK
COLUMN m(2)
BANK
tAC
DQ
tLZ
tRCD
CAS Latency
tAC
DOUT m
tAC
DOUT m+1
tOH
tOH
each row (x4) has
1,024 locations
tAC
DOUT m+2
tOH
tAC
DOUT m-1
tAC
DOUT m
tHZ
DOUT m+1
tOH
tOH
tOH
DON'T CARE
Full page Full-page burst not self-terminating.
completion Use BURST TERMINATE command.
UNDEFINED
Notes:
1. CAS latency = 2, burst length = full page
2. A8, A9, and A11 = "Don't Care"
48
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
5/28/2013
IS42S16400J
IS45S16400J
READ - DQM OPERATION
T0
CLK
tCK
T1
tCL
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
NOP
NOP
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
tCMS tCMH
DQM/
DQML, DQMH
tAS tAH
A0-A9, A11
ROW
tAS tAH
A10
ROW
tAS tAH
DISABLE AUTO PRECHARGE
BANK
BANK
BA0, BA1
COLUMN m(2)
ENABLE AUTO PRECHARGE
tAC
DQ
tLZ
tRCD
CAS Latency
tOH
DOUT m
tHZ
tAC
tLZ
tOH
DOUT m+2
tAC
tOH
DOUT m+3
tHZ
DON'T CARE
UNDEFINED
Notes:
1. CAS latency = 2, burst length = 4
2. A8, A9, and A11 = "Don't Care"
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Rev. D
5/28/2013
49
IS42S16400J
IS45S16400J
WRITE - WITHOUT AUTO PRECHARGE
T0
CLK
tCK
T1
tCL
T2
tCH
T3
T4
T5
T6
NOP
NOP
NOP
T7
T8
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
PRECHARGE
NOP
ACTIVE
tCMS tCMH
DQM/
DQML, DQMH
tAS tAH
A0-A9, A11
ROW
tAS tAH
A10
ROW
tAS tAH
BA0, BA1
COLUMN m(2)
ROW
ALL BANKS
ROW
SINGLE BANK
DISABLE AUTO PRECHARGE
BANK
BANK
tDS
DQ
tDH
DIN m
tRCD
tRAS
tRC
BANK
tDS tDH
DIN m+1
tDS tDH
DIN m+2
tDS
BANK
tDH
DIN m+3
tWR(3)
tRP
DON'T CARE
Notes:
1. burst length = 4
2. A8, A9, and A11 = "Don't Care"
3. tras must not be violated
50
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Rev. D
5/28/2013
IS42S16400J
IS45S16400J
WRITE - WITH AUTO PRECHARGE
T0
CLK
tCK
T1
T2
tCL
tCH
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQM/
DQML, DQMH
tAS tAH
A0-A9, A11
ROW
tAS tAH
A10
ROW
tAS tAH
BA0, BA1
BANK
COLUMN m(2)
ROW
ENABLE AUTO PRECHARGE
ROW
BANK
tDS
DQ
tDH
DIN m
tRCD
tRAS
tRC
BANK
tDS tDH
DIN m+1
tDS tDH
DIN m+2
tDS
tDH
DIN m+3
tWR
tRP
DON'T CARE
Notes:
1. burst length = 4
2. A8, A9, and A11 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.com51
Rev. D
5/28/2013
IS42S16400J
IS45S16400J
SINGLE WRITE - WITHOUT AUTO PRECHARGE
T0
tCK
CLK
T1
tCL
T2
tCH
T3
T4
T5
T6
T7
T8
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP(4)
NOP(4)
PRECHARGE
NOP
ACTIVE
NOP
tCMS tCMH
DQM/
DQML, DQMH
tAS tAH
A0-A9, A11
ROW
tAS tAH
A10
ROW
tAS tAH
BA0, BA1
COLUMN m(2)
ROW
ALL BANKS
ROW
SINGLE BANK
DISABLE AUTO PRECHARGE
BANK
BANK
BANK
BANK
tDS tDH
DQ
DIN m
tRCD
tRAS
tRC
tWR(3)
tRP
DON'T CARE
Notes:
1. burst length = 1
2. A8, A9, and A11 = "Don't Care"
3. tras must not be violated
52
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Rev. D
5/28/2013
IS42S16400J
IS45S16400J
SINGLE WRITE - WITH AUTO PRECHARGE
T0
tCK
CLK
T1
tCL
T2
tCH
T3
T4
T5
T6
T7
NOP
NOP
NOP
T8
T9
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP(3)
NOP(3)
NOP(3)
WRITE
ACTIVE
NOP
tCMS tCMH
DQM/
DQML, DQMH
tAS tAH
A0-A9, A11
ROW
tAS tAH
A10
ROW
tAS tAH
BA0, BA1
BANK
COLUMN m(2)
ROW
ENABLE AUTO PRECHARGE
ROW
BANK
BANK
tDS tDH
DQ
DIN m
tRCD
tRAS
tRC
tWR
tRP
DON'T CARE
Notes:
1. burst length = 1
2. A8, A9, and A11 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.com53
Rev. D
5/28/2013
IS42S16400J
IS45S16400J
ALTERNATING BANK WRITE ACCESS
T0
tCK
CLK
T1
T2
tCL
tCH
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
ACTIVE
NOP
WRITE
ACTIVE
tCMS tCMH
DQM/
DQML, DQMH
tAS tAH
A0-A9, A11
ROW
tAS tAH
A10
ROW
tAS tAH
BA0, BA1
BANK 0
COLUMN m(2)
COLUMN b(2)
ROW
ENABLE AUTO PRECHARGE
ROW
ENABLE AUTO PRECHARGE
ROW
BANK 0
tDS
DQ
tDH
DIN m
tRCD - BANK 0
tRRD
tRAS - BANK 0
tRC - BANK 0
ROW
BANK 1
tDS tDH
DIN m+1
BANK 1
tDS
tDS tDH
DIN m+2
tDH
DIN m+3
tDS
tDH
DIN b
tWR - BANK 0
tRCD - BANK 1
BANK 0
tDS
tDH
DIN b+1
tDS
tDH
DIN b+2
tRP - BANK 0
tDS
tDH
DIN b+3
tRCD - BANK 0
tWR - BANK 1
DON'T CARE
Notes:
1. burst length = 4
2. A8, A9, and A11 = "Don't Care"
54
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
5/28/2013
IS42S16400J
IS45S16400J
WRITE - FULL PAGE BURST
T0
T1
tCK
CLK
T2
tCL
T3
T4
T5
Tn+1
Tn+2
NOP
NOP
NOP
NOP
BURST TERM
tDS tDH
tDS tDH
tDS
DIN m+1
DIN m+2
DIN m+3
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
tCMS tCMH
DQM/
DQML, DQMH
tAS tAH
A0-A9, A11
ROW
tAS tAH
A10
ROW
tAS tAH
BA0, BA1
BANK
COLUMN m(2)
BANK
tDS
tDH
DIN m
DQ
tRCD
tDH
tDS
tDH
tDS
tDH
DIN m-1
Full page completed
DON'T CARE
Notes:
1. burst length = full page
2. A8, A9, and A11 = "Don't Care"
Integrated Silicon Solution, Inc. — www.issi.com55
Rev. D
5/28/2013
IS42S16400J
IS45S16400J
WRITE - DQM OPERATION
T0
T1
T2
tCK
CLK
tCL
T3
T4
T5
T6
T7
NOP
NOP
NOP
NOP
NOP
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQM/
DQML, DQMH
tAS tAH
A0-A9, A11
ROW
tAS tAH
A10
ROW
tAS tAH
DISABLE AUTO PRECHARGE
BANK
BANK
BA0, BA1
COLUMN m(2)
ENABLE AUTO PRECHARGE
tDS
tDH
DIN m
DQ
tRCD
tDS tDH
tDS
tDH
DIN m+2
DIN m+3
DON'T CARE
Notes:
1. burst length = 4
2. A8, A9, and A11 = "Don't Care"
56
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
5/28/2013
IS42S16400J
IS45S16400J
ORDERING INFORMATION
Commercial Range: 0°C to 70°C
requency
F
200 MHz
166 MHz
143 MHz
Speed (ns)
5
6
7
Order Part No.
IS42S16400J-5TL
IS42S16400J-5BL
IS42S16400J-6TL
IS42S16400J-6BL
IS42S16400J-7TL
IS42S16400J-7BL
Package
54-Pin TSOPII, Alloy42 leadframe plated with matte Sn
54-ball BGA, SnAgCu balls
54-Pin TSOPII, Alloy42 leadframe plated with matte Sn
54-ball BGA, SnAgCu balls
54-Pin TSOPII, Alloy42 leadframe plated with matte Sn
54-ball BGA, SnAgCu balls
Industrial Range: -40°C to 85°C
requency
F
200 MHz
166 MHz
143 MHz
Speed (ns)
5
6
7
Order Part No.
IS42S16400J-5BLI
IS42S16400J-6TLI
IS42S16400J-6BLI
IS42S16400J-7TLI
IS42S16400J-7BLI
IS42S16400J-7B2LI
Package
54-ball BGA, SnAgCu balls
54-Pin TSOPII, Alloy42 leadframe plated with matte Sn
54-ball BGA, SnAgCu balls
54-Pin TSOPII, Alloy42 leadframe plated with matte Sn
54-ball BGA, SnAgCu balls
60-ball BGA, SnAgCu balls
Automotive Range (A1): -40°C to 85°C
requency
F
200 MHz
166 MHz
143 MHz
Speed (ns)
5
6
7
Order Part No.
IS45S16400J-5TLA1
IS45S16400J-5CTLA1
IS45S16400J-5BLA1
IS45S16400J-6TLA1
IS45S16400J-6CTLA1
IS45S16400J-6BLA1
IS45S16400J-7TLA1
IS45S16400J-7CTLA1
IS45S16400J-7BLA1
Package
54-Pin TSOPII, Alloy42 leadframe plated with matte Sn
54-Pin TSOPII, Cu leadframe plated with matte Sn
54-ball BGA, SnAgCu balls
54-Pin TSOPII, Alloy42 leadframe plated with matte Sn
54-Pin TSOPII, Cu leadframe plated with matte Sn
54-ball BGA, SnAgCu balls
54-Pin TSOPII, Alloy42 leadframe plated with matte Sn
54-Pin TSOPII, Cu leadframe plated with matte Sn
54-ball BGA, SnAgCu balls
Automotive Range (A2): -40°C to 105°C
requency
F
143 MHz
Speed (ns)
7
Order Part No.
IS45S16400J-7TLA2
IS45S16400J-7CTLA2
IS45S16400J-7BLA2
Package
54-Pin TSOPII, Alloy42 leadframe plated with matte Sn
54-Pin TSOPII, Cu leadframe plated with matte Sn
54-ball BGA, SnAgCu balls
Notes:
1. Contact ISSI for leaded and copper leadframe parts support.
2. Part numbers with "L" or "N" are leadfree, and RoHS compliant.
Integrated Silicon Solution, Inc. — www.issi.com57
Rev. D
5/28/2013
IS42S16400J
IS45S16400J
58
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
5/28/2013
Package Outline
10/17/2007
IS42S16400J
IS45S16400J
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
5/28/2013
59
IS42S16400J
IS45S16400J
60
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
5/28/2013