ISSI IS61LPD51218T/D 256k x 32, 256k x 36, 512k x 18 synchronous pipeline, double-cycle deselect static ram Datasheet

IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
256K x 32, 256K x 36, 512K x 18
SYNCHRONOUS PIPELINE,
DOUBLE-CYCLE DESELECT STATIC RAM
FEATURES
ISSI
®
PRELIMINARY INFORMATION
SEPTEMBER 2000
DESCRIPTION
The ISSI IS61SPD25632, IS61SPD25636, S61SPD51218,
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control using
MODE input
• Three chip enable option for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and
119-pin PBGA package
• Single +3.3V, +10%, –5% power supply
IS61LPD25632, IS61LPD25636, and IS61LPD51218 are
high-speed, low-power synchronous static RAMs designed
to provide a burstable, high-performance, secondary cache for
the Pentium™, 680X0™, and PowerPC™ microprocessors.
The IS61SPD25632 and IS61LPD25632 are organized as
262,144 words by 32 bits and the IS61SPD25636 and
IS61LPD25636 are organized as 262,144 words by 36 bits.
The IS61SPD51218 and IS61LPS51218 are organized as
524,288 words by 18 bits. Fabricated with ISSI's advanced
CMOS technology, the device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous inputs
pass through registers controlled by a positive-edge-triggered
single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be from one
to four bytes wide as controlled by the write control inputs.
• Power-down snooze mode
• 3.3V I/O For SPD
• 2.5V I/O For LPD
• Double cycle deselect
• Snooze MODE for reduced-power standby
• T version (three chip selects)
Separate byte enables allow individual bytes to be written.
Byte write operation is performed by using byte write
enable (BWE).input combined with one or more individual
byte write signals (BWx). In addition, Global Write (GW)
is available for writing all bytes at one time, regardless of
the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address
advance) input pin.
• D version (two chip selects)
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol
tKQ
t KC
Parameter
Clock Access Time
Cycle Time
Frequency
-166*
3.5
6
166
-150
3.8
6.7
150
-133
4
7.5
133
-5
5
10
100
Units
ns
ns
MHz
*This speed available only in SPD version
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
04/17/01
Rev. 00A
1
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
ISSI
®
BLOCK DIAGRAM
MODE
CLK
Q0
CLK
A0
A0'
BINARY
COUNTER
ADV
ADSC
ADSP
A18-A0
(61SPD51218,
61LPD51218)
A17-A0
(61SPD25632/36,
61LPD25632/36)
Q1
CE
A1'
A1
256Kx32; 256Kx36;
512Kx18
MEMORY ARRAY
CLR
18/19
16/17
D
18/19
Q
ADDRESS
REGISTER
CE
CLK
32, 36,
or 18
GW
BWE
BWd
(x32/x36)
D
32, 36,
or 18
Q
DQd
BYTE WRITE
REGISTERS
CLK
BWc
(x32/x36)
D
DQc Q
BYTE WRITE
REGISTERS
CLK
D
BWb
(x32/x36/x18)
Q
DQb
BYTE WRITE
REGISTERS
CLK
BWa
(x32/x36/x18)
D
DQa Q
BYTE WRITE
REGISTERS
CLK
(T, D) CE
(T, D) CE2
(T) CE2
32, 36,
or 18
4
D
Q
ENABLE
REGISTER
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
DQa - DQd
OE
CE
CLK
D
Q
ENABLE
DELAY
REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
ISSI
®
PIN CONFIGURATION
100-Pin TQFP (D Version)
1
2
3
4
5
6
7
VCCQ
A6
A4
ADSP
A8
A16
VCCQ
NC
CE2
A3
ADSC
A9
A17
NC
NC
A7
A2
VCC
A12
A15
NC
DQc1
NC
GND
NC
GND
NC
DQb8
DQc2
DQc3
GND
CE
GND
DQb6
DQb7
VCCQ
DQc4
GND
OE
GND
DQb5
VCCQ
DQc5
DQc6
BWc
ADV
BWb
DQb4
DQb3
DQc7
DQc8
GND
GW
GND
DQb2
DQb1
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
DQd1
DQd2
GND
CLK
GND
DQa7
DQa8
DQd4
DQd3
BWd
NC
BWa
DQa5
DQa6
VCCQ
DQd5
GND
BWE
GND
DQa4
VCCQ
DQd6
DQd7
GND
A1
GND
DQa3
DQa2
DQd8
NC
GND
A0
GND
NC
DQa1
NC
A5
MODE
VCC
NC
A13
NC
NC
NC
A10
A11
A14
NC
ZZ
VCCQ
NC
NC
NC
NC
NC
VCCQ
A
B
A6
A7
CE
CE2
BWd
BWc
BWb
BWa
A17
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
119-pin PBGA (Top View)
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
NC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
C
D
E
F
G
H
J
K
L
M
N
P
R
T
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
U
256K x 32
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
GW
Synchronous Global Write Enable
CE, CE2
Synchronous Chip Enable
OE
Output Enable
DQa-DQd
Synchronous Data Input/Output
A2-A17
Synchronous Address Inputs
CLK
Synchronous Clock
ADSP
Synchronous Processor Address
Status
MODE
Burst Sequence Mode Selection
VCC
+3.3V Power Supply
ADSC
Synchronous Controller Address
Status
GND
Ground
VCCQ
ADV
Synchronous Burst Address Advance
Isolated Output Buffer Supply:
+3.3V or 2.5V
BWa-BWd
Synchronous Byte Write Enable
ZZ
Snooze Enable
BWE
Synchronous Byte Write Enable
GNDQ
Isolated Output Buffer Ground
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
04/17/01
Rev. 00A
3
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
ISSI
®
PIN CONFIGURATION
A6
A7
CE
CE2
BWd
BWc
BWb
BWa
CE2
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
100-Pin TQFP (T Version)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
A17
A10
A11
A12
A13
A14
A15
A16
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
NC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
256K x 32
PIN DESCRIPTIONS
A0, A1
4
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
GW
Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE
Output Enable
DQa-DQd
Synchronous Data Input/Output
Synchronous Processor Address
Status
MODE
Burst Sequence Mode Selection
VCC
+3.3V Power Supply
ADSC
Synchronous Controller Address
Status
GND
Ground
VCCQ
ADV
Synchronous Burst Address Advance
Isolated Output Buffer Supply:
+3.3V or 2.5V
BWa-BWd
Synchronous Byte Write Enable
ZZ
Snooze Enable
BWE
Synchronous Byte Write Enable
GNDQ
Isolated Output Buffer Ground
A2-A17
Synchronous Address Inputs
CLK
Synchronous Clock
ADSP
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
ISSI
®
PIN CONFIGURATION
100-Pin TQFP (D Version)
1
2
3
4
5
6
7
VCCQ
A6
A4
ADSP
A8
A16
VCCQ
NC
CE2
A3
ADSC
A9
A17
NC
NC
A7
A2
VCC
A12
A15
NC
DQc1
DQPc
GND
NC
GND
DQPb
DQb8
DQc2
DQc3
GND
CE
GND
DQb6
DQb7
VCCQ
DQc4
GND
OE
GND
DQb5
VCCQ
DQc5
DQc6
BWc
ADV
BWb
DQb4
DQb3
DQc7
DQc8
GND
GW
GND
DQb2
DQb1
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
DQd1
DQd2
GND
CLK
GND
DQa7
DQa8
DQd4
DQd3
BWd
NC
BWa
DQa5
DQa6
VCCQ
DQd5
GND
BWE
GND
DQa4
VCCQ
DQd6
DQd7
GND
A1
GND
DQa3
DQa2
DQd8
DQPd
GND
A0
GND
DQPa
DQa1
NC
A5
MODE
VCC
NC
A13
NC
NC
NC
A10
A11
A14
NC
ZZ
VCCQ
NC
NC
NC
NC
NC
VCCQ
A
B
A6
A7
CE
CE2
BWd
BWc
BWb
BWa
A17
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
119-pin PBGA (Top View)
DQPc
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
NC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
DQPd
C
D
E
F
G
H
J
K
L
M
N
P
R
T
DQPb
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
DQPa
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
U
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
256K x 36
PIN DESCRIPTIONS
A0, A1
A2-A17
CLK
ADSP
ADSC
ADV
BWa-BWd
BWE
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Individual Byte Write Enable
Synchronous Byte Write Enable
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
04/17/01
Rev. 00A
GW
CE, CE2
OE
DQa-DQd
MODE
VCC
GND
VCCQ
ZZ
DQPa-DQPd
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
Isolated Output Buffer Supply:
+3.3V or 2.5V
Snooze Enable
Parity Data I/O
5
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
ISSI
®
PIN CONFIGURATION
A6
A7
CE
CE2
BWd
BWc
BWb
BWa
CE2
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
100-Pin TQFP (T Version)
DQPc
DQPb
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
DQPa
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
A17
A10
A11
A12
A13
A14
A15
A16
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
NC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
256K x 36
PIN DESCRIPTIONS
A0, A1
A2-A17
CLK
ADSP
ADSC
ADV
BWa-BWd
BWE
6
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Individual Byte Write Enable
Synchronous Byte Write Enable
GW
CE, CE2, CE2
OE
DQa-DQd
MODE
VCC
GND
VCCQ
ZZ
DQPa-DQPd
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
Isolated Output Buffer Supply:
+3.3V or 2.5V
Snooze Enable
Parity Data I/O
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
ISSI
®
PIN CONFIGURATION
100-Pin TQFP (D Version)
1
2
3
4
5
6
7
VCCQ
A6
A4
ADSP
A8
A16
VCCQ
NC
CE2
A3
ADSC
A9
A18
NC
NC
A7
A2
VCC
A12
A15
NC
DQb1
NC
GND
NC
GND
DQPa
NC
NC
DQb2
GND
CE
GND
NC
DQa8
VCCQ
NC
GND
OE
GND
DQa7
VCCQ
NC
DQb3
BWb
ADV
GND
NC
DQa6
DQb4
NC
GND
GW
GND
DQa5
NC
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
NC
DQb5
GND
CLK
GND
NC
DQa4
DQb6
NC
GND
NC
BWa
DQa3
NC
VCCQ
DQb7
GND
BWE
GND
NC
VCCQ
DQb8
NC
GND
A1
GND
DQa2
NC
NC
DQPb
GND
A0
GND
NC
DQa1
NC
A5
MODE
VCC
NC
A13
NC
NC
A11
A10
NC
A14
A17
ZZ
VCCQ
NC
NC
NC
NC
NC
VCCQ
A
B
A6
A7
CE
CE2
NC
NC
BWb
BWa
A18
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
119-pin PBGA (Top View)
NC
NC
NC
VCCQ
GND
NC
NC
DQb1
DQb2
GND
VCCQ
DQb3
DQb4
VCC
VCC
NC
GND
DQb5
DQb6
VCCQ
GND
DQb7
DQb8
DQPb
NC
GND
VCCQ
NC
NC
NC
C
D
E
F
G
H
J
K
L
M
N
P
R
T
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
U
A17
NC
NC
VCCQ
GND
NC
DQPa
DQa8
DQa7
GND
VCCQ
DQa6
DQa5
GND
NC
VCC
ZZ
DQa4
DQa3
VCCQ
GND
DQa2
DQa1
NC
NC
GND
VCCQ
NC
NC
NC
512K x 18
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A18
Synchronous Address Inputs
CLK
Synchronous Clock
ADSP
Synchronous Processor Address
Status
GW
Synchronous Global Write Enable
CE, CE2
Synchronous Chip Enable
OE
Output Enable
DQa-DQb
Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
VCC
+3.3V Power Supply
GND
Ground
VCCQ
Isolated Output Buffer Supply:
+3.3V or 2.5V
ADSC
Synchronous Controller Address
Status
ADV
Synchronous Burst Address Advance
BWa-BWb
Synchronous Byte Write Enable
ZZ
Snooze Enable
BWE
Synchronous Byte Write Enable
DQPa-DQPb
Parity Data I/O DQPa is parity for DQa1-8;
DQPb is parity for DQb1-8
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
04/17/01
Rev. 00A
7
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
ISSI
®
PIN CONFIGURATION
A6
A7
CE
CE2
NC
NC
BWb
BWa
CE2
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
100-Pin TQFP (T Version)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A17
NC
NC
VCCQ
GND
NC
DQPa
DQa8
DQa7
GND
VCCQ
DQa6
DQa5
GND
NC
VCC
ZZ
DQa4
DQa3
VCCQ
GND
DQa2
DQa1
NC
NC
GND
VCCQ
NC
NC
NC
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
A18
A10
A11
A12
A13
A14
A15
A16
NC
NC
NC
VCCQ
GND
NC
NC
DQb1
DQb2
GND
VCCQ
DQb3
DQb4
VCC
VCC
NC
GND
DQb5
DQb6
VCCQ
GND
DQb7
DQb8
DQPb
NC
GND
VCCQ
NC
NC
NC
512K x 18
PIN DESCRIPTIONS
A0, A1
A2-A18
Synchronous Address Inputs
CLK
Synchronous Clock
ADSP
Synchronous Processor Address
Status
ADSC
8
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Controller Address
Status
GW
Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE
Output Enable
DQa-DQb
Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
VCC
+3.3V Power Supply
GND
Ground
VCCQ
Isolated Output Buffer Supply:
+3.3V or 2.5V
ADV
Synchronous Burst Address Advance
BWa-BWb
Synchronous Byte Write Enable
ZZ
Snooze Enable
BWE
Synchronous Byte Write Enable
DQPa-DQPb
Parity Data I/O DQPa is parity for DQa1-8;
DQPb is parity for DQb1-8
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
ISSI
®
TRUTH TABLE
Operation
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Address
Used
None
None
None
None
None
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
CE
H
L
L
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
CE2
X
X
L
X
L
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
CE2
X
H
X
H
X
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
ADSP ADSC
X
L
L
X
L
X
H
L
H
L
L
X
H
L
H
L
H
H
H
H
X
H
X
H
H
H
X
H
H
H
H
H
X
H
X
H
H
H
X
H
ADV WRITE
X
X
X
X
X
X
X
X
X
X
X
X
X
Read
X
Write
L
Read
L
Read
L
Read
L
Read
L
Write
L
Write
H
Read
H
Read
H
Read
H
Read
H
Write
H
Write
OE
X
X
X
X
X
X
X
X
L
H
L
H
X
X
L
H
L
H
X
X
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
Q
Q
D
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
PARTIAL TRUTH TABLE
Function
Read
Read
Write Byte 1
Write All Bytes
Write All Bytes
GW
BWE
BWa
BWb
BWc
BWd
H
H
H
H
L
H
L
L
L
X
X
H
L
L
X
X
H
H
L
X
X
H
H
L
X
X
H
H
L
X
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
04/17/01
Rev. 00A
9
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
ISSI
®
INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or No Connect)
External Address
A1 A0
1st Burst Address
A1 A0
2nd Burst Address
A1 A0
3rd Burst Address
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = GND)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
TBIAS
TSTG
PD
IOUT
VIN, VOUT
VIN
Parameter
Temperature Under Bias
Storage Temperature
Power Dissipation
Output Current (per I/O)
Voltage Relative to GND for I/O Pins
Voltage Relative to GND for
for Address and Control Inputs
VCC
Voltage on Vcc Supply Relatiive to GND
Value
Unit
–40 to +85
°C
–55 to +150
°C
1.6
W
100
mA
–0.5 to VCCQ + 0.5
V
–0.5 to VCC + 0.5
V
–0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or
electric fields; however, precautions may be taken to avoid application of any voltage higher than
maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
ISSI
®
OPERATING RANGE
Range
Commercial
Ambient Temperature
0°C to +70°C
3.3V, +10%, –5%
VCCQ
2.375–3.6V
–40°C to +85°C
3.3V, +10%, –5%
2.375–3.6V
Industrial
VCC
DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
IOH = –2.0 mA, VCCQ = 2.5V
IOH = –4.0 mA, VCCQ = 3.3V
1.7
2.4
—
—
V
V
VOL
Output LOW Voltage
IOL = 2.0 mA, VCCQ = 2.5V
IOL = 8.0 mA, VCCQ = 3.3V
—
—
0.7
0.4
V
V
VIH
Input HIGH Voltage
VCCQ = 2.5V
VCCQ = 3.3V
1.7
2.0
VCCQ + 0.3
VCCQ + 0.3
V
V
VIL
Input LOW Voltage
VCCQ = 2.5V
VCCQ = 3.3V
–0.3
–0.3
0.7
0.8
V
V
ILI
Input Leakage Current
GND ≤ VIN ≤ VCCQ(2)
Com.
Ind.
–2
–5
2
5
µA
ILO
Output Leakage Current
GND ≤ VOUT ≤ VCCQ, OE = VIH Com.
Ind.
–2
–5
2
5
µA
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
ICC
AC Operating
Supply Current
Device Selected,
All Inputs = VIL or VIH
OE = VIH, Vcc = Max.
Cycle Time ≥ tKC min.
ISB
Standby Current
Device Deselected,
VCC = Max.,
All Inputs = VIH or VIL
CLK Cycle Time ≥ tKC min.
-166*
Max.
-150
Max.
-133
Max.
-100
Max.
Unit
Com.
Ind.
400
—
370
400
350
380
300
330
mA
mA
Com.
Ind.
110
—
105
110
90
95
80
85
mA
mA
*This speed available only in SPD version
Notes:
1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to GND, or tied to VCC.
2. The MODE pin should be tied to Vcc or GND. It exhibits ±10 µA maximum leakage current when tied to - GND + 0.2V
or ≥ Vcc – 0.2V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
04/17/01
Rev. 00A
11
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
ISSI
®
CAPACITANCE(1,2)
Symbol
Parameter
CIN
Input Capacitance
COUT
Input/Output Capacitance
Conditions
Max.
Unit
VIN = 0V
6
pF
VOUT = 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
1.5 ns
1.5V for 3.3V I/O
VCCQ/2V for 2.5V I/O
See Figures 1 and 2
AC TEST LOADS
317 Ω/1667 Ω
ZO = 50Ω
3.3V for 3.3V I/O
/2.5V for 2.5v I/O
Output
Buffer
50Ω
1.5V for 3,3V I/O
VCCQ/2V for 2.5V I/O
Figure 1
12
OUTPUT
5 pF
Including
jig and
scope
351 Ω/1538 Ω
Figure 2
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
ISSI
®
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166*
Min.
Max.
Symbol Parameter
-150
Min.
Max.
-133
Min.
Max.
-100
Min.
Max.
Unit
fMAX
Clock Frequency
—
166
—
150
—
133
—
100
MHz
tKC
Cycle Time
6
—
6.7
—
7.5
—
10
—
ns
tKH
Clock High Pulse Width
2.3
—
2.5
—
2.8
—
3
—
ns
tKL
Clock Low Pulse Width
2.3
—
2.5
—
2.8
—
3
—
ns
Clock Access Time
—
3.5
—
3.8
—
4
—
5
ns
tKQX
Clock High to Output Invalid
1.5
—
1.5
—
1.5
—
1.5
—
ns
tKQLZ(1,2)
Clock High to Output Low-Z
0
—
0
—
0
—
0
—
ns
tKQHZ(1,2) Clock High to Output High-Z
—
3.5
—
3.8
—
4
—
5
ns
tOEQ
Output Enable to Output Valid
—
3.5
—
3.8
—
4
—
5
ns
Output Enable to Output Low-Z
0
—
0
—
0
—
0
—
ns
tOEHZ(1,2) Output Enable to Output High-Z
—
3.2
—
3.8
—
4
—
5
ns
tAS
Address Setup Time
1.5
—
1.5
—
1.5
—
2
—
ns
tSS
Address Status Setup Time
1.5
—
1.5
—
1.5
—
2
—
ns
tWS
Write Setup Time
1.5
—
1.5
—
1.5
—
2
—
ns
tCES
Chip Enable Setup Time
1.5
—
1.5
—
1.5
—
2
—
ns
tAVS
Address Advance Setup Time
1.5
—
1.5
—
1.5
—
2
—
ns
tAH
Address Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
tSH
Address Status Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
tWH
Write Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
tCEH
Chip Enable Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
tAVH
Address Advance Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
tKQ
(1)
(1,2)
tOELZ
*This speed available only in SPD version
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
04/17/01
Rev. 00A
13
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
ISSI
®
READ/WRITE CYCLE TIMING
tKC
CLK
tSS
tSH
tKH
tKL
ADSP is blocked by CE inactive
ADSP
tSS
tSH
ADSC initiate read
ADSC
tAVH
tAVS
Suspend Burst
ADV
tAS
Address
tAH
RD1
RD3
RD2
tWS
tWH
tWS
tWH
GW
BWE
BWx
tCES
tCEH
tCES
tCEH
tCES
tCEH
CE Masks ADSP
CE
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
CE2
CE2
tOEHZ
tOEQ
OE
DATAOUT
tKQX
tOEQX
tOELZ
High-Z
1a
2a
2b
2c
2d
tKQLZ
3a
tKQHZ
tKQ
DATAIN
High-Z
Pipelined Read
Single Read
14
Burst Read
Unselected
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
ISSI
®
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166*
Min.
Max.
Symbol Parameter
tKC
Cycle Time
tKH
-150
Min.
Max.
-133
Min.
Max.
-100
Min.
Max.
Unit
6
—
6.7
—
7.5
—
10
—
ns
Clock High Pulse Width
2.3
—
2.5
—
2.8
—
3
—
ns
tKL
Clock Low Pulse Width
2.3
—
2.5
—
2.8
—
3
—
ns
tAS
Address Setup Time
1.5
—
1.5
—
1.5
—
2
—
ns
tSS
Address Status Setup Time
1.5
—
1.5
—
1.5
—
2
—
ns
tWS
Write Setup Time
1.5
—
1.5
—
1.5
—
2
—
ns
tDS
Data In Setup Time
1.5
—
1.5
—
1.5
—
2
—
ns
tCES
Chip Enable Setup Time
1.5
—
1.5
—
1.5
—
2
—
ns
tAVS
Address Advance Setup Time
1.5
—
1.5
—
1.5
—
2
—
ns
tAH
Address Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
tSH
Address Status Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
tDH
Data In Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
tWH
Write Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
tCEH
Chip Enable Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
tAVH
Address Advance Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
*This speed available only in SPD version
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
04/17/01
Rev. 00A
15
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
ISSI
®
WRITE CYCLE TIMING
tKC
CLK
tSS
tSH
tKH
tKL
ADSP is blocked by CE inactive
ADSP
ADSC initiate Write
ADSC
tAVH
ADV must be inactive for ADSP Write tAVS
ADV
tAS
Address
tAH
WR1
WR3
WR2
tWS
tWH
tWS
tWH
tWS
tWH
GW
BWE
BWx
WR1
tCES
tCEH
tCES
tCEH
tCES
tCEH
tWS
tWH
WR2
WR3
CE Masks ADSP
CE
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
CE2
CE2
OE
DATAOUT
High-Z
tDS
DATAIN
High-Z
Single Write
16
tDH
1a
BW4-BW1 only are applied to first cycle of WR2
2a
2b
Burst Write
2c
2d
3a
Write
Unselected
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
ISSI
®
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Min.
Max.
Unit
ISB2
Current during SNOOZE MODE
ZZ ≥ Vih
—
30
mA
t PDS
ZZ active to input ignored
—
2
cycle
t PUS
ZZ inactive to input sampled
2
—
cycle
tZZI
ZZ active to SNOOZE current
—
2
cycle
tRZZI
ZZ inactive to exit SNOOZE current
0
—
ns
SLEEP MODE TIMING
CLK
tPDS
ZZ setup cycle
tPUS
ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2
tRZZI
All Inputs
(except ZZ)
Deselect or Read Only
Deselect or Read Only
Normal
operation
cycle
Outputs
(Q)
High-Z
Don't Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
04/17/01
Rev. 00A
17
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
ISSI
®
PAR
T IDENTIFICA
TION
PART
IDENTIFICATION
61XPDXXXXXX-XXXXXX
Rating
Commercial
I - Industrial
Package
TQ - TQFP
B - PBGA
Speed
T - Three chip selects
D - Two chip selects
166 - 166 MHz
150 - 150 MHz
133 - 133 MHz
5 - 100 MHz
Density 25632 - 256K x 32
25636 - 256K x 36
51218 - 512K x 18
D - double-cycle dedelect
S - single-cycle deselect
SP - 3.3V I/O synchronous pipeline
LP - 2.5V I/O synchronous pipeline
18
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed
Order Part Number
ISSI
Commercial Range: 0°C to +70°C
Package
Speed
Order Part Number
Package
166 MHz
IS61SPD25632T-166TQ
IS61SPD25632D-166TQ
IS61SPD25632D-166B
TQFP
TQFP
PBGA
166 MHz
IS61SPD25636T-166TQ
IS61SPD25636D-166TQ
IS61SPD25636D-166B
TQFP
TQFP
PBGA
150 MHz
IS61SPD25632T-150TQ
IS61SPD25632D-150TQ
IS61SPD25632D-150B
TQFP
TQFP
PBGA
150 MHz
IS61SPD25636T-150TQ
IS61SPD25636D-150TQ
IS61SPD25636D-150B
TQFP
TQFP
PBGA
133 MHz
IS61SPD25632T-133TQ
IS61SPD25632D-133TQ
IS61SPD25632D-133B
TQFP
TQFP
PBGA
133 MHz
IS61SPD25636T-133TQ
IS61SPD25636D-133TQ
IS61SPD25636D-133B
TQFP
TQFP
PBGA
100 MHz
IS61SPD25632T-5TQ
IS61SPD25632D-5TQ
IS61SPD25632D-5B
TQFP
TQFP
PBGA
100 MHz
IS61SPD25636T-5TQ
IS61SPD25636D-5TQ
IS61SPD25636D-5B
TQFP
TQFP
PBGA
Industrial Range: –40°C to +85°C
Speed
Order Part Number
Industrial Range: –40°C to +85°C
Package
Speed
Order Part Number
Package
150 MHz
IS61SPD25632T-150TQI
IS61SPD25632D-150TQI
TQFP
TQFP
150 MHz
IS61SPD25636T-150TQI
IS61SPD25636D-150TQI
TQFP
TQFP
133 MHz
IS61SPD25632T-133TQI
IS61SPD25632D-133TQI
TQFP
TQFP
133 MHz
IS61SPD25636T-133TQI
IS61SPD25636D-133TQI
TQFP
TQFP
100 MHz
IS61SPD25632T-5TQI
IS61SPD25632D-5TQI
TQFP
TQFP
100 MHz
IS61SPD25636T-5TQI
IS61SPD25636D-5TQI
TQFP
TQFP
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
04/17/01
Rev. 00A
®
19
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
ISSI
®
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed
Order Part Number
Package
166 MHz
IS61SPD51218T-166TQ
IS61SPD51218D-166TQ
IS61SPD51218D-166B
TQFP
TQFP
PBGA
150 MHz
IS61SPD51218T-150TQ
IS61SPD51218D-150TQ
IS61SPD51218D-150B
TQFP
TQFP
PBGA
133 MHz
IS61SPD51218T-133TQ
IS61SPD51218D-133TQ
IS61SPD51218D-133B
TQFP
TQFP
PBGA
100 MHz
IS61SPD51218T-5TQ
IS61SPD51218D-5TQ
IS61SPD51218D-5B
TQFP
TQFP
PBGA
Industrial Range: –40°C to +85°C
Speed
20
Order Part Number
Package
150 MHz
IS61SPD51218T-150TQI
IS61SPD51218D-150TQI
TQFP
TQFP
133 MHz
IS61SPD51218T-133TQI
IS61SPD51218D-133TQI
TQFP
TQFP
100 MHz
IS61SPD51218T-5TQI
IS61SPD51218D-5TQI
TQFP
TQFP
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed
Order Part Number
ISSI
Commercial Range: 0°C to +70°C
Package
Speed
Order Part Number
Package
150 MHz
IS61LPD25632T-150TQ
IS61LPD25632D-150TQ
IS61LPD25632D-150B
TQFP
TQFP
PBGA
150 MHz
IS61LPD25636T-150TQ
IS61LPD25636D-150TQ
IS61LPD25636D-150B
TQFP
TQFP
PBGA
133 MHz
IS61LPD25632T-133TQ
IS61LPD25632D-133TQ
IS61LPD25632D-133B
TQFP
TQFP
PBGA
133 MHz
IS61LPD25636T-133TQ
IS61LPD25636D-133TQ
IS61LPD25636D-133B
TQFP
TQFP
PBGA
100 MHz
IS61LPD25632T-5TQ
IS61LPD25632D-5TQ
IS61LPD25632D-5B
TQFP
TQFP
PBGA
100 MHz
IS61LPD25636T-5TQ
IS61LPD25636D-5TQ
IS61LPD25636D-5B
TQFP
TQFP
PBGA
Industrial Range: –40°C to +85°C
Speed
Order Part Number
Industrial Range: –40°C to +85°C
Package
Speed
Order Part Number
Package
133 MHz
IS61LPD25632T-133TQI
IS61LPD25632D-133TQI
TQFP
TQFP
133 MHz
IS61LPD25636T-133TQI
IS61LPD25636D-133TQI
TQFP
TQFP
100 MHz
IS61LPD25632T-5TQI
IS61LPD25632D-5TQI
TQFP
TQFP
100 MHz
IS61LPD25636T-5TQI
IS61LPD25636D-5TQI
TQFP
TQFP
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
04/17/01
Rev. 00A
®
21
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
ISSI
®
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed
Order Part Number
Package
150 MHz
IS61LPD51218T-150TQ
IS61LPD51218D-150TQ
IS61LPD51218D-150B
TQFP
TQFP
PBGA
133 MHz
IS61LPD51218T-133TQ
IS61LPD51218D-133TQ
IS61LPD51218D-133B
TQFP
TQFP
PBGA
100 MHz
IS61LPD51218T-5TQ
IS61LPD51218D-5TQ
IS61LPD51218D-5B
TQFP
TQFP
PBGA
Industrial Range: –40°C to +85°C
Speed
Order Part Number
Package
133 MHz
IS61LPD51218T-133TQI
IS61LPD51218D-133TQI
TQFP
TQFP
100 MHz
IS61LPD51218T-5TQI
IS61LPD51218D-5TQI
TQFP
TQFP
ISSI
®
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: [email protected]
www.issi.com
22
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
Similar pages