ISL43410 ® Data Sheet May 12, 2008 Low-Voltage, Single Supply, DPDT High Performance Analog Switch The Intersil ISL43410 is a precision, bidirectional, analog switch configured as a double pole/double throw (DPDT) switch. The ISL43410 is designed to operate from a single +2V to +12V supply. It is equipped with an inhibit pin to simultaneously open all signal paths. FN6044.4 Features • Fully Specified at 3V, 5V, and 12V Supplies for 10% Tolerances • ON-Resistance (rON), VS = 5V . . . . . . . . . . . . . . . . . 100Ω • rON Matching Between Channels . . . . . . . . . . . . . . . . . . <2Ω • Low Charge Injection . . . . . . . . . . . . . . . . . . . . . . 3pC (Max) ON-resistance is 115Ω with a +5V supply, 45Ω with a +12V supply, and 190Ω with a +3V supply. Each switch can handle rail-to-rail analog signals. The off-leakage current is only 3nA at +25°C or 5nA at +85°C. All digital inputs have 0.8V to 2.4V logic thresholds ensuring TTL/CMOS logic compatibility when using a single +5V supply. Some of the smallest packages are available, alleviating board space limitations, and making Intersil’s newest line of low-voltage switches an ideal solution. • Single Supply Operation. . . . . . . . . . . . . . . . . . . +2V to +12V The ISL43410 is a DPDT, which is perfect for use in 2-to-1 multiplexer applications. • TTL, CMOS Compatible Table 1 summarizes the performance of this switch. • Pb-Free Available (RoHS Compliant) TABLE 1. FEATURES AT A GLANCE CONFIGURATION 115Ω 4.5V tON/tOFF 60ns/30ns 3V rON 190Ω 3V tON/tOFF 120ns/45ns Packages 10 Ld MSOP, 16 Ld 3x3 QFN Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” • Application Note AN557 “Recommended Test Procedures for Analog Switches” • Application Note AN520 “CMOS Analog Multiplexers and Switches; Specifications and Application Considerations” • Application Note AN1034 “Analog Switch and Multiplexer Applications” 1 • Guaranteed Break-Before-Make • Available in 10 Ld MSOP and 16 Ld QFN Packages • Communications Systems - Radios - Telecom Infrastructure - ADSL, VDSL Modems 25ns/24ns 4.5V rON • Fast Switching Action (VS = 5V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30ns • Battery-Powered, Handheld, and Portable Equipment 45Ω 12V tON/tOFF • Low Off Leakage Current . . . . . . . . . . . . . . . . . . . . . . 5nA Applications DPDT 12V rON • Low Power Consumption (PD) . . . . . . . . . . . . . . . . . . . .<3µW • Test Equipment - Medical Ultrasound - Electrocardiograph - Magnetic Resonance Imaging - CT and PET Scanners (MRI) - ATE • Audio and Video Switching • Various Circuits - +3V/+5V DACs and ADCs - Sample and Hold Circuits - Operational Amplifier Gain Switching Networks - High Frequency Analog Switching - High Speed Multiplexing - Integrator Reset Circuits CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003, 2004, 2006, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL43410 (Note 1) NO2 NC2 9 COM2 COM1 2 COM2 10 V+ NO1 1 V+ ISL43410 (16 LD 3X3 QFN) TOP VIEW ISL43410 (10 LD MSOP) TOP VIEW 16 15 14 13 1 12 ADD 7 NC2 NC 2 11 NC NC 3 10 NC NO1 4 9 LOGIC GND 5 6 ADD NOTE: 1. Switches Shown for Logic “0” Inputs. Truth Table 5 6 INH ADD SWITCH ON 1 X NONE 0 0 NCx 0 1 NOx Logic “0” ≤0.8V. Logic “1” ≥2.4V, with VS between 3.3V and Pin Descriptions PIN V+ 8 NC Ordering Information ISL43410 NOTE: 11V. 7 GND NC INH 4 INH 8 NO2 NC1 NC1 3 COM1 Pinouts FUNCTION System Power Supply Input (+2V to +12V) PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. # ISL43410IU 3410 -40 to +85 10 Ld MSOP M10.118 ISL43410IU-T* 3410 -40 to +85 10 Ld MSOP M10.118 ISL43410IUZ (Note) 3410Z -40 to +85 10 Ld MSOP (Pb-free) M10.118 ISL43410IUZ-T* 3410Z (Note) -40 to +85 10 Ld MSOP (Pb-free) M10.118 ISL43410IR 410I -40 to +85 16 Ld QFN L16.3x3 ISL43410IR-T* 410I -40 to +85 16 Ld QFN L16.3x3 341Z -40 to +85 16 Ld QFN (Pb-free) L16.3x3 -40 to +85 16 Ld QFN (Pb-free) L16.3x3 GND Ground Connection ISL43410IRZ (Note) INH Digital Control Input. Connect to GND for Normal Operation. Connect to V+ to turn all switches off. ISL43410IRZ-T* 341Z (Note) Analog Switch Common Pin *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. COMx NOx Analog Switch Normally Open Pin NCx Analog Switch Normally Closed Pin ADD Address Input Pin NC No Internal Connection 2 FN6044.4 May 12, 2008 ISL43410 Absolute Maximum Ratings Thermal Information V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 15V Input Voltages INH, NO, NC, ADD (Note 2) . . . . . . . . . . . . -0.3V to ((V+) + 0.3V) Output Voltages COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . -0.3V to ((V+) + 0.3V) Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA Peak Current NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . 40mA Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 10 Ld MSOP Package (Note 3) . . . . . . 190 N/A 16 Ld QFN Package (Notes 4, 5). . . . . 58 11 Maximum Junction Temperature (Plastic Package). . . . . . . +150°C Moisture Sensitivity (See Technical Brief TB363) All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1 Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range ISL43410Ix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 2. Signals on NC, NO, COM, ADD, or INH exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications +5V Supply PARAMETER Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 6), Unless Otherwise Specified. TEST CONDITIONS TEMP MIN (°C) (Notes 7, 12) TYP MAX (Notes 7, 12) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Full 0 - V+ V 25 - 115 125 Ω Full - - 150 Ω 25 - 1 3 Ω Full - - 5 Ω 25 - 12 13 Ω Full - 13 18 Ω 25 -3 - 3 nA Full -5 - 5 nA 25 -3 - 3 nA Full -5 - 5 nA 25 -3 - 3 nA Full -5 - 5 nA Input Voltage High, VINH Full 2.4 1.4 - V Input Voltage Low, VINL Full - 1.3 0.8 V V+ = 5.5V, VIN = 0V or V+ Full -0.5 - 0.5 µA V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3 (See Figure 1) 25 - 60 - ns Full - 75 - ns ON-Resistance, rON V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V, (See Figure 5, Note 11) rON Matching Between Channels, ΔrON V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V, (Notes 9, 11) rON Flatness, rFLAT(ON) V+ = 5.5V, ICOM = 1.0mA, VNO or VNC = 1.5V, 2.5V, 3.5V, (Notes 10, 11) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V (Note 8) COM OFF Leakage Current, ICOM(OFF) V+ = 5.5V, VCOM = 4.5V, 1V, VNO or VNC = 1V, 4.5V (Note 8) COM ON Leakage Current, ICOM(ON) V+ = 5.5V, VCOM = 1V, 4.5V, or VNO or VNC = 1V, 4.5V, or Floating (Note 8) DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON 3 FN6044.4 May 12, 2008 ISL43410 Electrical Specifications +5V Supply PARAMETER Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 6), Unless Otherwise Specified. (Continued) TEST CONDITIONS Inhibit Turn-OFF Time, tOFF V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3 (See Figure 1) Address Transition Time, tTRANS V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3 (See Figure 1) TEMP MIN (°C) (Notes 7, 12) TYP MAX (Notes 7, 12) UNITS 25 - 30 - ns Full - 35 - ns 25 - 61 - ns Full - 76 - ns Break-Before-Make Time Delay, tD V+ = 5.5V, RL = 300Ω, CL = 35pF, VNO = VNC = 3V, VIN = 0 to 3 (See Figure 3) Full - 16 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2) 25 - 0.3 - pC OFF-Isolation RL = 50Ω, CL = 5pF, f = 1MHz (see Figure 4) 25 - 75 - dB Crosstalk (Channel-to-Channel) RL = 50Ω, CL = 5pF, f = 1MHz (see Figure 6) 25 - -85 - dB NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 7) 25 - 4 - pF COM OFF Capacitance, CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 7) 25 - 6 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 7) 25 - 12 - pF Full 2 - 12 V Full -1 0.0001 1 µA POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = 5.5V, VIN = 0V or V+, all channels on or off Electrical Specifications +3V Supply PARAMETER Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VAH = 2.4V, VAL= 0.8V (Note 6), Unless Otherwise Specified. TEST CONDITIONS TEMP MIN (°C) (Notes 7, 12) TYP MAX (Notes 7, 12) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Full 0 - V+ V 25 - 190 220 Ω Full - - 250 Ω 25 - 1 3 Ω Full - - 5 Ω 25 - 48 90 Ω Full - - 90 Ω 25 -3 - 3 nA Full -5 - 5 nA 25 -3 - 3 nA Full -5 - 5 nA 25 -3 - 3 nA Full -5 - 5 nA Input Voltage High, VINH Full 2.0 1.0 - V Input Voltage Low, VINL Full - 0.8 0.5 V Full -0.5 - 0.5 µA ON-Resistance, rON V+ = 3.0V, ICOM = 1.0mA, VNO or VNC = 1.5V (see Figure 5, Note 11) rON Matching Between Channels, ΔrON V+ = 3.0V, ICOM = 1.0mA, VNO or VNC = 1.5V (Notes 9, 11) rON Flatness, rFLAT(ON) V+ = 3.0V, ICOM = 1.0mA, VNO or VNC = 0.5V, 1.5V (Notes 10, 11) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 3.6V, VCOM = 1V, 3V, VNO or VNC = 3V, 1V (Note 8) COM OFF Leakage Current, ICOM(OFF) V+ = 3.6V, VCOM = 3V, 1V, VNO or VNC = 1V, 3V (Note 8) COM ON Leakage Current, ICOM(ON) V+ = 3.6V, VCOM = 1V, 3V, or VNO or VNC = 1V, 3V, or floating (Note 8) DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL V+ = 3.6V, VIN = 0V or V+ 4 FN6044.4 May 12, 2008 ISL43410 Electrical Specifications +3V Supply PARAMETER Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VAH = 2.4V, VAL= 0.8V (Note 6), Unless Otherwise Specified. (Continued) TEST CONDITIONS TEMP MIN (°C) (Notes 7, 12) TYP MAX (Notes 7, 12) UNITS DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON V+ = 2.7V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF VIN = 0 to 3 (see Figure 1) V+ = 2.7V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF VIN = 0 to 3 (see Figure 1) Inhibit Turn-OFF Time, tOFF Address Transition Time, tTRANS V+ = 2.7V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF VIN = 0 to 3 (see Figure 1) 25 - 144 - ns Full - 165 - ns 25 - 53 - ns Full - 60 - ns 25 - 145 - ns Full - 180 - ns Break-Before-Make Time Delay, tD V+ = 3.6V, RL = 300Ω, CL = 35pF, VNO or VNC = 1.5V VIN = 0 to 3 (see Figure 3) Full - 35 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2) 25 - 0.5 - pC OFF-Isolation RL = 50Ω, CL = 5pF, f = 1MHz (see Figure 4) 25 - 75 - dB Crosstalk (Channel-to-Channel) RL = 50Ω, CL = 5pF, f = 1MHz (see Figure 6) 25 - -85 - dB NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 7) 25 - 4 - pF COM OFF Capacitance, CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 7) 25 - 6 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 7) 25 - 12 - pF Full -1 0.0001 1 µA POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 3.6V, VIN = 0V or V+, all channels on or off Electrical Specifications + 12V Supply PARAMETER Test Conditions: V+ = +10.8V to +13.2V, GND = 0V, VINH = 4V, VINL = 0.8V (Note 6), Unless Otherwise Specified. TEST CONDITIONS TEMP MIN (°C) (Notes 7, 12) TYP MAX (Notes 7, 12) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Full 0 - V+ V 25 - 45 50 Ω Full - - 70 Ω 25 - 0.5 3 Ω Full - - 5 Ω 25 - 5 6 Ω Full - - 10 Ω 25 -3 - 3 nA Full -5 - 5 nA 25 -3 - 3 nA Full -5 - 5 nA 25 -3 - 3 nA Full -5 - 5 nA Input Voltage High, VINH Full 2.9 2.5 - V Input Voltage Low, VINL Full - 2.3 0.8 V Full -0.5 - 0.5 µA ON-Resistance, rON V+ = 12.0V, ICOM = 1.0mA, VNO or VNC = 9V (see Figure 5, Note 11) rON Matching Between Channels, ΔrON V+ = 12.0V, ICOM = 1.0mA, VNO or VNC = 9V (Notes 9,11) rON Flatness, rFLAT(ON) V+ = 13.2V, ICOM = 1.0mA, VNO or VNC = 3V, 6V, 9V (Notes 10, 11) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 13.0V, VCOM = 1V, 12V, VNO or VNC = 12V, 1V (Note 7) COM OFF Leakage Current, ICOM(OFF) V+ = 13.0V, VCOM = 12V, 1V, VNO or VNC = 1V, 12V (Note 7) COM ON Leakage Current, ICOM(ON) V+ = 13.0V, VCOM = 1V, 12V, VNO or VNC = 1V, 12V or floating (Note 7) DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL V+ = 13V, VIN = 0V or V+ 5 FN6044.4 May 12, 2008 ISL43410 Electrical Specifications + 12V Supply PARAMETER Test Conditions: V+ = +10.8V to +13.2V, GND = 0V, VINH = 4V, VINL = 0.8V (Note 6), Unless Otherwise Specified. (Continued) TEMP MIN (°C) (Notes 7, 12) TEST CONDITIONS TYP MAX (Notes 7, 12) UNITS DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON V+ = 10.8V, VNO or VNC = 10V, RL = 300Ω, CL = 35pF VIN = 0 to 4, (see Figure 1) V+ = 10.8V, VNO or VNC = 10V, RL = 300Ω, CL = 35pF VIN = 0 to 4, (see Figure 1) Inhibit Turn-OFF Time, tOFF Address Transition Time, tTRANS V+ = 10.8V, VNO or VNC = 10V, RL = 300Ω, CL = 35pF VIN = 0 to 4, (see Figure 1) 25 - 25 - ns Full - 30 - ns 25 - 24 - ns Full - 30 - ns 25 - 35 - ns Full - 50 - ns Break-Before-Make Time Delay, tD V+ = 13.0V, RL = 300Ω, CL = 35pF, VNO or VNC = 10V VIN = 0 to 4 (see Figure 3) Full - 9 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2) 25 - 1.2 - pC OFF-Isolation RL = 50Ω, CL = 5pF, f = 1MHz, (see Figure 4) 25 - 75 - dB Crosstalk (Channel-to-Channel) RL = 50Ω, CL = 5pF, f = 1MHz, (see Figure 6) 25 - -85 - dB NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (see Figure 7) 25 - 4 - pF COM OFF Capacitance, CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V, (see Figure 7) 25 - 6 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, (see Figure 7) 25 - 12 - pF Full -1 0.0001 1 µA POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 13.0V, VIN = 0V or V+, all channels on or off NOTES: 6. VIN = input voltage to perform proper function. 7. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 8. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at +25°C. 9. ΔrON = rON (MAX) - rON (MIN). 10. Flatness is defined as the difference between the maximum and minimum value of ON-resistance over the specified analog signal range. 11. Limits established by characterization and are not production tested. 12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Test Circuits and Waveforms 3V LOGIC INPUT tr < 20ns tf < 20ns 50% V+ C 0V V+ tON NC NO 90% SWITCH OUTPUT C VOUT INH 90% COM GND ADD LOGIC INPUT 0V VOUT CL 35pF RL 300Ω tOFF Logic input waveform is inverted for switches that have the opposite logic sense. FIGURE 1A. MEASUREMENT POINTS 6 Repeat test for other switches. CL includes fixture and stray capacitance. RL ----------------------V OUT = V (NO or NC) R + r L ON FIGURE 1B. TEST CIRCUIT FN6044.4 May 12, 2008 ISL43410 Test Circuits and Waveforms (Continued) LOGIC INPUT 50% 0V V+ tTRANS 90% SWITCH OUTPUT V+ C tr < 20ns tf < 20ns 3V C NC NO ADD VOUT 90% 0V tTRANS Logic input waveform is inverted for switches that have the opposite logic sense. VOUT COM INH GND LOGIC INPUT CL 35pF RL 300Ω Repeat test for other switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) -----------------------R L + r ON FIGURE 1D. ADDRESS TEST CIRCUIT FIGURE 1C. ADDRESS MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES V+ C 3V OFF OFF LOGIC INPUT VOUT RG ON COM NO or NC 0V ADD SWITCH OUTPUT VOUT ΔVOUT VG GND INH CL LOGIC INPUT Q = ΔVOUT x CL FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUIT FIGURE 2. CHARGE INJECTION V+ C C tr < 20ns tf < 20ns 3V LOGIC INPUT V+ VOUT NO COM 0V ADD 80% SWITCH OUTPUT VOUT CL 35pF RL 300Ω NC LOGIC INPUT GND INH 0V tD Repeat test for other switches. CL includes fixture and stray capacitance. FIGURE 3A. MEASUREMENT POINTS FIGURE 3B. TEST CIRCUIT FIGURE 3. BREAK-BEFORE-MAKE TIME 7 FN6044.4 May 12, 2008 ISL43410 Test Circuits and Waveforms (Continued) V+ V+ C C SIGNAL GENERATOR rON = V1/1mA NO OR NC NO OR NC VNX 0V OR V+ 1mA ADD COM ANALYZER 0V OR V+ V1 ADD 0V OR V+ GND INH COM RL FIGURE 4. OFF-ISOLATION TEST CIRCUIT GND INH FIGURE 5. rON TEST CIRCUIT V+ V+ C SIGNAL GENERATOR NO1 OR NC1 C 50Ω NO OR NC COM1 0V OR V+ ADD 0V OR V+ NO2 OR NC2 NC COM GND COM2 ANALYZER ADD IMPEDANCE ANALYZER GND INH INH RL FIGURE 6. CROSSTALK TEST CIRCUIT Detailed Descriptions The ISL43410 operates from a single 2V to 12V supply with low ON-resistance (115Ω) and high speed operation (tON = 60ns, tOFF = 30ns). The ISL43410 is especially well suited to portable battery powered equipment thanks to the low operating supply voltage (2.0V), low power consumption (3µW), low leakage currents (5nA max), and the tiny MSOP and QFN packaging. High frequency applications also benefit from the wide bandwidth, and the very high OFF-isolation (75dB) and crosstalk rejection (-85dB). Supply Sequencing And Overvoltage Protection With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents, which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and GND (see Figure 8). To prevent forward biasing these diodes, V+ must be applied before any input signals, and input signal 8 FIGURE 7. CAPACITANCE TEST CIRCUIT voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1kΩ resistor in series with the input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not applicable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low rON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 8). These additional diodes limit the analog signal from 1V below V+ to 1V above GND. The low leakage current performance is unaffected by this approach, but the switch resistance may increase, especially at low supply voltages. FN6044.4 May 12, 2008 ISL43410 Similar devices of competitors can draw 8x this amount of current. . OPTIONAL PROTECTION RESISTOR FOR LOGIC INPUTS 1kΩ 1kΩ OPTIONAL PROTECTION DIODE ADD IN VNO OR NC High-Frequency Performance In 50Ω systems, signal response is reasonably flat even past 100MHz (see Figure 17). Figure 17 also illustrates that the frequency response is very consistent over a wide V+ range, and for varying analog signal levels. V+ VCOM GND OPTIONAL PROTECTION DIODE FIGURE 8. OVERVOLTAGE PROTECTION Power-Supply Considerations The ISL43410 construction is typical of most CMOS analog switches, except that they have only two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 13V maximum supply voltage, the ISL43410’s 15V maximum supply voltage provides plenty of room for the 10% tolerance of 12V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 2.0V. It is important to note that the input signal range, switching times, and ON-resistance degrade at lower supply voltages. Refer to the Electrical Specification” tables beginning on page 3 and “Typical Performance Curves” on page 10 for details. V+ and GND also power the internal logic and level shifters. The level shifters convert the input logic levels to switched V+ and GND signals to drive the analog switch gate terminals. This device cannot be operated with bipolar supplies because the input switching point becomes negative in this configuration. Logic-Level Thresholds An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch’s input to its output. OFF-Isolation is the resistance to this feed through, while crosstalk indicates the amount of feed through from one switch to another. Figure 18 details the high OFF-Isolation and crosstalk rejection provided by this family. At 10MHz, OFF-Isolation is about 55dB in 50Ω systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease OFF-Isolation and crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance. Leakage Considerations Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analog-signal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND. The ISL43410 is TTL compatible (0.8V and 2.4V) over a supply range of 3V to 11V (see Figure 11). At 12V, the VIH level is about 2.5V. This is still below the TTL guaranteed high output minimum level of 2.8V, but noise margin is reduced. For best results with a 12V supply, use a logic family that provides a VOH greater than 3V. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails (see Figure 12). Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. The ISL43410 has been designed to minimize the supply current whenever the digital input voltage is not driven to the supply rails (0V to V+). For example, driving the device with 3V logic (0V to 3V) while operating with a 5V supply, the device draws only 10µA of current (see Figure 12 for VIN = 3V). 9 FN6044.4 May 12, 2008 ISL43410 Typical Performance Curves TA = +25°C, Unless Otherwise Specified. 500 225 VCOM = (V+) - 1V V+ = 3.3V 200 ICOM = 1mA 175 400 ICOM = 1mA +85°C +25°C 150 125 -40°C 100 rON (Ω) rON (Ω) 300 +85°C 200 +25°C -40°C 0 3 4 5 6 7 8 V+ (V) 9 10 11 12 13 VINH +85°C 100 +25°C 80 -40°C V+ = 5V V+ = 12V +25°C 2 4 6 VCOM (V) 8 10 140 -40°C V+ = +5V 2.5 120 2.0 +25°C +85°C 1.5 100 1.0 80 0.5 3.0 ICC (µA) VINH AND VINL (V) 12 FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE FIGURE 9. ON-RESISTANCE vs SUPPLY VOLTAGE 3.0 120 60 80 70 +85°C 60 50 40 -40°C 30 0 100 2 75 140 VINL -40°C 2.5 60 40 2.0 +25°C 1.5 20 1.0 85°C 0 0.5 2 3 4 6 5 7 8 V+ (V) 9 10 11 12 13 FIGURE 11. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE 350 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VIN(ADD) (V) FIGURE 12. SUPPLY CURRENT vs DIGITAL ADDRESS INPUT VOLTAGE 120 VCOM = (V+) - 1V VCOM = (V+) - 1V 110 300 100 90 250 tOFF (ns) tON (ns) 80 200 +85°C 150 70 60 +85°C 50 +25°C 100 -40°C 50 +25°C 40 30 -40°C 20 0 2 3 4 5 6 7 V+ (V) 8 9 10 11 FIGURE 13. TURN-ON TIME vs SUPPLY VOLTAGE 10 12 10 2 3 4 5 6 7 V+ (V) 8 9 10 11 12 FIGURE 14. TURN-OFF TIME vs SUPPLY VOLTAGE FN6044.4 May 12, 2008 ISL43410 Typical Performance Curves TA = +25°C, Unless Otherwise Specified. (Continued) 3 350 VCOM = (V+) - 1V 2 300 250 V+ = 5V 0 200 Q (pC) +85°C 150 V+ = 3.3V -1 -2 +25°C 100 -3 -40°C 50 -4 0 2 3 4 5 6 7 8 9 10 11 -5 12 0 2 4 V+ (V) 6 8 10 12 VCOM (V) FIGURE 15. ADDRESS TRANS TIME vs SUPPLY VOLTAGE FIGURE 16. CHARGE INJECTION vs SWITCH VOLTAGE +3 0 VIN = 2.5VP-P (V+ = 3V) GAIN VIN = 0.2VP-P (V+ = 13V) -3 VIN = 5VP-P (V+ = 13V) 0 PHASE 90 135 180 RL = 50Ω 10M 100M FREQUENCY (Hz) FIGURE 17. FREQUENCY RESPONSE 600M PHASE (°) 45 1M 10 V+ = 3V TO 12V CROSSTALK (dB) NORMALIZED GAIN (dB) -10 VIN = 0.2VP-P (V+ = 3V) -20 20 -30 30 -40 40 -50 50 -60 60 ISOLATION -70 70 -80 80 OFF-ISOLATION (dB) tTRANS (ns) V+ = 12V 1 CROSSTALK -90 90 -100 100 -110 1k 10k 100k 1M 10M 110 100M 500M FREQUENCY (Hz) FIGURE 18. CROSSTALK AND OFF-ISOLATION Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: 193 PROCESS: Si Gate CMOS 11 FN6044.4 May 12, 2008 ISL43410 Package Outline Drawing L16.3x3 16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 4/07 4X 1.5 3.00 12X 0.50 A B 6 PIN 1 INDEX AREA 6 PIN #1 INDEX AREA 16 13 1 3.00 12 1 .50 ± 0 . 15 9 4 0.15 (4X) 5 8 0.10 M C A B + 0.07 4 16X 0.23 - 0.05 TOP VIEW 16X 0.40 ± 0.10 BOTTOM VIEW SEE DETAIL "X" 0.10 C C 0 . 90 ± 0.1 BASE PLANE ( 2. 80 TYP ) ( SEATING PLANE 0.08 C 1. 50 ) SIDE VIEW ( 12X 0 . 5 ) ( 16X 0 . 23 ) C ( 16X 0 . 60) 0 . 2 REF 5 0 . 00 MIN. 0 . 05 MAX. TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 12 FN6044.4 May 12, 2008 ISL43410 Mini Small Outline Plastic Packages (MSOP) N M10.118 (JEDEC MO-187BA) 10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE E1 INCHES E -B- INDEX AREA 0.20 (0.008) 1 2 A B C TOP VIEW 4X θ 0.25 (0.010) R1 R GAUGE PLANE SEATING PLANE -CA 4X θ A2 A1 b -H- 0.10 (0.004) L SEATING PLANE C MIN MAX MIN MAX NOTES A 0.037 0.043 0.94 1.10 - A1 0.002 0.006 0.05 0.15 - A2 0.030 0.037 0.75 0.95 - b 0.007 0.011 0.18 0.27 9 c 0.004 0.008 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.116 0.120 2.95 3.05 4 0.020 BSC 0.20 (0.008) C C a SIDE VIEW CL E1 0.20 (0.008) C D - 0.187 0.199 4.75 5.05 - L 0.016 0.028 0.40 0.70 6 0.037 REF N -A- 0.50 BSC E L1 e D SYMBOL e L1 MILLIMETERS 0.95 REF 10 R 0.003 R1 - 10 - 0.07 0.003 - θ 5o 15o α 0o 6o 7 - - 0.07 - - 5o 15o - 0o 6o -B- Rev. 0 12/02 END VIEW NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension “D” does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (.004) at seating Plane. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B - to be determined at Datum plane 11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 FN6044.4 May 12, 2008