ISL5120, ISL5121, ISL5122, ISL5123 ® Data Sheet November 17, 2004 Low-Voltage, Single Supply, Dual SPST, SPDT Analog Switches The Intersil ISL5120, ISL5121, ISL5122, ISL5123 devices are precision, bidirectional, dual analog switches designed to operate from a single +2.7V to +12V supply. Targeted applications include battery powered equipment that benefit from the devices’ low power consumption (5µW), low leakage currents (100pA max), and fast switching speeds (tON = 28ns, tOFF = 20ns). Cell phones, for example, often face ASIC functionality limitations. The number of analog input or GPIO pins may be limited and digital geometries are not well suited to analog switch performance. This family of parts may be used to “mux-in” additional functionality while reducing ASIC design risk. Some of the smallest packages are available, alleviating board space limitations, and making Intersil’s newest line of low-voltage switches an ideal solution. The ISL5120, ISL5121, ISL5122 are dual single-pole/singlethrow (SPST) devices. The ISL5120 has two normally open (NO) switches; the ISL5121 has two normally closed (NC) switches; the ISL5122 has one NO and one NC switch and can be used as an SPDT. The ISL5123 is a committed SPDT, which is perfect for use in 2-to-1 multiplexer applications. FN6022.6 Features • Improved (lower RON, faster switching), pin compatible replacements for ISL84541–44 • Fully specified at 3.3V, 5V, and 12V supplies • ON resistance (RON) . . . . . . . . . . . . . . . . . . . . . . . . . 19Ω • RON matching between channels . . . . . . . . . . . . . . . . . ≤ 1Ω • Low charge injection . . . . . . . . . . . . . . . . . . . . . . . . 5pC (Max) • Single supply operation . . . . . . . . . . . . . . . . . . +2.7V to +12V • Low power consumption (PD) . . . . . . . . . . . . . . . . . . . .<5µW • Low leakage current. . . . . . . . . . . . . . . . . . . . . . . . . .10nA • Fast switching action - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ns • Guaranteed break-before-make (ISL5122/ISL5123 only) • Minimum 2000V ESD protection per method 3015.7 • TTL, CMOS compatible • Available in SOT-23 packaging • Pb-Free Available (RoHS Compliant) TABLE 1. FEATURES AT A GLANCE ISL5120 ISL5121 ISL5122 ISL5123 Number of Switches 2 2 2 1 SW 1/SW 2 NO/NO NC/NC NO/NC SPDT 3.3V RON 32Ω 32Ω 32Ω 32Ω 3.3V tON/tOFF 40ns /20ns 40ns /20ns 40ns /20ns 40ns /20ns 5V RON 5V tON/tOFF 19Ω 19Ω 19Ω 28ns/2y0ns 28ns/20ns 28ns/20ns 11Ω 11Ω 19Ω 28ns/20ns 12V RON 11Ω 11Ω 12V tON/tOFF 25ns/17ns 25ns/17ns 25ns/17ns 25ns/17ns Packages 8 Ld SOIC, 8 Ld SOT-23 8 Ld SOIC, 8 Ld SOT-23 8 Ld SOIC, 6 Ld SOT-23 Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” 1 Applications • Battery powered, handheld, and portable equipment - Cellular/mobile phones - Pagers - Laptops, notebooks, palmtops • Communications systems - Military radios - PBX, PABX • Test equipment - Ultrasound - Electrocardiograph • Heads-up displays • Audio and video switching • Various circuits - +3V/+5V DACs and ADCs - Sample and hold circuits - Digital filters - Operational amplifier gain switching networks - High frequency analog switching - High speed multiplexing - Integrator reset circuits CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2002-2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL5120, ISL5121, ISL5122, ISL5123 Pinouts (Note 1) ISL5120 (SOIC) TOP VIEW ISL5120 (SOT-23) TOP VIEW NO1 1 8 V+ NO1 1 COM1 2 7 IN1 V+ 2 7 IN1 IN2 3 6 GND COM2 4 5 NO2 6 COM2 IN2 3 5 NO2 GND 4 ISL5121 (SOIC) TOP VIEW 8 COM1 ISL5121 (SOT-23) TOP VIEW NC1 1 8 V+ COM1 2 7 IN1 V+ 2 7 IN1 6 COM2 IN2 3 6 GND COM2 4 5 NC2 IN2 3 5 NC2 GND 4 8 COM1 NC1 1 ISL5122 (SOIC) TOP VIEW ISL5122 (SOT-23) TOP VIEW NO1 1 8 V+ NO1 1 COM1 2 7 IN1 V+ 2 7 IN1 IN2 3 6 GND COM2 4 5 NC2 6 COM2 IN2 3 5 NC2 GND 4 ISL5123 (SOIC) TOP VIEW 8 COM1 ISL5123 (SOT-23) TOP VIEW NO 1 8 V+ IN 1 6 NO COM 2 7 IN V+ 2 5 COM NC 3 6 N.C. GND 4 5 N.C. 4 NC GND 3 NOTE: 1. Switches Shown for Logic “0” Input. Truth Table Pin Descriptions PIN FUNCTION PIN NC PIN NO V+ System Power Supply Input (+2.7V to +12V) OFF GND Ground Connection ON IN Digital Control Input COM Analog Switch Common Pin NO Analog Switch Normally Open Pin NC Analog Switch Normally Closed Pin N.C. No Internal Connection ISL5121 LOGIC SW 1,2 SW 1,2 SW 1 SW 2 0 OFF ON OFF ON ON 1 ON OFF ON OFF OFF NOTE: ISL5122 ISL5123 ISL5120 Logic “0” ≤0.8V. Logic “1” ≥2.4V. 2 FN6022.6 November 17, 2004 ISL5120, ISL5121, ISL5122, ISL5123 Ordering Information PART NO. (BRAND)* TEMP. RANGE (°C) PACKAGE PKG. DWG. # ISL5120CB 0 to 70 8 Ld SOIC M8.15 ISL5120CBZ (Note) 0 to 70 8 Ld SOIC (Pb-free) M8.15 ISL5120IB -40 to 85 8 Ld SOIC M8.15 ISL5120IBZ (Note) -40 to 85 8 Ld SOIC (Pb-free) M8.15 ISL5120IH-T (120I) -40 to 85 8 Ld SOT-23 P8.064 ISL5120IHZ-T (Note) (120I) -40 to 85 8 Ld SOT-23 (Pb-free) P8.064 M8.15 ISL5121CB 0 to 70 8 Ld SOIC ISL5121CBZ (Note) 0 to 70 8 Ld SOIC (Pb-free) M8.15 ISL5121IB -40 to 85 8 Ld SOIC M8.15 ISL5121IBZ (Note) -40 to 85 8 Ld SOIC (Pb-free) M8.15 ISL5121IH-T (121I) -40 to 85 8 Ld SOT-23 P8.064 ISL5121IHZ-T (Note) (121I) -40 to 85 8 Ld SOT-23 (Pb-free) P8.064 M8.15 ISL5122CB 0 to 70 8 Ld SOIC ISL5122CBZ (Note) 0 to 70 8 Ld SOIC (Pb-free) M8.15 ISL5122IB -40 to 85 8 Ld SOIC M8.15 ISL5122IBZ (Note) -40 to 85 8 Ld SOIC (Pb-free) M8.15 ISL5122IH-T (122I) -40 to 85 8 Ld SOT-23 P8.064 ISL5122IHZ-T (Note) (122I) -40 to 85 8 Ld SOT-23 (Pb-free) P8.064 M8.15 ISL5123CB 0 to 70 8 Ld SOIC ISL5123CBZ (Note) 0 to 70 8 Ld SOIC (Pb-free) M8.15 ISL5123IB -40 to 85 8 Ld SOIC M8.15 ISL5123IBZ (Note) -40 to 85 8 Ld SOIC (Pb-free) M8.15 ISL5123IH-T (123I) -40 to 85 6 Ld SOT-23 P6.064 ISL5123IHZ-T (Note) (123I) -40 to 85 6 Ld SOT-23 (Pb-free) P6.064 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C. *Most surface mount devices are available on tape and reel; add “-T” to suffix. 3 FN6022.6 November 17, 2004 ISL5120, ISL5121, ISL5122, ISL5123 Absolute Maximum Ratings Thermal Information V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V Input Voltages IN (Note 3). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) NO, NC (Note 3) . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Output Voltages COM (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA Peak Current NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . 40mA ESD Rating (Per MIL-STD-883 Method 3015). . . . . . . . . . . . . .>2kV Thermal Resistance (Typical, Note 4) Operating Conditions θJA (°C/W) 6 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . . 230 8 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . . 215 8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 170 Maximum Junction Temperature (Plastic Package). . . . . . . . 150°C Moisture Sensitivity (See Technical Brief TB363) All Other Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1 8 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 2 Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C (Lead Tips Only) Temperature Range ISL512XCX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C ISL512XIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 2. Signals on NC, NO, COM, or IN exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications - 5V Supply PARAMETER Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5), Unless Otherwise Specified TEST CONDITIONS TEMP (°C) (NOTE 6) MIN TYP (NOTE 6) MAX UNITS Full 0 - V+ V 25 - 19 30 Ω Full - 23 40 Ω 25 - 0.8 2 Ω Full - 1 4 Ω ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V, (See Figure 5) RON Matching Between Channels, ∆RON V+ = 5V, ICOM = 1.0mA, VNO or VNC= 3.5V RON Flatness, RFLAT(ON) V+ = 5V, ICOM = 1.0mA, VNO or VNC = 1V, 2V, 3V Full - 7 8 Ω NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V, (Note 7) 25 -0.1 0.01 0.1 nA Full -5 - 5 nA COM OFF Leakage Current, ICOM(OFF) V+ = 5.5V, VCOM = 4.5V, 1V, VNO or VNC = 1V, 4.5V, (Note 7) 25 -0.1 - 0.1 nA Full -5 - 5 nA COM ON Leakage Current, ICOM(ON) V+ = 5.5V, VCOM = 1V, 4.5V, or VNO or VNC = 1V, 4.5V, or Floating, (Note 7) 25 -0.2 - 0.2 nA Full -10 - 10 nA 25 - 28 75 ns Full - 40 150 ns 25 - 20 50 ns Full - 30 100 ns DYNAMIC CHARACTERISTICS Turn-ON Time, tON VNO or VNC = 3V, RL =1kΩ, CL = 35pF, VIN = 0 to 3V, (See Figure 1) Turn-OFF Time, tOFF VNO or VNC = 3V, RL =1kΩ, CL = 35pF, VIN = 0 to 3V, (See Figure 1) Break-Before-Make Time Delay (ISL5122, ISL5123), tD RL = 300Ω, CL = 35pF, VNO = VNC = 3V, VIN = 0 to 3V, (See Figure 3) Full 3 10 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2) 25 - 3 5 pC OFF Isolation RL = 50Ω, CL = 5pF, f = 1MHz, (See Figure 4) 25 - 76 - dB Crosstalk (Channel-to-Channel) RL = 50Ω, CL = 5pF, f = 1MHz, (See Figure 6) 25 - -105 - dB 4 FN6022.6 November 17, 2004 ISL5120, ISL5121, ISL5122, ISL5123 Electrical Specifications - 5V Supply Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5), Unless Otherwise Specified (Continued) TEMP (°C) (NOTE 6) MIN TYP 25 - 60 - dB NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) 25 - 8 - pF COM OFF Capacitance, CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) 25 - 8 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7), ISL5120/1/2 25 - 21 - pF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7), ISL5123 25 - 28 - pF Full 2.7 12 V Full -1 0.0001 1 µA Input Voltage Low, VINL Full - - 0.8 V Input Voltage High, VINH Full 2.4 - - V Full -1 - 1 µA PARAMETER TEST CONDITIONS Power Supply Rejection Ratio RL = 50Ω, CL = 5pF, f = 1MHz (NOTE 6) MAX UNITS POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = 5.5V, VIN = 0V or V+, all channels on or off DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL V+ = 5.5V, VIN = 0V or V+ NOTES: 4. VIN = input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at 25°C. Electrical Specifications - 3.3V Supply PARAMETER Test Conditions: V+ = +3.0V to +3.6V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5), Unless Otherwise Specified TEST CONDITIONS TEMP (°C) (NOTE 6) MIN TYP (NOTE 6) MAX UNITS Full 0 - V+ V 25 - 32 50 Ω Full - 40 60 Ω 25 - 0.8 2 Ω Full - 1 4 Ω 25 - 6 8 Ω Full - 7 12 Ω 25 -0.1 0.01 0.1 nA Full -5 - 5 nA 25 -0.1 0.01 0.1 nA Full -5 - 5 nA 25 -0.2 - 0.2 nA Full -10 - 10 nA ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON V+ = 3V, ICOM = 1.0mA, VNO or VNC = 1.5V RON Matching Between Channels, ∆RON V+ = 3.3V, ICOM = 1.0mA, VNO or VNC = 1.5V RON Flatness, RFLAT(ON) V+ = 3.3V, ICOM = 1.0mA, VNO or VNC = 0.5V, 1V, 1.5V NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 3.6V, VCOM = 1V, 3V, VNO or VNC = 3V, 1V, (Note 7) COM OFF Leakage Current, ICOM(OFF) V+ = 3.6V, VCOM = 3V, 1V, VNO or VNC = 1V, 3V, (Note 7) COM ON Leakage Current, ICOM(ON) V+ = 3.6V, VCOM = 1V, 3V, or VNO or VNC = 1V, 3V, or floating, (Note 7) 5 FN6022.6 November 17, 2004 ISL5120, ISL5121, ISL5122, ISL5123 Electrical Specifications - 3.3V Supply Test Conditions: V+ = +3.0V to +3.6V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5), Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP (°C) (NOTE 6) MIN TYP VNO or VNC = 1.5V, RL =1kΩ, CL = 35pF, VIN = 0 to 3V 25 - 40 120 ns Full - 60 200 ns 25 - 20 50 ns Full - 30 120 ns PARAMETER (NOTE 6) MAX UNITS DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF VNO or VNC = 1.5V, RL =1kΩ, CL = 35pF, VIN = 0 to 3V Break-Before-Make Time Delay (ISL5122, ISL5123), tD RL = 300Ω, CL = 35pF, VNO or VNC = 1.5V, VIN = 0 to 3V Full 3 20 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω 25 - 1 5 pC OFF Isolation RL = 50Ω, CL = 5pF, f = 1MHz 25 - 76 - dB 25 - -105 - dB 25 - 56 - dB NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V 25 - 8 - pF COM OFF Capacitance, CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V 25 - 8 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, ISL5120/1/2 25 - 21 - pF f = 1MHz, VNO or VNC = VCOM = 0V, ISL5123 25 - 28 - pF Full -1 - 1 µA Input Voltage Low, VINL Full - - 0.8 V Input Voltage High, VINH Full 2.4 - - V Full -1 - 1 µA Crosstalk (Channel-to-Channel) Power Supply Rejection Ratio RL = 50Ω, CL = 5pF, f = 1MHz POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 3.6V, VIN = 0V or V+, all channels on or off DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL V+ = 3.6V, VIN = 0V or V+ Electrical Specifications - 12V Supply PARAMETER Test Conditions: V+ = +10.8V to +13.2V, GND = 0V, VINH = 4V, VINL = 0.8V (Note 5), Unless Otherwise Specified TEST CONDITIONS TEMP (°C) (NOTE 6) MIN TYP (NOTE 6) MAX UNITS Full 0 - V+ V 25 - 11 20 Ω Full - 15 25 Ω 25 - 0.8 2 Ω Full - 1 4 Ω 25 - 1 4 Ω Full - - 6 Ω 25 -0.1 0.01 0.1 nA Full -5 - 5 nA 25 -0.1 0.01 0.1 nA Full -5 - 5 nA ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON V+ = 10.8V, ICOM = 1.0mA, VNO or VNC = 10V RON Matching Between Channels, ∆RON V+ = 12V, ICOM = 1.0mA, VNO or VNC = 10V RON Flatness, RFLAT(ON) V+ = 12V, ICOM = 1.0mA, VNO or VNC = 3V, 6V, 9V NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 13V, VCOM = 1V, 12V, VNO or VNC = 12V, 1V, (Note 7 COM OFF Leakage Current, ICOM(OFF) V+ = 13V, VCOM = 12V, 1V, VNO or VNC = 1V, 12V, (Note 7 6 FN6022.6 November 17, 2004 ISL5120, ISL5121, ISL5122, ISL5123 Electrical Specifications - 12V Supply PARAMETER Test Conditions: V+ = +10.8V to +13.2V, GND = 0V, VINH = 4V, VINL = 0.8V (Note 5), Unless Otherwise Specified (Continued) TEST CONDITIONS COM ON Leakage Current, ICOM(ON) V+ = 13V, VCOM = 1V, 12V, or VNO or VNC = 1V, 12V, or floating, (Note 7) TEMP (°C) (NOTE 6) MIN TYP (NOTE 6) MAX UNITS 25 -0.2 - 0.2 nA Full -10 - 10 nA 25 - 25 35 ns Full - 35 55 ns 25 - 17 30 ns Full - 26 50 ns DYNAMIC CHARACTERISTICS Turn-ON Time, tON VNO or VNC = 10V, RL =1kΩ, CL = 35pF, VIN = 0 to 4V Turn-OFF Time, tOFF VNO or VNC = 10V, RL =1kΩ, CL = 35pF, VIN = 0 to 4V Break-Before-Make Time Delay (ISL5122, ISL5123), tD RL = 300Ω, CL = 35pF, VNO or VNC = 10V, VIN = 0 to 4V Full 0 2 Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω 25 - 5 15 pC OFF Isolation RL = 50Ω, CL = 5pF, f = 1MHz 25 - 76 - dB 25 - -105 - dB 25 - 63 - dB NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V 25 - 8 - pF COM OFF Capacitance, CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V 25 - 8 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, ISL5120/1/2 25 - 21 - pF f = 1MHz, VNO or VNC = VCOM = 0V, ISL5123 25 - 28 - pF Full -1 - 1 µA Full - - 0.8 V Full 2.9 - - V Full 4 3 - V Full -1 - 1 µA Crosstalk (Channel-to-Channel) Power Supply Rejection Ratio RL = 50Ω, CL = 5pF, f = 1MHz ns POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 13V, VIN = 0V or V+, all channels on or off DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH ISL5120CX only Input Voltage High, VINH Input Current, IINH, IINL V+ = 13V, VIN = 0V or V+ Test Circuits and Waveforms 3V OR 4V LOGIC INPUT V+ tr < 20ns tf < 20ns 50% C 0V tOFF SWITCH INPUT SWITCH INPUT VNO VOUT 90% SWITCH OUTPUT VOUT NO or NC COM IN 90% 0V LOGIC INPUT GND RL 1kΩ CL 35pF tON Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for all switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) -----------------------------R L + R ( ON ) FIGURE 1A. MEASUREMENT POINTS FIGURE 1B. TEST CIRCUIT FIGURE 1. SWITCHING TIMES 7 FN6022.6 November 17, 2004 ISL5120, ISL5121, ISL5122, ISL5123 Test Circuits and Waveforms (Continued) V+ SWITCH OUTPUT VOUT RG ∆VOUT C VOUT COM NO or NC V+ LOGIC INPUT VG ON ON GND IN CL OFF 0V LOGIC INPUT Q = ∆VOUT x CL FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUIT FIGURE 2. CHARGE INJECTION V+ 3V OR 4V LOGIC INPUT 0V C VOUT1 NO1 VNX COM1 VOUT2 RL1 300Ω NC2 SWITCH OUTPUT VOUT1 COM2 90% IN1 0V RL2 300Ω IN2 SWITCH OUTPUT VOUT2 CL1 35pF 90% 0V LOGIC INPUT CL2 35pF GND tD tD CL includes fixture and stray capacitance. FIGURE 3A. MEASUREMENT POINTS (ISL5122 ONLY) FIGURE 3B. TEST CIRCUIT (ISL5122 ONLY) V+ 3V OR 4V LOGIC INPUT 0V C NO VNX RL 300Ω IN SWITCH OUTPUT VOUT VOUT COM NC 90% CL 35pF GND LOGIC INPUT 0V tD CL includes fixture and stray capacitance. FIGURE 3C. MEASUREMENT POINTS (ISL5123 ONLY) FIGURE 3D. TEST CIRCUIT (ISL5123 ONLY) FIGURE 3. BREAK-BEFORE-MAKE TIME 8 FN6022.6 November 17, 2004 ISL5120, ISL5121, ISL5122, ISL5123 Test Circuits and Waveforms (Continued) V+ V+ C C RON = V1/1mA SIGNAL GENERATOR NO or NC NO or NC VNX INX 0V or VINH 1mA 0.8V or VINH COM COM ANALYZER IN V1 GND GND RL FIGURE 4. OFF ISOLATION TEST CIRCUIT FIGURE 5. RON TEST CIRCUIT V+ C V+ C SIGNAL GENERATOR NO1 or NC1 COM1 50Ω NO or NC IN1 COM2 ANALYZER INX IN2 0V or VINH 0V or 2.4V NO2 or NC2 GND 0V or VINH IMPEDANCE ANALYZER COM NC GND RL FIGURE 6. CROSSTALK TEST CIRCUIT FIGURE 7. CAPACITANCE TEST CIRCUIT Detailed Description Supply Sequencing And Overvoltage Protection The ISL5120–ISL5123 bidirectional, dual analog switches offer precise switching capability from a single 2.7V to 12V supply with low on-resistance (19Ω) and high speed operation (tON = 28ns, tOFF = 20ns). The devices are especially well suited to portable battery powered equipment thanks to the low operating supply voltage (2.7V), low power consumption (5µW), low leakage currents (100pA max), and the tiny SOT-23 packaging. High frequency applications also benefit from the wide bandwidth, and the very high off isolation and crosstalk rejection. With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and GND (See Figure 8). To prevent forward biasing these diodes, V+ must be applied before any input signals, and input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. 9 Logic inputs can easily be protected by adding a 1kΩ resistor in series with the input (See Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current FN6022.6 November 17, 2004 ISL5120, ISL5121, ISL5122, ISL5123 produces an insignificant voltage drop during normal operation. Adding a series resistor to the switch input defeats the purpose of using a low RON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (See Figure 8). These additional diodes limit the analog signal from 1V below V+ to 1V above GND. The low leakage current performance is unaffected by this approach, but the switch resistance may increase, especially at low supply voltages. OPTIONAL PROTECTION DIODE V+ OPTIONAL PROTECTION RESISTOR INX VNO or NC VCOM GND OPTIONAL PROTECTION DIODE FIGURE 8. OVERVOLTAGE PROTECTION Power-Supply Considerations The ISL512X construction is typical of most CMOS analog switches, except that they have only two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 13V maximum supply voltage, the ISL512X 15V maximum supply voltage provides plenty of room for the 10% tolerance of 12V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 2.7V. It is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance curves for details. V+ and GND also power the internal logic and level shifters. The level shifters convert the input logic levels to switched V+ and GND signals to drive the analog switch gate terminals. This family of switches cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration. 10 Logic-Level Thresholds This switch family is TTL compatible (0.8V and 2.4V) over a supply range of 3V to 11V (See Figure 15). At 12V the VIH level is about 2.5V. This is still below the TTL guaranteed high output minimum level of 2.8V, but the noise margin is reduced. For best results with a 12V supply, use a logic family the provides a VOH greater than 3V. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. High-Frequency Performance In 50Ω systems, signal response is reasonably flat even past 300MHz (See Figure 16). Figure 16 also illustrates that the frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch’s input to its output. Off Isolation is the resistance to this feedthrough, while Crosstalk indicates the amount of feedthrough from one switch to another. Figure 17 details the high Off Isolation and Crosstalk rejection provided by this family. At 10MHz, Off Isolation is about 50dB in 50Ω systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation and Crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance. Leakage Considerations Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND. FN6022.6 November 17, 2004 ISL5120, ISL5121, ISL5122, ISL5123 Typical Performance Curves TA = 25°C, Unless Otherwise Specified 45 40 V+ = 3.3V 40 35 35 30 30 RON (Ω) 20 25°C 15 25°C 20 25 RON (Ω) 85°C 25 85°C -40°C 15 30 25 V+ = 5V 20 85°C 25°C -40°C 15 10 20 -40°C 10 85°C 15 5 3 4 5 6 7 8 V+ (V) 9 10 11 12 10 13 -40°C 5 0 6 VCOM (V) 8 10 12 V+ = 3.3V 60 25°C 50 0.2 0.1 0 0.25 0.2 0.15 85°C 40 -40°C 30 V+ = 5V 25°C 0.1 Q (pC) ∆RON (Ω) 4 2 FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE 0.5 0.4 0.3 V+ = 12V 25°C 85°C 20 V+ = 12V 10 85°C 0.05 0 0.15 V+ = 5V V+ = 3.3V -40°C 0 V+ = 12V 25°C 0.1 -40°C 0.05 -10 85°C 25°C -40°C -20 2 0 4 6 8 2 0 0 10 4 6 VCOM (V) 12 VCOM (V) FIGURE 11. RON MATCH vs SWITCH VOLTAGE 8 10 12 FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE 100 35 90 80 30 85°C tOFF (ns) tON (ns) 70 60 85°C 25 50 -40°C -40°C 40 20 -40°C 25°C 30 25°C 20 15 2 3 4 5 6 7 V+ (V) 8 9 10 11 FIGURE 13. TURN-ON TIME vs SUPPLY VOLTAGE 11 12 2 3 4 5 6 7 V+ (V) 8 9 10 11 12 FIGURE 14. TURN-OFF TIME vs SUPPLY VOLTAGE FN6022.6 November 17, 2004 ISL5120, ISL5121, ISL5122, ISL5123 3.0 2.5 VINH AND VINL (V) VINH -40°C 2.0 85°C V+ = 3.3V to 12V 0 GAIN -3 -6 0 PHASE 20 25°C 1.5 85°C 40 -40°C 60 25°C 1.0 RL = 50Ω VIN = 0.2VP-P to 2.5VP-P (V+ = 3.3V) VIN = 0.2VP-P to 4VP-P (V+ = 5V) VIN = 0.2VP-P to 5VP-P (V+ = 12V) VINL 85°C 0.5 2 3 4 5 6 7 8 V+ (V) 9 10 11 12 13 1 10 80 PHASE (DEGREES) NORMALIZED GAIN (dB) Typical Performance Curves TA = 25°C, Unless Otherwise Specified (Continued) 100 100 600 FREQUENCY (MHz) FIGURE 16. FREQUENCY RESPONSE FIGURE 15. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE -10 10 RL = 50Ω V+ = 3V to 13V -20 20 0 -30 30 10 -40 40 20 -50 50 60 ISOLATION -70 70 -80 80 -90 ±PSRR (dB) -60 OFF ISOLATION (dB) CROSSTALK (dB) V+ = 3.3V, SWITCH OFF V+ = 12V, SWITCH OFF 30 40 V+ = 12V, SWITCH ON 50 60 90 70 100 80 V+ = 3.3V, SWITCH ON CROSSTALK -100 -110 1k 10k 100k 1M 10M 110 100M 500M 0.3 1 10 100 1000 FREQUENCY (Hz) FREQUENCY (MHz) FIGURE 17. CROSSTALK AND OFF ISOLATION FIGURE 18. ±PSRR vs FREQUENCY Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: ISL5120: 66 ISL5121: 66 ISL5122: 66 ISL5123: 58 PROCESS: Si Gate CMOS 12 FN6022.6 November 17, 2004 ISL5120, ISL5121, ISL5122, ISL5123 Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) N INDEX AREA H 0.25(0.010) M 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M E INCHES -B- 1 2 SYMBOL 3 L SEATING PLANE -A- h x 45o A D -C- e α A1 B 0.25(0.010) M C C A M B S 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. MILLIMETERS MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 0.050 BSC H 0.2284 h L α 1.27 BSC - 0.2440 5.80 6.20 - 0.0099 0.0196 0.25 0.50 5 0.016 0.050 0.40 1.27 6 8o 0o N NOTES: MAX A1 e 0.10(0.004) MIN 8 0o 8 7 8o Rev. 0 12/93 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 13 FN6022.6 November 17, 2004 ISL5120, ISL5121, ISL5122, ISL5123 Small Outline Transistor Plastic Packages (SOT23-6) 0.20 (0.008) M P6.064 VIEW C C 6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE CL INCHES e b SYMBOL 6 5 4 CL CL E1 E 1 2 3 e1 C D CL A A2 SEATING PLANE A1 -C- WITH b PLATING b1 c c1 MILLIMETERS MAX MIN MAX NOTES A 0.036 0.057 0.90 1.45 - A1 0.000 0.0059 0.00 0.15 - A2 0.036 0.051 0.90 1.30 - b 0.012 0.020 0.30 0.50 - b1 0.012 0.018 0.30 0.45 c 0.003 0.009 0.08 0.22 6 c1 0.003 0.008 0.08 0.20 6 D 0.111 0.118 2.80 3.00 3 E 0.103 0.118 2.60 E1 0.060 0.068 1.50 3.00 - 1.75 3 e 0.0374 Ref 0.95 Ref - e1 0.0748 Ref 1.90 Ref - L 0.10 (0.004) C MIN 0.014 0.022 0.35 0.55 L1 0.024 Ref. 0.60 Ref. L2 0.010 Ref. 0.25 Ref. N 6 6 4 5 R 0.004 - 0.10 - R1 0.004 0.010 0.10 0.25 α 0o 8o 0o 8o Rev. 3 9/03 BASE METAL NOTES: 1. Dimensioning and tolerance per ASME Y14.5M-1994. 4X θ1 2. Package conforms to EIAJ SC-74 and JEDEC MO178AB. 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. R1 4. Footlength L measured at reference to gauge plane. R 5. “N” is the number of terminal positions. GAUGE PLANE SEATING PLANE L C L1 α L2 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only 4X θ1 VIEW C 14 FN6022.6 November 17, 2004 ISL5120, ISL5121, ISL5122, ISL5123 Small Outline Transistor Plastic Packages (SOT23-8) 0.20 (0.008) M CL P8.064 C VIEW C 8 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE e b INCHES SYMBOL 8 6 7 5 CL CL E 1 2 3 E1 MILLIMETERS MAX MIN MAX NOTES A 0.036 0.057 0.90 1.45 - A1 0.000 0.0059 0.00 0.15 - A2 0.036 0.051 0.90 1.30 - b 0.009 0.015 0.22 0.38 - b1 0.009 0.013 0.22 0.33 c 0.003 0.009 0.08 0.22 6 4 e1 C D CL A MIN A2 A1 SEATING PLANE -C- c1 0.003 0.008 0.08 0.20 6 D 0.111 0.118 2.80 3.00 3 E 0.103 0.118 2.60 3.00 - E1 0.060 0.067 1.50 1.70 3 e 0.0256 Ref 0.65 Ref - e1 0.0768 Ref 1.95 Ref - L 0.10 (0.004) C 0.014 0.022 0.35 0.55 L1 0.024 Ref. 0.60 Ref. L2 0.010 Ref. 0.25 Ref. N 8 8 5 WITH b R 0.004 - 0.10 - PLATING b1 R1 0.004 0.010 0.10 0.25 α 0o 8o 0o 8o c c1 4 Rev. 2 9/03 NOTES: BASE METAL 1. Dimensioning and tolerance per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC-74 and JEDEC MO178BA. 4X θ1 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. 4. Footlength L measured at reference to gauge plane. R1 5. “N” is the number of terminal positions. R GAUGE PLANE SEATING PLANE L C L1 α 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only L2 4X θ1 VIEW C All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 15 FN6022.6 November 17, 2004