PD - 9.1718A IRFE330 REPETITIVE AVALANCHE AND dv/dt RATED JANTX2N6800U ® HEXFET TRANSISTOR JANTXV2N6800U [REF:MIL-PRF-19500/557] N-CHANNEL Ω , HEXFET 400Volt, 1.0Ω Product Summary The leadless chip carrier (LCC) package represents the logical next step in the continual evolution of surface mount technology. The LCC provides designers the extra flexibility they need to increase circuit board density. International Rectifier has engineered the LCC package to meet the specific needs of the power market by increasing the size of the bottom source pad, thereby enhancing the thermal and electrical performance. The lid of the package is grounded to the source to reduce RF interference. HEXFET transistors also feature all of the well-established advantages of MOSFETs, such as voltage control, very fast switching, ease of paralleling and electrical parameter temperature stability. They are well-suited for applications such as switching power supplies, motor controls, inverters, choppers, audio amplifiers and high-energy pulse circuits, and virtually any application where high reliability is required. Part Number BVDSS RDS(on) ID IRFE330 400V 1.0Ω 3.0A Features: n n n n n n Hermetically Sealed Simple Drive Requirements Ease of Paralleling Small footprint Surface Mount Lightweight Absolute Maximum Ratings Parameter ID @ VGS = -10V, TC = 25°C ID @ VGS = -10V, TC = 100°C IDM PD @ TC = 25°C VGS EAS dv/dt TJ TSTG Continuous Drain Current Continuous Drain Current Pulsed Drain Current ➀ Max. Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy ➁ Peak Diode Recovery dv/dt ➂ Operating Junction Storage Temperature Range Surface Temperature Weight www.irf.com IRFE330, JANTX-, JANTXV-, 2N6800U Units 3.0 A 2.0 12 25 W 0.20 W/K ➄ ±20 V 0.51 mJ 8.4 V/ns -55 to 150 o 300 ( for 5 seconds) 0.42 (typical) C g 1 3/25/98 IRFE330, JANTX-, JANTXV-, 2N6800U Device Electrical Characteristics @ Tj = 25°C (Unless Otherwise Specified) Parameter Min Drain-to-Source Breakdown Voltage 400 — — V VGS =0 V, ID = 1.0mA — 0.35 — V/°C Reference to 25°C, ID = 1.0mA — — 2.0 2.4 — — — — — — — — 1.0 1.15 4.0 — 25 250 — — — — — — — — — — — — — — — — — — — 1.8 100 -100 33 5.8 17 30 35 55 35 — ∆BVDSS/∆TJ Temperature Coefficient of Breakdown Voltage RDS(on) Static Drain-to-Source On-State Resistance VGS(th) Gate Threshold Voltage gfs Forward Transconductance IDSS Zero Gate Voltage Drain Current IGSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD Gate-to-Source Leakage Forward Gate-to-Source Leakage Reverse Total Gate Charge Gate-to-Source Charge Gate-to-Drain (‘Miller’) Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Typ Max Units Ω V S( ) Ω BVDSS µA nA nC ns Internal Source Inductance — 4.3 — Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance — — — 660 190 68 — — — VGS = 10V, ID = 2.0A ➃ VGS = 10V, ID = 3.0A VDS = VGS, ID = 250µA VDS > 15V, IDS = 2.0A ➃ VDS= 0.8 x Max Rating,VGS=0V VDS = 0.8 x Max Rating VGS = 0V, TJ = 125°C VGS = 20 V VGS = -20V VGS = 10V, ID = 3.0A VDS = Max Rating x 0.5 VDD = 200V, ID = 3.0A, RG = 7.5Ω Measured from drain pad to die. nH LS Test Conditions pF Modified MOSFET symbol showing the internal inductances. Measured from center of source pad to the end of source bonding wire. VGS = 0V, VDS = 25 V f = 1.0MHz Source-Drain Diode Ratings and Characteristics Parameter Min Typ Max Units IS ISM Continuous Source Current (Body Diode) Pulse Source Current (Body Diode) ➀ — — — — 3.0 12 A VSD trr QRR Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge — — — — — — 1.4 700 6.2 V ns µC ton Forward Turn-On Time Test Conditions Modified MOSFET symbol showing the integral reverse p-n junction rectifier. Tj = 25°C, IS = 3.0A, VGS = 0V ➃ Tj = 25°C, IF = 3.0A, di/dt ≤ 100A/µs VDD ≤ 50V ➃ Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LD. Thermal Resistance Parameter Min Typ Max RthJC Junction-to-Case — — 5.0 RthJPCB Junction-to-PC Board — — 19 Units Test Conditions K/W ➄ Details of notes 2 through Soldered to a copper clad PC board are on the last page www.irf.com IRFE330, JANTX-, JANTXV-, 2N6800U Device 100 100 VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 10 1 4.5V 0.1 20µs PULSE WIDTH TJ = 25 °C 0.01 0.1 1 10 10 4.5V 1 R DS(on) , Drain-to-Source On Resistance (Normalized) I D , Drain-to-Source Current (A) 3.5 TJ = 150 ° C TJ = 25 ° C 1 V DS = 50V 20µs PULSE WIDTH 5 6 VGS , Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics www.irf.com 10 100 Fig 2. Typical Output Characteristics 100 4 1 VDS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics 0.1 20µs PULSE WIDTH TJ = 150 °C 0.1 0.1 100 VDS , Drain-to-Source Voltage (V) 10 VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP I D , Drain-to-Source Current (A) I D , Drain-to-Source Current (A) TOP 7 ID = 3.0A 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -60 -40 -20 VGS = 10V 0 20 40 60 80 100 120 140 160 TJ , Junction Temperature( °C) Fig 4. Normalized On-Resistance Vs. Temperature 3 IRFE330, JANTX-, JANTXV-, 2N6800U Device VGS = Ciss = Crss = Coss = C, Capacitance (pF) 1200 20 0V, f = 1MHz Cgs + Cgd , Cds SHORTED Cgd Cds + Cgd VGS , Gate-to-Source Voltage (V) 1500 900 C iss 600 Coss 300 C rss ID = 3.0 A VDS = 320V VDS = 200V VDS = 80V 16 12 8 4 FOR TEST CIRCUIT SEE FIGURE 13 0 0 1 10 0 100 100 30 40 100 OPERATION IN THIS AREA LIMITED BY RDS(on) 10 I D , Drain Current (A) ISD , Reverse Drain Current (A) 20 Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage TJ = 150 ° C TJ = 25 ° C 1 0.1 0.0 V GS = 0 V 0.2 0.4 0.6 0.8 1.0 VSD ,Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 4 10 Q G , Total Gate Charge (nC) VDS , Drain-to-Source Voltage (V) 10 10us 100us 1 1ms TC = 25 ° C TJ = 150 ° C Single Pulse 0.1 1.2 1 10ms 10 100 1000 VDS , Drain-to-Source Voltage (V) Fig 8. Maximum Safe Operating Area www.irf.com IRFE330, JANTX-, JANTXV-, 2N6800U Device RD VDS 3.0 VGS D.U.T. I D , Drain Current (A) RG + -VDD 2.0 10V Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % Fig 10a. Switching Time Test Circuit 1.0 VDS 90% 0.0 25 50 75 100 125 150 TC , Case Temperature ( ° C) 10% VGS td(on) Fig 9. Maximum Drain Current Vs. Case Temperature tr t d(off) tf Fig 10b. Switching Time Waveforms Thermal Response (Z thJC ) 10 D = 0.50 0.20 1 0.10 0.05 0.02 0.01 0.1 P DM SINGLE PULSE (THERMAL RESPONSE) t1 t2 0.01 0.00001 Notes: 1. Duty factor D = t 1 / t 2 2. Peak TJ = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1 1 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRFE330, JANTX-, JANTXV-, 2N6800U Device 1 5V L VD S + - VD D IA S 20V 1 BOTTOM ID 1.3A 1.9A 3.0A A 0.50 0 .0 1 Ω tp TOP 1.00 D R IV E R D .U .T RG EAS , Single Pulse Avalanche Energy (mJ) 1.50 Fig 12a. Unclamped Inductive Test Circuit V (B R )D S S tp 0.00 25 50 75 100 125 150 Starting TJ , Junction Temperature ( °C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current IAS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ QG 12V 0 .2µF .3µF 10 V QGS D.U.T. QGD + V - DS VGS VG 3mA IG Charge Fig 13a. Basic Gate Charge Waveform 6 ID Current Sampling Resistors Fig 13b. Gate Charge Test Circuit www.irf.com IRFE330, JANTX-, JANTXV-, 2N6800U Device Peak Diode Recovery dv/dt Test Circuit + D.U.T Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer + - - + • • • • RG Driver Gate Drive P.W. + dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test D= Period - VDD P.W. Period VGS=10V * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent Ripple ≤ 5% ISD * VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS www.irf.com 7 IRFE330, JANTX-, JANTXV-, 2N6800U Device Notes: ➀ Repetitive Rating; Pulse width limited by ➁ @ VDD = 50 V, Starting TJ = 25°C, maximum junction temperature. Refer to current HEXFET reliability report. ➃ Pulse width ≤ 300 µs; Duty Cycle ≤ 2% EAS = [0.5 * L * (IL2) ] Peak IL = 3.0A, VGS = 10 V, 25 ≤ RG ≤ 200Ω ➂ ISD ≤ 3.0A, di/dt ≤ 63 A/µs, VDD ≤ BVDSS, TJ ≤ 150°C Suggested RG = 2.35Ω ➄ K/W = °C/W Case Outline and Dimensions — Leadless Chip Carrier (LCC) Package IR Case Style Leadless Chip Carrier (LCC) WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331 EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020 IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) 475 1897 IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590 IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111 IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086 IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371 http://www.irf.com/ Data and specifications subject to change without notice. 3/98 8 www.irf.com