Samsung K4B4G0446B Ddp 4gb b-die ddr3 sdram specification Datasheet

K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
DDP 4Gb B-die DDR3 SDRAM Specification
78 FBGA with Lead-Free & Halogen-Free
(RoHS Compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE
CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT
GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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Rev. 1.0 March 2009
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DDP 4Gb DDR3 SDRAM
Revision History
Revision
Month
Year
1.0
March
2009
History
- First release
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DDP 4Gb DDR3 SDRAM
Table Contents
1.0 Ordering Information ................................................................................................................... 5
2.0 Key Features ................................................................................................................................ 5
3.0 Package pinout/Mechanical Dimension & Addressing ............................................................ 6
3.1 x4 DDP Package Pinout (Top view) : 78ball FBGA Package .............................................................. 6
3.2 x8 DDP Package Pinout (Top view) : 78ball FBGA Package .............................................................. 7
3.3 FBGA Package Dimension (x4) ..................................................................................................... 8
3.4 FBGA Package Dimension (x8) ..................................................................................................... 9
4.0 Input/Output Functional Description ....................................................................................... 10
5.0 DDR3 SDRAM Addressing ........................................................................................................ 11
6.0 Absolute Maximum Ratings ...................................................................................................... 12
6.1 Absolute Maximum DC Ratings ................................................................................................... 12
6.2 DRAM Component Operating Temperature Range ......................................................................... 12
7.0 AC & DC Operation Conditions ................................................................................................ 12
7.1 Recommended DC operating Conditions (SSTL_1.5) ..................................................................... 12
8.0 AC & DC Input Measurement Levels ........................................................................................ 13
8.1 AC and DC Logic input levels for single-ended singnals ................................................................ 13
8.2 VREF Tolerances ....................................................................................................................... 14
8.3 AC and DC Logic Input Levels for Ditterential Signals ................................................................... 15
8.3.1 Differential signal definition ................................................................................................ 15
8.3.2 Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS) .............................. 15
8.3.3 Single-ended requirements for differential signals ................................................................. 16
8.4 Differential Input Cross Point Voltage .......................................................................................... 17
8.5 Slew Rate Definition for Single Ended Input Signals ...................................................................... 17
8.6 Slew rate definition for Differential Input Signals ........................................................................... 17
9.0 AC and DC Output Measurement Levels ................................................................................. 18
9.1 Single Ended AC and DC Output Levels ....................................................................................... 18
9.2 Differential AC and DC Output Levels .......................................................................................... 18
9.3 Single Ended Output Slew Rate ................................................................................................... 18
9.4 Differential Output Slew Rate ...................................................................................................... 19
9.5 Reference Load for AC Timing and Output Slew Rate .................................................................... 19
9.6 Overshoot/Undershoot Specification ........................................................................................... 20
9.6.1 Address and Control Overshoot and Undershoot specifications ............................................. 20
9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot specifications ................................. 20
9.7 34 ohm Output Driver DC Electrical Characteristics ....................................................................... 21
................................................................. 22
9.8 On-Die Termination (ODT) Levels and I-V Characteristics ............................................................... 22
9.8.1 ODT DC electrical characteristics ........................................................................................ 23
9.8.2 ODT Temperature and Voltage sensitivity ............................................................................. 24
9.7.1 Output Drive Temperature and Voltage sensitivity
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.............................................................................................................. 25
9.9.1 Test Load for ODT Timings ................................................................................................. 25
9.9.2 ODT Timing Definition ........................................................................................................ 25
9.9 ODT Timing Definitions
10.0 IDD Specification Parameters and Test Conditions ............................................................. 28
10.1 IDD Measurement Conditions .................................................................................................... 28
10.2 IDD Specifications definition ..................................................................................................... 30
11.0 DDP 4Gb DDR3 SDRAM B-die IDD Spec Table ..................................................................... 37
12.0 Input/Output Capacitance ....................................................................................................... 38
13.0 Electrical Characteristics and AC timing for DDR3-800 to DDR3-1600 .............................. 39
13.1 Clock specification ............................................................................................................. 39
13.1.1 Definition for tCK (avg) ..................................................................................................... 39
13.1.2 Definition for tCK (abs) ..................................................................................................... 39
13.1.3 Definition for tCH(avg) and tCL(avg) ................................................................................... 39
13.1.4 Definition for note for tJIT(per), tJIT(per,Ick) ........................................................................ 39
...................................................................................... 39
13.1.6 Definition for tERR(nper) ................................................................................................... 39
13.2 Refresh Parameters by Device Density ....................................................................................... 40
13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ............................................. 40
13.3.1 Speed Bin Table Notes........................................................................................................................... 43
13.1.5 Definition for tJIT(cc), tJIT(cc,Ick)
14.0 Timing Parameters by Speed Grade ...................................................................................... 44
14.1 Jitter Notes ............................................................................................................................. 47
14.2 Timing Parameter Notes ........................................................................................................... 48
14.3 Address / Command Setup, Hold and Derating: ........................................................................... 49
14.4 Data Setup, Hold and Slew Rate Derating: .................................................................................. 55
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1.0 Ordering Information
[ Table 1 ] Samsung DDP 4Gb DDR3 B-die ordering information table
Organization
DDR3-800 (6-6-6)
DDR3-1066 (7-7-7)
DDR3-1333 (9-9-9)
Package
1Gx4
K4B4G0446B-MCF7
K4B4G0446B-MCF8
K4B4G0446B-MCH9
78 FBGA
512Mx8
K4B4G0846B-MCF7
K4B4G0846B-MCF8
K4B4G0846B-MCH9
78 FBGA
Note :
1. Speed bin is in order of CL-tRCD-tRP.
2.0 Key Features
[ Table 2 ] DDP 4Gb DDR3 B-die Speed bins
Speed
DDR3-800
DDR3-1066
DDR3-1333
6-6-6
7-7-7
9-9-9
2.5
1.875
1.5
ns
tCK(min)
Unit
CAS Latency
6
7
9
nCK
tRCD(min)
15
13.125
13.5
ns
tRP(min)
15
13.125
13.5
ns
tRAS(min)
37.5
37.5
36
ns
tRC(min)
52.5
50.625
49.5
ns
• JEDEC standard 1.5V ± 0.075V Power Supply
• VDDQ = 1.5V ± 0.075V
• 400 MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin,
667MHz fCK for 1333Mb/sec/pin
• 8 Banks
• Posted CAS
• Programmable CAS Latency(posted CAS): 6, 7, 8, 9, 10
• Programmable Additive Latency: 0, CL-2 or CL-1 clock
• Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6
(DDR3-1066) and 7 (DDR3-1333)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting
address “000” only), 4 with tCCD = 4 which does not allow seamless
read or write [either On the fly using A12 or MRS]
• Bi-directional Differential Data-Strobe
The DDP 4Gb DDR3 SDRAM B-die is organized as a 128Mbit x 4 I/Os x
8banks, 64Mbit x 8 I/Os x 8banks. This synchronous device achieves high
speed double-data-rate transfer rates of up to 1333Mb/sec/pin (DDR31333) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM features such as posted CAS, Programmable CWL, Internal (Self) Calibration, On Die Termination using ODT pin and Asynchronous Reset .
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the crosspoint of differential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. The DDR3 device operates
with a single 1.5V ± 0.075V power supply and 1.5V ± 0.075V VDDQ.
The 4Gb DDR3 B-die device is available in 78ball FBGAs(x4/x8).
Note : 1. The functionality described and the timing specifications included
in this data sheet are for the DLL Enabled mode of operation.
• Internal(self) calibration : Internal self calibration through ZQ pin
(RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at
85°C < TCASE < 95 °C
• Asynchronous Reset
• Package : 78 balls FBGA - x4/x8
• All of Lead-Free products are compliant for RoHS
• All of products are Halogen-free
Note : This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device
Operation & Timing Diagram”.
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DDP 4Gb DDR3 SDRAM
3.0 Package pinout/Mechanical Dimension & Addressing
3.1 x4 DDP Package Pinout (Top view) : 78ball FBGA Package
1
2
3
4
5
6
7
8
9
A
VSS
VDD
NC
NC
VSS
VDD
A
B
VSS
VSSQ
DQ0
DM
VSSQ
VDDQ
B
C
VDDQ
DQ2
DQS
DQ1
DQ3
VSSQ
C
D
VSSQ
NC
DQS
VDD
VSS
VSSQ
D
E
VREFDQ
VDDQ
NC
NC
NC
VDDQ
E
F
ODT1
VSS
RAS
CK
VSS
CKE1
F
G
ODT0
VDD
CAS
CK
VDD
CKE0
G
H
CS1
CS0
WE
A10/AP
ZQ0
ZQ1
H
J
VSS
BA0
BA2
NC
VREFCA
VSS
J
K
VDD
A3
A0
A12/BC
BA1
VDD
K
L
VSS
A5
A2
A1
A4
VSS
L
M
VDD
A7
A9
A11
A6
VDD
M
N
VSS
RESET
A13
A14
A8
VSS
N
1
Ball Locations (x4)
2
3
4
5
6
7
8
9
A
B
C
Populated ball
Ball not populated
D
E
F
G
H
Top view
(See the balls through the package)
J
K
L
M
N
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K4B4G0846B
DDP 4Gb DDR3 SDRAM
3.2 x8 DDP Package Pinout (Top view) : 78ball FBGA Package
1
2
3
4
5
6
7
8
9
A
VSS
VDD
NC
NU/TDQS
VSS
VDD
A
B
VSS
VSSQ
DQ0
DM/TDQS
VSSQ
VDDQ
B
C
VDDQ
DQ2
DQS
DQ1
DQ3
VSSQ
C
D
VSSQ
DQ6
DQS
VDD
VSS
VSSQ
D
E
VREFDQ
VDDQ
DQ4
DQ7
DQ5
VDDQ
E
F
ODT1
VSS
RAS
CK
VSS
CKE1
F
G
ODT0
VDD
CAS
CK
VDD
CKE0
G
H
CS1
CS0
WE
A10/AP
ZQ0
ZQ1
H
J
VSS
BA0
BA2
NC
VREFCA
VSS
J
K
VDD
A3
A0
A12/BC
BA1
VDD
K
L
VSS
A5
A2
A1
A4
VSS
L
M
VDD
A7
A9
A11
A6
VDD
M
N
VSS
RESET
A13
A14
A8
VSS
N
1
Ball Locations (x8)
2
3
4
5
6
7
8
9
A
B
C
Populated ball
Ball not populated
D
E
F
G
H
Top view
(See the balls through the package)
J
K
L
M
N
Page 7 of 59
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DDP 4Gb DDR3 SDRAM
3.3 FBGA Package Dimension (x4)
Units : Millimeters
10.00 ± 0.10
A
0.80 x 8 = 6.40
(Datum A)
0.80
1.60
#A1 INDEX MARK
3.20
B
11.50 ± 0.10
4.80
0.80
0.80
(Datum B)
A
B
C
D
E
F
G
H
J
K
L
M
N
0.80 x 12 = 9.60
9 8 7 6 5 4 3 2 1
78 - ∅0.45 Solder ball
(Post Reflow ∅0.50 ± 0.05)
0.2 M A B
0.10MAX
BOTTOM VIEW
10.00 ± 0.10
11.50 ± 0.10
#A1
0.35 ± 0.05
TOP VIEW
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1.40 ± 0.10
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DDP 4Gb DDR3 SDRAM
3.4 FBGA Package Dimension (x8)
Units : Millimeters
10.00 ± 0.10
A
0.80 x 8 = 6.40
(Datum A)
0.80
1.60
#A1 INDEX MARK
3.20
B
11.50 ± 0.10
4.80
0.80
0.80
(Datum B)
A
B
C
D
E
F
G
H
J
K
L
M
N
0.80 x 12 = 9.60
9 8 7 6 5 4 3 2 1
78 - ∅0.45 Solder ball
(Post Reflow ∅0.50 ± 0.05)
0.2 M A B
0.10MAX
BOTTOM VIEW
10.00 ± 0.10
11.50 ± 0.10
#A1
0.35 ± 0.05
TOP VIEW
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1.40 ± 0.10
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DDP 4Gb DDR3 SDRAM
4.0 Input/Output Functional Description
[ Table 3 ] Input/Output function description
Symbol
Type
Function
CK, CK
Input
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of
the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and
output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or
Active Power-Down (Row Active in any bank). CKE is asynchronous for self refresh exit. After VREFCA has become
CKE
Input
CS
Input
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on
systems with multiple Ranks. CS is considered part of the command code.
ODT
Input
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When
enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS, NU/TDQS (When TDQS is enabled via Mode
Register A11=1 in MR1) signal for x8 configurations. The ODT pin will be ignored if the Mode Register (MR1) is programmed to disable ODT.
RAS, CAS, WE
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
DM
(DMU), (DML)
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. For x8 device, the function of
DM or TDQS/TDQS is enabled by Mode Register A11 setting in MR1.
BA0 - BA2
Input
Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being
applied. Bank address also determines if the mode register or extended mode register is to be accessed during a
MRS cycle.
Input
Address Inputs: Provided the row address for Active commands and the column address for Read/Write commands
to select one location out of the memory array in the respective bank. (A10/AP and A12/BC have additional functions,
see below)
The address inputs also provide the op-code during Mode Register Set commands.
A10 / AP
Input
Autoprecharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH:Autoprecharge; LOW: No Autoprecharge)
A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or
all banks (A10 HIGH). if only one bank is to be precharged, the bank is selected by bank addresses.
A12 / BC
Input
Burst Chop:A12 is sampled during Read and Write commands to determine if burst chop(on-the-fly) will be performed. (HIGH : no burst chop, LOW : burst chopped). See command truth table for details
RESET
Input
Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH.
RESET must be HIGH during normal operation. RESET is a CMOS rail to rail signal with DC high and low at 80% and
20% of VDD, i.e. 1.20V for DC high and 0.30V for DC low.
DQ
Input/Output
Data Input/ Output: Bi-directional data bus.
Input/Output
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. For the
x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on DQU0-DQU7. The data
strobe DQS, DQSL and DQSU are paired with differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling to the system during reads and writes. DDR3 SDRAM supports differential data strobe only and
does not support single-ended.
Output
Termination Data Strobe: TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in
MR1, DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When
disabled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. x4/
x16 DRAMs must disable the TDQS function via mode register A11=0 in MR1.
A0 - A14
DQS, (DQS)
TDQS, (TDQS)
NC
stable during the power on and initialization sequence, it must be maintained during all operations (including SelfRefresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT
and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during Self -Refresh.
No Connect: No internal electrical connection is present.
VDDQ
Supply
DQ Power Supply: 1.5V +/- 0.075V
VSSQ
Supply
DQ Ground
VDD
Supply
Power Supply: 1.5V +/- 0.075V
VSS
Supply
Ground
VREFDQ
Supply
Reference voltage for DQ
VREFCA
Supply
Reference voltage for CA
ZQ
Supply
Reference Pin for ZQ calibration
Note : Input only pins (BA0-BA2, A0-A12, RAS, CAS, WE, CS, CKE, ODT and RESET) do not supply termination.
Page 10 of 59
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DDP 4Gb DDR3 SDRAM
5.0 DDR3 SDRAM Addressing
1Gb
Configuration
256Mb x 4
128Mb x 8
64Mb x 16
# of Bank
8
8
8
Bank Address
BA0 - BA2
BA0 - BA2
BA0 - BA2
Auto precharge
A10/AP
A10/AP
A10/AP
Row Address
A0 - A13
A0 - A13
A0 - A12
Column Address
A0 - A9,A11
A0 - A 9
A0 - A 9
BC switch on the fly
A12/BC
A12/BC
A12/BC
1 KB
1 KB
2 KB
512Mb x 4
256Mb x 8
128Mb x 16
Page size
*1
2Gb
Configuration
# of Bank
8
8
8
Bank Address
BA0 - BA2
BA0 - BA2
BA0 - BA2
Auto precharge
A10/AP
A10/AP
A10/AP
Row Address
A0 - A14
A0 - A14
A0 - A13
Column Address
A0 - A9,A11
A0 - A 9
A0 - A 9
BC switch on the fly
A12/BC
A12/BC
A12/BC
Page size *1
1 KB
1 KB
2 KB
Configuration
1Gb x 4
512Mb x 8
256Mb x 16
# of Bank
8
8
8
Bank Address
BA0 - BA2
BA0 - BA2
BA0 - BA2
Auto precharge
A10/AP
A10/AP
A10/AP
4Gb
Row Address
A0 - A15
A0 - A15
A0 - A14
Column Address
A0 - A9,A11
A0 - A 9
A0 - A 9
BC switch on the fly
A12/BC
A12/BC
A12/BC
1 KB
1 KB
2 KB
Configuration
2Gb x 4
1Gb x 8
512Mb x 16
# of Bank
8
8
8
Bank Address
BA0 - BA2
BA0 - BA2
BA0 - BA2
Auto precharge
A10/AP
A10/AP
A10/AP
Page size
*1
8Gb
Row Address
A0 - A15
A0 - A15
A0 - A15
Column Address
A0 - A9,A11,A13
A0 - A9,A11
A0 - A 9
BC switch on the fly
A12/BC
A12/BC
A12/BC
2 KB
2 KB
2 KB
Page size
*1
Note 1 : Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered.
Page size is per bank, calculated as follows:
page size = 2 COLBITS * ORG÷8
where, COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits
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DDP 4Gb DDR3 SDRAM
6.0 Absolute Maximum Ratings
6.1 Absolute Maximum DC Ratings
[ Table 4 ] Absolute Maximum DC Ratings
Symbol
Parameter
Rating
Units
Notes
VDD
Voltage on VDD pin relative to Vss
-0.4 V ~ 1.975 V
V
1,3
VDDQ
Voltage on VDDQ pin relative to Vss
-0.4 V ~ 1.975 V
V
1,3
VIN, VOUT
Voltage on any pin relative to Vss
-0.4 V ~ 1.975 V
V
1
TSTG
Storage Temperature
-55 to +100
°C
1, 2
Note :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2
standard.
3. VDD and VDDQ must be within 300mV of each other at all times;and VREF must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than
500mV; VREF may be equal to or less than 300mV.
6.2 DRAM Component Operating Temperature Range
[ Table 5 ] Temperature Range
Symbol
Parameter
rating
Unit
Notes
TOPER
Operating Temperature Range
0 to 95
°C
1, 2, 3
Note :
1. Operating Temperature TOPER is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the
JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0-85°C under all operating conditions
3. Some applications require operation of the Extended Temperature Range between 85°C and 95°C case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us. It is also possible to specify a component
with 1X refresh (tREFI to 7.8us) in the Extended Temperature Range.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with
Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 =
0b)
7.0 AC & DC Operation Conditions
7.1 Recommended DC operating Conditions (SSTL_1.5)
[ Table 6 ] Recommended DC Operating Conditions
Symbol
VDD
VDDQ
Parameter
Rating
Units
Notes
1.575
V
1,2
1.575
V
1,2
Min.
Typ.
Max.
Supply Voltage
1.425
1.5
Supply Voltage for Output
1.425
1.5
Note :
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
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DDP 4Gb DDR3 SDRAM
8.0 AC & DC Input Measurement Levels
8.1 AC and DC Logic input levels for single-ended singnals
[ Table 7 ] Single Ended AC and DC input levels for Command and Address
Symbol
Parameter
DDR3-800/1066
DDR3-1333/1600
Unit
Notes
mV
1
Min.
Max.
Min.
Max.
DC input logic high
VREF + 100
VDD
VREF + 100
VDD
VIL.CA(DC)
DC input logic low
VSS
VREF - 100
VSS
VREF - 100
mV
1
VIH.CA(AC)
AC input logic high
VREF + 175
-
VREF + 175
-
mV
1,2
VIL.CA(AC)
AC input logic low
-
VREF - 175
-
VREF - 175
mV
1,2
VIH.CA(AC150) AC input logic high
-
-
VREF+150
-
mV
1,2
VIL.CA(AC150) AC input logic lowM
-
-
-
VREF-150
mV
1,2
0.49*VDD
0.51*VDD
0.49*VDD
0.51*VDD
V
3,4
Unit
Notes
VIH.CA(DC)
VREFCA(DC)
Reference Voltage for ADD,
CMD inuts
Note :
1. For input only pins except RESET, VREF = VREFCA(DC)
2. See 9.6 "Overshoot and Undershoot specifications"
3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)
4. For reference : approx. VDD/2 ± 15mV
[ Table 8 ] Single Ended AC and DC input levels for DQ and DM
Symbol
Parameter
DDR3-800/1066
DDR3-1333
Min.
Max.
Min.
Max.
VIH.DQ(DC100) DC input logic high
VREF + 100
VDD
VREF + 100
VDD
mV
1
VIL.DQ(DC100) DC input logic low
VSS
VREF - 100
VSS
VREF - 100
mV
1
VIH.DQ(AC175) AC input logic high
VREF + 175
-
VREF + 150
-
mV
1,2,5
VIL.DQ(AC175) AC input logic low
-
VREF - 175
-
VREF - 150
mV
1,2,5
VIH.DQ(AC150) AC input logic high
VREF + 150
Note 2
-
-
mV
1,2,5
VIL.DQ(AC150) AC input logic low
Note 2
VREF - 150
-
-
mV
1,2,5
0.49*VDD
0.51*VDD
0.49*VDD
0.51*VDD
V
3,4
VREFDQ(DC)
I/O Reference Voltage(DQ)
Note :
1. For input only pins except RESET, VREF = VREFDQ(DC)
2. See "Overshoot and Undershoot specifications"
3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)
4. For reference : approx. VDD/2 ± 15mV
5. Single ended swing requirement for DQS - DQS is 350mV (peak to peak). Differential swing for DQS - DQS is 700mV (peak to peak).
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8.2 VREF Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in Figure 1. It shows a valid reference voltage
VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise).
VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requiremts in table 7. Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than ± 1% VDD.
voltage
VDD
VSS
time
Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF.
"VREF" shall be understood as VREF(DC), as defined in Figure 1.
This clarifies, that dc-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to
which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the
data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF ac-noise. Timing
and voltage effects due to ac-noise on VREF up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.
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8.3 AC and DC Logic Input Levels for Ditterential Signals
8.3.1 Differential signal definition
tDVAC
Differential Input Voltage (i.e. DQS-DQS, CK-CK)
VIH.DIFF.AC.MIN
VIH.DIFF.MIN
0.0
half cycle
VIL.DIFF.MAX
VIL.DIFF.AC.MAX
tDVAC
time
Figure 2 : Definition of differential ac-swing and "time above ac level" tDVAC
8.3.2 Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)
[ Table 9 ] Defferential AC and DC Input Levels
Symbol
Parameter
VIHdiff
DDR3-800/1066/1333/1600
unit
Note
note 3
V
1
note 3
-0.2
V
1
differential input high ac
2 x (VIH(AC)-VREF)
note 3
V
2
differential input low ac
note 3
2 x (VREF - VIL(AC))
V
2
min
max
differential input high
+0.2
VILdiff
differential input low
VIHdiff(AC)
VILdiff(AC)
Notes:
1. Used to define a differential signal slew-rate.
2. for CK - CK use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - DQS, DQSL - DQSL, DQSU - DQSU use VIH/VIL(AC) of DQs and VREFDQ; if a
reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective
limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Reter to "overshoot and Undersheet
Specification "
[ Table 10 ] Allowed time before ringback (tDVAC) for CLK - CLK and DQS - DQS
Slew Rate [V/ns]
tDVAC [ps] @ |VIH/Ldiff(AC)| = 350mV
tDVAC [ps] @ |VIH/Ldiff(AC)| = 300mV
min
max
min
max
> 4.0
75
-
175
-
4.0
57
-
170
-
3.0
50
-
167
-
2.0
38
-
163
-
1.8
34
-
162
-
1.6
29
-
161
-
1.4
22
-
159
-
1.2
13
-
155
-
1.0
0
-
150
-
< 1.0
0
-
150
-
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8.3.3 Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for
single-ended signals.
CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels ( VIH(AC) / VIL(AC) ) for ADD/CMD signals) in every
half-cycle.
DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels ( VIH(AC) / VIL(AC) ) for DQ signals) in every half-cycle
preceeding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if VIH150(AC)/VIL150(AC) is used for ADD/CMD signals, then these ac-levels apply also for the single-ended signals CK and CK .
VDD or VDDQ
VSEH min
VSEH
VDD/2 or VDDQ/2
CK or DQS
VSEL max
VSEL
VSS or VSSQ
time
Figure 3 : Single-ended requirement for differential signals.
Note that while ADD/CMD and DQ signal requirements are with respect to VREF, the single-ended components of differential signals have a requirement
with respect to VDD/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For singleended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common
mode charateristics of these signals.
[ Table 11 ] Single ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU
Symbol
VSEH
VSEL
Parameter
DDR3-800/1066/1333/1600
Unit
Notes
Note3
V
1, 2
Note3
V
1, 2
Note3
(VDD/2)-0.175
V
1, 2
Note3
(VDD/2)-0.175
V
1, 2
Min
Max
Single-ended high-level for strobes
(VDD/2)+0.175
Single-ended high-level for CK, CK
(VDD/2)+0.175
Single-ended low-level for strobes
Single-ended low-level for CK, CK
Notes:
1. For CK, CK use VIH/VIL(AC) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL(AC) of DQs.
2. VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VIH(AC)/VIL(AC) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a
signal group, then the reduced level applies also here
3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective
limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot
Specification"
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8.4 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input
signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage VIX is measured from the actual
cross point of true and complement signal to the mid level between of VDD and VSS.
VDD
CK, DQS
VIX
VDD/2
VIX
VIX
CK, DQS
VSS
Figure 4. VIX Definition
[ Table 12 ] Cross point voltage for differential input signals (CK, DQS)
Symbol
DDR3-800/1066/1333/1600
Parameter
VIX
Differential Input Cross Point Voltage relative to VDD/2 for CK,CK
VIX
Differential Input Cross Point Voltage relative to VDD/2 for DQS,DQS
Unit
Min
Max
-150
150
mV
-175
175
mV
-150
150
mV
Notes
1
Note :
1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CKand CK are monotonic, have a single-ended swing VSEL /
VSEH of at least VDD/2 =/-250 mV, and the differential slew rate of CK-CK is larger than 3 V/ ns. Refer to table 11 on page 17 for VSEL and VSEH standard values.
8.5 Slew Rate Definition for Single Ended Input Signals
See 14.3 "Address / Command Setup, Hold and Derating" for single-ended slew rate definitions for address and command signals.
See 14.4 "Data Setup, Hold and Slew Rate Derating" for single-ended slew rate definitions for data signals.tDH nominal slew rate for a falling signal is
defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF
8.6 Slew rate definition for Differential Input Signals
Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in Table 13 and Figure 5.
[ Table 13 ] Differential input slew rate definition
Measured
Description
Differential input slew rate for rising edge (CK-CK and DQS-DQS)
Differential input slew rate for falling edge (CK-CK and DQS-DQS)
From
To
VILdiffmax
VIHdiffmin
VIHdiffmin
Defined by
VIHdiffmin - VILdiffmax
Delta TRdiff
VIHdiffmin - VILdiffmax
VILdiffmax
Delta TFdiff
Note : The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds
VIHdiffmin
0
VILdiffmax
delta TRdiff
delta TFdiff
Figure 5. Differential Input Slew Rate definition for DQS, DQS and CK, CK
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9.0 AC and DC Output Measurement Levels
9.1 Single Ended AC and DC Output Levels
[ Table 14 ] Single Ended AC and DC output levels
Symbol
Parameter
DDR3-800/1066/1333/1600
Units
VOH(DC)
DC output high measurement level (for IV curve linearity)
0.8 x VDDQ
V
VOM(DC)
DC output mid measurement level (for IV curve linearity)
0.5 x VDDQ
V
VOL(DC)
DC output low measurement level (for IV curve linearity)
0.2 x VDDQ
V
Notes
VOH(AC)
AC output high measurement level (for output SR)
VTT + 0.1 x VDDQ
V
1
VOL(AC)
AC output low measurement level (for output SR)
VTT - 0.1 x VDDQ
V
1
Note : 1. The swing of +/-0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω
and an effective test load of 25Ω to VTT=VDDQ/2.
9.2 Differential AC and DC Output Levels
[ Table 15 ] Differential AC and DC output levels
Symbol
Parameter
DDR3-800/1066/1333/1600
Units
Notes
VOHdiff(AC)
AC differential output high measurement level (for output SR)
+0.2 x VDDQ
V
1
VOLdiff(DC)
AC differential output low measurement level (for output SR)
-0.2 x VDDQ
V
1
Note : 1. The swing of +/-0.2xVDDQ is based on approximately 50% of the static singel ended output high or low swing with a driver impedance of 40Ω
and an effective test load of 25Ω to VTT=VDDQ/2 at each of the differential outputs.
9.3 Single Ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC)
for single ended signals as shown in Table 16 and figure 6.
[ Table 16 ] Single Ended Output slew rate definition
Measured
Description
Defined by
From
To
Single ended output slew rate for rising edge
VOL(AC)
VOH(AC)
Single ended output slew rate for falling edge
VOH(AC)
VOL(AC)
VOH(AC)-VOL(AC)
Delta TRse
VOH(AC)-VOL(AC)
Delta TFse
Note : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 17 ] Single Ended Output slew rate
Parameter
Single ended output slew rate
Symbol
SRQse
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Min
Max
Min
Max
Min
Max
Min
Max
2.5
5
2.5
5
2.5
5
TBD
5
Units
V/ns
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output
se : Singe-ended Signals
For Ron = RZQ/7 setting
VOH(AC)
VTT
VOL(AC)
delta TFse
delta TRse
Figure 6. Single Ended Output Slew Rate definition
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9.4 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and
VOHdiff(AC) for differential signals as shown inTable 18 and figure 7.
[ Table 18 ] Differential Output slew rate definition
Measured
Description
Differential output slew rate for rising edge
To
VOLdiff(AC)
VOHdiff(AC)
VOHdiff(AC)
Differential output slew rate for falling edge
Defined by
From
VOHdiff(AC)-VOLdiff(AC)
Delta TRdiff
VOHdiff(AC)-VOLdiff(AC)
VOLdiff(AC)
Delta TFdiff
Note : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 19 ] Differential Output slew rate
Parameter
Differential output slew rate
Symbol
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Min
Max
Min
Max
Min
Max
Min
Max
5
10
5
10
5
10
TBD
10
SRQse
Units
V/ns
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output
diff : Singe-ended Signals
For Ron = RZQ/7 setting
VOHdiff(AC)
VTT
VOLdiff(AC)
delta TFdiff
delta TRdiff
Figure 7. Differential Output Slew Rate definition
9.5 Reference Load for AC Timing and Output Slew Rate
Figure 8 represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate
measurements.
It is not intended as a precise representation of any particular system environment of a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their
production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.
VDDQ
CK/CK
DUT
DQ
DQS
DQS
VTT = VDDQ/2
25Ω
Reference
Point
Figure 8. Reference Load for AC Timing and Output Slew Rate
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9.6 Overshoot/Undershoot Specification
9.6.1 Address and Control Overshoot and Undershoot specifications
[ Table 20 ] AC overshoot/undershoot specification for Address and Control pins (A0-A12, BA0-BA2, CS, RAS, CAS, WE, CKE, ODT)
Specification
Parameter
Maximum peak amplitude allowed for overshoot area (See Figure 9)
Maximum peak amplitude allowed for undershoot area (See Figure 9)
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
0.4V
0.4V
0.4V
0.4V
Unit
V
0.4V
0.4V
0.4V
0.4V
V
Maximum overshoot area above VDD (See Figure 9)
0.67V-ns
0.5V-ns
0.4V-ns
0.33V-ns
V-ns
Maximum undershoot area below VSS (See Figure 9)
0.67V-ns
0.5V-ns
0.4V-ns
0.33V-ns
V-ns
Maximum Amplitude
Volts
(V)
Overshoot Area
VDD
VSS
Undershoot Area
Maximum Amplitude
Time (ns)
Figure 9. Address and Control Overshoot and Undershoot definition
9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot specifications
[ Table 21 ] AC overshoot/undershoot specification for Clock, Data, Strobe and Mask (DQ, DQS, DQS, DM, CK, CK)
Specification
Parameter
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Unit
Maximum peak amplitude allowed for overshoot area (See Figure 11)
0.4V
0.4V
0.4V
0.4V
V
Maximum peak amplitude allowed for undershoot area (See Figure 11)
0.4V
0.4V
0.4V
0.4V
V
Maximum overshoot area above VDDQ (See Figure 11)
0.25V-ns
0.19V-ns
0.15V-ns
0.13V-ns
V-ns
Maximum undershoot area below VSSQ (See Figure 11)
0.25V-ns
0.19V-ns
0.15V-ns
0.13V-ns
V-ns
Maximum Amplitude
Volts
(V)
Overshoot Area
VDDQ
VSSQ
Maximum Amplitude
Undershoot Area
Time (ns)
Figure 10. Clock, Data, Strobe and Mask Overshoot and Undershoot definition
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9.7 34 ohm Output Driver DC Electrical Characteristics
A functional representation of the output buffer is shown below. Output driver impedance RON is defined by the value of external reference resistor RZQ
as follows:
RON34 = RZQ/7 (Nominal 34ohms +/- 10% with nominal RZQ=240ohm)
RON40 = RZQ/6 (Nominal 40ohms +/- 10% with nominal RZQ=240ohm)
The individual Pull-up and Pull-down resistors (RONpu and RONpd) are defined as follows
VDDQ-VOUT
RONpu =
under the condition that RONpd is turned off
l Iout l
VOUT
RONpd =
under the condition that RONpu is turned off
l Iout l
Output Driver : Definition of Voltages and Currents
Output Driver
VDDQ
Ipu
To
other
circuity
RON
Pu
DQ
Iout
RON
Pd
Vout
Ipd
VSSQ
Figure 11. Output Driver : Definition of Voltages and Currents
[ Table 22 ] Output Driver DC Electrical Characteristics, assuming RZQ=240 ohms ;
entire operating temperature range; after proper ZQ calibration
RONnom
Resistor
RON34pd
34Ohms
RON34pu
RON40pd
40Ohms
RON40pu
Mismatch between Pull-up and Pull-down,
MMpupd
Vout
Min
Nom
Max
Units
VOLdc = 0.2 x VDDQ
0.6
1.0
1.1
1,2,3
VOMdc = 0.5 x VDDQ
0.9
1.0
1.1
1,2,3
VOHdc = 0.8 x VDDQ
0.9
1.0
1.4
VOLdc = 0.2 x VDDQ
0.9
1.0
1.4
VOMdc = 0.5 x VDDQ
0.9
1.0
1.1
1,2,3
VOHdc = 0.8 x VDDQ
0.6
1.0
1.1
1,2,3
VOLdc = 0.2 x VDDQ
0.6
1.0
1.1
1,2,3
VOMdc = 0.5 x VDDQ
0.9
1.0
1.1
1,2,3
VOHdc = 0.8 x VDDQ
0.9
1.0
1.4
RZQ/7
RZQ/6
Notes
1,2,3
1,2,3
1,2,3
VOLdc = 0.2 x VDDQ
0.9
1.0
1.4
VOMdc = 0.5 x VDDQ
0.9
1.0
1.1
1,2,3
VOHdc = 0.8 x VDDQ
0.6
1.0
1.1
1,2,3
VOMdc = 0.5 x VDDQ
-10
10
%
1,2,3
1,2,4
Note :
1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity
2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS
3. Pull-down and pull-up output driver impedance are recommended to be calibrated at 0.5 X VDDQ. Other calibration schemes may be used to achieve the linearity spec shown
above, e.g. calibration at 0.2 X VDDQ and 0.8 X VDDQ
4. Measurement definition for mismatch between pull-up and pull-down, MMpupd: Measure RONpu and RONpd. both at 0.5 X VDDQ:
MMpupd =
RONpu - RONpd
RONnom
x 100
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9.7.1 Output Drive Temperature and Voltage sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to table 23 and 24.
∆T = T - T(@calibration); ∆V = VDDQ - VDDQ (@calibration); VDD = VDDQ
*dRONdT and dRONdV are not subject to production test but are verified by design and characterization
[ Table 23 ] Output Driver Sensitivity Definition
Min
Max
Units
RONPU@VOHDC
0.6 - dRONdTH * |∆T| - dRONdVH * |∆V|
1.1 + dRONdTH * |∆T| + dRONdVH * |∆V|
RZQ/7
RON@VOMDC
0.9 - dRONdTM * |∆T| - dRONdVM * |∆V|
1.1 + dRONdTM * |∆T| + dRONdVM * |∆V|
RZQ/7
RONPD@VOLDC
0.6 - dRONdTL * |∆T| - dRONdVL * |∆V|
1.1 + dRONdTL * |∆T| + dRONdVL * |∆V|
RZQ/7
[ Table 24 ] Output Driver Voltage and Temperature Sensitivity
Speed Bin
800/1066/1333
1600
Min
Max
Min
Max
Units
dRONdTM
0
1.5
0
1.5
%/°C
dRONdVM
0
0.15
0
0.13
%/mV
dRONdTL
0
1.5
0
1.5
%/°C
dRONdVL
0
0.15
0
0.13
%/mV
dRONdTH
0
1.5
0
1.5
%/°C
dRONdVH
0
0.15
0
0.13
%/mV
9.8 On-Die Termination (ODT) Levels and I-V Characteristics
On-Die Termination effective resistance RTT is defined by bits A9, A6 and A2 of MR1 register.
ODT is applied to the DQ,DM, DQS/DQS and TDQS,TDQS (x8 devices only) pins.
A functional representation of the on-die termination is shown below. The individual pull-up and pull-down resistors (RTTpu and RTTpd) are defined as
follows :
RTTpu =
RTTpd =
VDDQ-VOUT
under the condition that RTTpd is turned off
l Iout l
VOUT
under the condition that RTTpu is turned off
l Iout l
On-Die Termination : Definition of Voltages and Currents
Chip in Termination Mode
ODT
VDDQ
Ipu
To
other
circuitry
like
RCV,
...
RTT
Iout=Ipd-Ipu
Pu
DQ
RTT
Iout
Pd
Ipd
VOUT
VSSQ
Figure 12. On-Die Termination : Definition of Voltages and Currents
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9.8.1 ODT DC electrical characteristics
Table 26 provides and overview of the ODT DC electrical characteristics. They values for RTT60pd120, RTT60pu120, RTT120pd240, RTT120pu240, RTT40pd80,
RTT40pu80, RTT30pd60, RTT30pu60, RTT20pd40, RTT20pu40 are not specification requirements, but can be used as design guide lines:
[ Table 25 ] ODT DC Electrical characteristics, assuming RZQ=240 ohm +/- 1% entire operationg temperature range ;
after proper ZQ calibration.
MR1 (A9,A6,A2)
RTT
RESISTOR
RTT120pd240
(0,1,0)
120 ohm
RTT120pu240
RTT120
RTT60pd240
(0,0,1)
60 ohm
RTT60pu240
RTT60
RTT40pd240
(0,1,1)
40 ohm
RTT40pu240
RTT40
RTT60pd240
(1,0,1)
30 ohm
RTT60pu240
RTT60
RTT60pd240
Vout
Min
Nom
Max
Unit
Notes
VOL(DC) 0.2XVDDQ
0.6
1.0
1.1
RZQ
1,2,3,4
1,2,3,4
0.5XVDDQ
0.9
1.0
1.1
RZQ
VOH(DC) 0.8XVDDQ
0.9
1.0
1.4
RZQ
1,2,3,4
VOL(DC) 0.2XVDDQ
0.9
1.0
1.4
RZQ
1,2,3,4
0.5XVDDQ
0.9
1.0
1.1
RZQ
1,2,3,4
VOH(DC) 0.8XVDDQ
0.6
1.0
1.1
RZQ
1,2,3,4
VIL(AC) to VIH(AC)
0.9
1.0
1.6
RZQ/2
1,2,5
VOL(DC) 0.2XVDDQ
0.6
1.0
1.1
RZQ/2
1,2,3,4
1,2,3,4
0.5XVDDQ
0.9
1.0
1.1
RZQ/2
VOH(DC) 0.8XVDDQ
0.9
1.0
1.4
RZQ/2
1,2,3,4
VOL(DC) 0.2XVDDQ
0.9
1.0
1.4
RZQ/2
1,2,3,4
0.5XVDDQ
0.9
1.0
1.1
RZQ/2
1,2,3,4
VOH(DC) 0.8XVDDQ
0.6
1.0
1.1
RZQ/2
1,2,3,4
VIL(AC) to VIH(AC)
0.9
1.0
1.6
RZQ/4
1,2,5
VOL(DC) 0.2XVDDQ
0.6
1.0
1.1
RZQ/3
1,2,3,4
1.1
RZQ/3
1,2,3,4
1,2,3,4
0.5XVDDQ
20 ohm
RTT60pu240
RTT60
1.0
0.9
1.0
1.4
RZQ/3
VOL(DC) 0.2XVDDQ
0.9
1.0
1.4
RZQ/3
1,2,3,4
0.5XVDDQ
0.9
1.0
1.1
RZQ/3
1,2,3,4
VOH(DC) 0.8XVDDQ
0.6
1.0
1.1
RZQ/3
1,2,3,4
VIL(AC) to VIH(AC)
0.9
1.0
1.6
RZQ/6
1,2,5
VOL(DC) 0.2XVDDQ
0.6
1.0
1.1
RZQ/4
1,2,3,4
0.5XVDDQ
0.9
1.0
1.1
RZQ/4
1,2,3,4
1,2,3,4
VOH(DC) 0.8XVDDQ
0.9
1.0
1.4
RZQ/4
VOL(DC) 0.2XVDDQ
0.9
1.0
1.4
RZQ/4
1,2,3,4
0.5XVDDQ
0.9
1.0
1.1
RZQ/4
1,2,3,4
VOH(DC) 0.8XVDDQ
0.6
1.0
1.1
RZQ/4
1,2,3,4
VIL(AC) to VIH(AC)
0.9
1.0
1.6
RZQ/8
1,2,5
VOL(DC) 0.2XVDDQ
0.6
1.0
1.1
RZQ/6
1,2,3,4
0.5XVDDQ
0.9
1.0
1.1
RZQ/6
1,2,3,4
1.4
RZQ/6
1,2,3,4
1,2,3,4
VOH(DC) 0.8XVDDQ
(1,0,0)
0.9
VOH(DC) 0.8XVDDQ
0.9
1.0
VOL(DC) 0.2XVDDQ
0.9
1.0
1.4
RZQ/6
0.5XVDDQ
0.9
1.0
1.1
RZQ/6
1,2,3,4
VOH(DC) 0.8XVDDQ
0.6
1.0
1.1
RZQ/6
1,2,3,4
VIL(AC) to VIH(AC)
0.9
1.0
1.6
RZQ/12
1,2,5
5
%
1,2,5,6
Deviation of VM w.r.t VDDQ/2, ∆VM
-5
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Note :
1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage
changes after calibration, see following section on voltage and temperature sensitivity
2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS
3. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5XVDDQ. Other calibration schemes may be used to achieve the linearity
spec shown above, e.g. calibration at 0.2XVDDQ and 0.8XVDDQ.
4. Not a specification requirement, but a design guide line
5. Measurement definition for RTT:
Apply VIH(AC) to pin under test and measure current I(VIH(AC)), then apply VIL(AC) to pin under test and measure current I(VIL(AC)) perspectively
RTT
=
VIH(AC) - VIL(AC)
I(VIH(AC)) - I(VIL(AC))
6. Measurement definition for VM and ∆VM : Measure voltage (VM) at test pin (midpoint) with no load
∆ VM =
2 x VM
VDDQ
-1
x 100
9.8.2 ODT Temperature and Voltage sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to table below
∆T = T - T(@calibration); ∆V = VDDQ - VDDQ (@calibration); VDD = VDDQ
[ Table 26 ] ODT Sensitivity Definition
Min
Max
Units
0.9 - dRTTdT * |∆T| - dRTTdV * |∆V|
1.6 + dRTTdT * |∆T| + dRTTdV * |∆V|
RZQ/2,4,6,8,12
Min
Max
Units
dRTTdT
0
1.5
%/°C
dRTTdV
0
0.15
%/mV
RTT
[ Table 27 ] ODT Voltage and Temperature Sensitivity
These parameters may not be subject to production test. They are verified by design and characterization.
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9.9 ODT Timing Definitions
9.9.1 Test Load for ODT Timings
Different than for timing measurements, the reference load for ODT timings is defined in Figgure 13.
VDDQ
DUT DQ, DM
CK,CK
VTT=
VSSQ
RTT
=25 ohm
DQS , DQS
TDQS , TDQS
VSSQ
Timing Reference Points
Figure 13. ODT Timing Reference Load
9.9.2 ODT Timing Definition
Definitions for tAON, tAONPD, tAOF, tAOFPD and tADC are provided in Table 28 and subsequent figures. Measurement reference settings are provided
in Table 29.
[ Table 28 ] ODT Timing Definitions
Symbol
Begin Point Definition
End Point Definition
Figute
tAON
Rising edge of CK - CK defined by the end point of ODTLon
Extrapolated point at VSSQ
Figure 14
tAONPD
Rising edge of CK - CK with ODT being first registered high
Extrapolated point at VSSQ
Figure 15
tAOF
Rising edge of CK - CK defined by the end point of ODTLoff
End point: Extrapolated point at VRTT_Nom
Figure 16
tAOFPD
Rising edge of CK - CK with ODT being first registered low
End point: Extrapolated point at VRTT_Nom
Figure 17
tADC
Rising edge of CK - CK defined by the end point of ODTLcnw,
ODTLcwn4 of ODTLcwn8
End point: Extrapolated point at VRTT_Wr and VRTT_Nom
respectively
Figure 18
[ Table 29 ] Reference Settings for ODT Timing Measurements
Measured
Parameter
tAON
tAONPD
tAOF
tAOFPD
tADC
RTT_Nom Setting
RTT_Wr Setting
VSW1[V]
VSW2[V]
RZQ/4
NA
0.05
0.10
RZQ/12
NA
0.10
0.20
RZQ/4
NA
0.05
0.10
RZQ/12
NA
0.10
0.20
RZQ/4
NA
0.05
0.10
RZQ/12
NA
0.10
0.20
RZQ/4
NA
0.05
0.10
RZQ/12
NA
0.10
0.20
RZQ/12
RZQ/2
0.20
0.30
Page 25 of 59
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Begin point : Rising edge of CK - CK
defined by the end point of ODTLon
CK
VTT
CK
tAON
TSW2
DQ, DM
DQS , DQS
TDQS , TDQS
TSW1
VSW2
VSW1
VSSQ
VSSQ
End point Extrapolated point at VSSQ
Figure 14. Definition of tAON
Begin point : Rising edge of CK - CK
with ODT being first registered high
CK
VTT
CK
tAONPD
TSW2
DQ, DM
DQS , DQS
TDQS , TDQS
TSW1
VSW2
VSW1
VSSQ
VSSQ
End point Extrapolated point at VSSQ
Figure 15. Definition of tAONPD
Begin point : Rising edge of CK - CK
defined by the end point of ODTLoff
CK
VTT
CK
tAOF
End point Extrapolated point at VRTT_Nom
VRTT_Nom
DQ, DM
DQS , DQS
TDQS , TDQS
TSW2
TSW1
VSW2
VSW1
VSSQ
TD_TAON_DEF
Figure 16. Definition of tAOF
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Begin point : Rising edge of CK - CK
with ODT being first registered low
CK
VTT
CK
tAOFPD
End point Extrapolated point at VRTT_Nom
VRTT_Nom
DQ, DM
DQS , DQS
TDQS , TDQS
TSW2
TSW1
VSW2
VSW1
VSSQ
Figure 17. Definition of tAOFPD
Begin point : Rising edge of CK - CK
defined by the end point of ODTLcnw
Begin point : Rising edge of CK - CK defined by
the end point of ODTLcwn4 or ODTLcwn8
CK
VTT
CK
tADC
VRTT_Nom
DQ, DM
DQS , DQS
TDQS , TDQS
tADC
End point Extrapolated point at VRTT_Nom
TSW21
End point
Extrapolated point
TSW11
at VRTT_Nom
TSW22
VSW2
VRTT_Nom
TSW12
VSW1
VRTT_Wr
End point Extrapolated point at VRTT_Wr
VSSQ
Figure 18. Definition of tADC
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10.0 IDD Specification Parameters and Test Conditions
10.1 IDD Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 19 shows the setup and test load for IDD and
IDDQ measurements.
- IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and
IDD7) are measured as time-averaged currents with all VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in
IDD currents.
- IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied
together. Any IDD current is not included in IDDQ currents.
Attention : IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO
power to actual IO power as outlined in Figure 20. In DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ
are using one merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply :
- "0" and "LOW" is defined as VIN <= VILAC(max).
- "1" and "HIGH" is defined as VIN >= VIHAC(min).
- "FLOATING" is defined as inputs are VREF = VDD / 2.
- Timings used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 30.
- Basic IDD and IDDQ Measurement Conditions are described in Table 31.
- Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 32 on page 33 through Table 39.
- IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0B (Output Buffer enabled in MR1);
RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
- Attention : The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started.
- Define D = {CS, RAS, CAS, WE} := {HIGH, LOW, LOW, LOW}
- Define D = {CS, RAS, CAS, WE} := {HIGH, HIGH, HIGH, HIGH}
Timing parameters are listed in the following table:
[ Table 30 ] Timing used for IDD and IDDQ Measured-Loop Patterns.
Parameter
Bin
DDR3-800
5-5-5
tCKmin(IDD)
DDR3-1066
6-6-6
6-6-6
6
6
2.5
CL(IDD)
5
7-7-7
DDR3-1333
8-8-8
7-7-7
8-8-8
8
7
8
1.875
7
9-9-9
DDR3-1600
10-10-10
8-8-8
9-9-9
10
8
9
1.5
10-10-10
11-11-11
1.25
9
10
Unit
ns
11
nCK
tRCDmin(IDD)
5
6
6
7
8
7
8
9
10
8
9
10
11
nCK
tRCmin(IDD)
20
21
26
27
28
31
32
33
34
36
37
38
39
nCK
6
6
8
7
8
9
10
8
9
10
11
tRASmin(IDD)
15
tRPmin(IDD)
tFAW(IDD)
5
20
7
24
28
nCK
nCK
x4/x8
16
20
20
24
nCK
x16
20
27
30
32
nCK
x4/x8
4
4
4
5
nCK
x16
4
6
5
6
nCK
tRFC(IDD) - 512Mb
36
48
60
72
nCK
tRFC(IDD) - 1Gb
44
59
74
88
nCK
tRRD(IDD)
tRFC(IDD) - 2Gb
64
86
107
128
nCK
tRFC(IDD) - 4Gb
120
160
200
240
nCK
tRFC(IDD) - 8Gb
140
187
234
280
nCK
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[ Table 31 ] Basic IDD and IDDQ Measurement Conditions
Symbol
Description
Operating One Bank Active-Precharge Current
IDD0
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 30 ; BL: 8a); AL: 0; CS: High between ACT and PRE; Command, Address, Bank Address
Inputs: partially toggling according to Table 32 ; Data IO: MID-LEVEL; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,...
(see Table32); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 32
Operating One Bank Active-Read-Precharge Current
IDD1
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 30 ; BL: 8a); AL: 0; CS: High between ACT, RD and PRE; Command, Address,
Bank Address Inputs, Data IO: partially toggling according to Table 33 ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,...
(see Table33); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 33
Precharge Standby Current
IDD2N
CKE: High; External clock: On; tCK, CL: see Table 30 ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling
according to Table 34 ; Data IO: MID-LEVEL; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT
Signal: stable at 0; Pattern Details: see Table 34
Precharge Standby ODT Current
DD2NT
DDQ2NT
(optional)
CKE: High; External clock: On; tCK, CL: see Table 30 ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling
according to Table 35 ; Data IO: MID-LEVEL;DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT
Signal: toggling according to Table 35 ; Pattern Details: see Table 35
Precharge Standby ODT IDDQ Current
Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current
Precharge Power-Down Current Slow Exit
IDD2P0
CKE: Low; External clock: On; tCK, CL: see Table 30 ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO:
MID-LEVEL; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pecharge
Power Down Mode: Slow Exic)
Precharge Power-Down Current Fast Exit
IDD2P1
CKE: Low; External clock: On; tCK, CL: see Table 30 ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO:
MID-LEVEL; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pecharge
Power Down Mode: Fast Exitc)
Precharge Quiet Standby Current
IDD2Q
CKE: High; External clock: On; tCK, CL: see Table 30 ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO:
MID-LEVEL; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
Active Standby Current
IDD3N
CKE: High; External clock: On; tCK, CL: see Table 30 ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling
according to Table 34 ; Data IO: MID-LEVEL; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 34
Active Power-Down Current
IDD3P
CKE: Low; External clock: On; tCK, CL: see Table 30 ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO:
MID-LEVEL;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
Operating Burst Read Current
IDD4R
CKE: High; External clock: On; tCK, CL: see Table 30 ; BL: 8a); AL: 0; CS: High between RD; Command, Address, Bank Address Inputs: partially toggling
according to Table 36 ; Data IO: seamless read data burst with different data between one burst and the next one according to Table 36 ; DM:stable at 0; Bank
Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... (see Table 7 on page 10); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 36
IDDQ4R
(optional)
Operating Burst Read IDDQ Current
Same definition like for IDD4R, however measuring IDDQ current instead of IDD current
Operating Burst Write Current
IDD4W
CKE: High; External clock: On; tCK, CL: see Table 30 ; BL: 8a); AL: 0; CS: High between WR; Command, Address, Bank Address Inputs: partially toggling according to Table 37 ; Data IO: seamless write data burst with different data between one burst and the next one according to Table 37; DM: stable at 0;
Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... (see Table 37); Output Buffer and RTT: Enabled in Mode Registersb);
ODT Signal: stable at HIGH; Pattern Details: see Table 37
Burst Refresh Current
IDD5B
CKE: High; External clock: On; tCK, CL, nRFC: see Table 30 ; BL: 8a); AL: 0; CS: High between REF; Command, Address, Bank Address Inputs: partially
toggling according to Table 38 ; Data IO: MID-LEVEL;DM:stable at 0; Bank Activity: REF command every nRFC (see Table 38); Output Buffer and RTT:
Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 38
Self Refresh Current: Normal Temperature Range
IDD6
TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabledd); Self-Refresh Temperature Range (SRT): Normale); CKE: Low; External clock: Off; CK and CK:
LOW; CL: see Table 30 ; BL: 8a); AL: 0; CS, Command, Address, Bank Address, Data IO: MID-LEVEL;DM:stable at 0; Bank Activity: Self-Refresh operation;
Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID-LEVEL
Page 29 of 59
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[ Table 31 ] Basic IDD and IDDQ Measurement Conditions
Symbol
Description
Self-Refresh Current: Extended Temperature Range (optional)f)
IDD6ET
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabledd); Self-Refresh Temperature Range (SRT): Extendede); CKE: Low; External clock: Off; CK and CK:
LOW; CL: see Table 30 ; BL: 8a); AL: 0; CS, Command, Address, Bank Address, Data IO: MID-LEVEL;DM:stable at 0; Bank Activity: Extended Temperature
Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID-LEVEL
Auto Self-Refresh Current (optional)f)
IDD6TC
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Enabledd); Self-Refresh Temperature Range (SRT): Normale); CKE: Low; External clock: Off; CK and CK:
LOW; CL: see Table 30 ; BL: 8a); AL: 0; CS, Command, Address, Bank Address, Data IO: MID-LEVEL; DM:stable at 0; Bank Activity: Auto
Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID-LEVEL
Operating Bank Interleave Read Current
IDD7
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 30 ; BL: 8a, g); AL: CL-1; CS: High between ACT and RDA; Command,
Address, Bank Address Inputs: partially toggling according to Table 39 ; Data IO: read data bursts with different data between one burst and the next one
according to Table 39 ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see Table 39 ; Output
Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 39
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B
c) Pecharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
e) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range
f) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device
10.2 IDD Specifications definition
Editorial Instruction: Chapter 10.2 in JESD79-3B in principal stays at it is. See Reference Material at the end of this ballot.
Only the following changes will be done to Chapter 10.2:
Table 53 "IDD Specification Example 512M DDR3", add the following Rows:
- Between IDD2N and IDD2Q: Add 2 rows (one for x4/x8, one for x16) with a straddled cell for Symbol "IDD2NT".
- Between IDD2NT (as inserted with above bullet) and IDD2Q: Add 2 rows (one for x4/x8, one for x16) with a straddled cell for Symbol ’IDDQ2NT".
- Between IDD4R and IDD4W: Add 3 rows (one for x4, one for x8 and one for x16) with a straddled cell for Symbol "IDDQ4R".
Page 30 of 59
Rev. 1.0 March 2009
K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
IDD
IDDQ
VDD
(optional)
VDDQ
RESET
CK/CK
CKE
DQS, DQS
CS
RTT = 25 Ohm
VDDQ/2
DQ, DM,
RAS, CAS, WE
TDQS, TDQS
A, BA
ODT
ZQ
VSS
VSSQ
[Note: DIMM level Output test load condition may be different from above ]
Figure 19 : Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements
Application specific
memory channel
environment
Channel
IO Power
Simulation
IDDQ
Test Load
IDDQ
Simulation
IDDQ
Measurement
Correlation
Correction
Channel IO Power
Number
Figure 20 :Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement.
Page 31 of 59
Rev. 1.0 March 2009
K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data2)
0
Cycle
Number
Sub-Loop
CKE
CK/CK
[ Table 32 ] IDD0 Measurement - Loop Pattern1
0
ACT
0
0
1
1
0
0
00
0
0
0
0
-
1,2
D, D
1
0
0
0
0
0
00
0
0
0
0
-
D, D
1
1
1
1
0
0
00
0
0
0
0
-
00
0
0
0
0
-
3,4
...
nRAS
Static High
toggling
...
repeat pattern 1...4 until nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC + 0
ACT
0
0
1
1
0
0
00
0
0
F
0
-
1*nRC + 1, 2
D, D
1
0
0
0
0
0
00
0
0
F
0
-
D, D
1
1
1
1
0
0
00
0
0
F
0
-
0
0
F
0
1*nRC + 3, 4
...
1*nRC + nRAS
...
repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
00
repeat 1...4 until 2*nRC - 1, truncate if necessary
1
2*nRC
repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
4*nRC
repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
6*nRC
repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
8*nRC
repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
10*nRC
repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
12*nRC
repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
14*nRC
repeat Sub-Loop 0, use BA[2:0] = 7 instead
Note :
1. DM must be driben LOW all the time. DQS, DQS are MID-LEVEL.
2. DQ signals are MID-LEVEL.
Page 32 of 59
Rev. 1.0 March 2009
K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data2)
0
Cycle
Number
Sub-Loop
CKE
CK/CK
[ Table 33 ] IDD1 Measurement - Loop Pattern1
0
ACT
0
0
1
1
0
0
00
0
0
0
0
-
1,2
D, D
1
0
0
0
0
0
00
0
0
0
0
-
D, D
1
1
1
1
0
0
00
0
0
0
0
-
00
0
0
0
0
00000000
00
0
0
0
0
-
3,4
...
nRCD
...
nRAS
Static High
toggling
...
repeat pattern 1...4 until nRCD- 1, truncate if necessary
RD
0
1
0
1
0
0
repeat pattern 1...4 until nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0
ACT
0
0
1
1
0
0
00
0
0
F
0
-
1*nRC + 1, 2
D, D
1
0
0
0
0
0
00
0
0
F
0
-
D, D
1
1
1
1
0
0
00
0
0
F
0
-
F
0
00110011
F
0
-
1*nRC + 3, 4
...
1*nRC + nRCD
...
1*nRC + nRAS
...
repeat pattern nRC + 1,..., 4 until nRC + nRCD - 1, truncate if necessary
RD
0
1
0
1
0
0
00
0
0
repeat pattern nRC + 1,..., 4 until nRC +nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
00
0
0
repeat pattern nRC + 1,..., 4 until 2 * nRC - 1, truncate if necessary
1
2*nRC
repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
4*nRC
repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
6*nRC
repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
8*nRC
repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
10*nRC
repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
12*nRC
repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
14*nRC
repeat Sub-Loop 0, use BA[2:0] = 7 instead
Note :
1. DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
1
0
0
0
0
0
00
0
1
D
1
0
0
0
0
0
00
0
2
D
1
1
1
1
0
0
00
0
D
1
1
1
1
0
0
00
0
0
Static High
toggling
3
1
4-7
Data2)
CS
D
A[2:0]
Command
0
A[6:3]
Cycle
Number
0
A[9:7]
Sub-Loop
CKE
CK/CK
[ Table 34 ] IDD2 and IDD3N Measurement - Loop Pattern1
0
0
0
-
0
0
0
-
0
F
0
-
F
0
-
repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
8-11
repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
12-15
repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
16-19
repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
20-23
repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
24-27
repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
28-31
repeat Sub-Loop 0, use BA[2:0] = 7 instead
Note :
1. DM must be driven Low all the time. DQS, DQS are MID-LEVEL.
2. DQ signals are MID-LEVEL.
Page 33 of 59
Rev. 1.0 March 2009
K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data2)
CKE
Static High
toggling
CK/CK
[ Table 35 ] IDD2NT and IDDQ2NT Measurement - Loop Pattern1
0
0
D
1
0
0
0
0
0
00
0
0
0
0
-
1
D
1
0
0
0
0
0
00
0
0
0
0
2
D
1
1
1
1
0
0
00
0
0
F
0
3
D
1
1
1
1
0
0
00
0
0
F
0
1
4-7
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1
2
8-11
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 2
3
12-15
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 3
4
16-19
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4
5
20-23
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5
6
24-27
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 6
7
28-31
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 7
Note :
1. DM must be driven Low all the time. DQS, DQS are MID-LEVEL.
2. DQ signals are MID-LEVEL.
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data2)
CKE
Static High
toggling
CK/CK
[ Table 36 ] IDD4R and IDDQ4R Measurement - Loop Pattern1
0
0
RD
0
1
0
1
0
0
00
0
0
0
0
00000000
1
D
1
0
0
0
0
0
00
0
0
0
0
-
2,3
D,D
1
1
1
1
0
0
00
0
0
0
0
-
4
RD
0
1
0
1
0
0
00
0
0
F
0
00110011
5
D
1
0
0
0
0
0
00
0
0
F
0
-
6,7
D,D
1
1
1
1
0
0
00
0
0
F
0
-
1
8-15
repeat Sub-Loop 0, but BA[2:0] = 1
2
16-23
repeat Sub-Loop 0, but BA[2:0] = 2
3
24-31
repeat Sub-Loop 0, but BA[2:0] = 3
4
32-39
repeat Sub-Loop 0, but BA[2:0] = 4
5
40-47
repeat Sub-Loop 0, but BA[2:0] = 5
6
48-55
repeat Sub-Loop 0, but BA[2:0] = 6
7
56-63
repeat Sub-Loop 0, but BA[2:0] = 7
Note :
1. DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
2. Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
Page 34 of 59
Rev. 1.0 March 2009
K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data2)
CKE
Static High
toggling
CK/CK
[ Table 37 ] IDD4W Measurement - Loop Pattern1
0
0
WR
0
1
0
0
1
0
00
0
0
0
0
00000000
1
D
1
0
0
0
1
0
00
0
0
0
0
-
2,3
D,D
1
1
1
1
1
0
00
0
0
0
0
-
4
WR
0
1
0
0
1
0
00
0
0
F
0
00110011
5
D
1
0
0
0
1
0
00
0
0
F
0
-
6,7
D,D
1
1
1
1
1
0
00
0
0
F
0
-
1
8-15
repeat Sub-Loop 0, but BA[2:0] = 1
2
16-23
repeat Sub-Loop 0, but BA[2:0] = 2
3
24-31
repeat Sub-Loop 0, but BA[2:0] = 3
4
32-39
repeat Sub-Loop 0, but BA[2:0] = 4
5
40-47
repeat Sub-Loop 0, but BA[2:0] = 5
6
48-55
repeat Sub-Loop 0, but BA[2:0] = 6
7
56-63
repeat Sub-Loop 0, but BA[2:0] = 7
Note :
1. DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
2. Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data2)
0
0
1
0
0
00
0
0
0
0
-
1
0
0
0
0
0
00
0
0
0
0
-
D,D
1
1
1
1
0
0
00
0
0
F
0
-
3,4
Static High
toggling
5...8
2
repeat cycles 1...4, but BA[2:0] = 1
9...12
repeat cycles 1...4, but BA[2:0] = 2
13...16
repeat cycles 1...4, but BA[2:0] = 3
17...20
repeat cycles 1...4, but BA[2:0] = 4
21...24
repeat cycles 1...4, but BA[2:0] = 5
25...28
repeat cycles 1...4, but BA[2:0] = 6
29...32
repeat cycles 1...4, but BA[2:0] = 7
33...nRFC - 1
WE
0
D
CAS
REF
1,2
RAS
Command
0
1
CS
Cycle
Number
0
Sub-Loop
CKE
CK/CK
[ Table 38 ] IDD5B Measurement - Loop Pattern1
repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
Note :
1. DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
2. DQ signals are MID-LEVEL.
Page 35 of 59
Rev. 1.0 March 2009
K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
0
0
00
0
0
0
0
-
1
0
0
00
1
0
0
0
00000000
D
1
0
0
0
0
0
00
0
0
0
0
-
2
Static High
toggling
repeat above D Command until nRRD - 1
nRRD
ACT
0
0
1
1
0
1
00
0
0
F
0
-
nRRD + 1
RDA
0
1
0
1
0
1
00
1
0
F
0
00110011
D
1
0
0
0
0
1
00
0
0
F
0
-
0
3
00
0
0
F
0
-
0
F
0
-
nRRD + 2
...
repeat above D Command until 2*nRRD-1
2
2 * nRRD
repeat Sub-Loop 0, but BA[2:0] = 2
3
3 * nRRD
repeat Sub-Loop 1, but BA[2:0] = 3
4
4 * nRRD
D
1
0
0
5
nFAW
repeat Sub-Loop 0, but BA[2:0] = 4
nFAW+nRRD
repeat Sub-Loop 1, but BA[2:0] = 5
7
nFAW+2*nRRD
repeat Sub-Loop 0, but BA[2:0] = 6
8
nFAW+3*nRRD
repeat Sub-Loop 1, but BA[2:0] = 7
9
nFAW+4*nRRD
D
1
0
0
0
0
7
00
0
Assert and repeat above D Command until 2*nFAW - 1, if necessary
2*nFAW+0
ACT
0
0
1
1
0
0
00
0
0
F
0
-
2*nFAW+1
RDA
0
1
0
1
0
0
00
1
0
F
0
00110011
D
1
0
0
0
0
0
00
0
0
F
0
-
2*nFAW+2
11
0
Assert and repeat above D Command until nFAW - 1, if necessary
6
10
Data2)
BA[2:0]
1
0
WE
1
1
CAS
0
0
RAS
0
RDA
CS
ACT
1
...
1
Command
ODT
0
0
Cycle
Number
Sub-Loop
CKE
CK/CK
[ Table 39 ] IDD7 Measurement - Loop Pattern1
Repeat above D Command until 2*nFAW + nRRD - 1
2*nFAW+nRRD
ACT
0
0
1
1
0
1
00
0
0
0
0
-
2*nFAW+nRRD+1
RDA
0
1
0
1
0
1
00
1
0
0
0
00000000
D
1
0
0
0
0
1
00
0
0
0
0
-
0
0
0
0
-
0
0
-
2*nFAW+nRRD+2
Repeat above D Command until 2*nFAW + 2*nRRD - 1
12
2*nFAW+2*nRRD
repeat Sub-Loop 10, but BA[2:0] = 2
13
2*nFAW+3*nRRD
repeat Sub-Loop 11, but BA[2:0] = 3
14
2*nFAW+4*nRRD
D
1
0
0
0
0
3
00
Assert and repeat above D Command until 3*nFAW - 1, if necessary
15
3*nFAW
repeat Sub-Loop 10, but BA[2:0] = 4
16
3*nFAW+nRRD
repeat Sub-Loop 11, but BA[2:0] = 5
17
3*nFAW+2*nRRD
repeat Sub-Loop 10, but BA[2:0] = 6
18
3*nFAW+3*nRRD
repeat Sub-Loop 11, but BA[2:0] = 7
19
3*nFAW+4*nRRD
D
1
0
0
0
0
7
00
0
0
Assert and repeat above D Command until 4*nFAW - 1, if necessary
Note :
1. DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otheerwise MID-LEVEL.
2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation. DQ signals are MID-LEVEL.
Page 36 of 59
Rev. 1.0 March 2009
K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
11.0 DDP 4Gb DDR3 SDRAM B-die IDD Spec Table
[ Table 40 ] IDD Specification for DDP 4Gb DDR3 B-die
1Gx4 (K4B4G0446B)
Symbol
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
6-6-6
7-7-7
9-9-9
TBD
Unit
IDD0
100
110
115
TBD
IDD1
115
125
130
TBD
mA
IDD2P0(slow exit)
24
24
24
TBD
mA
Notes
mA
IDD2P1(fast exit)
50
50
50
TBD
mA
IDD2N
70
80
80
TBD
mA
mA
IDD2NT
70
80
90
TBD
IDD2Q
60
70
70
TBD
mA
IDD3P(fast exit)
60
70
70
TBD
mA
IDD3N
85
95
100
TBD
mA
IDD4R
135
160
175
TBD
mA
IDD4W
140
165
180
TBD
mA
IDD5B
220
225
225
TBD
mA
IDD6
24
24
24
TBD
mA
IDD7
235
250
300
TBD
mA
Symbol
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Unit
6-6-6
7-7-7
9-9-9
TBD
512Mx8 (K4B4G0846B)
IDD0
100
110
115
TBD
IDD1
115
125
130
TBD
mA
IDD2P0(slow exit)
24
24
24
TBD
mA
IDD2P1(fast exit)
50
60
70
TBD
mA
mA
IDD2N
70
80
80
TBD
mA
IDD2NT
80
80
90
TBD
mA
IDD2Q
64
70
80
TBD
mA
IDD3P(fast exit)
60
70
70
TBD
mA
IDD3N
85
95
100
TBD
mA
IDD4R
140
165
185
TBD
mA
IDD4W
145
170
190
TBD
mA
IDD5B
220
225
225
TBD
mA
IDD6
24
24
24
TBD
mA
IDD7
245
270
320
TBD
mA
Page 37 of 59
Notes
Rev. 1.0 March 2009
K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
12.0 Input/Output Capacitance
[ Table 41 ] Input/Output Capacitance
Parameter
Symbol
Input/output capacitance
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input capacitance
(CK and CK)
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Units
Notes
TBD
pF
1,2,3
TBD
TBD
pF
2,3
TBD
TBD
TBD
pF
2,3,4
TBD
TBD
TBD
TBD
pF
2,3,6
TBD
TBD
TBD
TBD
TBD
pF
2,3,5
TBD
TBD
TBD
TBD
TBD
TBD
pF
2,3,7,8
TBD
TBD
TBD
TBD
TBD
TBD
TBD
pF
2,3,9,10
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
pF
2,3,11
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
pF
2, 3, 12
Min
Max
Min
Max
Min
Max
Min
Max
CIO
TBD
TBD
TBD
TBD
TBD
TBD
TBD
CCK
TBD
TBD
TBD
TBD
TBD
TBD
CDCK
TBD
TBD
TBD
TBD
TBD
CI
TBD
TBD
TBD
TBD
CDDQS
TBD
TBD
TBD
CDI_CTRL
TBD
TBD
CDI_ADD_CMD
TBD
Input/output capacitance delta
(DQ, DM, DQS, DQS, TDQS, TDQS)
CDIO
Input/output capacitance of ZQ pin
CZQ
Input capacitance delta
(CK and CK)
Input capacitance
(All other input-only pins)
Input capacitance delta
(DQS and DQS)
Input capacitance delta
(All control input-only pins)
Input capacitance delta
(all ADD and CMD input-onlypins)
Note :
1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS
2. This parameter is not subject to production test. It is verified by design and characterization.
The capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK
ANALYZER( VNA)") with VDD, VDDQ, VSS, VSSQ applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary).
VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off.
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
4. Absolute value of CCK-CCK
5. Absolute value of CIO(DQS)-CIO(DQS)
6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE.
7. CDI_CTRL applies to ODT, CS and CKE
8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK))
9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))
11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS))
12. Maximum external load capacitance on ZQ pin: 5pF
Page 38 of 59
Rev. 1.0 March 2009
K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
13.0 Electrical Characteristics and AC timing for DDR3-800 to DDR3-1600
13.1 Clock specification
The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may result in malfunction of the DDR3
SDRAM device.
13.1.1 Definition for tCK (avg)
tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is calculated from rising edge to
rising edge.
N
∑
tCKj
N
N=200
j=1
13.1.2 Definition for tCK (abs)
tCK(abs) is the absolute clock period, as measured from one rising edge to the next consecutive rising edge. tCK(abs) is not subject to production test.
13.1.3 Definition for tCH(avg) and tCL(avg)
tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses:
tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses:
N
∑ tCHj
N
N x tCK(avg)
N=200
j=1
∑
tCLj
N x tCK(avg)
N=200
j=1
13.1.4 Definition for note for tJIT(per), tJIT(per,Ick)
tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg). tJIT(per) = min/max of {tCKi-tCK(avg) where i=1 to 200}
tJIT(per) defines the single period jitter when the DLL is already locked.
tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.
tJIT(per) and tJIT(per,lck) are not subject to production test.
13.1.5 Definition for note for tJIT(cc), tJIT(cc,Ick)
tJIT(cc) is defined as the absolute difference in clock period between two consecutive clock cycles: tJIT(cc) = Max of {tCKi+1-tCKi}
tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked.
tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.
tJIT(cc) and tJIT(cc,lck) are not subject to production test.
13.1.6 Definition for tERR(nper)
tERR is defined as the cumulative error across n multiple consecutive cycles from tCK(avg). tERR is not subject to production test.
Page 39 of 59
Rev. 1.0 March 2009
K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
13.2 Refresh Parameters by Device Density
[ Table 42 ] Refresh parameters by device density
Parameter
Symbol
1Gb
2Gb
4Gb
8Gb
Units
tRFC
All Bank Refresh to active/refresh cmd time
Average periodic refresh interval
tREFI
110
160
300
350
ns
0 °C ≤ TCASE ≤ 85°C
7.8
7.8
7.8
7.8
µs
85 °C < TCASE ≤ 95°C
3.9
3.9
3.9
3.9
µs
Note
1
Note :
1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or
requirements referred to in this material.
13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin
DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
[ Table 43 ] DDR3-800 Speed Bins
Speed
DDR3-800
CL-nRCD-nRP
Parameter
Intermal read command to first data
ACT to internal read or write delay time
6-6-6
Units
Symbol
min
max
tAA
15
20
ns
tRCD
15
-
ns
Note
PRE command period
tRP
15
-
ns
ACT to ACT or REF command period
tRC
52.5
-
ns
tRAS
37.5
9*tREFI
ns
8
tCK(AVG)
2.5
3.3
ns
1,2,3
ACT to PRE command period
CL = 6 / CWL = 5
Supported CL Settings
6
nCK
Supported CWL Settings
5
nCK
[ Table 44 ] DDR3-1066 Speed Bins
Speed
DDR3-1066
CL-nRCD-nRP
Parameter
Intermal read command to first data
7-7-7
Units
Symbol
min
max
tAA
13.125
20
ns
tRCD
13.125
-
ns
PRE command period
tRP
13.125
-
ns
ACT to ACT or REF command period
tRC
50.625
-
ns
ACT to internal read or write delay time
ACT to PRE command period
CL = 6
CL = 7
CL = 8
Note
tRAS
37.5
9*tREFI
ns
8
CWL = 5
tCK(AVG)
2.5
3.3
ns
1,2,3,6
CWL = 6
tCK(AVG)
Reserved
ns
1,2,3,4
CWL = 5
tCK(AVG)
Reserved
ns
4
CWL = 6
tCK(AVG)
ns
1,2,3,4
CWL = 5
tCK(AVG)
ns
4
CWL = 6
tCK(AVG)
ns
1,2,3
1.875
<2.5
Reserved
1.875
Supported CL Settings
Supported CWL Settings
Page 40 of 59
<2.5
6,7,8
nCK
5,6
nCK
Rev. 1.0 March 2009
K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
[ Table 45 ] DDR3-1333 Speed Bins
Speed
DDR3-1333
CL-nRCD-nRP
Parameter
9 -9 - 9
Units
Symbol
min
max
tAA
13.5
(13.125)5,9
20
ns
tRCD
13.5
(13.125)5,9
-
ns
PRE command period
tRP
13.5
(13.125)5,9
-
ns
ACT to ACT or REF command period
tRC
49.5
(49.125)5,9
-
ns
Intermal read command to first data
ACT to internal read or write delay time
ACT to PRE command period
CL = 6
CL = 7
CL = 8
CL = 9
CL = 10
Note
tRAS
36
9*tREFI
ns
8
CWL = 5
tCK(AVG)
2.5
3.3
ns
1,2,3,7
CWL = 6
tCK(AVG)
Reserved
ns
1,2,3,4,7
CWL = 7
tCK(AVG)
Reserved
ns
4
CWL = 5
tCK(AVG)
ns
4
ns
1,2,3,4,7
ns
1,2,3,4,
CWL = 6
tCK(AVG)
CWL = 7
tCK(AVG)
CWL = 5
tCK(AVG)
CWL = 6
tCK(AVG)
Reserved
1.875
<2.5
(Optional) Note 5,9
Reserved
Reserved
1.875
<2.5
ns
4
ns
1,2,3,7
CWL = 7
tCK(AVG)
Reserved
ns
1,2,3,4,
CWL = 5,6
tCK(AVG)
Reserved
ns
4
ns
1,2,3,4
ns
4
CWL = 7
tCK(AVG)
CWL = 5,6
tCK(AVG)
CWL = 7
tCK(AVG)
1.5
<1.875
Reserved
1.5
Supported CL Settings
Supported CWL Settings
Page 41 of 59
ns
1,2,3
(Optional)
<1.875
ns
5
6,7,8,9
nCK
5,6,7
nCK
Rev. 1.0 March 2009
K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
[ Table 46 ] DDR3-1600 Speed Bins
Speed
DDR3-1600
CL-nRCD-nRP
Parameter
11-11-11
Units
Symbol
min
max
tAA
13.75
(13.125)5,9
20
ns
tRCD
13.75
(13.125)5,9
-
ns
PRE command period
tRP
13.75
(13.125)5,9
-
ns
ACT to ACT or REF command period
tRC
48.75
(48.125)5,9
-
ns
Intermal read command to first data
ACT to internal read or write delay time
ACT to PRE command period
CL = 6
CL = 7
CL = 8
CL = 9
CL = 10
CL = 11
Note
tRAS
35
9*tREFI
ns
CWL = 5
tCK(AVG)
2.5
3.3
ns
1,2,3,8
CWL = 6
tCK(AVG)
Reserved
ns
1,2,3,4,8
CWL = 7, 8
tCK(AVG)
Reserved
ns
4
CWL = 5
tCK(AVG)
ns
4
ns
1,2,3,4,8
Reserved
1.875
<2.5
CWL = 6
tCK(AVG)
CWL = 7
tCK(AVG)
Reserved
ns
1,2,3,4,8
CWL = 8
tCK(AVG)
Reserved
ns
4
CWL = 5
tCK(AVG)
Reserved
ns
4
CWL = 6
tCK(AVG)
ns
1,2,3,8
CWL = 7
tCK(AVG)
Reserved
ns
1,2,3,4,8
(Optional) Note 5,9
1.875
<2.5
CWL = 8
tCK(AVG)
Reserved
ns
1,2,3,4
CWL = 5,6
tCK(AVG)
Reserved
ns
4
CWL = 7
tCK(AVG)
ns
1,2,3,4,8
1.5
<1.875
(Optional) Note 9,10
CWL = 8
tCK(AVG)
TBD
ns
1,2,3,4
CWL = 5,6
tCK(AVG)
Reserved
ns
4
CWL = 7
tCK(AVG)
ns
1,2,3,8
1.5
<1.875
(Optional) Note 9,10
CWL = 8
tCK(AVG)
Reserved
ns
1,2,3,4
CWL = 5,6,7
tCK(AVG)
Reserved
ns
4
CWL = 8
tCK(AVG)
ns
1,2,3,5
1.25
Supported CL Settings
Supported CWL Settings
Page 42 of 59
<1.5
6,7,8,9,10,11
nCK
5,6,7,8
nCK
Rev. 1.0 March 2009
K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
13.3.1 Speed Bin Table Notes
Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V);
Note :
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next "SupportedCL".
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns
or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED.
4. "Reserved" settings are not allowed. User must program a different value.
5. "Optional" settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to supplier’s data sheet and/
or the DIMM SPD information if and how this setting is supported.
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but
verified by Design/Characterization.
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but
verified by Design/Characterization.
8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but
verified by Design/Characterization.
9. For devices supporting optional downshift to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 ns or lower. SPD settings must be programmed to
match. For example, DDR3-1333(CL9) devices supporting downshift to DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte
16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600(CL11) devices supporting downshift to DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin
(Byte 21,23) also should be programmed accodingly. For example, 49.125ns (tRASmin + tRPmin=36ns+13.125ns) for DDR3-1333(CL9) and 48.125ns
(tRASmin+tRPmin=35ns+13.125ns) for DDR3-1600(CL11).
Page 43 of 59
Rev. 1.0 March 2009
K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
14.0 Timing Parameters by Speed Grade
[ Table 47 ] Timing Parameters by Speed Bin
Speed
Parameter
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tCK(DLL_OF
F)
8
-
8
-
8
-
8
-
Units
Note
ns
6
Clock Timing
Minimum Clock Cycle Time (DLL off mode)
Average Clock Period
tCK(avg)
See Speed Bins Table
Clock Period
tCK(abs)
tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max +
tJIT(per)min
tJIT(per)max
tJIT(per)min
tJIT(per)max
tJIT(per)min
tJIT(per)max
tJIT(per)min
tJIT(per)max
Average high pulse width
tCH(avg)
Average low pulse width
Clock Period Jitter
Clock Period Jitter during DLL locking period
Cycle to Cycle Period Jitter
ps
ps
0.47
0.53
0.47
0.53
0.47
0.53
0.47
0.53
tCK(avg)
tCL(avg)
0.47
0.53
0.47
0.53
0.47
0.53
0.47
0.53
tCK(avg)
tJIT(per)
-100
100
-90
90
-80
80
-70
70
ps
tJIT(per, lck)
-90
90
-80
80
-70
70
-60
60
ps
tJIT(cc)
200
180
160
140
Cycle to Cycle Period Jitter during DLL locking period
tJIT(cc, lck)
180
160
140
120
Cumulative error across 2 cycles
tERR(2per)
- 147
147
- 132
132
- 118
118
-103
103
ps
Cumulative error across 3 cycles
tERR(3per)
- 175
175
- 157
157
- 140
140
-122
122
ps
Cumulative error across 4 cycles
tERR(4per)
- 194
194
- 175
175
- 155
155
-136
136
ps
Cumulative error across 5 cycles
tERR(5per)
- 209
209
- 188
188
- 168
168
-147
147
ps
Cumulative error across 6 cycles
tERR(6per)
- 222
222
- 200
200
- 177
177
-155
155
ps
Cumulative error across 7 cycles
tERR(7per)
- 232
232
- 209
209
- 186
186
-163
163
ps
Cumulative error across 8 cycles
tERR(8per)
- 241
241
- 217
217
- 193
193
-169
169
ps
Cumulative error across 9 cycles
tERR(9per)
- 249
249
- 224
224
- 200
200
-175
175
ps
Cumulative error across 10 cycles
tERR(10per)
- 257
257
- 231
231
- 205
205
-180
180
ps
Cumulative error across 11 cycles
tERR(11per)
- 263
263
- 237
237
- 210
210
-184
184
ps
Cumulative error across 12 cycles
tERR(12per)
- 269
269
- 242
242
- 215
215
-188
188
ps
Cumulative error across n = 13, 14 ... 49, 50 cycles
ps
ps
tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min
tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max
tERR(nper)
ps
24
Absolute clock HIGH pulse width
tCH(abs)
0.43
-
0.43
-
0.43
-
0.43
-
tCK(avg)
25
Absolute clock Low pulse width
tCL(abs)
0.43
-
0.43
-
0.43
-
0.43
-
tCK(avg)
26
tDQSQ
-
200
-
150
-
125
-
100
ps
13
tQH
0.38
-
0.38
-
0.38
-
0.38
-
tCK(avg)
13, g
DQ low-impedance time from CK, CK
tLZ(DQ)
-800
400
-600
300
-500
250
-450
225
ps
13,14, f
DQ high-impedance time from CK, CK
tHZ(DQ)
-
400
-
300
-
250
-
225
ps
13,14, f
Data setup time to DQS, DQS referenced to
VIH(AC)VIL(AC) levels
tDS(base)
75
-
25
-
30
-
10
ps
d, 17
Data hold time to DQS, DQS referenced to
VIH(AC)VIL(AC) levels
tDH(base)
150
-
100
-
65
-
45
ps
d, 17
DQ and DM Input pulse width for each input
tDIPW
600
-
490
-
400
-
360
ps
28
DQS, DQS READ Preamble
tRPRE
0.9
Note 19
0.9
Note 19
0.9
Note 19
0.9
Note 19
tCK
13, 19, g
DQS, DQS differential READ Postamble
tRPST
0.3
Note 11
0.3
Note 11
0.3
Note 11
0.3
Note 11
tCK
11, 13, b
DQS, DQS output high time
tQSH
0.38
-
0.38
-
0.4
-
0.4
-
tCK(avg)
13, g
DQS, DQS output low time
tQSL
0.38
-
0.38
-
0.4
-
0.4
-
tCK(avg)
13, g
DQS, DQS WRITE Preamble
tWPRE
0.9
-
0.9
-
0.9
-
0.9
-
tCK
DQS, DQS WRITE Postamble
Data Timing
DQS,DQS to DQ skew, per group, per access
DQ output hold time from DQS, DQS
Data Strobe Timing
tWPST
0.3
-
0.3
-
0.3
-
0.3
-
tCK
DQS, DQS rising edge output access time from rising
CK, CK
tDQSCK
-400
400
-300
300
-255
255
-225
225
ps
13,f
DQS, DQS low-impedance time (Referenced from RL-1)
tLZ(DQS)
-800
400
-600
300
-500
250
-450
225
ps
13,14,f
DQS, DQS high-impedance time (Referenced from
RL+BL/2)
tHZ(DQS)
-
400
-
300
-
250
-
225
ps
12,13,14
DQS, DQS differential input low pulse width
tDQSL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
29, 31
DQS, DQS differential input high pulse width
tDQSH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
30, 31
DQS, DQS rising edge to CK, CK rising edge
tDQSS
-0.25
0.25
-0.25
0.25
-0.25
0.25
-0.27
0.27
tCK(avg)
c
DQS,DQS faling edge setup time to CK, CK rising edge
tDSS
0.2
-
0.2
-
0.2
-
0.18
-
tCK(avg)
c, 32
DQS,DQS faling edge hold time to CK, CK rising edge
tDSH
0.2
-
0.2
-
0.2
-
0.18
-
tCK(avg)
c, 32
Page 44 of 59
Rev. 1.0 March 2009
K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
[ Tabel 47 ] Timing Parameters by Speed Bin (Cont.)
Speed
Parameter
DDR3-800
Symbol
DDR3-1066
MIN
MAX
DDR3-1333
MIN
MAX
DDR3-1600
MIN
MAX
MIN
MAX
Units
Note
Command and Address Timing
DLL locking time
tDLLK
512
-
512
-
512
-
512
-
internal READ Command to PRECHARGE Command
delay
tRTP
max
(4nCK,7.5ns)
-
max
(4nCK,7.5ns)
-
max
(4nCK,7.5ns)
-
max
(4nCK,7.5ns)
-
e
Delay from start of internal write transaction to internal
read command
tWTR
max
(4nCK,7.5ns)
-
max
(4nCK,7.5ns)
-
max
(4nCK,7.5ns)
-
max
(4nCK,7.5ns)
-
e,18
WRITE recovery time
nCK
tWR
15
-
15
-
15
-
15
-
ns
Mode Register Set command cycle time
tMRD
4
-
4
-
4
-
4
-
nCK
Mode Register Set command update delay
tMOD
max
(12nCK,15ns
)
-
max
(12nCK,15ns
)
-
max
(12nCK,15ns
)
-
max
(12nCK,15ns
)
-
tCCD
4
-
4
-
4
-
4
-
-
1
-
CAS# to CAS# command delay
Auto precharge write recovery + precharge time
Multi-Purpose Register Recovery Time
ACTIVE to PRECHARGE command period
tDAL(min)
tMPRR
WR + roundup (tRP / tCK(AVG))
1
tRAS
-
1
-
1
-
-
max
(4nCK,6ns)
nCK
nCK
See 13.3 " Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin" on page 37
max
(4nCK,7.5ns)
e
nCK
22
ns
e
ACTIVE to ACTIVE command period for 1KB page size
tRRD
max
(4nCK,10ns)
-
max
(4nCK,6ns)
-
e
ACTIVE to ACTIVE command period for 2KB page size
tRRD
max
(4nCK,10ns)
-
max
(4nCK,10ns)
-
max
(4nCK,7.5ns)
-
max
(4nCK,7.5ns)
-
e
Four activate window for 1KB page size
tFAW
40
-
37.5
-
30
-
30
-
ns
e
Four activate window for 2KB page size
tFAW
50
-
50
-
45
-
40
-
ns
e
Command and Address setup time to CK, CK referenced to VIH(AC) / VIL(AC) levels
tIS(base)
200
-
125
-
65
-
TBD
-
ps
b,16
Command and Address hold time from CK, CK referenced to VIH(AC) / VIL(AC) levels
tIH(base)
275
-
200
-
140
-
TBD
-
ps
b,16
Command and Address setup time to CK, CK referenced to VIH(AC) / VIL(AC) levels
tIS(base)
AC150
200 + 150
-
125 + 150
-
65+125
-
TBD+125
-
ps
b,16,27
Control & Address Input pulse width for each input
tIPW
900
-
780
-
620
-
560
-
ps
28
Power-up and RESET calibration time
tZQinitI
512
-
512
-
512
-
512
-
nCK
Normal operation Full calibration time
tZQoper
256
-
256
-
256
-
256
-
nCK
Normal operation short calibration time
tZQCS
64
-
64
-
64
-
64
-
nCK
tXPR
max(5nCK,
tRFC + 10ns)
-
max(5nCK,
tRFC + 10ns)
-
max(5nCK,
tRFC + 10ns)
-
max(5nCK,
tRFC + 10ns)
-
Exit Self Refresh to commands not requiring a locked
DLL
tXS
max(5nCK,tR
FC + 10ns)
-
max(5nCK,tR
FC + 10ns)
-
max(5nCK,tR
FC + 10ns)
-
max(5nCK,tR
FC + 10ns)
-
Exit Self Refresh to commands requiring a locked DLL
tXSDLL
tDLLK(min)
-
tDLLK(min)
-
tDLLK(min)
-
tDLLK(min)
-
Calibration Timing
23
Reset Timing
Exit Reset from CKE HIGH to a valid command
Self Refresh Timing
Minimum CKE low width for Self refresh entry to exit
timing
tCKESR
tCKE(min) +
1tCK
-
tCKE(min) +
1tCK
-
tCKE(min) +
1tCK
-
tCKE(min) +
1tCK
Valid Clock Requirement after Self Refresh Entry
(SRE) or Power-Down Entry (PDE)
tCKSRE
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
Valid Clock Requirement before Self Refresh Exit
(SRX) or Power-Down Exit (PDX) or Reset Exit
tCKSRX
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
Page 45 of 59
nCK
Rev. 1.0 March 2009
K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
[ Table 47 ] Timing Parameters by Speed Bin (Cont.)
Speed
Parameter
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tXP
max
(3nCK,
7.5ns)
-
max
(3nCK,
7.5ns)
-
max
(3nCK,6ns)
-
max
(3nCK,6ns)
-
tXPDLL
max
(10nCK,
24ns)
-
max
(10nCK,
24ns)
-
max
(10nCK,
24ns)
-
max
(10nCK,
24ns)
-
tCKE
max
(3nCK,
7.5ns)
-
max
(3nCK,
5.625ns)
-
max
(3nCK,
5.625ns)
-
max
(3nCK,5ns)
-
Units
Note
Power Down Timing
Exit Power Down with DLL on to any valid command;Exit Percharge Power Down with DLL
frozen to commands not requiring a locked DLL
Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL
CKE minimum pulse width
Command pass disable delay
2
tCPDED
1
-
1
-
1
-
1
-
tPD
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tCK
15
Timing of ACT command to Power Down entry
tACTPDEN
1
-
1
-
1
-
1
-
nCK
20
Timing of PRE command to Power Down entry
tPRPDEN
1
-
1
-
1
-
1
-
nCK
20
Timing of RD/RDA command to Power Down entry
tRDPDEN
RL + 4 +1
-
RL + 4 +1
-
RL + 4 +1
-
RL + 4 +1
-
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BL4OTF)
tWRPDEN
WL + 4
+(tWR/
tCK(avg))
-
WL + 4
+(tWR/
tCK(avg))
-
WL + 4
+(tWR/
tCK(avg))
-
WL + 4
+(tWR/
tCK(avg))
-
nCK
9
tWRAPDEN
WL + 4
+WR +1
-
WL + 4
+WR +1
-
WL + 4
+WR +1
-
WL + 4
+WR +1
-
nCK
10
tWRPDEN
WL + 2
+(tWR/
tCK(avg))
-
WL + 2
+(tWR/
tCK(avg))
-
WL + 2
+(tWR/
tCK(avg))
-
WL + 2
+(tWR/
tCK(avg))
-
nCK
9
tWRAPDEN
WL +2 +WR
+1
-
WL +2 +WR
+1
-
WL +2 +WR
+1
-
WL +2 +WR
+1
-
nCK
10
Power Down Entry to Exit Timing
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BL4OTF)
Timing of WR command to Power Down entry
(BL4MRS)
Timing of WRA command to Power Down entry
(BL4MRS)
nCK
Timing of REF command to Power Down entry
tREFPDEN
1
-
1
-
1
-
1
-
Timing of MRS command to Power Down entry
tMRSPDEN
tMOD(min)
-
tMOD(min)
-
tMOD(min)
-
tMOD(min)
-
20,21
ODT high time without write command or with wirte
command and BC4
ODTH4
4
-
4
-
4
-
4
-
nCK
ODT high time with Write command and BL8
ODTH8
6
-
6
-
6
-
6
-
nCK
Asynchronous RTT tum-on delay (Power-Down with
DLL frozen)
tAONPD
2
8.5
2
8.5
2
8.5
2
8.5
ns
Asynchronous RTT tum-off delay (Power-Down with
DLL frozen)
ODT Timing
tAOFPD
2
8.5
2
8.5
2
8.5
2
8.5
ns
ODT turn-on
tAON
-400
400
-300
300
-250
250
-225
225
ps
7,f
RTT_NOM and RTT_WR turn-off time from ODTLoff
reference
tAOF
0.3
0.7
0.3
0.7
0.3
0.7
0.3
0.7
tCK(avg)
8,f
RTT dynamic change skew
tADC
0.3
0.7
0.3
0.7
0.3
0.7
0.3
0.7
tCK(avg)
f
First DQS pulse rising edge after tDQSS margining
mode is programmed
tWLMRD
40
-
40
-
40
-
40
-
tCK
3
DQS/DQS delay after tDQS margining mode is programmed
tWLDQSEN
25
-
25
-
25
-
25
-
tCK
3
-
245
-
195
-
165
-
ps
Write Leveling Timing
Setup time for tDQSS latch
tWLS
325
Write leveling hold time from rising DQS, DQS crossing to rising CK, CK crossing
tWLH
325
-
245
-
195
-
165
-
ps
Write leveling output delay
tWLO
0
9
0
9
0
9
0
7.5
ns
Write leveling output error
tWLOE
0
2
0
2
0
2
0
2
ns
Page 46 of 59
Rev. 1.0 March 2009
K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
14.1 Jitter Notes
Specific Note a
Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the input
clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm, another
Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min.
Specific Note b These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge
to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per),
tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not.
Specific Note c These parameters are measured from a data strobe signal (DQS(L/U), DQS(L/U)) crossing to its respective clock signal (CK, CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the
clock signal crossing. That is, these parameters should be met whether clock jitter is present or not.
Specific Note d These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition edge to its respective data strobe
signal (DQS(L/U), DQS(L/U)) crossing. Specific Note e For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] =
RU{ tPARAM [ns] / tCK(avg) [ns] }, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the
device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means: For
DDR3-800 6-6-6, of which tRP = 15ns, the device will support tnRP = RU{tRP / tCK(avg)} = 6, as long as the input clock jitter specifications are met, i.e. Precharge command at Tm and Active command at Tm+6 is valid even if (Tm+6 - Tm) is less than 15ns due to
input clock jitter.
Specific Note f When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input clock,
where 2 <= m <= 12. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = - 172 ps and tERR(mper),act,max = + 193 ps,
then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = - 400 ps - 193 ps = - 593 ps and tDQSCK,max(derated) =
tDQSCK,max - tERR(mper),act,min = 400 ps + 172 ps = + 572 ps. Similarly, tLZ(DQ) for DDR3-800 derates to tLZ(DQ),min(derated) =
- 800 ps - 193 ps = - 993 ps and tLZ(DQ),max(derated) = 400 ps + 172 ps = + 572 ps. (Caution on the min/max usage!)
Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <=
12, and tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12.
Specific Note g When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has tCK(avg),act =
2500 ps, tJIT(per),act,min = - 72 ps and tJIT(per),act,max = + 93 ps, then tRPRE,min(derated) = tRPRE,min + tJIT(per),act,min = 0.9
x tCK(avg),act + tJIT(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. Similarly, tQH,min(derated) = tQH,min + tJIT(per),act,min =
0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (Caution on the min/max usage!)
Page 47 of 59
Rev. 1.0 March 2009
K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
14.2 Timing Parameter Notes
1. Actual value dependant upon measurement level definitions which are TBD.
2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.
3. The max values are system dependent.
4. WR as programmed in mode register
5. Value must be rounded-up to next higher integer value
6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.
7. For definition of RTT turn-on time tAON see "Device Operation"
8. For definition of RTT turn-off time tAOF see "Device Operation".
9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.
10. WR in clock cycles as programmed in MR0
11. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. Device Operation.
12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated
by TBD
13. Value is valid for RON34
14. Single ended signal parameter. Refer to chapter 8 and chapter 9 for definition and measurement method.
15. tREFI depends on TOPER
16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate, Note for DQ and DM signals,
VREF(DC) = VREFDQ(DC). FOr input only pins except RESET, VREF(DC)=VREFCA(DC).
See "Address/ Command Setup, Hold and Derating"
17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for DQ and DM signals,
VREF(DC)= VREFDQ(DC). For input only pins except RESET, VREF(DC)=VREFCA(DC).
See "Data Setup, Hold and Slew Rate Derating"
18. Start of internal write transaction is definited as follows ;
For BL8 (fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL.
For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL
For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL
19. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side. See "Device Operation"
20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down
IDD spec will not be applied until finishing those operations.
21. Altough CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time
such as tXPDLL(min) is also required. See "Device Operation".
22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
23. One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming
the maximum sensitivities specified in the ’Output Driver Voltage and Temperature Sensitivity’ and ’ODT Voltage and Temperature Sensitivity’ tables. The
appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters.
One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. The interval could be defined by the following formula:
ZQCorrection
(TSens x Tdriftrate) + (VSens x Vdriftrate)
where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities.
For example, if TSens = 1.5% /°C, VSens = 0.15% / mV, Tdriftrate = 1°C / sec and Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calculated as:
0.5
(1.5 x 1) + (0.15 x 15)
= 0.133 ~
~ 128ms
24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.
25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge.
26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge.
27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100 ps of derating to accommodate for the lower alternate threshold of 150 mV and another 25 ps to account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns].
28. Pulse width of a input signal is defined as the width between the first crossing of VREF(DC) and the consecutive crossing of VREF(DC)
29. tDQSL describes the instantaneous differential input low pulse width on DQS-DQS, as measured from one falling edge to the next consecutive rising edge.
30. tDQSH describes the instantaneous differential input high pulse width on DQS-DQS, as measured from one rising edge to the next consecutive falling edge.
31. tDQSH, act + tDQSL, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.
32. tDSH, act + tDSS, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.
Page 48 of 59
Rev. 1.0 March 2009
K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
14.3 Address / Command Setup, Hold and Derating:
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value (see Table
48) to the ∆tIS and ∆tIH derating value (see Table 49) respectively.
Example: tIS (total setup time) = tIS(base) + ∆tIS Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VREF(DC) and the first crossing of VIH(AC)min. Setup (tIS) nominal slew rate for a falling signal is defined as
the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max. If the actual signal is always earlier than the nominal slew rate
line between shaded ’VREF(DC) to ac region’, use nominal slew rate for derating value (see Figure 23). If the actual signal is later than the nominal slew
rate line anywhere between shaded ’VREF(DC) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see Figure 25).
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC).
Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC). If
the actual signal is always later than the nominal slew rate line between shaded ’dc to VREF(DC) region’, use nominal slew rate for derating value (see
Figure 24). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to VREF(DC) region’, the slew rate of a tangent line
to the actual signal from the dc level to VREF(DC) level is used for derating value (see Figure 26).
For a valid transition the input signal has to remain above/below VIH/IL(AC) for some time tVAC (see Table 50).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(AC) at the time of the rising clock
transition) a valid input signal is still required to complete the transition and reach VIH/IL(AC).
For slew rates in between the values listed in Table 51, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
[ Table 48 ] ADD/CMD Setup and Hold Base-Values for 1V/ns
[ps]
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
reference
tIS(base)
200
125
65
45
VIH/L(AC)
tIH(base)
275
200
140
120
VIH/L(DC)
tIS(base)-AC150
200 + 150
125 + 150
65+125
45+125
VIH/L(AC)
Note : AC/DC referenced for 1V/ns DQ-slew rate and 2V/ns DQS slew rate
Note : The tIS(base)-AC150 specifications are further adjusted to add an addi-tional 100ps of derating to accommodate for the lower alternate thresh-old
of 150mV and another 25ps to acccount for the earlier reference point [(175mv-150mV)/1 V/ns].
[ Table 49 ] Derating values DDR3-800/1066/1333/1600 tIS/tIH-ac/dc based
∆tIS, ∆tIH Derating [ps] AC/DC based
AC175 Threshold -> VIH(AC) = VREF(DC) + 175mV, VIL(AC) = VREF(DC) - 175mV
CLK,CLK Differential Slew Rate
4.0 V/ns
CMD/
ADD
Slew
rate
V/ns
3.0 V/ns
∆tIH
2.0 V/ns
∆tIS
∆tIH
∆tIS
∆tIS
∆tIH
2.0
88
50
88
50
88
50
1.5
59
34
59
34
59
34
1.8 V/ns
∆tIS
1.6 V/ns
1.4V/ns
1.2V/ns
1.0V/ns
∆tIH
∆tIS
∆tIH
∆tIS
∆tIH
∆tIS
∆tIH
∆tIS
∆tIH
96
58
104
66
112
74
120
84
128
100
67
42
75
50
83
58
91
68
99
84
1.0
0
0
0
0
0
0
8
8
16
16
24
24
32
34
40
50
0.9
-2
-4
-2
-4
-2
-4
6
4
14
12
20
20
30
30
38
46
0.8
-6
-10
-6
-10
-6
-10
2
-2
10
6
13
14
26
24
34
40
0.7
-11
-16
-11
-16
-11
-16
-3
-8
5
0
13
8
21
18
29
34
0.6
-17
-26
-17
-26
-17
-26
-9
-18
-1
-10
7
-2
15
8
23
24
0.5
-35
-40
-35
-40
-35
-40
-27
-32
-19
-24
-11
-16
-2
-6
5
10
0.4
-62
-60
-62
-60
-62
-60
-54
-52
-46
-44
-38
-36
-30
-26
-22
-10
Page 49 of 59
Rev. 1.0 March 2009
K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
[ Table 50 ] Derating values DDR3-1333/1600 tIS/tIH-ac/dc based - Alternate AC150 Threshold
∆tIS, ∆tIH Derating [ps] AC/DC based
Alternate AC150 Threshold -> VIH(AC) = VREF(DC) + 150mV, VIL(AC) = VREF(DC) - 150mV
CLK,CLK Differential Slew Rate
4.0 V/ns
CMD/
ADD
Slew
rate
V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4V/ns
1.2V/ns
1.0V/ns
∆tIS
∆tIH
∆tIS
∆tIH
∆tIS
∆tIH
∆tIS
∆tIH
∆tIS
∆tIH
∆tIS
∆tIH
∆tIS
∆tIH
∆tIS
∆tIH
2.0
75
50
75
50
75
50
83
58
91
66
99
74
107
84
115
100
1.5
50
34
50
34
50
34
58
42
66
50
74
58
82
68
90
84
1.0
0
0
0
0
0
0
8
8
16
16
24
24
32
34
40
50
0.9
0
-4
0
-4
0
-4
8
4
16
12
24
20
32
30
40
46
0.8
0
-10
0
-10
0
-10
8
-2
16
6
24
14
32
24
40
40
0.7
0
-16
0
-16
0
-16
8
-8
16
0
24
8
32
18
40
34
0.6
-1
-26
-1
-26
-1
-26
7
-18
15
-10
23
-2
31
8
39
24
0.5
-10
-40
-10
-40
-10
-40
-2
-32
6
-24
14
-16
22
-6
30
10
0.4
-25
-60
-25
-60
-25
-60
-17
-52
-9
-44
-1
-36
7
-26
15
-10
[ Table 51 ] Required time tVAC above VIH(AC) {blow VIL(AC)} for valid transition
tVAC @175mV [ps]
Slew Rate[V/ns]
min
tVAC @150mV [ps]
max
min
max
>2.0
75
-
175
-
2.0
57
-
170
-
1.5
50
-
167
-
1.0
38
-
163
-
0.9
34
-
162
-
0.8
29
-
161
-
0.7
22
-
159
-
0.6
13
-
155
-
0.5
0
-
150
-
< 0.5
0
-
150
-
Page 50 of 59
Rev. 1.0 March 2009
K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
Note :Clock and Strobe are drawn on a different time scale.
tIS
tIH
tIS
tIH
tDS
tDH
tDS
tDH
CK
CK
DQS
DQS
VDDQ
tVAC
VIH(AC) min
VREF to ac
region
VIH(DC) min
nominal
slew rate
VREF(DC)
nominal slew
rate
VIL(DC) max
VREF to ac
region
VIL(AC) max
tVAC
VSS
Delta TF
Delta TR
Setup Slew Rate= VREF(DC) - VIL(AC)max
Falling Signal
Delta TF
Setup Slew Rate VIH(AC)min - VREF(DC)
=
Rising Signal
Delta TR
Figure 21 - Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and tIS
(for ADD/CMD with respect to clock).
Page 51 of 59
Rev. 1.0 March 2009
K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
Note :Clock and Strobe are drawn on a different time scale.
tIS
tIH
tIS
tIH
tDS
tDH
tDS
tDH
CK
CK
DQS
DQS
VDDQ
VIH(AC) min
VIH(DC) min
dc to VREF
region
nominal
slew rate
VREF(DC)
dc to VREF
region
nominal
slew rate
dc to VREF
region
VIL(DC) max
VIL(AC) max
VSS
Delta TR
Hold Slew Rate VREF(DC) - VIL(DC)max
Rising Signal =
Delta TR
Delta TF
Hold Slew Rate VIH(DC)min - VREF(DC)
=
Falling Signal
Delta TF
Figure 22 - Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe) and tIH
(for ADD/CMD with respect to clock).
Page 52 of 59
Rev. 1.0 March 2009
K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
Note :Clock and Strobe are drawn on a different time scale.
tIS
tIH
tIS
tIH
tDS
tDH
tDS
tDH
CK
CK
DQS
DQS
VDDQ
nominal
line
tVAC
VIH(AC) min
VREF to ac
region
VIH(DC) min
tangent
line
VREF(DC)
tangent
line
VIL(DC) max
VREF to ac
region
VIL(AC) max
nominal
line
Delta TR
VSS
Delta TF
Setup Slew Rate tangent line[VIH(AC)min - VREF(DC)]
=
Rising Signal
Delta TR
Setup Slew Rate tangent line[VREF(DC) - VIL(AC)max]
Falling Signal =
Delta TF
Figure 23. Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS
(for ADD/CMD with respect to clock)
Page 53 of 59
Rev. 1.0 March 2009
K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
Note :Clock and Strobe are drawn on a different time scale.
tIS
tIH
tIS
tIH
tDS
tDH
tDS
tDH
CK
CK
DQS
DQS
VDDQ
VIH(AC) min
nominal
line
VIH(DC) min
dc to VREF
region
tangent
line
VREF(DC)
dc to VREF
region
tangent
line
nominal
line
VIL(DC) max
VIL(AC) max
VSS
Delta TR
Delta TF
Hold Slew Rate tangent line [ VREF(DC) - VIL(DC)max ]
Rising Signal =
Delta TR
Hold Slew Rate tangent line [ VIH(DC)min - VREF(DC) ]
Falling Signal =
Delta TF
Figure 24 - Illustration of tangent line for hold time tDH (for DQ with respect to strobe) and tIH
(for ADD/CMD with respect to clock)
Page 54 of 59
Rev. 1.0 March 2009
K4B4G0446B
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DDP 4Gb DDR3 SDRAM
14.4 Data Setup, Hold and Slew Rate Derating:
or all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and tDH(base) value (see
Table 52) to the ∆ tDS and ∆tDH (see Table 53) derating value respectively. Example: tDS (total setup time) = tDS(base) + ∆tDS.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC)min.
Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max
(see Figure 25). If the actual signal is always earlier than the nominal slew rate line between shaded ’VREF(DC) to ac region’, use nominal slew rate for
derating value. If the actual signal is later than the nominal slew rate line anywhere
between shaded ’VREF(DC) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see
Figure 27).
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC).
Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC)
(see Figure 26). If the actual signal is always later than the nominal slew rate line between shaded ’dc level to VREF(DC) region’, use nominal slew rate for
derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to VREF(DC) region’, the slew rate of a tangent
line to the actual signal from the dc level to VREF(DC) level is used for derating value (see Figure 28).
For a valid transition the input signal has to remain above/below VIH/IL(AC) for some time tVAC (see Table 54).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(AC) at the time of the rising clock
transition) a valid input signal is still required to complete the transition and reach VIH/IL(AC).
For slew rates in between the values listed in the tables the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization
[ Table 52 ] Data Setup and Hold Base-Value
[ps]
tDS(base)
tDH(base)
tDS(AC150)
DDR3-800
75
150
75+50
DDR3-1066
25
100
25+50
DDR3-1333
30
65
-
DDR3-1600
10
45
-
reference
VIH/L(AC)
VIH/L(DC)
VIH/L(AC)
Note : AC/DC referenced for 1V/ns DQ-slew rate and 2 V/ns DQS slew rate)
[ Table 53 ] Derating values DDR3-800/1066/1333/1600 tIS/tIH-ac/dc based
DDR3 DQ
Slew
800/ rate
1066 V/ns
DDR3 DQ
Slew
1333/ rate
1600 V/ns
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
4.0 V/ns
∆tDS ∆tDH
88
50
59
34
0
0
75
50
50
34
0
0
-
∆tDS, ∆tDH Derating [ps] AC/DC baseda
DQS,DQS Differential Slew Rate
2.0 V/ns
1.8 V/ns
1.6 V/ns
∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH
88
50
59
34
67
42
0
0
8
8
16
16
-2
-4
6
4
14
12
-6
-10
2
-2
10
6
-3
-8
5
0
-1
-10
75
50
50
34
58
42
0
0
8
8
16
16
0
-4
8
4
16
12
0
-10
8
-2
16
6
8
-8
16
0
15
-10
-
3.0 V/ns
∆tDS ∆tDH
88
50
59
34
0
0
-2
-4
75
50
50
34
0
0
0
-4
-
1.4V/ns
∆tDS ∆tDH
22
20
18
14
13
8
7
-2
-11
-16
24
20
24
14
24
8
23
-2
14
-16
-
1.2V/ns
∆tDS ∆tDH
26
24
21
18
15
8
-2
-6
-30
-26
32
24
32
18
31
8
22
-6
7
-26
1.0V/ns
∆tDS ∆tDH
29
34
23
24
6
10
-22
-10
40
34
39
24
30
10
15
-10
Note : a. Cell contents shaded in red are defined as ’not supported’.
[ Table 54 ] Required time tVAC above VIH(AC) {blow VIL(AC)} for valid transition
Slew Rate[V/ns]
>2.0
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
<0.5
tVAC[ps] DDR3-800/1066
tVAC[ps] DDR3-1333/1600
min
max
min
max
75
57
50
38
34
29
22
13
0
0
-
175
170
167
163
162
161
159
155
155
150
-
Page 55 of 59
Rev. 1.0 March 2009
K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
Note :Clock and Strobe are drawn on a different time scale.
tIS
tIH
tIS
tIH
tDS
tDH
tDS
tDH
CK
CK
DQS
DQS
VDDQ
tVAC
VIH(AC) min
VREF to ac
region
VIH(DC) min
nominal
slew rate
VREF(DC)
nominal slew
rate
VIL(DC) max
VREF to ac
region
VIL(AC) max
tVAC
VSS
Delta TF
Delta TR
Setup Slew Rate= VREF(DC) - VIL(AC)max
Falling Signal
Delta TF
Setup Slew Rate VIH(AC)min - VREF(DC)
=
Rising Signal
Delta TR
Figure 25 - Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and tIS
(for ADD/CMD with respect to clock).
Page 56 of 59
Rev. 1.0 March 2009
K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
Note :Clock and Strobe are drawn on a different time scale.
tIS
tIH
tIS
tIH
tDS
tDH
tDS
tDH
CK
CK
DQS
DQS
VDDQ
VIH(AC) min
VIH(DC) min
dc to VREF
region
nominal
slew rate
VREF(DC)
dc to VREF
region
nominal
slew rate
dc to VREF
region
VIL(DC) max
VIL(AC) max
VSS
Delta TR
Hold Slew Rate
=
Rising Signal
VREF(DC) - VIL(DC)max
Delta TR
Delta TF
VIH(DC)min - VREF(DC)
Hold Slew Rate
Falling Signal =
Delta TF
Figure 26 - Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe) and tIH
(for ADD/CMD with respect to clock).
Page 57 of 59
Rev. 1.0 March 2009
K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
Note :Clock and Strobe are drawn on a different time scale.
tIS
tIH
tIS
tIH
tDS
tDH
tDS
tDH
CK
CK
DQS
DQS
VDDQ
nominal
line
tVAC
VIH(AC) min
VREF to ac
region
VIH(DC) min
tangent
line
VREF(DC)
tangent
line
VIL(DC) max
VREF to ac
region
VIL(AC) max
nominal
line
Delta TR
VSS
Delta TF
Setup Slew Rate tangent line[VIH(AC)min - VREF(DC)]
=
Rising Signal
Delta TR
Setup Slew Rate tangent line[VREF(DC) - VIL(AC)max]
Falling Signal =
Delta TF
Figure 27 - Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS
(for ADD/CMD with respect to clock)
Page 58 of 59
Rev. 1.0 March 2009
K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
Note :Clock and Strobe are drawn on a different time scale.
tIS
tIH
tIS
tIH
tDS
tDH
tDS
tDH
CK
CK
DQS
DQS
VDDQ
VIH(AC) min
nominal
line
VIH(DC) min
dc to VREF
region
tangent
line
VREF(DC)
dc to VREF
region
tangent
line
nominal
line
VIL(DC) max
VIL(AC) max
VSS
Delta TR
Delta TF
Hold Slew Rate tangent line [ VREF(DC) - VIL(DC)max ]
Rising Signal =
Delta TR
Hold Slew Rate tangent line [ VIH(DC)min - VREF(DC) ]
Falling Signal =
Delta TF
Figure 28 - Illustration of tangent line for hold time tDH (for DQ with respect to strobe) and tIH
(for ADD/CMD with respect to clock)
Page 59 of 59
Rev. 1.0 March 2009