K4F170811D, K4F160811D K4F170812D, K4F160812D CMOS DRAM 2M x 8Bit CMOS Dynamic RAM with Fast Page Mode DESCRIPTION This is a family of 2,097,152 x 8 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K Ref.), access time (-50 or -60), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CASbefore-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 2Mx8 Fast Page Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines. FEATURES • Fast Page Mode operation • Part Identification • CAS-before-RAS refresh capability • RAS-only and Hidden refresh capability - K4F170811D-B(F) (5V, 4K Ref.) - K4F160811D-B(F) (5V, 2K Ref.) - K4F170812D-B(F) (3.3V, 4K Ref.) - K4F160812D-B(F) (3.3V, 2K Ref.) • Self-refresh capability (L-ver only) • Fast parallel test mode capability • TTL(5V)/LVTTL(3.3V) compatible inputs and outputs • Early Write or output enable controlled write • JEDEC Standard pinout • Active Power Dissipation • Available in Plastic SOJ and TSOP(II) packages Unit : mW 3.3V Speed 4K • Single +5V±10% power supply (5V product) 5V 2K 4K • Single +3.3V±0.3V power supply (3.3V product) 2K -50 324 396 495 605 -60 288 360 440 550 FUNCTIONAL BLOCK DIAGRAM • Refresh Cycles VCC K4F170811D 5V K4F170812D 3.3V K4F160811D 5V K4F160812D 3.3V Refresh Refresh period cycle Normal L-ver 4K RAS CAS W Control Clocks Vcc Vss VBB Generator 64ms Data in 128ms 2K Refresh Timer 32ms Refresh Control Refresh Counter • Performance Range Speed tRAC tCAC tRC tPC Remark -50 50ns 13ns 90ns 35ns 5V/3.3V -60 60ns 15ns 110ns 40ns 5V/3.3V A0-A11 (A0 - A10) *1 A0 - A8 (A0 - A9)*1 Buffer Row Decoder Memory Array 2,097,152 x 8 Cells Row Address Buffer Sense Amps & I/O Part NO. DQ0 to DQ7 Data out Col. Address Buffer Column Decoder Note) *1 : 2K Refresh SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. Buffer OE K4F170811D, K4F160811D K4F170812D, K4F160812D CMOS DRAM PIN CONFIGURATION (Top Views) • K4F17(6)0811(2)D-F • K4F17(6)0811(2)D-B VCC DQ0 DQ1 DQ2 DQ3 W RAS *A11(N.C) A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC DQ0 DQ1 DQ2 DQ3 W RAS *A11(N.C) A10 A0 A1 A2 A3 VCC VSS DQ7 DQ6 DQ5 DQ4 CAS OE A9 A8 A7 A6 A5 A4 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 *A11 is N.C for K160811(2)D(5V/3.3V, 2K Ref. product) B : 300mil 28 SOJ F : 300mil 28 TSOP II Pin Name Pin Function A0 - A11 Address Inputs (4K Product) A0 - A10 Address Inputs (2K Product) DQ0 - 7 Data In/Out VSS Ground RAS Row Address Strobe CAS Column Address Strobe W Read/Write Input OE Data Output Enable VCC Power(+5V) Power(+3.3V) N.C No Connection (2K Ref. product) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS DQ7 DQ6 DQ5 DQ4 CAS OE A9 A8 A7 A6 A5 A4 VSS K4F170811D, K4F160811D K4F170812D, K4F160812D CMOS DRAM ABSOLUTE MAXIMUM RATINGS Parameter Rating Symbol Units 3.3V 5V VIN,VOUT -0.5 to +4.6 -1.0 to +7.0 V Voltage on VCC supply relative to VSS VCC -0.5 to +4.6 -1.0 to +7.0 V Storage Temperature Tstg -55 to +150 -55 to +150 °C Power Dissipation PD 1 1 W IOS Address 50 50 mA Voltage on any pin relative to V SS Short Circuit Output Current * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C) Parameter 3.3V Symbol 5V Units Min Typ Max Min Typ Max Supply Voltage VCC 3.0 3.3 3.6 4.5 5.0 5.5 V Ground VSS 0 0 0 0 0 0 V Input High Voltage VIH 2.0 - VCC+0.3*1 2.4 - VCC+1.0*1 V Input Low Voltage VIL -0.3*2 - 0.8 -1.0*2 - 0.8 V *1 : VCC+1.3V/15ns(3.3V), VCC+2.0V/20ns(5V), Pulse width is measured at VCC *2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at VSS DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Max 3.3V 5V Parameter Symbol Min Max Units Input Leakage Current (Any input 0≤VIN≤VIN+0.3V, all other input pins not under test=0 Volt) II(L) -5 5 uA Output Leakage Current (Data out is disabled, 0V≤VOUT≤VCC) IO(L) -5 5 uA Output High Voltage Level(IOH=-2mA) VOH 2.4 - V Output Low Voltage Level(IOL=2mA) VOL - 0.4 V Input Leakage Current (Any input 0≤VIN≤VIN+0.5V, all other input pins not under test=0 Volt) II(L) -5 5 uA Output Leakage Current (Data out is disabled, 0V≤VOUT≤VCC) IO(L) -5 5 uA Output High Voltage Level(IOH=-5mA) VOH 2.4 - V Output Low Voltage Level(IOL=4.2mA) VOL - 0.4 V K4F170811D, K4F160811D K4F170812D, K4F160812D CMOS DRAM DC AND OPERATING CHARACTERISTICS (Continued) Symbol Power Speed ICC1 Don′t care ICC2 Max Units K4F170812D K4F160812D K4F170811D K4F160811D -50 -60 90 80 110 100 90 80 110 100 mA mA Normal L Don′t care 1 1 1 1 2 1 2 1 mA mA ICC3 Don′t care -50 -60 90 80 110 100 90 80 110 100 mA mA ICC4 Don′t care -50 -60 80 70 90 80 80 70 90 80 mA mA ICC5 Normal L Don′t care 0.5 200 0.5 200 1 250 1 250 mA uA ICC6 Don′t care -50 -60 90 80 110 100 90 80 110 100 mA mA ICC7 L Don′t care 250 250 300 300 uA ICCS L Don′t care 200 200 250 250 uA ICC1* : Operating Current (RAS and CAS cycling @tRC=min.) ICC2 : Standby Current (RAS=CAS=W=VIH) ICC3* : RAS-only Refresh Current (CAS=VIH, RAS cycling @tRC=min.) ICC4* : Fast Page Mode Current (RAS=VIL, CAS, Address cycling @tPC=min.) ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V) ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @t RC=min.) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=0.2V, DQ=Don′t care, TRC=31.25us(4K/L-ver), 62.5us(2K/L-ver), TRAS=TRASmin~300ns ICCS : Self Refresh Current RAS=CAS=VIL, W=OE=A0 ~ A11=VCC-0.2V or 0.2V, DQ0 ~ DQ7=VCC-0.2V, 0.2V or Open *Note : ICC1, ICC3, I CC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1, ICC3 and ICC6 address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one fast page mode cycle time, t PC. K4F170811D, K4F160811D K4F170812D, K4F160812D CMOS DRAM CAPACITANCE (TA=25°C, VCC=5V or 3.3V, f=1MHz) Parameter Symbol Min Max Units Input capacitance [A0 ~ A11] CIN1 - 5 pF Input capacitance [RAS, CAS, W, OE] CIN2 - 7 pF Output capacitance [DQ0 - DQ7] CDQ - 7 pF AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2) Test condition (5V device) : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V Test condition (3.3V device) : VCC=3.3V±0.3V, Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V Parameter -50 Symbol Min -60 Max Min Units Notes Max Random read or write cycle time tRC 90 110 ns Read-modify-write cycle time tRWC 133 155 ns Access time from RAS tRAC 50 60 ns 3,4,10 Access time from CAS tCAC 13 15 ns 3,4,5 Access time from column address tAA 25 30 ns 3,10 CAS to output in Low-Z tCLZ 0 ns 3 Output buffer turn-off delay tOFF 0 13 0 15 ns 6 Transition time (rise and fall) tT 3 50 3 50 ns 2 RAS precharge time tRP 30 RAS pulse width tRAS 50 RAS hold time tRSH 13 15 ns CAS hold time tCSH 50 60 ns CAS pulse width tCAS 13 10K 15 10K ns RAS to CAS delay time tRCD 20 37 20 45 ns 4 RAS to column address delay time tRAD 15 25 15 30 ns 10 CAS to RAS precharge time tCRP 5 5 ns Row address set-up time tASR 0 0 ns Row address hold time tRAH 10 10 ns Column address set-up time tASC 0 0 ns Column address hold time tCAH 10 10 ns Column address to RAS lead time tRAL 25 30 ns Read command set-up time tRCS 0 0 ns Read command hold time referenced to CAS tRCH 0 0 ns 8 Read command hold time referenced to RAS tRRH 0 0 ns 8 Write command hold time tWCH 10 10 ns Write command pulse width tWP 10 10 ns Write command to RAS lead time tRWL 13 15 ns Write command to CAS lead time tCWL 13 15 ns 0 40 10K 60 ns 10K ns K4F170811D, K4F160811D K4F170812D, K4F160812D CMOS DRAM AC CHARACTERISTICS (Continued) Parameter -50 Symbol Min Data set-up time tDS 0 Data hold time tDH 10 Refresh period (2K, Normal) Refresh period (4K, Normal) -60 Max Min Units Note ns 9 ns 9 Max 0 10 tREF 32 32 ms tREF 64 64 ms Refresh period (L-ver) tREF 128 128 ms Write command set-up time tWCS 0 0 ns 7 CAS to W delay time tCWD 36 40 ns 7 RAS to W delay time tRWD 73 85 ns 7 Column address to W delay time tAWD 48 55 ns 7 CAS precharge to W delay time tCPWD 53 60 ns CAS set-up time (CAS -before-RAS refresh) tCSR 5 5 ns CAS hold time (CAS -before-RAS refresh) tCHR 10 10 ns RAS to CAS precharge time tRPC 5 5 ns Access time from CAS precharge tCPA Fast Page cycle time Fast Page read-modify-write cycle time 30 35 ns tPC 35 40 ns tPRWC 76 85 ns CAS precharge time (Fast Page cycle) tCP 10 10 ns RAS pulse width (Fast Page cycle) tRASP 50 RAS hold time from CAS precharge tRHCP 30 OE access time tOEA 200K 60 200K 35 13 3 ns ns 15 15 ns OE to data delay tOED 13 Output buffer turn off delay time from OE tOEZ 0 OE command hold time tOEH 13 15 ns Write command set-up time (Test mode in) tWTS 10 10 ns 11 Write command hold time (Test mode in) 11 13 0 ns 15 ns 6 tWTH 10 10 ns W to RAS precharge time(C-B-R refresh) tWRP 10 10 ns W to RAS hold time(C-B-R refresh) tWRH 10 10 ns RAS pulse width (C-B-R self refresh) tRASS 100 100 us 13,14,15 RAS precharge time (C-B-R self refresh) tRPS 90 110 ns 13,14,15 CAS hold time (C-B-R self refresh) tCHS -50 -50 ns 13,14,15 K4F170811D, K4F160811D K4F170812D, K4F160812D CMOS DRAM TEST MODE CYCLE Parameter ( Note 11 ) -50 Symbol Min Random read or write cycle time tRC 95 Read-modify-write cycle time tRWC 138 Access time from RAS -60 Max Min Units Notes Max 115 ns 160 ns tRAC 55 65 ns 3,4,10,12 Access time from CAS tCAC 18 20 ns 3,4,5,12 Access time from column address tAA 30 35 ns 3,10,12 RAS pulse width tRAS 55 10K 65 10K ns CAS pulse width tCAS 18 10K 20 10K ns RAS hold time tRSH 18 20 ns CAS hold time tCSH 55 65 ns Column address to RAS lead time tRAL 30 35 ns CAS to W delay time tCWD 41 45 ns 7 RAS to W delay time tRWD 78 90 ns 7 Column address to W delay time tAWD 53 60 ns 7 CAS precharge to W delay time tCPWD 58 65 ns Fast Page cycle time tPC 40 45 ns Fast Page read-modify-write cycle time tPRWC 81 90 ns RAS pulse width (Fast Page cycle) tRASP 55 Access time from CAS precharge tCPA OE access time tOEA OE to data delay tOED 18 20 ns tOEH 18 20 ns OE command hold time 200K 65 200K ns 35 40 ns 18 20 ns 3 K4F170811D, K4F160811D K4F170812D, K4F160812D CMOS DRAM NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and V IL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCD≥tRCD(max). 6. tOFF(min)and tOEZ(max) define the time at which the output achieves the open circuit condition and are not referenced V oh or Vol. 7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS≥tWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD≥tCWD(min), tRWD≥tRWD(min) and tAWD≥tAWD(min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in read-modify-write cycles. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. 11. These specifications are applied in the test mode. 12. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 13. If tRASS≥100us, then RAS precharge time must use tRPS instead of tRP. 14. For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/2048(2K) cycles of burst refresh must be executed within 64ms/32ms before and after self refresh, in order to meet refresh specification. 15. For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification. K4F170811D, K4F160811D K4F170812D, K4F160812D CMOS DRAM READ CYCLE tRC tRAS RAS tRP VIH VIL - tCSH tCRP CAS tRCD tCRP tRSH tCAS VIH VIL - tRAD tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tRCH tRCS W tRRH VIH VIL - tOFF tAA OE VIH - tOEZ tOEA VIL - tCAC DQ0 ~ DQ3(7) VOH VOL - tRAC OPEN tCLZ DATA-OUT Don′t care Undefined K4F170811D, K4F160811D K4F170812D, K4F160812D CMOS DRAM WRITE CYCLE ( EARLY WRITE ) NOTE : D OUT = OPEN tRAS RAS tRC tRP VIH VIL - tCSH tCRP CAS tRCD tRSH tCAS VIH VIL - tRAD tASR A tCRP VIH VIL - tRAH tASC ROW ADDRESS tRAL tCAH COLUMN ADDRESS tCWL tRWL tWCS W OE tWCH VIH - tWP VIL - VIH VIL - DQ0 ~ DQ3(7) VIH VIL - tDS tDH DATA-IN Don′t care Undefined K4F170811D, K4F160811D K4F170812D, K4F160812D CMOS DRAM WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : D OUT = OPEN tRC tRAS RAS tRP VIH VIL - tCSH tCRP CAS tRSH tCAS VIH VIL - VIH VIL - tCRP tRAD tASR A tRCD tRAH tRAL tASC ROW ADDRESS tCAH COLUMN ADDRESS tCWL tRWL W OE VIH - tWP VIL - VIH VIL - DQ0 ~ DQ3(7) VIH VIL - tOED tOEH tDS tDH DATA-IN Don′t care Undefined K4F170811D, K4F160811D K4F170812D, K4F160812D CMOS DRAM READ - MODIFY - WRTIE CYCLE tRWC tRP tRAS RAS VIH VIL - tCRP CAS tRCD tRSH tCAS VIH VIL - tASR tRAD tRAH tASC tCAH tCSH A VIH VIL - ROW ADDR COLUMN ADDRESS tRWL tAWD tCWD W OE tCWL VIH - tWP VIL - tRWD tOEA VIH VIL - tCLZ tCAC DQ0 ~ DQ3(7) VI/OH VI/OL - tAA tOED tOEZ tRAC VALID DATA-OUT tDS tDH VALID DATA-IN Don′t care Undefined K4F170811D, K4F160811D K4F170812D, K4F160812D CMOS DRAM FAST PAGE READ CYCLE tRP tRASP RAS VIH - tRHCP VIL - ¡ó tCRP CAS tCP tRCD VIH - VIH VIL - OE tRSH tCAS ¡ó tCSH tRAH tCAH ROW ADDR tASC COLUMN ADDRESS tRCS W tCP tCAS tCAS tRAD tASC VIL - tASR A tPC tCAH COLUMN ADDRESS tRCH tRCS VIH - tASC ¡ó tCAH COLUMN ADDRESS ¡ó tRAL tRCS ¡ó tRRH tRCH VIL - tCAC tOEA tCAC tOEA VIH VIL - VOH VOL - ¡ó ¡ó tAA DQ0 ~ DQ3(7) tCAC tOEA tRAC tCLZ tOEZ VALID DATA-OUT tAA tOFF tCLZ tOEZ VALID DATA-OUT tAA tOFF tCLZ tOFF tOEZ VALID DATA-OUT Don′t care Undefined K4F170811D, K4F160811D K4F170812D, K4F160812D CMOS DRAM FAST PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : D OUT = OPEN tRP tRASP RAS tRHCP VIH VIL - ¡ó tPC tCRP CAS tRAD tASC VIL - tCAS tRAL tCSH tCAH tRAH ROW ADDR tASC COLUMN ADDRESS VIH - tWCH tCAH tASC ¡ó COLUMN ADDRESS tWCS tWP ¡ó tWCH tWP tCAH COLUMN ADDRESS tWCS ¡ó tWCH tWP VIL - tCWL OE tRSH ¡ó tWCS W tCP tCAS tCAS VIL - tASR A tCP tRCD VIH - VIH - tPC ¡ó VIH VIL - DQ0 ~ DQ3(7) VIH VIL - tCWL tRWL tCWL ¡ó tDS tDH VALID DATA-IN tDS tDH VALID DATA-IN tDS tDH ¡ó VALID DATA-IN ¡ó Don′t care Undefined K4F170811D, K4F160811D K4F170812D, K4F160812D CMOS DRAM FAST PAGE READ - MODIFY - WRITE CYCLE tRP tRASP RAS VIH - tCSH VIL - tRSH tRCD CAS tCP VIH - tCRP tCAS tCAS VIL - tRAD tPRWC tRAH tASR A VIH VIL - tCAH tASC COL. ADDR ROW ADDR COL. ADDR tRWL tRCS W tRAL tCAH tASC tCWL VIH - tCWL tWP VIL - tWP tCWD tCWD tAWD OE tAWD tCPWD tRWD tOEA VIH - tOEA VIL - tOED tCAC tCAC tAA DQ0 ~ DQ3(7) tRAC tOEZ tDH tOED tDH tAA tDS tDS tOEZ VI/OH VI/OL - tCLZ tCLZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN Don′t care Undefined K4F170811D, K4F160811D K4F170812D, K4F160812D CMOS DRAM RAS - ONLY REFRESH CYCLE NOTE : W, OE, DIN = Don ′t care DOUT = OPEN tRAS RAS tRC tRP VIH VIL - tRPC tCRP CAS VIH VIL - tASR A tCRP VIH VIL - tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE, A = Don′t care tRC tRP RAS tRAS tRP VIH VIL - tRPC tCP CAS tRPC tCSR VIH - tWRP W tCHR VIL - tWRH VIH VIL - DQ0 ~ DQ3(7) VOH - tOFF OPEN VOL Don′t care Undefined K4F170811D, K4F160811D K4F170812D, K4F160812D CMOS DRAM HIDDEN REFRESH CYCLE ( READ ) tRC tRC tRP tRAS RAS VIH VIL - tCRP CAS tRP tRAS tRCD tRSH tCHR VIH VIL - tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tWRH tRAL tRCS W VIH VIL - tAA OE VIH - tOEA VIL - tOFF tCAC DQ0 ~ DQ3(7) VOH VOL - tRAC OPEN tCLZ tOEZ DATA-OUT Don′t care Undefined K4F170811D, K4F160811D K4F170812D, K4F160812D CMOS DRAM HIDDEN REFRESH CYCLE ( WRITE ) NOTE : D OUT = OPEN tRC RAS VIH - tRP tRCD tRSH tCHR VIH VIL - tRAD tASR A tRAS VIL - tCRP CAS tRC tRP tRAS VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tRAL tWRH tWRP W OE VIH - tWCS tWCH tWP VIL - VIH VIL - tDS DQ0 ~ DQ3(7) VIH VIL - tDH DATA-IN Don′t care Undefined K4F170811D, K4F160811D K4F170812D, K4F160812D CMOS DRAM CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Don ′t care tRP RAS tRASS tRPS VIH VIL - tRPC tRPC tCP CAS tCHS VIH - tCSR VIL - DQ0 ~ DQ3(7) VOH - tOFF OPEN VOL - tWRP W tWRH VIH VIL - TEST MODE IN CYCLE NOTE : OE, A = Don′t care tRC tRP RAS tRAS tRP VIH VIL - tRPC tCP CAS tRPC VIH - tCSR tWTS W tCHR VIL - tWTH VIH VIL - DQ0 ~ DQ3(7) VOH VOL - tOFF OPEN Don′t care Undefined K4F170811D, K4F160811D K4F170812D, K4F160812D CMOS DRAM PACKAGE DIMENSION 28 SOJ 300mil Units : Inches (millimeters) 0.280 (7.11) 0.260 (6.61) 0.300 (7.62) 0.330 (8.39) 0.340 (8.63) #28 0.006 (0.15) 0.012 (0.30) #1 0.148 (3.76) MAX 0.027 (0.69) MIN 0.741 (18.82) MAX 0.720 (18.30) 0.730 (18.54) 0.0375 (0.95) 0.050 (1.27) 0.026 (0.66) 0.032 (0.81) 0.015 (0.38) 0.021 (0.53) 28 TSOP(II) 300mil 0.300 (7.62) 0.355 (9.02) 0.371 (9.42) Units : Inches (millimeters) 0.004 (0.10) 0.010 (0.25) 0.741 (18.81) MAX 0.721 (18.31) 0.729 (18.51) 0.037 (0.95) 0.050 (1.27) 0.047 (1.20) MAX 0.002 (0.05) MIN 0.012 (0.30) 0.020 (0.50) 0.010 (0.25) TYP 0.018 (0.45) 0.030 (0.75) 0~8 O