General Information DDR SDRAM DDR SDRAM Product Guide December 2007 Memory Division December 2007 General Information DDR SDRAM A. DDR SDRAM Component Ordering Information 1 2 3 4 5 6 7 8 9 10 11 K 4 H X X X X X X X - X X X X Speed SAMSUNG Memory DRAM Temperature & Power Product Package Type Density & Refresh Revision Organization Interface (VDD, VDDQ) Bank 1. SAMSUNG Memory : K 2. DRAM : 4 3. Product H : DDR SDRAM 8. Revision M : 1st Gen. A : 2nd Gen. B : 3rd Gen. C : 4th Gen. D : 5th Gen. E : 6th Gen. F : 7th Gen. G : 8th Gen. H : 9th Gen. J : 11st Gen. N : 14th Gen. 4. Density & Refresh 28 : 128Mb, 4K/64ms 56 : 256Mb, 8K/64ms 51 : 512Mb, 8K/64ms 1G: 1Gb, 8K/64ms 2G: 2Gb, 8K/64ms 5. Organization 04 : 06 : 07 : 08 : 16 : x4 x 4 Stack x 8 Stack x8 x16 6. Bank 3 : 4 Banks 7. Interface ( VDD, VDDQ) 8 : SSTL-2 (2.5V, 2.5V) 9. Package Type T : TSOP II N : sTSOP II G : FBGA L H F 6 : : : : U : TSOP II (Lead-free)*1 V : sTSOP II (Lead-free)*1 Z : FBGA (Lead-free)*1 TSOP II (Lead-free & Halogen-free)*1 FBGA (Lead-free & Halogen-free)*1 FBGA for 64Mb DDR (Lead-free & Halogen-free)*1 sTSOP II (Lead-free & Halogen-free)*1 Note 1: All of Lead-free or Halogen-free product are in compliance with RoHS 10. Temperature & Power C : Commercial Temp.( 0°C ~ 70°C) & Normal Power L : Commercial Temp.( 0°C ~ 70°C) & Low Power I : Industrial Temp.( -40°C ~ 85°C) & Normal Power P : Industrial Temp.( -40°C ~ 85°C) & Low Power 11. Speed CC B3 A2 B0 : : : : DDR400 DDR333 DDR266 DDR266 (200MHz @ CL=3, tRCD=3, tRP=3) (166MHz @ CL=2.5, tRCD=3, tRP=3)*1 (133MHz @ CL=2 , tRCD=3, tRP=3) (133MHz @ CL=2.5, tRCD=3, tRP=3) Note 1: "B3" has compatibility with "A2" and "B0" December 2007 General Information DDR SDRAM B. DDR SDRAM Component Product Guide Density 64Mb N-die Bank Part Number 4Banks K4H641638N K4H560438H 256Mb H-die 4Banks K4H560838H K4H561638H 256Mb J-die Speed*3 LCCC/CB3 LLCC/LB3 FCCC/CB3 FLCC/LB3 UCA2/CB0 ULA2/LB0 Power (V) SSTL_2 2.5 ± 0.2V Avail. 66pinTSOPII Now 60ball FBGA CS 60ball FBGA UCCC/CB3 ULCC/LB3 60ball FBGA 32M x 8 ZCCC/CB3 ZLCC/LB3 SSTL_2 8K/64m 2.5 ± 0.2V*4 Now 60ball FBGA UCCC/CB3 ULCC/LB3 66pinTSOPII 16M x 16 ZCCC/CB3 ZLCC/LB3 60ball FBGA 4Banks K4H560838J LCCC/CB3 LLCC/LB3 32M x 8 K4H561638J LCCC/CB3 LLCC/LB3 16M x 16 UCB0 ULB0 SSTL_2 8K/64m 2.5 ± 0.2V*4 66pinTSOPII CS 66pinTSOPII CS 66pinTSOPII CS 66pinTSOPII 128M x 4 ZCCC ZLCC 60ball FBGA UCCC/CB3 ULCC/LB3 66pinTSOPII 64M x 8 ZCCC/CB3 ZLCC/LB3 SSTL_2 8K/64m 2.5 ± 0.2V*4 Now 60ball FBGA UCCC/CB3 ULCC/LB3 66pinTSOPII 32M x 16 ZCCC/CB3 ZLCC/LB3 60ball FBGA Note 2 : TSOP II (Lead-free & Halogen-free) FBGA (Lead-free & Halogen-free) FBGA for 64Mb DDR (Lead-free & Halogen-free) sTSOP II (Lead-free & Halogen-free) 4K/64m Package 66pinTSOPII 64M x 4 4Banks K4H510838D Interface Refresh 64M x 4 ZCCC/CB3 ZLCC/LB3 Note 1 : U : TSOP II (Lead-free) V : sTSOP II (Lead-free) Z : FBGA (Lead-free) : : : : 4M x 16 LCB3/CB0 LLB3/LB0 K4H511638D L H F 6 Org. K4H560438J K4H510438D 512Mb D-die Package*1 & Power*2 & C Commercial Temperature, Normal Power L Commercial Temperature, Low Power - Commercial Temp. (0°C <Ta< 70°C) Note 3 : 133Mhz 166Mhz CL = 2 DDR266(A2) - 200Mhz - CL = 2.5 DDR266(B0) DDR333(B3) - CL = 3 - - DDR400(CC) - "B3" has compatibility with "A2" and "B0" Note 4 : VDD/VDDQ DDR400 DDR333/266 2.6V ± 0.1V 2.5V ± 0.2V December 2007 General Information DDR SDRAM C. Industrial temp DDR SDRAM Component Product Guide Density 256Mb H-die 256Mb J-die Bank Part Number 4Banks K4H561638J 4Banks K4H561638J K4H510838D 512Mb D-die 4Banks K4H511638D Package*1 & Power*2 & Speed*3 UICC/IB3/IB0 UPCC/PB3/PB0 : : : : Interface Refresh Power (V) 16M x 16 SSTL_2 8K/64m 2.5 ± 0.2V*4 Avail. Now 60ball FBGA LICC/IB3 LPCC/PB3 16M x 16 UIB3/IB0 UPB3/PB0 SSTL_2 8K/64m 2.5 ± 0.2V*4 66pinTSOPII CS 66pinTSOPII 64M x 8 ZIB3/IB0 ZPB3/PB0 60ball FBGA SSTL_2 UIB3/IB0 UPB3/PB0 8K/64m 2.5 ± 0.2V*4 Now 66pinTSOPII 32M x 16 ZIB3/IB0 ZPB3/PB0 60ball FBGA Note 2 : TSOP II (Lead-free & Halogen-free) FBGA (Lead-free & Halogen-free) FBGA for 64Mb DDR (Lead-free & Halogen-free) sTSOP II (Lead-free & Halogen-free) Package 66pinTSOPII ZIB3/IB0 ZPB3/PB0 Note 1 : U : TSOP II (Lead-free) V : sTSOP II (Lead-free) Z : FBGA (Lead-free) L H F 6 Org. I Industrial Temperature, Normal Power P Industrial Temperature, Low Power - Industrial Temp. (-40°C <Ta< 85°C) Note 3 : 133Mhz 166Mhz CL = 2 DDR266(A2) - 200Mhz - CL = 2.5 DDR266(B0) DDR333(B3) - CL = 3 - - DDR400(CC) - "B3" has compatibility with "A2" and "B0" Note 4 : VDD/VDDQ DDR400 DDR333/266 2.6V ± 0.1V 2.5V ± 0.2V December 2007 General Information DDR SDRAM D. DDR SDRAM Module Ordering Information 1 2 3 4 5 6 7 8 9 10 11 12 M X X X L X X X X X X X - X X X Memory Module Speed DIMM Configuration Power PCB revision & Type Data bits Package Feature Component Revision Depth Composition Component Refresh, # of Banks in Comp. & Interface 1. Memory Module : M 7. Composition Component 0 3 4 8 9 2. DIMM Configuration 3 : DIMM 4 : SODIMM 3. Data Bits 68 : 81 : 83 : 12 : 70 : 63 : x64 x72 x72 x72 x64 x64 184pin Unbuffered DIMM 184pin ECC unbuffered DIMM 184pin Registered DIMM 184pin Low Profile Registered DIMM 200pin Unbuffered SODIMM 172pin Micro DIMM 4. Feature L : DDR SDRAM (2.5V VDD) : : : : : x4 x8 x16 x 4 Stack x 8 Stack 8. Component Revision A : 2nd Gen. M : 1st Gen. C : 4th Gen. B : 3rd Gen. E : 6th Gen. D : 5th Gen. G : 8th Gen F : 7th Gen. J : 11th Gen. H : 9th Gen. 9. Package U : TSOP II*1 (Lead-Free) T : TSOP II (400mil) V : sTSOP II*1 (Lead-Free) N : sTSOP : Z : FBGA*1 (Lead-Free) G FBGA (Note 1 : All of Lead-free product are in compliance with RoHS) 10. PCB Revision & Type 5. Depth 16 : 16M 32 : 32M 64 : 64M 28 : 128M 56 : 256M 51 : 512M 17 33 65 29 57 : 16M (for 128Mb/512Mb) : 32M (for 128Mb/512Mb) : 64M (for 128Mb/512Mb) : 128M (for 128Mb/512Mb) : 256M (for 512Mb) 0 : Mother PCB 1 : 1st Rev. 2 : 2nd Rev. 3 : 3rd Rev. S : Reduced layer PCB 11. Temp & Power C : Commercial Temp.( 0°C ~ 70°C) & Normal Power L : Commercial Temp.( 0°C ~ 70°C) & Low Power 6. Refresh, # of Banks in comp. & Interface 1 : 2 : 4K/ 64ms Ref., 4Banks & SSTL-2 8K/ 64ms Ref., 4Banks & SSTL-2 12. Speed CC : B3 : A2 : B0 : DDR400 DDR333 DDR266 DDR266 (200MHz @ CL=3, tRCD=3, tRP=3) (166MHz @ CL=2.5, tRCD=3, tRP=3) (133MHz @ CL=2 , tRCD=3, tRP=3) (133MHz @ CL=2.5, tRCD=3, tRP=3) December 2007 General Information DDR SDRAM E. DDR SDRAM Module Product Guide Org. Density Part Number Speed Composition Comp. Version Voltage Internal Banks External Banks PKG*1 Feature Avail. SS,1250mil Now DS,1250mil Now 184Pin DDR Unbuffered DIMM 32Mx 64 64Mx 64 128Mx 64 M368L3223HUS CCC/CB3 32Mx 8 * 8pcs 256Mb H-die M368L3223JUS CCC/CB3 32Mx 8 * 8pcs 256Mb J-die 256MB 1 M368L6423HUN CCC/CB3 64Mx 8 * 16pcs 256Mb H-die 512MB M368L6423JUN CCC/CB3 64Mx 8 * 16pcs 256Mb J-die M368L6523DUS*2 CCC/CB3 64Mx 8 * 8pcs 512Mb D-die M368L2923DUN*2 CCC/CB3 64Mx 8 * 16pcs 512Mb D-die 1GB 2.5 ± 0.2V*3 4 1 66pin TSOP(II) SS,1250mil Now DS,1250mil Now 66pin TSOP(II) DS,1200mil Now 60ball FBGA SS,1125mil Now 1 66pin TSOP(II) DS,1200mill Now 2 60ball FBGA DS,1125mil Now 2 184Pin DDR Low Profile Registered DIMM 64Mx 72 512MB M312L6420HUS CB0 64Mx 4 * 18pcs 256Mb H-die M312L6420JUS CB0 64Mx 4 * 18pcs 256Mb J-die CCC/CB3 64Mx 8 * 9pcs 512Mb D-die M312L6523DZ3*2 M312L2920DUS*2 128Mx 72 CB0 128Mx 4 * 18pcs 512Mb 1 2.5 ± 0.2V*3 4 D-die 1GB M312L2923DZ3*2 CCC/CB3 64Mx 8 * 18pcs 512Mb D-die 200Pin DDR SODIMM 32Mx 64 64Mx 64 128Mx 64 M470L3224HU0 CB3 16Mx 16 * 8pcs 256Mb H-die M470L3224JU0 CB3 16Mx 16 * 8pcs 256Mb J-die 256MB 512MB 1GB M470L6524DU0*2 M470L2923DV0*2 CB3 CB3 32Mx 16 * 8pcs 64Mx 8 * 16pcs 512Mb 512Mb D-die 2.5 ± 0.2V*3 4 2 DS,1250mi 54pin sTSOP(II) D-die Note 1 : (All of DDR DIMMs can support Lead-free) U : TSOP II (Lead-Free) V : sTSOP II (Lead-Free) Z : FBGA (Lead-Free) Now 66pin TSOP(II) Now Now Note 3 : VDD/VDDQ DDR400 DDR333/266 2.6V ± 0.1V 2.5V ± 0.2V Note 2 : All of DDR components support both Leaded and Lead-free. And 256Mb H-die, Jdie and 512Mb D-die Lead-free is default PKG Type. December 2007 General Information DDR SDRAM F. Package Dimension #33 (0.50) #1 (1.50) (10.76) (0.50) (R NOTE 1. ( ) IS REFERENCE 2. [ ] IS ASS’Y OUT QUALITY 0.45 ~ 0.75 25 ) 0. 0.075 MAX (4°) [ (R 0.30 ± 0.08 25 ) (10°) 0. (0.71) 0.65TYP [0.65 ± 0.08] 0.05 MIN 0. 15 ) 0.10 MAX (R (10°) (10°) 1.20 MAX 1.00 ± 0.10 (10°) 5) (0.80) (1.50) 0.210 ± 0.05 0 .1 0.125 - 0.035 [ 0.665 ± 0.05 +0.075 22.22 ± 0.10 (R 11.76 ± 0.20 #34 10.16 ± 0.10 #66 (0.80) Unit : mm 0.25TYP (0° ∼ 8°) 66Pin TSOP(II) Package Dimension December 2007 General Information DDR SDRAM 60Ball FBGA (For 64Mb) Units : Millimeters #A1 0.10 Max 8.00 ± 0.10 8.0 0 ± 0.10 A #A1 MARK 0.80 x 8 = 6.40 0.80 9 8 1.60 7 6 5 4 B 3 2 1 (Datum A) A B (Datum B) C F 0.50 G H 12.00 ± 0.10 12.00 ± 0.10 E 1.00 x 11 = 11.00 D J 1.00 K L M 0.32 ± 0.05 1.10 ± 0.10 60 - ∅ 0.45 SOLDER BALL (Post Reflow 0.50 ± 0.05) ∅0.20 M A B TOP VIEW BOTTOM VIEW 60Ball FBGA (For 256Mb) Units : Millimeters 0.10 Max 8.0 0 ± 0.10 A #A1 MARK 0.80 9 8 1.60 7 6 5 4 B 3 2 1 (Datum A) A (Datum B) B C F 0.50 G H 14.00 ± 0.10 E 1.00 x 11 = 11.00 D 14.00 ± 0.10 J K 1.00 #A1 8.00 ± 0.10 0.80 x 8 = 6.40 L M 0.35 ± 0.05 1.10 ± 0.10 TOP VIEW 60 - ∅ 0.45 SOLDER BALL (Post Reflow 0.50 ± 0.05) ∅0.20 M A B ENCAPSULANT AREA BOTTOM VIEW December 2007 General Information DDR SDRAM 60Ball FBGA (For 512Mb) 10.00 ± 0.10 A 1.00MAX 10.00 ± 0.10 0.80 x8 = 6.40 #A1 MARK(option) 3.20 (Datum A) #A1 1.60 0.80 9 8 7 6 5 4 3 2 1 (Datum B) B A F 1.00 0.50 G H J K 12.00 ± 0.10 5.50 E 0.45 ± 0.05 12.00 ± 0.10 12.00 ± 0.10 D 1.00 x 11 = 11.00 B C L M 1.20 MAX (0.90) (0.90) (1.80) WINDOW MOLD AREA 4-CORNER MARK(option) 60-∅0.45 ± 0.05 Top view 0.20 M A B Bottom view December 2007 General Information DDR SDRAM For further information, [email protected] December 2007