SAMSUNG K4S560432E-NC

SDRAM 256Mb E-die (x4, x8
x8)
CMOS SDRAM
256Mb E-die SDRAM Specification
54pin sTSOP-II
Revision 1.1
February. 2004
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.1 February, 2004
SDRAM 256Mb E-die (x4, x8
x8)
CMOS SDRAM
Revision History
Revision 1.0 (August. 2003)
- First release.
Revision 1.1 (February. 2004)
- Deleted x16 for data book.
Rev. 1.1 February, 2004
CMOS SDRAM
SDRAM 256Mb E-die (x4, x8
x8)
16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks SDRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x4,x8)
• Auto & self refresh
• 64ms refresh period (8K Cycle)
GENERAL DESCRIPTION
The K4S560432E / K4S560832E is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 16,777,216 words by
4bits / 4 x 8,388,608 words by 8bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high
performance memory system applications.
Ordering Information
Part No.
Orgainization
Max Freq.
Interface
Package
K4S560432E-NC(L)75
64M x 4
133MHz
LVTTL
54pin sTSOP
K4S560832E-NC(L)75
32M x 8
133MHz
LVTTL
54pin sTSOP
Organization
Row Address
Column Address
64Mx4
A0~A12
A0-A9, A11
32Mx8
A0~A12
A0-A9
Row & Column address configuration
Rev. 1.1 February, 2004
CMOS SDRAM
SDRAM 256Mb E-die (x4, x8
x8)
Package Physical Dimension
54pin sTSOP(II)-300
(0.50)
Units : Millimeters
(2-R 0.15)
(2-R 0.30)
#28
(0.80)
#54
(8.22)
7.6
(1.00)
(1.00)
NOTE
1. (
) IS REFERENCE
2. [
] IS ASS’Y OUT QUALITY
0.20
(14°)
0.40~0.60
(R
5)
0.10 MAX
0.
( 14
25
°)
)
(0.80)
1.20MAX
(1.10)
+0.075
-0.035
0 .2
0.50TYP
0.50±0.05
[
0.07 MAX ]
0.125 +0.075
-0.035
0.25TYP
(R
0.
30
(2
-R
(0.50)
1.00±0.05
(14°)
5)
0.05 MIN
14.40MAX
(14.20)
14.00±0.10
)
0.210±0.05
0.665±0.05
0 .1
#27
(0.50)
(14°)
#1
(2R
9.22±0.20
(∅ 2.00 Dp0~0.05 BTM)
0×~8×
Rev. 1.1 February, 2004
CMOS SDRAM
SDRAM 256Mb E-die (x4, x8
x8)
FUNCTIONAL BLOCK DIAGRAM
I/O Control
Data Input Register
LWE
LDQM
Bank Select
16M x 4 / 8M x 8 / 4M x 16
16M x 4 / 8M x 8 / 4M x 16
Output Buffer
16M x 4 / 8M x 8 / 4M x 16
Sense AMP
Row Decoder
ADD
Row Buffer
Refresh Counter
DQi
Column Decoder
Col. Buffer
LCBR
LRAS
Address Register
CLK
16M x 4 / 8M x 8 / 4M x 16
Latency & Burst Length
LCKE
Programming Register
LRAS
LCBR
LCAS
LWE
LWCBR
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.1 February, 2004
CMOS SDRAM
SDRAM 256Mb E-die (x4, x8
x8)
PIN CONFIGURATION (Top view)
x8
x4
x4
x8
VDD
VDD
1
54
VSS
VSS
DQ0
NC
2
53
NC
DQ7
VDDQ
VDDQ
3
52
VSSQ
VSSQ
NC
NC
4
51
NC
NC
DQ1
DQ0
5
50
DQ3
DQ6
VSSQ
VSSQ
6
49
VDDQ
VDDQ
NC
NC
7
48
NC
NC
DQ2
NC
8
47
NC
DQ5
VDDQ
VDDQ
9
46
VSSQ
VSSQ
NC
NC
10
45
NC
NC
DQ3
DQ1
11
44
DQ2
DQ4
VSSQ
VSSQ
12
43
VDDQ
VDDQ
NC
NC
13
42
NC
NC
VDD
VDD
14
41
VSS
VSS
NC
NC
15
40
NC
NC
WE
WE
16
39
DQM
DQM
CAS
CAS
17
38
CLK
CLK
RAS
RAS
18
37
CKE
CKE
CS
CS
19
36
A12
A12
BA0
BA0
20
35
A11
A11
BA1
BA1
21
34
A9
A9
AP/A10
AP/A10
22
33
A8
A8
A0
A0
23
32
A7
A7
A1
A1
24
31
A6
A6
A2
A2
25
30
A5
A5
A3
A3
26
29
A4
A4
VDD
VDD
27
28
VSS
VSS
54 PIN sTSOP(II)
300mil x 551mil
(7.62mm x 14.00mm)
(0.5 mm pin pitch)
PIN FUNCTION DESCRIPTION
Pin
Name
Input Function
CLK
System clock
Active on the positive going edge to sample all inputs.
CS
Chip select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A0 ~ A12
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12,
Column address : (x4 : CA0 ~ CA9,CA11), (x8 : CA0 ~ CA9)
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column address strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM
Data input/output mask
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
DQ0 ~ N
Data input/output
Data inputs/outputs are multiplexed on the same pins.
(x4 : DQ0 ~ 3), (x8 : DQ0 ~ 7)
VDD/VSS
Power supply/ground
Power and ground for the input buffers and the core logic.
VDDQ/VSSQ
Data output power/ground
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
N.C/RFU
No connection
/reserved for future use
This pin is recommended to be left No Connection on the device.
Rev. 1.1 February, 2004
CMOS SDRAM
SDRAM 256Mb E-die (x4, x8
x8)
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
Voltage on any pin relative to Vss
Parameter
VIN, VOUT
-1.0 ~ 4.6
V
Voltage on VDD supply relative to Vss
VDD, VDDQ
-1.0 ~ 4.6
V
TSTG
-55 ~ +150
°C
Power dissipation
PD
1
W
Short circuit current
IOS
50
mA
Storage temperature
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Supply voltage
Symbol
Min
Typ
Max
Unit
VDD, VDDQ
3.0
3.3
3.6
V
Note
Input logic high voltage
VIH
2.0
3.0
VDD+0.3
V
1
Input logic low voltage
VIL
-0.3
0
0.8
V
2
Output logic high voltage
VOH
2.4
-
-
V
IOH = -2mA
Output logic low voltage
VOL
-
-
0.4
V
IOL = 2mA
ILI
-10
-
10
uA
3
Input leakage current
Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
Pin
Clock
RAS, CAS, WE, CS, CKE, DQM
Symbol
Min
Max
Unit
CCLK
2.5
3.5
pF
CIN
2.5
3.8
pF
Address
CADD
2.5
3.8
pF
(x4 : DQ0 ~ DQ3), (x8 : DQ0 ~ DQ7)
COUT
4.0
6.0
pF
Note
Rev. 1.1 February, 2004
CMOS SDRAM
SDRAM 256Mb E-die (x4, x8
x8)
DC CHARACTERISTICS (x4, x8)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Operating current
(One bank active)
Precharge standby current in
power-down mode
Precharge standby current in
non power-down mode
Active standby current in
power-down mode
Active standby current in
non power-down mode
(One bank active)
Symbol
ICC1
ICC2P
75
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
80
CKE ≤ VIL(max), tCC = 10ns
2
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞
ICC2N
ICC2NS
ICC3P
2
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
20
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
10
CKE ≤ VIL(max), tCC = 10ns
ICC3N
ICC3NS
Note
mA
1
mA
6
mA
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
25
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
25
mA
100
mA
1
ICC4
IO = 0 mA
Page burst
4banks Activated.
tCCD = 2CLKs
Refresh current
ICC5
tRC ≥ tRC(min)
ICC6
Unit
mA
6
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞
Operating current
(Burst mode)
Self refresh current
Version
Test Condition
CKE ≤ 0.2V
180
mA
2
C
3
mA
3
L
1.5
mA
4
Notes : 1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S5604(08)32E-NC75
4. K4S5604(08)32E-NL75
5. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
Rev. 1.1 February, 2004
CMOS SDRAM
SDRAM 256Mb E-die (x4, x8
x8)
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
Value
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Unit
2.4/0.4
V
1.4
V
tr/tf = 1/1
ns
1.4
V
See Fig. 2
3.3V
Vtt = 1.4V
50Ω
1200Ω
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
870Ω
Z0 = 50Ω
Output
50pF
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Version
75
Unit
Note
Row active to row active delay
tRRD(min)
15
ns
1
RAS to CAS delay
tRCD(min)
20
ns
1
Row precharge time
tRP(min)
20
ns
1
tRAS(min)
45
ns
1
Row active time
tRAS(max)
Row cycle time
tRC(min)
us
65
ns
1
2
Last data in to row precharge
tRDL(min)
2
CLK
Last data in to Active delay
tDAL(min)
2 CLK + tRP
-
Last data in to new col. address delay
tCDL(min)
1
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Col. address to col. address delay
tCCD(min)
1
CLK
3
ea
4
Number of valid output data
CAS latency=3
2
CAS latency=2
1
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Rev. 1.1 February, 2004
CMOS SDRAM
SDRAM 256Mb E-die (x4, x8
x8)
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
CAS latency=3
CLK cycle time
CAS latency=2
CAS latency=3
CLK to valid
output delay
CAS latency=2
CAS latency=3
Output data
hold time
75
Symbol
CAS latency=2
CLK high pulse width
Min
Max
7.5
tCC
1000
10
5.4
tSAC
6
3
tOH
3
Unit
Note
ns
1
ns
1,2
ns
2
tCH
2.5
ns
3
CLK low pulse width
tCL
2.5
ns
3
Input setup time
tSS
1.5
ns
3
Input hold time
tSH
0.8
ns
3
CLK to output in Low-Z
tSLZ
1
ns
2
CAS latency=3
CLK to output in Hi-Z
CAS latency=2
5.4
tSHZ
6
ns
Notes : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter
Symbol
Condition
Min
Output rise time
trh
Measure in linear
region : 1.2V ~ 1.8V
Output fall time
tfh
Output rise time
Output fall time
Typ
Max
Unit
Notes
1.37
4.37
Volts/ns
3
Measure in linear
region : 1.2V ~ 1.8V
1.30
3.8
Volts/ns
3
trh
Measure in linear
region : 1.2V ~ 1.8V
2.8
3.9
5.6
Volts/ns
1,2
tfh
Measure in linear
region : 1.2V ~ 1.8V
2.0
2.9
5.0
Volts/ns
1,2
Notes : 1. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to.
2. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to VSS.
Rev. 1.1 February, 2004
CMOS SDRAM
SDRAM 256Mb E-die (x4, x8
x8)
IBIS SPECIFICATION
66MHz and 100MHz/133MHz Pull-up
0
IOH Characteristics (Pull-up)
(V)
3.45
3.3
3.0
2.6
2.4
2.0
1.8
1.65
1.5
1.4
1.0
0.0
100MHz
133MHz
Min
I (mA)
0.0
-21.1
-34.1
-58.7
-67.3
-73.0
-77.9
-80.8
-88.6
-93.0
100MHz
133MHz
Max
I (mA)
-2.4
-27.3
-74.1
-129.2
-153.3
-197.0
-226.2
-248.0
-269.7
-284.3
-344.5
-502.4
66MHz
Min
1
1.5
2
2.5
3
3.5
-100
I (mA)
-200
-0.7
-7.5
-13.3
-27.5
-35.5
-41.1
-47.9
-52.4
-72.5
-93.0
mA
Voltage
0.5
0
-300
-400
-500
-600
Voltage
IOH Min (100MHz)
IOH Min (66MHz)
IOH Max (66 and 100MHz)
66MHz and 100MHz/133MHz Pull-down
IOL Characteristics (Pull-down)
(V)
0.0
0.4
0.65
0.85
1.0
1.4
1.5
1.65
1.8
1.95
3.0
3.45
100MHz
133MHz
Max
I (mA)
0.0
70.2
107.5
133.8
151.2
187.7
194.4
202.5
208.6
212.0
219.6
222.6
250
66MHz
Min
I (mA)
0.0
17.7
26.9
33.3
37.6
46.6
48.0
49.5
50.7
51.5
54.2
54.9
200
150
mA
Voltage
100MHz
133MHz
Min
I (mA)
0.0
27.5
41.8
51.6
58.0
70.7
72.9
75.4
77.0
77.6
80.3
81.4
100
50
0
0
0.5
1
1.5
2
2.5
3
3.5
Voltage
IOL Min (100MHz)
IOL Min (66MHz)
IOL Max (100MHz)
Rev. 1.1 February, 2004
CMOS SDRAM
SDRAM 256Mb E-die (x4, x8
x8)
Minimum VDD clamp current
(Referenced to VDD)
VDD Clamp @ CLK, CKE, CS, DQM & DQ
I (mA)
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.23
1.34
3.02
5.06
7.35
9.83
12.48
15.30
18.31
20
15
mA
VDD (V)
0.0
0.2
0.4
0.6
0.7
0.8
0.9
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
10
5
0
0
1
2
3
Voltage
I (mA)
Minimum VSS clamp current
VSS Clamp @ CLK, CKE, CS, DQM & DQ
I (mA)
-57.23
-45.77
-38.26
-31.22
-24.58
-18.37
-12.56
-7.57
-3.37
-1.75
-0.58
-0.05
0.0
0.0
0.0
0.0
-3
-2
-1
0
0
-10
-20
mA
VSS (V)
-2.6
-2.4
-2.2
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.9
-0.8
-0.7
-0.6
-0.4
-0.2
0.0
-30
-40
-50
-60
Voltage
I (mA)
Rev. 1.1 February, 2004
CMOS SDRAM
SDRAM 256Mb E-die (x4, x8
x8)
SIMPLIFIED TRUTH TABLE
Command
Register
CKEn-1
Mode register set
Auto refresh
Refresh
Entry
Self
refresh
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
Exit
H
H
CKEn
CS
RAS
CAS
WE
DQM
X
L
L
L
L
X
OP code
L
L
L
H
X
X
L
H
H
H
X
X
H
L
BA0,1
L
H
H
X
X
X
Bank active & row addr.
H
X
L
L
H
H
X
V
Read &
column address
Auto precharge disable
H
X
L
H
L
H
X
V
Write &
column address
Auto precharge disable
H
X
L
H
L
L
X
V
H
X
L
H
H
L
X
Auto precharge enable
Auto precharge enable
Burst stop
Precharge
Bank selection
H
X
Entry
H
L
Exit
L
H
Entry
H
L
Exit
L
H
All banks
Clock suspend or
active power down
Precharge power down mode
DQM
No operation command
L
L
H
L
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
V
V
V
L
H
H
X
X
H
X
X
X
L
H
H
H
X
X
A10/AP
A0 ~ A9
A11, A12
Note
1,2
3
3
3
3
Row address
L
Column
address
H
L
Column
address
H
X
V
L
X
H
4
4,5
4
4,5
6
X
X
X
X
X
X
V
X
X
X
7
Notes : 1. OP Code : Operand code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 1.1 February, 2004