K4S643233F-S(D)E/N/I/P CMOS SDRAM 2Mx32 Mobile SDRAM 90FBGA (VDD/VDDQ 3.0V/3.0V or 3.3V/3.3V) Revision 1.5 December 2002 Rev. 1.5 Dec. 2002 K4S643233F-S(D)E/N/I/P CMOS SDRAM 512K x 32Bit x 4 Banks SDRAM FEATURES GENERAL DESCRIPTION • • • • The K4S643233F is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabri- • • • • • • • 3.0V & 3.3 power supply. LVCMOS compatible with multiplexed address. Four banks operation. MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). All inputs are sampled at the positive going edge of the system clock . Burst read single-bit write operation. DQM for masking. Auto & self refresh. 64ms refresh period (4K cycle). Extended temperature operation (-25°C to 85 °C). Industrial temperature operation ( -40°C to 85°C). 90balls FBGA(-SXXX -Pb, -DXXX -Pb Free). cated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications. ORDERING INFORMATION Part No. Max Freq. K4S643233F-SE/N/I/P75 133MHz(CL=3) 105MHz(CL=2) Interface Package K4S643233FSE/N/I/P1H 105MHz(CL=2) K4S643233F-SE/N/I/P1L 105MHz(CL=3)*1 K4S643233F-DE/N/I/P75 133MHz(CL=3) 105MHz(CL=2) K4S643233F-DE/N/I/P1H 105MHz(CL=2) K4S643233F-DE/N/I/P1L 105MHz(CL=3)*1 90FBGA Pb LVCMOS 90FBGA Pb Free -S(D)E/N ; Normal/Low Power, Temp : -25 °C ~ 85 °C. -S(D)I/P ; Normal/Low Power, Temp : -40°C ~ 85 °C. Note : 1. In case of 40MHz Frequency, CL1 can be supported. FUNCTIONAL BLOCK DIAGRAM I/O Control Data Input Register LWE LDQM Bank Select 512K x 32 512K x 32 Output Buffer 512K x 32 Sense AMP Row Decoder ADD Row Buffer Refresh Counter DQi Column Decoder Col. Buffer LCBR LRAS Address Register CLK 512K x 32 Latency & Burst Length LCKE Programming Register LRAS LCBR LWE LCAS LWCBR LDQM Timing Register CLK CKE CS RAS CAS WE DQM *Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.5 Dec. 2002 K4S643233F-S(D)E/N/I/P CMOS SDRAM 90-Ball FBGA Package Dimension and Pin Configuration < Bottom View*1 > < Top View*2 > E1 9 8 7 6 5 4 3 2 90Ball(6x15) CSP 1 1 2 3 7 8 9 B A DQ26 DQ24 V SS VD D DQ23 DQ21 C B DQ28 V DDQ VSSQ V DDQ V SSQ DQ19 D C VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ e A D D1 E D VSSQ DQ29 DQ30 DQ17 DQ18 VDDQ F E V DDQ DQ31 NC NC DQ16 V SSQ G F V SS DQM3 A3 A2 DQM2 VD D G A4 A5 A6 A10 A0 A1 H A7 A8 NC NC BA1 NC H J K D/2 L M J CLK CKE A9 BA0 CS RAS K DQM1 NC NC CAS WE DQM0 L V DDQ DQ8 V SS VD D DQ7 V SSQ P M VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ R N VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ P DQ11 V DDQ VSSQ V DDQ V SSQ DQ4 R DQ13 DQ15 V SS VD D DQ0 DQ2 N E E/2 *2: Top View A A1 Substrate(4Layer) b *1: Bottom View < Top View*2 > #A1 Ball Origin Indicator z Pin Name Pin Function CLK System Clock CS Chip Select CKE Clock Enable A 0 ~ A10 Address BA0 ~ BA 1 Bank Select Address RAS Row Address Strobe CAS Column Address Strobe WE Write Enable DQM 0 ~ DQM 3 Data Input/Output Mask DQ 0 ~ 31 Data Input/Output SAMSUNG Week K4S643233F-XXXX V DD /VSS Power Supply/Ground V DDQ /VSSQ Data Output Power/Ground [Unit:mm] Symbol Min Typ Max A - 1.30 1.40 A1 0.30 0.35 0.40 E - 11.00 - E1 - 6.40 - D - 13.00 - D1 - 11.20 - e - 0.80 - b 0.40 0.45 0.50 z - - 0.10 Rev. 1.5 Dec. 2002 K4S643233F-S(D)E/N/I/P CMOS SDRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss V I N, VOUT -1.0 ~ 4.6 V Voltage on V D D supply relative to Vss VDD , V DDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 °C Power dissipation PD 1 W Short circuit current IOS 50 mA Storage temperature Notes : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 °C to 85 °C for Extended, -40°C to 85°C for Industrial) Parameter Symbol Min Typ Max Unit VD D 2.7 3.0 3.6 V V DDQ 2.7 3.0 3.6 V Input logic high voltage VI H 2.2 3.0 V DDQ +0.3 V 1 Input logic low voltage VIL -0.3 0 0.5 V 2 Output logic high voltage VO H 2.4 - - V I O H = -2mA Output logic low voltage V OL - - 0.4 V IOL = 2mA ILI -10 - 10 uA 3 Supply voltage Input leakage current Note Notes : 1. VIH (max) = 5.3V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ V IN ≤ VDDQ . Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. Dout is disabled, 0V ≤ V OUT ≤ V DDQ. CAPACITANCE (VDD = 3.0V & 3.3, TA = 23 °C, f = 1MHz, VREF =0.9V ± 50 mV) Pin Symbol Min Max Unit CCLK - 4.0 pF CIN - 4.0 pF Address(A0 ~ A10, BA 0 ~ BA 1 ) CADD - 4.0 pF D Q0 ~ DQ31 COUT - 6.0 pF Clock RAS, CAS, WE, CS, CKE, DQM0 ~ DQM3 Note Rev. 1.5 Dec. 2002 K4S643233F-S(D)E/N/I/P CMOS SDRAM DC CHARACTERISTICS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25°C to 85 °C for Extended, -40 °C to 85°C for Industrial) Parameter Symbol Operating Current (One Bank Active) Precharge Standby Current in power-down mode ICC1 I CC2P IC C 2N I CC2NS Active Standby Current in non power-down mode (One Bank Active) Burst length = 1 tRC ≥ tR C(min) IO = 0 mA -75 -1H -1L 80 75 75 CKE ≤ V IL (max), t CC = 10ns 0.5 ICC2 PS CKE & CLK ≤ V IL (max), tCC = ∞ Precharge Standby Current in non power-down mode Active Standby Current in power-down mode Version Test Condition I CC3P I CC3NS Note mA 1 mA 0.5 CKE ≥ V IH (min), CS ≥ V I H(min), tCC = 10ns Input signals are changed one time during 20ns 11 mA CKE ≥ V IH (min), CLK ≤ V IL (max), tCC = ∞ Input signals are stable 8 CKE ≤ V IL (max), t CC = 10ns 5 ICC3 PS CKE & CLK ≤ V IL (max), tCC = ∞ IC C 3N Unit mA 5 CKE ≥ V IH (min), CS ≥ V I H(min), tCC = 10ns Input signals are changed one time during 20ns 22 mA CKE ≥ V IH (min), CLK ≤ V IL (max), tCC = ∞ Input signals are stable 22 mA Operating Current ICC4 IO = 0 mA ,Page burst 95 75 75 mA 1 Refresh Current ICC5 tRC ≥ tRC (min) 135 120 120 mA 2 Self Refresh Current ICC6 CKE ≤ 0.2V -S(D)E/I 2 -S(D)N/P 0.4 mA 3 4 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S643233F-S(D)E/I** 4. K4S643233F-S(D)N/P** 5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL =V DDQ /V SSQ). Rev. 1.5 Dec. 2002 K4S643233F-S(D)E/N/I/P CMOS SDRAM AC OPERATING TEST CONDITIONS (V DD = 2.7V ~ 3.6V, TA = -25 °C to 85 °C for Extended, -40 °C to 85°C for Industrial) Parameter Value Unit 2.4 / 0.4 V 0.5 x VDDQ V tr/tf = 1/1 ns Output timing measurement reference level 0.5 x VDDQ V Output load condition See Fig. 2 AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time V DDQ Vtt = 0.5 x VDDQ 1200 Ω 50Ω V O H (DC) = 2.4V, IO H = -2mA V OL (DC) = 0.4V, I OL = 2mA Output 870Ω Output Z0 = 50Ω 30pF 30pF (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit OPERATING AC PARAMETER(AC operating conditions unless otherwise noted) Parameter Version Symbol - 75 -1H -1L Unit Note Row active to row active delay tRRD (min) 15 19 19 ns 1 RAS to CAS delay tRCD (min) 19 19 24 ns 1 tRP (min) 19 19 24 ns 1 tRAS (min) 45 50 60 ns 1 Row precharge time Row active time tRAS (max) Row cycle time t R C(min) Last data in to row precharge tR D L(min) Last data in to Active delay tDAL (min) Last data in to new col. address delay tC D L(min) Last data in to burst stop Col. address to col. address delay Number of valid output data 100 65 70 us ns 1 2 CLK 2,3 tRDL + tRP - 3 1 CLK 2 tBDL (min) 1 CLK 2 tCCD (min) 1 CLK 4 ea 5 CAS latency=3 2 CAS latency=2 1 CAS latency=1 - 84 0 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. Minimum tRDL=2CLK and tDAL(=tRDL + tRP) is required to complete both of last data wite command(tRDL) and precharge command(tRP). tRDL=1CLK can be supported only in the case under 100MHz with manual precharge mode. 4. All parts allow every cycle column address change. 5. In case of row precharge interrupt, auto precharge and read burst stop. Rev. 1.5 Dec. 2002 K4S643233F-S(D)E/N/I/P CMOS SDRAM AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter - 75 Symbol Min CAS latency=3 CLK cycle time CAS latency=2 tC C 9.5 tSAC CAS latency=1 CAS latency=3 Output data hold time CAS latency=2 tO H CAS latency=1 Min -1L Max 9.5 1000 - CAS latency=3 CAS latency=2 Max 7.5 CAS latency=1 CLK to valid output delay -1H 9.5 Min Unit Note ns 1 ns 1,2 ns 2 Max 9.5 1000 - 12 1000 25 5.4 7 7 7 7 8 - - 20 2.5 2.5 2.5 2.5 2.5 2.5 - - 2.5 CLK high pulse width tC H 2.5 3 3 ns 3 CLK low pulse width tC L 2.5 3 3 ns 3 Input setup time tSS 2.0 2.5 2.5 ns 3 Input hold time tSH 1.0 1.5 1.5 ns 3 CLK to output in Low-Z tSLZ 1 1 1 ns 2 CAS latency=3 CLK to output in Hi-Z CAS latency=2 tSHZ CAS latency=1 5.4 7 7 7 7 8 - - 20 ns Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Notes : 1. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use. Rev. 1.5 Dec. 2002 K4S643233F-S(D)E/N/I/P CMOS SDRAM SIMPLIFIED TRUTH TABLE (V=Valid, X=Don′t Care, H=Logic High, L=Logic Low) COMMAND Register Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit CKEn-1 CKEn CS RAS CAS WE DQM H X L L L L X OP CODE L L L H X X X X H H L L H H H H X X X X L L H H X V X L H L H X V L H Bank Active & Row Addr. H Read & Column Address Auto Precharge Disable H Write & Column Address Auto Precharge Disable Auto Precharge Enable Auto Precharge Enable Burst Stop Precharge Bank Selection X L H L L X H X L H H L X H X L L H L X Entry H L Exit L H Entry H L Precharge Power Down Mode Exit A10 /AP L DQM H No Operation Command H H H X X X L V V V X X X X H X X X L H H H H X X X L V V V X X H X X X L H H H X V A9 ~ A 0 Note 1, 2 3 3 3 3 Row Address L Column Address (A 0 ~ A7) H L H All Banks Clock Suspend or Active Power Down BA0,1 Column Address (A 0 ~ A7) H X V L X H 4 4, 5 4 4, 5 6 X X X X X X V X X X 7 Notes : 1. OP Code : Operand Code A 0 ~ A 10 & BA0 ~ BA 1 : Program keys. (@MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are the same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA 0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA 0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank B is selected. If BA 0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA 0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A 10 /AP is "High" at row precharge, BA0 and BA 1 are ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency is 0), but in read operation it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2). Rev. 1.5 Dec. 2002