TECHNICAL DATA KK4024B 7 Stage Ripple-Carry Binary Counter/Divider High-Voltage Silicon-Gate CMOS The KK4024B is ripple-carry binary counter. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state. Schmitt trigger action on the inputpulse line permits unlimited rise and fall times. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C • Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply ORDERING INFORMATION KK4024BN Plastic KK4024BD SOIC TA = -55° to 125° C for all packages LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE Inputs Clock PIN 14 =VCC PIN 7 = GND PIN 8,10,13 = NO CONNECTION X Output Reset Output state L No change L Advance to next state H All Outputs are low X=don’t care 1 KK4024B MAXIMUM RATINGS* Symbol Parameter Value Unit -0.5 to +20 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V VOUT IIN DC Input Current, per Pin ±10 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW PD Power Dissipation per Output Transistor 100 mW -65 to +150 °C 260 °C Tstg TL Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min Max Unit 3.0 18 V 0 VCC V -55 +125 °C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK4024B DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Guaranteed Limit V ≥-55°C 25°C ≤125 °C Unit VOUT=0.5V or VCC - 0.5V VOUT=1.0V or VCC - 1.0V VOUT=1.5V or VCC - 1.5V 5.0 10 15 3.5 7 11 3.5 7 11 3.5 7 11 V Maximum Low Level Input Voltage VOUT=0.5V or VCC - 0.5V VOUT=1.0V or VCC - 1.0V VOUT=1.5V or VCC - 1.5V 5.0 10 15 1.5 3 4 1.5 3 4 1.5 3 4 V VOH Minimum High-Level Output Voltage VIN=GND or VCC 5.0 10 15 4.95 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.95 V VOL Maximum Low-Level Output Voltage VIN=GND or VCC 5.0 10 15 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 V IIN Maximum Input Leakage Current VIN= GND or VCC 18 ±0.1 ±0.1 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) VIN= GND or VCC 5.0 10 15 20 5 10 20 100 5 10 20 100 150 300 600 3000 µA IOL Minimum Output Low (Sink) Current VIN= GND or VCC UOL=0.4 V UOL=0.5 V UOL=1.5 V 5.0 10 15 0.64 1.6 4.2 0.51 1.3 3.4 0.36 0.9 2.4 Minimum Output VIN= GND or VCC High (Source) Current UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V 5.0 5.0 10 15 -2.0 -0.64 -1.6 -4.2 -1.6 -0.51 -1.3 -3.4 -1.15 -0.36 -0.9 -2.4 Symbol Parameter VIH Minimum High-Level Input Voltage VIL IOH Test Conditions mA mA 3 KK4024B AC ELECTRICAL CHARACTERISTICS (CL=50pF, RL=200kΩ, Input tr=tf=20 ns) Guaranteed Limit VCC Symbol Parameter V ≥-55°C 25°C ≤125°C Unit tPLH, tPHL Maximum Propagation Delay, Clock to Q1 (Figure 1) 5.0 10 15 360 160 130 360 160 130 720 320 260 ns tPLH, tPHL Maximum Propagation Delay, Qn to Qn+1 (Figure 3) 5.0 10 15 330 80 60 330 80 60 660 160 120 ns tPHL Maximum Propagation Delay, Reset to Any Q (Figure 2) 5.0 10 15 280 120 100 280 120 100 560 240 200 ns tTLH, tTHL Maximum Output Transition Time (Figure 1) 5.0 10 15 200 100 80 200 100 80 400 200 160 ns fmax Maximum Clock Frequency(Figure 1) 5.0 10 15 3.5 8 12 3.5 8 12 1.75 4 6 MHz CIN Maximum Input Capacitance - 7.5 pF TIMING REQUIREMENTS (CL=50pF, RL=200kΩ, Input tr=tf=20 ns) Guaranteed Limit VCC Symbol Parameter V ≥-55°C 25°C ≤125°C Unit tw Minimum Pulse Width, Clock (Figure 1) 5.0 10 15 140 60 40 140 60 40 280 120 80 ns tw Minimum Pulse Width, Reset (Figure 2) 5.0 10 15 200 80 60 200 80 60 400 160 120 ns trem Minimum Removal Time, Reset(Figure 2) 5.0 10 15 350 150 100 350 150 100 700 300 200 ns tr, tf Maximum Input Rise and Fall Times, Clock (Figure 1) 5.0 10 15 µs Unlimited 4 KK4024B Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms 5 KK4024B TIMING DIAGRAM EXPANDED LOGIC DIAGRAM 6 KK4024B N SUFFIX PLASTIC DIP (MS - 001AA) A 8 14 B Dimensions, mm 7 1 F L -T- SEATING PLANE M K G H D MIN MAX A 18.67 19.69 B 6.10 7.11 C C N Symbol J 5.33 D 0.36 0.56 F 1.14 1.78 G 2.54 H 7.62 J 0° 10° K 2.92 3.81 L 7.62 8.26 M 0.20 0.36 N 0.38 0.25 (0.010) M T NOTES: 1. Dimensions “A”, “B” do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. D SUFFIX SOIC (MS - 012AB) A 14 Dimensions, mm 8 H B 1 G P 7 R x 45 C -TK D SEATING PLANE J F 0.25 (0.010) M T C M NOTES: 1.Dimensions A and B do not include mold flash or protrusion. 2.Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B - 0.25 mm (0.010) per side. M Symbol. MIN MAX A 8.55 8.75 B 3.80 4.00 C 1.35 1.75 D 0.33 0.51 F 0.40 1.27 G 1.27 H 5.72 J 0° 8° K 0.10 0.25 M 0.19 0.25 P 5.80 6.20 R 0.25 0.50 7