SAMSUNG KM6161002BI-8

CMOS SRAM
KM6161002B, KM6161002BI
Document Title
64Kx16 Bit High Speed Static RAM(5.0V Operating), Revolutionary Pin out.
Operated at Commercial and Industrial Temperature Range.
Revision History
Rev No.
History
Draft Data
Remark
Rev. 0.0
Initial release with Design Target.
Apr. 1st, 1997
Design Target
Rev. 1.0
Release to Preliminary Data Sheet.
1. Replace Design Target to Preliminary.
Jun. 1st, 1997
Preliminary
Rev. 2.0
Release to Final Data Sheet.
2.1. Delete Preliminary
2.2. Delete L-version.
2.3. Delete Data Retention Characteristics and Waveform.
2.4. Add Capacitive load of the test environment in A.C test load
2.5. Change D.C characteristics
Previous spec.
Changed spec.
Items
(8/10/12ns part)
(8/10/12ns part)
Icc
200/190/180mA
200/195/190mA
Isb
30mA
50mA
Feb. 25th, 1998
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of th is
device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 2.0
February 1998
CMOS SRAM
KM6161002B, KM6161002BI
64K x 16 Bit High-Speed CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
• Fast Access Time 8,10,12ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 50 mA(Max.)
(CMOS) : 10 mA(Max.)
Operating KM6161002B - 8 : 200 mA(Max.)
KM6161002B - 10 : 195 mA(Max.)
KM6161002B - 12 : 190 mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Data Byte Control : LB : I/O1~ I/O8, UB : I/O9~ I/O16
• Standard Pin Configuration
KM6161002BJ : 44-SOJ-400
KM6161002BT : 44-TSOP2-400F
The KM6161002B is a 1,048,576-bit high-speed Static Random
Access Memory organized as 65,536 words by 16 bits. The
KM6161002B uses 16 common input and output lines and has
at output enable pin which operates faster than address access
time at read cycle. Also it allows that lower and upper byte
access by data byte control ( UB, LB). The device is fabricated
using SAMSUNG′s advanced CMOS process and designed for
high-speed circuit technology. It is particularly well suited for
use in high-density high-speed system applications. The
KM6161002B is packaged in a 400mil 44-pin plastic SOJ or
TSOP2 forward.
PIN CONFIGURATION
ORDERING INFORMATION
KM6161002B -8/10/12
KM6161002BI -8/10/12
Commercial Temp.
Industrial Temp.
A0
1
44 A15
A1
2
43 A14
A2
3
42 A13
A3
4
41 OE
A4
5
40 UB
CS
6
39 LB
I/O1
7
38 I/O16
I/O2
8
37 I/O15
I/O3
9
I/O4 10
Vcc 11
Vss 12
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
Pre-Charge Circuit
A0
A2
A3
A4
A5
Row Select
A1
Memory Array
256 Rows
256x16 Columns
I/O9~I/O16
36 I/O14
SOJ/
TSOP2
35 I/O13
34 Vss
33 Vcc
I/O5 13
32 I/O12
I/O6 14
31 I/O11
I/O7 15
30 I/O10
I/O8 16
29 I/O9
WE 17
28 N.C.
A5 18
27 A12
A6 19
26 A11
A7 20
25 A10
A8 21
24 A9
N.C. 22
A6
A7
I/O1~I/O8
(Top View)
23 N.C.
PIN FUNCTION
Data
Cont.
I/O Circuit &
Column Select
Pin Name
A0 - A15
Data
Cont.
Gen.
CLK
A8 A9 A10 A11 A12 A13 A14 A15
WE
OE
WE
Write Enable
CS
Chip Select
OE
Output Enable
LB
Lower-byte Control(I/O 1~I/O8)
UB
Upper-byte Control(I/O 9~I/O16)
I/O1 ~ I/O 16
UB
LB
CS
-2-
Pin Function
Address Inputs
Data Inputs/Outputs
VCC
Power(+5.0V)
VSS
Ground
N.C
No Connection
Rev 2.0
February 1998
CMOS SRAM
KM6161002B, KM6161002BI
ABSOLUTE MAXIMUM RATINGS*
Parameter
Symbol
Voltage on Any Pin Relative to V SS
Unit
VIN, VOUT
-0.5 to 7.0
V
VCC
-0.5 to 7.0
V
Voltage on V CC Supply Relative to V SS
Power Dissipation
PD
1.0
W
TSTG
-65 to 150
°C
Commercial
TA
0 to 70
°C
Industrial
TA
-40 to 85
°C
Storage Temperature
Operating Temperature
Rating
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress r ating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this spec ification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (TA= to 70°C)
Symbol
Min
Typ
Max
Unit
Supply Voltage
Parameter
VCC
4.5
5.0
5.5
V
Ground
VSS
0
0
0
V
Input High Voltage
VIH
2.2
-
VCC+0.5**
V
Input Low Voltage
VIL
-0.5*
-
0.8
V
NOTE: The above parameters are also guaranteed at industrial temperature range.
* VIL(Min) = -2.0V a.c(Pulse Width≤6ns) for I≤20mA
** VIH(Max) = VCC + 2.0V a.c (Pulse Width≤6ns) for I≤20mA
DC AND OPERATING CHARACTERISTICS (TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)
Min
Max
Unit
Input Leakage Current
Parameter
Symbol
ILI
VIN=VSS to VCC
Test Conditions
-2
2
µA
Output Leakage Current
ILO
CS=VIH or OE=VIH or WE=VIL
VOUT=VSS to VCC
-2
2
µA
Operating Current
ICC
Min. Cycle, 100% Duty
CS=VIL, VIN = VIH or VIL, IOUT=0mA
8ns
-
200
mA
10ns
-
195
-
190
ISB
Min. Cycle, CS=VIH
12ns
-
50
mA
ISB1
f=0MHz, CS ≥VCC-0.2V,
VIN≥VCC-0.2V or V IN ≤0.2V
-
10
mA
Output Low Voltage Level
VOL
IOL=8mA
-
0.4
V
Output High Voltage Level
VOH
IOH=-4mA
2.4
-
V
-
3.95
V
Standby Current
VOH1*
IOH1=-0.1mA
NOTE: The above parameters are also guaranteed at industrial temperature range.
* VCC=5.0V, Temp.=25°C
CAPACITANCE* (TA=25°C , f=1.0MHz)
Item
Symbol
Test Conditions
MIN
Max
Unit
Input/Output Capacitance
CI/O
VI/O=0V
-
8
pF
Input Capacitance
CIN
VIN=0V
-
6
pF
* NOTE : Capacitance is sampled and not 100% tested.
-3-
Rev 2.0
February 1998
CMOS SRAM
KM6161002B, KM6161002BI
AC CHARACTERISTICS (TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS
Parameter
Value
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3ns
Input and Output timing Reference Levels
1.5V
Output Loads
See below
NOTE: The above test conditions are also applied at industrial temperature range.
Output Loads(B)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
Output Loads(A)
+5.0V
RL = 50Ω
DOUT
480Ω
VL = 1.5V
ZO = 50Ω
DOUT
30pF*
255Ω
5pF*
* Including Scope and Jig Capacitance
* Capacitive Load consists of all components of the
test environment.
READ CYCLE
Parameter
Symbol
KM6161002B-8
KM6161002B-10
KM6161002B-12
Unit
Min
Max
Min
Max
Min
Max
tRC
8
-
10
-
12
-
ns
Address Access Time
tAA
-
8
-
10
-
12
ns
Chip Select to Output
tCO
-
8
-
10
-
12
ns
Output Enable to Valid Output
tOE
-
4
-
5
-
6
ns
UB, LB Access Time
tBA
-
4
-
5
-
6
ns
Read Cycle Time
Chip Enable to Low-Z Output
tLZ
3
-
3
-
3
-
ns
Output Enable to Low-Z Output
tOLZ
0
-
0
-
0
-
ns
UB, LB Enable to Low-Z Output
tBLZ
0
-
0
-
0
-
ns
Chip Disable to High-Z Output
tHZ
0
4
0
5
0
6
ns
Output Disable to High-Z Output
tOHZ
0
4
0
5
0
6
ns
UB, LB Disable to High-Z Output
tBHZ
0
4
0
5
0
6
ns
Output Hold from Address Change
tOH
3
-
3
-
3
-
ns
NOTE: The above parameters are also guaranteed at industrial temperature range.
-4-
Rev 2.0
February 1998
CMOS SRAM
KM6161002B, KM6161002BI
WRITE CYCLE
Parameter
Symbol
KM6161002B-8
KM6161002B-10
KM6161002B-12
Min
Max
Min
Max
Min
Max
Unit
Write Cycle Time
tWC
8
-
10
-
12
-
ns
Chip Select to End of Write
tCW
6
-
7
-
8
-
ns
Address Set-up Time
tAS
0
-
0
-
0
-
ns
Address Valid to End of Write
tAW
6
-
7
-
8
-
ns
Write Pulse Width( OE High)
tWP
6
-
7
-
8
-
ns
Write Pulse Width( OE Low)
tWP1
8
-
10
-
12
-
ns
UB, LB Valid to End of Write
tBW
6
-
7
-
8
-
ns
Write Recovery Time
tWR
0
-
0
-
0
-
ns
Write to Output High-Z
tWHZ
0
4
0
5
0
6
ns
Data to Write Time Overlap
tDW
4
-
5
-
6
-
ns
Data Hold from Write Time
tDH
0
-
0
-
0
-
ns
End Write to Output Low-Z
tOW
3
-
3
-
3
-
ns
NOTE: The above parameters are also guaranteed at industrial temperature range.
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled, CS=OE=VIL, WE=VIH, UB, LB=VIL)
tRC
Address
tOH
Data Out
tAA
Valid Data
Previous Valid Data
-5-
Rev 2.0
February 1998
CMOS SRAM
KM6161002B, KM6161002BI
TIMING WAVEFORM OF READ CYCLE(2)
(WE=VIH)
tRC
Address
tAA
tCO
CS
tHZ(3,4,5)
tBHZ(3,4,5)
tBA
UB, LB
tBLZ(4,5)
tOHZ
tOE
OE
tOLZ
Data out
tOH
tLZ(4,5)
High-Z
Valid Data
NOTES(READCYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V OH or VOL
levels.
4. At any given temperature and voltage condition, t HZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e.
TIMING WAVEFORM OF WRITE CYCLE(1)
(OE Clock)
tWC
Address
tAW
tWR(5)
OE
tCW(3)
CS
tBW
UB, LB
tAS(4)
tWP(2)
WE
tDW
Data in
High-Z
Valid Data
tDH
High-Z
tOHZ(6)
Data out
-6-
Rev 2.0
February 1998
CMOS SRAM
KM6161002B, KM6161002BI
TIMING WAVEFORM OF WRITE CYCLE(2)
(OE =Low fixed)
tWC
Address
tAW
tWR(5)
tCW(3)
CS
tBW
UB, LB
tWP1(2)
tAS(4)
WE
tDW
High-Z
Data in
tDH
Valid Data
tWHZ(6)
tOW
(10)
(9)
High-Z
Data out
TIMING WAVEFORM OF WRITE CYCLE(3)
(CS=Controlled)
tWC
Address
tAW
tWR(5)
tCW(3)
CS
tBW
UB, LB
tWP(2)
tAS(4)
WE
tDW
Data in
High-Z
High-Z
Valid Data
tLZ
Data out
tDH
tWHZ(6)
High-Z(8)
High-Z
-7-
Rev 2.0
February 1998
CMOS SRAM
KM6161002B, KM6161002BI
TIMING WAVEFORM OF WRITE CYCLE(4)
(UB, LB Controlled)
tWC
Address
tAW
tCW(3)
tWR(5)
CS
tBW
UB, LB
tAS(4)
tWP(2)
WE
tDH
tDW
High-Z
Data in
Valid Data
tBLZ
tWHZ(6)
High-Z(8)
High-Z
Data out
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS, WE, LB and UB. A write begins at the latest transition CS going low and WE
going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write
to the end of write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. t WR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10.When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
FUNCTIONAL DESCRIPTION
CS
WE
OE
LB
UB
I/O Pin
Mode
Supply Current
I/O1~I/O8
I/O9~I/O16
H
X
X*
X
X
Not Select
High-Z
High-Z
ISB, ISB1
L
H
H
X
X
Output Disable
High-Z
High-Z
ICC
L
X
X
H
H
L
H
L
L
H
DOUT
High-Z
ICC
H
L
High-Z
DOUT
L
L
X
Read
L
L
L
H
H
L
High-Z
DIN
L
L
DIN
DIN
Write
DOUT
DOUT
DIN
High-Z
ICC
* NOTE : X means Don′t Care.
-8-
Rev 2.0
February 1998
CMOS SRAM
KM6161002B, KM6161002BI
PACKAGE DIMENSIONS
Units:millimeters/Inches
44-SOJ-400
#44
#23
9.40 ±0.25
0.370 ±0.010
10.16
0.400
11.18 ±0.12
0.440 ±0.005
0.20 +0.10
-0.05
0.008 +0.004
-0.002
#1
#22
28.98 MAX
1.141
0.69 MIN
0.027
25.58 ±0.12
1.125 ±0.005
1.19
)
0.047
3.76
1.27
MAX
( 0.050 ) 0.148
0.10
MAX
0.004
(
( 0.95 )
0.0375
0.43
0.017
+0.10
-0.05
+0.004
-0.002
+0.10
0.71 -0.05
0.028 +0.004
-0.002
1.27
0.050
44-TSOP2-400F
Units:millimeters/Inches
0~8°
( 0.25 )
0.010
#23
0.45 ~0.75
0.018 ~ 0.030
11.76 ±0.20
0.463 ±0.008
#1
10.16
0.400
#44
0
+ 0.1
0.05
0.15 - .00 4
+0
02
.006 - 0.0
#22
18.81
MAX.
0.741
18.41 ±0.10
0.725 ±0.004
0
1.00 ±0.10
0.039 ±0.004
( 0.805 )
0.032
0.35 ±0.10
0.014 ±0.004
( 0.50 )
0.020
0.80
0.0315
1.20
MAX.
0.047
0.10
0.004 MAX
0.05
MIN.
0.002
-9-
Rev 2.0
February 1998