STMicroelectronics L5980TR 0.7 a step-down switching regulator Datasheet

L5980
0.7 A step-down switching regulator
Features
■
0.7 A DC output current
■
2.9 V to 18 V input voltage
■
Output voltage adjustable from 0.6 V
■
250 kHz switching frequency, programmable
up to 1 MHz
■
Internal soft-start and inhibit
■
Low dropout operation: 100 % duty cycle
■
Voltage feed-forward
■
Zero load current operation
■
Over current and thermal protection
■
VFQFPN8 3 x 3 mm package
Applications
■
Consumer: STB, DVD, DVD recorder, car
audio, LCD TV and monitors
■
Industrial: Chargers, PLD, PLA, FPGA
■
Networking: XDSL, modems, DC-DC modules
■
Computer: Optical storage, hard disk drive,
printers, audio/graphic cards
■
LED driving
Figure 1.
VFQFPN8 3 x 3 mm
Description
The L5980 is step down switching regulator with
1 A (min.) current limited embedded power
MOSFET, so it is able to deliver in excess of 0.7 A
DC current to the load depending on the
application condition.
The input voltage can range from 2.9 V to 18 V,
while the output voltage can be set starting from
0.6 V to VIN. Having a minimum input voltage of
2.9 V, the device is suitable also for 3.3 V bus.
Requiring a minimum set of external components,
the device includes an internal 250 kHz switching
frequency oscillator that can be externally
adjusted up to 1 MHz.
The FVQFPN package with exposed pad allows
reducing the RthJA down to approximately
60 °C/W.
Application circuit
September 2008
Rev 3
1/37
www.st.com
37
Contents
L5980
Contents
1
2
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5
4.1
Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3
Error amplifier and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4
Over-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.5
Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.6
Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1
Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2
Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3
Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4
Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4.1
Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.4.2
Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.5
Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.6
Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.7
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2/37
Pin settings
L5980
1
Pin settings
1.1
Pin connection
Figure 2.
Pin connection (top view)
OUT
SYNCH
GND
INH
FSW
COMP
1.2
FB
Pin description
Table 1.
3/37
VCC
Pin description
N.
Type
1
OUT
Description
Regulator output
2
SYNCH
Master/slave synchronization. When it is left floating, a signal with a
phase shift of half a period respect to the power turn on is present at the
pin. When connected to an external signal at a frequency higher than the
internal one, then the device is synchronized by the external signal, with
zero phase shift.
Connecting together the SYNCH pin of two devices, the one with higher
frequency works as master and the other one as slave; so the two
powers turn on have a phase shift of half a period.
3
INH
A logical signal (active high) disable the device. With INH higher than
1.9 V the device is OFF and with INH lower than 0.6 V the device is ON.
4
COMP
5
FB
6
FSW
The switching frequency can be increased connecting an external
resistor from FSW pin and ground. If this pin is left floating the device
works at its free-running frequency of 250 kHz.
7
GND
Ground
8
VCC
Unregulated DC input voltage
Error amplifier output to be used for loop frequency compensation
Feedback input. Connecting the output voltage directly to this pin the
output voltage is regulated at 0.6 V. To have higher regulated voltages an
external resistor divider is required from Vout to FB pin.
Maximum ratings
L5980
2
Maximum ratings
2.1
Absolute maximum ratings
Table 2.
Absolute maximum ratings
Symbol
Parameter
Vcc
Input voltage
OUT
Output DC voltage
-0.3 to 4
Inhibit pin
-0.3 to VCC
FB
Feedback voltage
-0.3 to 1.5
Power dissipation at TA < 60 °C
V
1.5.
W
TJ
Junction temperature range
-40 to 150
°C
Tstg
Storage temperature range
-55 to 150
°C
Thermal data
Table 3.
Thermal data
Symbol
Parameter
Value
Unit
RthJA
Maximum thermal resistance
VFQFPN
junction-ambient (1)
60
°C/W
1. Package mounted on demonstration board.
4/37
-0.3 to VCC
INH
PTOT
Unit
20
FSW, COMP, SYNCH Analog pin
2.2
Value
Electrical characteristics
3
L5980
Electrical characteristics
TJ = 25 °C, VCC = 12 V, unless otherwise specified.
Table 4.
Electrical characteristics
Values
Symbol
Parameter
Test condition
Unit
Min
VCC
Operating input voltage
range
(1)
VCCON
Turn on VCC threshold
(1)
VCCOFF
Turn off VCC threshold
(1)
RDS(on)
MOSFET on resistance
ILIM
2.9
Max
18
2.9
V
2.4
140
170
140
220
1.0
1.3
1.6
225
250
275
mΩ
(1)
Maximum limiting current
Typ
A
Oscillator
FSW
Switching frequency
VFSW
FSW pin voltage
D
FADJ
(1)
275
1.254
Duty cycle
Adjustable switching
frequency
kHz
220
0
RFSW = 33 kΩ
V
100
1000
%
kHz
Dynamic characteristics
VFB
Feedback voltage
2.9 V < VCC < 18 V (1)
0.593
0.6
0.607
V
2.4
mA
30
μA
DC characteristics
IQ
IQST-BY
Quiescent current
Duty cycle = 0,
VFB = 0.8 V
Total stand-by quiescent
current
20
Inhibit
Device ON level
0.6
INH threshold voltage
V
Device OFF level
INH current
1.9
INH = 0
7.5
10
8.2
9.1
μA
Soft-start
FSW pin floating
TSS
5/37
Soft-start duration
FSW = 1 MHz,
RFSW = 33 kΩ
7.4
ms
2
Electrical characteristics
Table 4.
L5980
Electrical characteristics (continued)
Values
Symbol
Parameter
Test condition
Unit
Min
Typ
Max
Error amplifier
VCH
High level output voltage
VFB < 0.6 V
VCL
Low level output voltage
VFB > 0.6 V
IFB
Bias source current
VFB = 0 V to 0.8 V
1
μA
VFB = 0.5 V, VCOMP = 1 V
17
mA
Sink COMP pin
VFB = 0.7 V, VCOMP = 1 V
25
mA
Open loop voltage gain
(2)
100
dB
IO SOURCE Source COMP pin
IO SINK
GV
3
V
0.1
Synchronization function
High input voltage
2
3.3
V
Low input voltage
1
Slave sink current
VSYNCH = 2.9 V
0.7
Master output amplitude
ISOURCE = 200 μA
3.0
Output pulse width
SYNCH floating
110
0.9
mA
V
ns
Input pulse width
70
Protection
IFBDISC
TSHDN
FB disconnection source
current
1
Thermal shutdown
150
Hysteresis
30
μA
°C
1. Specification referred to TJ from -40 to +125 °C. Specification in the -40 to +125 °C temperature range are
assured by design, characterization and statistical correlation.
2. Guaranteed by design.
6/37
Functional description
4
L5980
Functional description
The L5980 is based on a “voltage mode”, constant frequency control. The output voltage
VOUT is sensed by the feedback pin (FB) compared to an internal reference (0.6 V) providing
an error signal that, compared to a fixed frequency sawtooth, controls the on and off time of
the power switch.
The main internal blocks are shown in the block diagram in Figure 3. They are:
z
A fully integrated oscillator that provides sawtooth to modulate the duty cycle and the
synchronization signal. Its switching frequency can be adjusted by and external
resistor. The voltage and frequency feed forward are implemented.
z
The soft-start circuitry to limit inrush current during the start up phase.
z
The voltage mode error amplifier
z
The pulse width modulator and the relative logic circuitry necessary to drive the internal
power switch.
z
The high-side driver for embedded p-channel power MOSFET switch.
z
The peak current limit sensing block, to handle over load and short circuit conditions.
z
A voltage regulator and internal reference. It supplies internal circuitry and provides a
fixed internal reference.
z
A voltage monitor circuitry (UVLO) that checks the input and internal voltages.
z
A thermal shutdown block, to prevent thermal run away.
Figure 3.
7/37
Block diagram
Functional description
4.1
L5980
Oscillator and synchronization
Figure 4 shows the block diagram of the oscillator circuit. The internal oscillator provides a
constant frequency clock. Its frequency depends on the resistor externally connect to FSW
pin. In case the FSW pin is left floating the frequency is 250 kHz; it can be increased as
shown in Figure 6 by external resistor connected to ground.
To improve the line transient performance keeping the PWM gain constant versus the input
voltage, the voltage feed forward is implemented by changing the slope of the sawtooth
according to the input voltage change (see Figure 5.a).
The slope of the sawtooth also changes if the oscillator frequency is increased by the
external resistor. In this way a frequency feed forward is implemented (Figure 5.b) in order to
keep the PWM gain constant versus the switching frequency (see Section 5.4 for PWM gain
expression).
On the SYNCH pin the synchronization signal is generated. This signal has a phase shift of
180° with respect to the clock. This delay is useful when two devices are synchronized
connecting the SYNCH pin together. When SYNCH pins are connected, the device with
higher oscillator frequency works as Master, so the Slave device switches at the frequency
of the Master but with a delay of half a period. This minimizes the RMS current flowing
through the input capacitor [see L5988D data sheet].
Figure 4.
Oscillator circuit block diagram
Clock
FSW
Clock
Generator
Synchronization
SYNCH
Ramp
Generator
Sawtooth
The device can be synchronized to work at higher frequency feeding an external clock
signal. The synchronization changes the sawtooth amplitude, changing the PWM gain
(Figure 5.c). This changing has to be taken into account when the loop stability is studied.
To minimize the change of the PWM gain, the free running frequency should be set (with a
resistor on FSW pin) only slightly lower than the external clock frequency. This pre-adjusting
of the frequency will change the sawtooth slope in order to get negligible the truncation of
sawtooth, due to the external synchronization.
8/37
Functional description
9/37
L5980
Figure 5.
Sawtooth: voltage and frequency feed forward; external synchronization
Figure 6.
Oscillator frequency versus FSW pin resistor
Functional description
4.2
L5980
Soft-start
The soft-start is essential to assure correct and safe start up of the step-down converter. It
avoids inrush current surge and makes the output voltage increases monothonically.
The soft-start is performed by a staircase ramp on the non-inverting input (VREF) of the error
amplifier. So the output voltage slew rate is:
Equation 1
SR OUT = SR VREF ⋅ ⎛ 1 + R1
--------⎞
⎝
R2⎠
where SRVREF is the slew rate of the non-inverting input while R1 and R2 the resistor divider
to regulate the output voltage (see Figure 7). The soft-start stair case consists of 64 steps of
9.5 mV each one, from 0 V to 0.6 V. The time base of one step is of 32 clock cycles. So the
soft-start time and then the output voltage slew rate depend on the switching frequency.
Figure 7.
Soft-start scheme
Soft-start time results:
Equation 2
32 ⋅ 64
SS TIME = ----------------Fsw
For example with a switching frequency of 250 kHz the SSTIME is 8 ms.
10/37
Functional description
4.3
L5980
Error amplifier and compensation
The error amplifier (E/A) provides the error signal to be compared with the sawtooth to
perform the pulse width modulation. Its non-inverting input is internally connected to a 0.6 V
voltage reference, while its inverting input (FB) and output (COMP) are externally available
for feedback and frequency compensation. In this device the error amplifier is a voltage
mode operational amplifier so with high DC gain and low output impedance.
The uncompensated error amplifier characteristics are the following:
Table 5.
Uncompensated error amplifier characteristics
Error amplifier
Value
Low frequency gain
100 dB
GBWP
4.5 MHz
Slew rate
7 V/μs
Output voltage swing
0 to 3.3 V
Maximum source/sink current
25 mA/40 mA
In continuos conduction mode (CCM), the transfer function of the power section has two
poles due to the LC filter and one zero due to the ESR of the output capacitor. Different
kinds of compensation networks can be used depending on the ESR value of the output
capacitor. In case the zero introduced by the output capacitor helps to compensate the
double pole of the LC filter a type II compensation network can be used. Otherwise, a type
III compensation network has to be used (see Chapter 5.4 for details about the
compensation network selection).
Anyway the methodology to compensate the loop is to introduce zeros to obtain a safe
phase margin.
11/37
Functional description
4.4
L5980
Over-current protection
The L5980 implements the over current protection sensing current flowing through the
power MOSFET. Due to the noise created by the switching activity of the power MOSFET,
the current sensing is disabled during the initial phase of the conduction time. This avoids an
erroneous detection of a fault condition. This interval is generally known as “masking time”
or “blanking time”. The masking time is about 200 ns.
When the over current is detected, two different behaviors are possible depending on the
operating condition.
1.
Output voltage in regulation. When the over current is sensed, the power MOSFET is
switched off and the internal reference (VREF), that biases the non-inverting input of the
error amplifier, is set to zero and kept in this condition for a soft-start time (TSS, 2048
clock cycles). After this time, a new soft-start phase takes place and the internal
reference begins ramping (see Figure 8.a).
2.
Soft-start phase. If the over current limit is reached the power MOSFET is turned off
implementing the pulse by pulse over current protection. During the soft-start phase,
under over current condition, the device can skip pulses in order to keep the output
current constant and equal to the current limit. If at the end of the "masking time" the
current is higher than the over current threshold, the power MOSFET is turned off and it
will skip one pulse. If, at the next switching on at the end of the "masking time" the
current is still higher than the threshold, the device will skip two pulses. This
mechanism is repeated and the device can skip up to seven pulses. While, if at the end
of the "masking time" the current is lower than the over current threshold, the number of
skipped cycles is decreased of one unit. At the end of soft-start phase the output
voltage is in regulation and if the over current persists the behavior explained above
takes place. (see Figure 8.b)
So the over current protection can be summarized as an “hiccup” intervention when the
output is in regulation and a constant current during the soft-start phase. If the output is
shorted to ground when the output voltage is on regulation, the over current is triggered and
the device starts cycling with a period of 2048 clock cycles between “hiccup” (power
MOSFET off and no current to the load) and “constant current” with very short on-time and
with reduced switching frequency (up to one eighth of normal switching frequency). See
Figure 30. for short circuit behavior.
12/37
Functional description
Figure 8.
4.5
L5980
Over current protection strategy
Inhibit function
The inhibit feature allows to put in stand-by mode the device.With INH pin higher than 1.9 V
the device is disabled and the power consumption is reduced to less than 30 μA. With INH
pin lower than 0.6 V, the device is enabled. If the INH pin is left floating, an internal pull up
ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled.
The pin is also VCC compatible.
4.6
Hysteretic thermal shutdown
The thermal shutdown block generates a signal that turns off the power stage if the junction
temperature goes above 150 °C. Once the junction temperature goes back to about 130 °C,
the device restarts in normal operation. The sensing element is very close to the PDMOS
area, so ensuring an accurate and fast temperature detection.
13/37
Application information
L5980
5
Application information
5.1
Input capacitor selection
The capacitor connected to the input has to be capable to support the maximum input
operating voltage and the maximum RMS input current required by the device. The input
capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR,
affecting the overall system efficiency.
So the input capacitor must have a RMS current rating higher than the maximum RMS input
current and an ESR value compliant with the expected efficiency.
The maximum RMS input current flowing through the capacitor can be calculated as:
Equation 3
2
2
⋅ D- D
-------------I RMS = I O ⋅ D – 2
+ ------2
η
η
Where Io is the maximum DC output current, D is the duty cycle, η is the efficiency.
Considering η = 1, this function has a maximum at D = 0.5 and it is equal to Io/2.
In a specific application the range of possible duty cycles has to be considered in order to
find out the maximum RMS input current. The maximum and minimum duty cycles can be
calculated as:
Equation 4
V OUT + V F
D MAX = -----------------------------------V INMIN – V SW
and
Equation 5
V OUT + V F
D MIN = ------------------------------------V INMAX – V SW
Where VF is the forward voltage on the freewheeling diode and VSW is voltage drop across
the internal PDMOS. In Table 6. some multi layer ceramic capacitors suitable for this device
are reported
Table 6.
Input MLCC capacitors
Manufacture
Series
Cap value (μF)
Rated voltage (V)
GRM31
10
25
GRM55
10
25
C3225
10
25
MURATA
TDK
14/37
Application information
5.2
L5980
Inductor selection
The inductance value fixes the current ripple flowing through the output capacitor. So the
minimum inductance value in order to have the expected current ripple has to be selected.
The rule to fix the current ripple value is to have a ripple at 20 %-40 % of the output current.
The inductance value can be calculated by the following equation:
Equation 6
V IN – V OUT
V OUT + V F
ΔI L = ------------------------------ ⋅ T ON = ---------------------------- ⋅ T OFF
L
L
Where TON is the conduction time of the internal high side switch and TOFF is the conduction
time of the external diode (in CCM, FSW = 1 / (TON + TOFF)).The maximum current ripple, at
fixed Vout, is obtained at maximum TOFF that is at minimum duty cycle (see previous section
to calculate minimum duty). So fixing ΔIL = 20 % to 40 % of the maximum output current, the
minimum inductance value can be calculated:
Equation 7
V OUT + V F 1 – D MIN
L MIN = ---------------------------- ⋅ ----------------------ΔI MAX
F SW
where FSW is the switching frequency, 1/(TON + TOFF).
For example for VOUT = 3.3 V, VIN = 12 V, IO = 0.7 A and FSW = 250 kHz the minimum
inductance value to have ΔIL = 30 % of IO is about 45 μH.
The peak current through the inductor is given by:
Equation 8
ΔI
I L, PK = I O + -------L2
So if the inductor value decreases, the peak current (that has to be lower than the current
limit of the device) increases. The higher is the inductor value, the higher is the average
output current that can be delivered, without reaching the current limit.
In the table below some inductor part numbers are listed.
Table 7.
Inductors
Manufacturer
Series
Inductor value (μH)
Saturation current (A)
Wurth
PD3 L
33 to 68
1.35 to 1.8
MSS1038
39 to 68
1.62 to 2.04
LPS6235
12 to 33
1.4 to 2.2
DRQ73
10 to 22
1.67 to 2.47
LD2
27 to 47
1.64 to 2.1
CDR6D28MN
10 to 22
1.65 to 2.5
CDRH105RNP
27 to 56
1.9 to 2.7
Coilcraft
Coiltronics
SUMIDA
15/37
Application information
5.3
L5980
Output capacitor selection
The current in the capacitor has a triangular waveform which generates a voltage ripple
across it. This ripple is due to the capacitive component (charge and discharge of the output
capacitor) and the resistive component (due to the voltage drop across its ESR). So the
output capacitor has to be selected in order to have a voltage ripple compliant with the
application requirements.
The amount of the voltage ripple can be calculated starting from the current ripple obtained
by the inductor selection.
Equation 9
ΔI MAX
ΔV OUT = ESR ⋅ ΔI MAX + -----------------------------------8 ⋅ C OUT ⋅ f SW
Usually the resistive component of the ripple is much higher than the capacitive one, if the
output capacitor adopted is not a multi layer ceramic capacitor (MLCC) with very low ESR
value.
The output capacitor is important also for loop stability: it fixes the double LC filter pole and
the zero due to its ESR. In Chapter 5.4, it will be illustrated how to consider its effect in the
system stability.
For example with VOUT = 3.3 V, VIN = 12 V, ΔIL = 0.21 A (resulting by the inductor value), in
order to have a ΔVOUT = 0.01·VOUT, if the multi layer capacitor are adopted, 10 μF are
needed and the ESR effect on the output voltage ripple can be neglected. In case of not
negligible ESR (electrolytic or tantalum capacitors), the capacitor is chosen taking into
account its ESR value. So in case of 100 μF with ESR = 40 mΩ, the resistive component of
the drop dominates and the voltage ripple is 8.4 mV
The output capacitor is also important to sustain the output voltage when a load transient
with high slew rate is required by the load. When the load transient slew rate exceeds the
system bandwidth the output capacitor provides the current to the load. So if the high slew
rate load transient is required by the application the output capacitor and system bandwidth
have to be chosen in order to sustain the load transient.
In the table below some capacitor series are listed.
Table 8.
Output capacitors
Manufacturer
Series
Cap value (μF)
Rated voltage (V)
ESR (mΩ)
GRM32
22 to 100
6.3 to 25
<5
GRM31
10 to 47
6.3 to 25
<5
ECJ
10 to 22
6.3
<5
EEFCD
10 to 68
6.3
15 to 55
SANYO
TPA/B/C
100 to 470
4 to 16
40 to 80
TDK
C3225
22 to 100
6.3
<5
MURATA
PANASONIC
16/37
Application information
5.4
L5980
Compensation network
The compensation network has to assure stability and good dynamic performance. The loop
of the L5980 is based on the voltage mode control. The error amplifier is a voltage
operational amplifier with high bandwidth. So selecting the compensation network the E/A
will be considered as ideal, that is, its bandwidth is much larger than the system one.
The transfer functions of PWM modulator and the output LC filter are studied (see). The
transfer function of the PWM modulator, from the error amplifier output (COMP pin) to the
OUT pin, results:
Equation 10
V IN
G PW0 = -------Vs
where VS is the sawtooth amplitude. As seen in Chapter 4.1, the voltage feed forward
generates a sawtooth amplitude directly proportional to the input voltage, that is:
Equation 11
V S = K ⋅ V IN
In this way the PWM modulator gain results constant and equals to:
Equation 12
V IN
1- = 9
- = --G PW0 = -------Vs
K
The synchronization of the device with an external clock provided trough SYNCH pin can
modifies the PWM modulator gain (see Chapter 4.1 to understand how this gain changes
and how to keep it constant in spite of the external synchronization).
Figure 9.
The error amplifier, the PWM modulator and the LC output filter
VCC
VS
VREF
FB
PWM
E/A
OUT
COMP
L
ESR
GPW0
The transfer function on the LC filter is given by:
17/37
GLC
COUT
Application information
L5980
Equation 13
s
1 + ------------------------2π ⋅ f zESR
G LC ( s ) = ------------------------------------------------------------------------2
s
s
1 + ---------------------------+ ⎛⎝ -------------------⎞⎠
2π ⋅ f LC
2π ⋅ Q ⋅ f LC
where:
Equation 14
1
f LC = -----------------------------------------------------------------------,
ESR
2π ⋅ L ⋅ C OUT ⋅ 1 + --------------R OUT
1
f zESR = ------------------------------------------2π ⋅ ESR ⋅ C OUT
Equation 15
R OUT ⋅ L ⋅ C OUT ⋅ ( R OUT + ESR )
Q = ------------------------------------------------------------------------------------------ ,
L + C OUT ⋅ R OUT ⋅ E SR
V OUT
R OUT = -------------I OUT
As seen in Chapter 4.3 two different kind of network can compensate the loop. In the two
following paragraph the guidelines to select the type II and type III compensation network
are illustrated.
5.4.1
Type III compensation network
The methodology to stabilize the loop consists of placing two zeros to compensate the effect
of the LC double pole, so increasing phase margin; then to place one pole in the origin to
minimize the dc error on regulated output voltage; finally to place other poles far away the
zero dB frequency.
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a
frequency higher than the desired bandwidth (that is: 2π * ESR * COUT < 1/BW), the type III
compensation network is needed. Multi layer ceramic capacitors (MLCC) have very low ESR
(< 1 mΩ), with very high frequency zero, so type III network is adopted to compensate the
loop.
In Figure 10 the type III compensation network is shown. This network introduces two zeros
(fZ1, fZ2) and three poles (fP0, fP1, fP2). They expression are:
Equation 16
1
-,
f Z1 = ----------------------------------------------2π ⋅ C 3 ⋅ ( R 1 + R 3 )
18/37
1
f Z2 = ----------------------------2π ⋅ R 4 ⋅ C 4
Application information
L5980
Equation 17
f P0 = 0,
1
-,
f P1 = ----------------------------2π ⋅ R 3 ⋅ C 3
1
f P2 = ------------------------------------------C4 ⋅ C5
------------------2π ⋅ R 4 ⋅
C4 + C5
Figure 10. Type III compensation network
In Figure 11 the Bode diagram of the PWM and LC filter transfer function (GPW0 · GLC(f))
and the open loop gain (GLOOP(f) = GPW0 · GLC(f) · GTYPEIII(f)) are drawn.
Figure 11. Open loop gain: module bode diagram
The guidelines for positioning the poles and the zeroes and for calculating the component
values can be summarized as follow:
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1.
Choose a value for R1, usually between 1 kΩ and 5 kΩ.
2.
Choose a gain (R4/R1) in order to have the required bandwidth (BW), that means:
Application information
L5980
Equation 18
BW 1
R 4 = ---------- ⋅ ---- ⋅ R 1
f LC K
where K is the feed forward constant and 1/K is equals to 9.
3.
Calculate C4 by placing the zero at 50 % of the output filter double pole frequency (fLC):
Equation 19
1
C 4 = --------------------------π ⋅ R 4 ⋅ f LC
4.
Calculate C5 by placing the second pole at four times the system bandwidth (BW):
Equation 20
C4
C 5 = ------------------------------------------------------------2π ⋅ R 4 ⋅ C 4 ⋅ 4 ⋅ BW – 1
5.
Set also the first pole at four times the system bandwidth and also the second zero at
the output filter double pole:
Equation 21
R1
R 3 = --------------------------,
4
⋅
BW
----------------- – 1
f LC
1
C 3 = ---------------------------------------2π ⋅ R 3 ⋅ 4 ⋅ BW
The suggested maximum system bandwidth is equals to the switching frequency divided by
3.5 (FSW/3.5), anyway lower than 100 kHz if the FSW is set higher than 500 kHz.
For example with VOUT = 3.3 V, VIN = 12 V, IO = 0.7 A, L = 47 μH, COUT = 22 μF,
ESR < 1 mΩ, the type III compensation network is:
R 1 = 4.99kΩ,
R 2 = 1.1kΩ, R 3 = 120Ω, R 4 = 5.6kΩ,
C 3 = 6.8nF,
C 4 = 10nF,
C 5 = 100pF
In Figure 12 is shown the module and phase of the open loop gain. The bandwidth is about
57 kHz and the phase margin is 45°.
20/37
Application information
Figure 12. Open loop gain bode diagram with ceramic output capacitor
21/37
L5980
Application information
5.4.2
L5980
Type II compensation network
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a
frequency lower than the desired bandwidth (that is: 2π * ESR * COUT > 1/BW), this zero
helps stabilize the loop. Electrolytic capacitors show not negligible ESR (>30 mΩ), so with
this kind of output capacitor the type II network combined with the zero of the ESR allows
stabilizing the loop.
In Figure 13 the type II network is shown.
Figure 13. Type II compensation network
The singularities of the network are:
1
-,
f Z1 = ----------------------------2π ⋅ R 4 ⋅ C 4
f P0 = 0,
1
f P1 = ------------------------------------------C4 ⋅ C5
2π ⋅ R 4 ⋅ -------------------C4 + C5
In Figure 14 the Bode diagram of the PWM and LC filter transfer function (GPW0 · GLC(f))
and the open loop gain (GLOOP(f) = GPW0 · GLC(f) · GTYPEII(f)) are drawn.
22/37
Application information
L5980
Figure 14. Open loop gain: module bode diagram
The guidelines for positioning the poles and the zeroes and for calculating the component
values can be summarized as follow:
1.
Choose a value for R1, usually between 1 k and 5 k, in order to have values of C4 and
C5 not comparable with parasitic capacitance of the board.
2.
Choose a gain (R4/R1) in order to have the required bandwidth (BW), that means:
Equation 22
f ESR 2 BW V S
R 4 = ⎛ ------------⎞ ⋅ ------------ ⋅ --------- ⋅ R 1
⎝ f LC ⎠ f ESR V IN
Where fESR is the ESR zero:
Equation 23
1
f ESR = -------------------------------------------2π ⋅ ESR ⋅ C OUT
and Vs is the saw-tooth amplitude. The voltage feed forward keeps the ratio Vs/Vin constant.
3.
Calculate C4 by placing the zero one decade below the output filter double pole:
Equation 24
10
C 4 = -----------------------------2π ⋅ R 4 ⋅ f LC
4.
23/37
Then calculate C3 in order to place the second pole at four times the system bandwidth
(BW):
Application information
L5980
Equation 25
C4
C 5 = ------------------------------------------------------------2π ⋅ R 4 ⋅ C 4 ⋅ 4 ⋅ BW – 1
For example with VOUT = 1.2 V, VIN = 12 V, IO = 0.7 A, L = 22 μH, COUT = 220 μF,
ESR = 50 mΩ, the type II compensation network is:
R 1 = 1.1kΩ,
R 2 = 249Ω,
R 4 = 12kΩ,
C 4 = 47nF,
C 5 = 68pF
In Figure 15 is shown the module and phase of the open loop gain. The bandwidth is about
35 kHz and the phase margin is 49°.
24/37
Application information
L5980
Figure 15. Open loop gain bode diagram with electrolytic/tantalum output capacitor
25/37
Application information
5.5
L5980
Thermal considerations
The thermal design is important to prevent the thermal shutdown of device if junction
temperature goes above 150 °C. The three different sources of losses within the device are:
a)
conduction losses due to the not negligible RDS(on) of the power switch; these are
equal to:
Equation 26
2
P ON = R DS ( on ) ⋅ ( I OUT ) ⋅ D
Where D is the duty cycle of the application and the maximum RDS(on) is 300 mΩ. Note that
the duty cycle is theoretically given by the ratio between VOUT an VIN, but actually it is quite
higher to compensate the losses of the regulator. So the conduction losses increases
compared with the ideal case.
b)
switching losses due to power MOSFET turn ON and OFF; these can be
calculated as:
Equation 27
( T RISE + T FALL )
P SW = V IN ⋅ I OUT ⋅ ------------------------------------------- ⋅ Fsw = V IN ⋅ I OUT ⋅ T SW ⋅ F SW
2
Where TRISE and TFALL are the overlap times of the voltage across the power switch (VDS)
and the current flowing into it during turn ON and turn OFF phases, as shown in Figure 16.
TSW is the equivalent switching time. For this device the typical value for the equivalent
switching time is 50 ns.
c)
Quiescent current losses, calculated as:
Equation 28
P Q = V IN ⋅ I Q
where IQ is the quiescent current (IQ = 2.4 mA).
The junction temperature TJ can be calculated as:
Equation 29
T J = T A + Rth JA ⋅ P TOT
Where TA is the ambient temperature and PTOT is the sum of the power losses just seen.
RthJA is the equivalent thermal resistance junction to ambient of the device; it can be
calculated as the parallel of many paths of heat conduction from the junction to the ambient.
For this device the path through the exposed pad is the one conducting the largest amount
26/37
Application information
L5980
of heat. The RthJA measured on the demonstration board described in the following
paragraph is about 60 °/W.
Figure 16. Switching losses
5.6
Layout considerations
The PC board layout of switching DC/DC regulator is very important to minimize the noise
injected in high impedance nodes and interferences generated by the high switching current
loops.
In a step down converter the input loop (including the input capacitor, the power MOSFET
and the free wheeling diode) is the most critical one. This is due to the fact that the high
value pulsed current are flowing through it. In order to minimize the EMI, this loop has to be
as short as possible.
The feedback pin (FB) connection to external resistor divider is a high impedance node, so
the interferences can be minimized placing the routing of feedback node as far as possible
from the high current paths. To reduce the pick up noise the resistor divider has to be placed
very close to the device.
To filter the high frequency noise, a small capacitor (100 nF) can be added as close as
possible to the input voltage pin of the device.
Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal
resistance junction to ambient; so a large ground plane enhances the thermal performance
of the converter allowing high power conversion.
In Figure 17 a layout example is shown.
27/37
Application information
Figure 17. Layout example
28/37
L5980
Application information
5.7
L5980
Application circuit
In Figure 18 the demonstration board application circuit is shown.
Figure 18. Demonstration board application circuit
VIN=3.3V to 18V
INH
GND
C1
C6
10uF
68nF
L1 15uH
OUT
VCC
8
1
3
2
SYNCH
D1
STPS2L25U
L5985
L5980
7
Vout=3.3V
C2
R1 4.99K
FB
22uF
5
6
FSW
4
C4 10nF
COMP
R5 100K
R3 180
R4 3.9K
C3 3.3nF
R2 1.1K
C5 150pF
Table 9.
Component list
Reference
29/37
Part number
Description
Manufacturer
C1
GRM31CR61E106KA12
10 μF, 25 V
Murata
C2
GRM32ER61E226KE15
22 μF, 25 V
Murata
C3
3.3 nF, 50 V
C4
10 nF, 50 V
C5
150 pF, 50 V
C6
68 nF, 25 V
R1
4.99 kΩ, 1 %, 0.1 W 0603
R2
1.1 kΩ, 1 %, 0.1 W 0603
R3
180 Ω, 1 %, 0.1 W 0603
R4
3.9 kΩ, 1 %, 0.1 W 0603
R5
100 kΩ, 1 %, 0.1 W 0603
D1
STPS2L25V
2 A, 25 V
STMicroelectronics
L1
7447779115
15 μH, 20 %, 2.2 A
Wurth elektronik
Application information
Figure 19. PCB layout (component side)
Figure 20. PCB layout (bottom side)
Figure 21. PCB layout (front side)
30/37
L5980
L5980
Figure 22. Junction temperature vs output
current
Application information
Figure 25. Efficiency vs output current
95
E fficiency [% ]
90
Vo=5.0V
85
Vo=3.3
80
Vo=2.5V
VCC=12V
FSW =250KHz
75
70
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Io [A]
Figure 23. Junction temperature vs output
current
Figure 26. Efficiency vs output current
94
92
Vo=3.3V
E ffic ie n c y [% ]
90
88
Vo=2.5V
86
84
82
Vo=1.8V
80
VCC=5V
FSW=250KHz
78
76
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Io [A]
Figure 27. Efficiency vs output current
95
Vo=2.5V
90
E ffic ie n c y [% ]
Figure 24. Junction temperature vs output
current
85
Vo=1.8V
80
Vo=1.2V
75
VCC=3.3V
FSW =250KHz
70
65
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Io [A]
31/37
L5980
Application information
Figure 31. Load transient: from 0.1 A to 0.7 A
Figure 28. Load regulation
0.14
FSW=250KHz
VOUT
50mV/div
AC coupled
ΔVFB/VFB [%]
0.12
0.1
0.08
VCC=3.3V
0.06
VCC=5.0V
0.04
VCC=12V
0.02
IL
200mA/div
Time base 100μs/div
Load slew rate 2.5A/μs
0
0.1
0.2
0.3
0.4
0.5
0.6
COUT=47μF
L=15μH
FSW=520KHz
0.7
Io [A]
Figure 32. Soft-start
Figure 29. Line regulation
0.4
Δ V F B /VF B [% ]
0.35
VOUT
500mV/div
0.3
0.25
VFB
200mV/div
0.2
IL
500mA/div
0.15
0.1
Io=0.7A
0.05
0
-0.05 2
Time base 1ms/div
4
6
8
10
12
14
16
18
VCC [V]
Figure 30. Short circuit behavior
OUT
10V/div
OUTPUT
SHORTED
IL
250mA/div
VOUT
1V/div
Time base 5ms/div
32/37
Package mechanical data
6
L5980
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of the
second level interconnect is marked on the package and on the inner box label, in
compliance with the JEDEC Standard JESD97. The maximum ratings related to soldering
condition are also marked on the inner box label. ECOPACK® is an ST trademark.
ECOPACK specifications are available at: www.st.com
33/37
Package mechanical data
Table 10.
L5980
VFQFPN8 (3x3 x 1.08 mm) mechanical data
mm
inch
Dim.
Min
Typ
Max
Min
Typ
Max
0.80
0.90
1.00
0.0315
0.0354
0.0394
A1
0.02
0.05
0.0008
0.0020
A2
0.70
0.0276
A3
0.20
0.0079
A
b
0.18
0.23
0.30
0.0071
0.0091
0.0118
D
2.95
3.00
3.05
0.1161
0.1181
0.1200
D2
2.23
2.38
2.48
0.0878
0.0937
0.0976
E
2.95
3.00
3.05
0.1161
0.1181
0.1200
E2
1.49
1.64
1.74
0.0587
0.0646
0.0685
e
L
0.50
0.30
0.40
ddd
Figure 33. Package dimensions
34/37
0.0197
0.50
0.08
0.0118
0.0157
0.0197
0.0031
Order codes
7
L5980
Order codes
Table 11.
Order codes
Order codes
Package
L5980
Packaging
Tube
VFQFPN8 (3x3x1.08 mm)
L5980TR
35/37
Tube and reel
Revision history
8
L5980
Revision history
Table 12.
Document revision history
Date
Revision
21-Dec-2006
1
Initial release
18-Oct-2007
2
Document status promoted from preliminary data to datasheet
3
Updated: Cover page, Figure 2 on page 3, Figure 8 on page 13,
Figure 9 on page 17, Figure 17 on page 28, Figure 18 on page 29,
Table 4 on page 5, Table 8 on page 16, Table 10 on page 34
Added: Table 3 on page 4
09-Sep-2008
36/37
Changes
L5980
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