Am29LV640MT/B Data Sheet RETIRED PRODUCT This product has been retired and is not available for designs. For new and current designs, S29GL064A supersedes Am29LV640MT/B and is the factory-recommended migration path. Please refer to the S29GL064A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary. For More Information Please contact your local sales office for additional information about Spansion memory solutions. Publication Number 26190 Revision C Amendment 8 Issue Date February 1, 2007 THIS PAGE LEFT INTENTIONALLY BLANK. DATA SHEET Am29LV640MT/B 64 Megabit (4 M x 16-Bit/8 M x 8-Bit) MirrorBit™ 3.0 Volt-only Boot Sector Flash Memory This product has been retired and is not available for designs. For new and current designs, S29GL064A supersedes Am29LV640M T/B and is the factory-recommended migration path. Please refer to the S29GL064A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES Single power supply operation — 3 V for read, erase, and program operations Manufactured on 0.23 µm MirrorBit process technology Secured Silicon Sector region — 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random Electronic Serial Number, accessible through a command sequence — Can be programmed and locked at the factory or by the customer Flexible sector architecture — One hundred twenty-seven 32 Kword/64-Kbyte sectors — Eight 4 Kword/8 Kbyte boot sectors Compatibility with JEDEC standards — Provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection Minimum 100,000 erase cycle guarantee per sector 20-year data retention at 125°C PERFORMANCE CHARACTERISTICS High performance — 90 ns access time — 25 ns page read times — 0.5 s typical sector erase time — 22 µs typical effective write buffer word programming time: 16-word/32-byte write buffer reduces overall programming time for multiple-word/byte updates — 4-word/8-byte page read buffer — 16-word/32-byte write buffer Low power consumption (typical values at 3.0 V, 5 MHz) — 30 mA typical active read current — 50 mA typical erase/program current — 1 µA typical standby mode current Package options — 48-pin TSOP — 63-ball Fine-pitch BGA — 64-ball Fortified BGA SOFTWARE & HARDWARE FEATURES Software features — Program Suspend & Resume: read other sectors before programming operation is completed — Erase Suspend & Resume: read/program other sectors before an erase operation is completed — Data# polling & toggle bits provide status — Unlock Bypass Program command reduces overall multiple-word programming time — CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices Hardware features — Sector Group Protection: hardware-level method of preventing write operations within a sector group — Temporary Sector Unprotect: VID-level method of changing code in locked sectors — WP#/ACC input: Write Protect input (WP#) protects top or bottom two sectors regardless of sector protection settings ACC (high voltage) accelerates programming time for higher throughput during system production — Hardware reset input (RESET#) resets device — Ready/Busy# output (RY/BY#) indicates program or erase cycle completion Publication# 26190 Rev: C Amendment/8 Issue Date: February 1, 2007 D A T A S H E E T GENERAL DESCRIPTION The Am29LV640M is a 64 Mbit, 3.0 volt single power supply flash memory device organized as 4,194,304 words o r 8,388 ,6 08 bytes. The device has an 8-bit/16-bit bus and can be programmed either in the host system or in standard EPROM programmers. An access time of 90, 100, 110, or 120 ns is available. Note that each access time has a specific operating voltage range (VCC) and an I/O voltage range (VIO), as specified in Product Selector Guide on page 6 and Ordering Information on page 10. The device is offered in a 48-pin TSOP, 63-ball Fine-pitch BGA or 64-ball Fortified BGA package. Each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a V CC input, a high-voltage accelerated program (ACC) function provides shorter programming times through increased current on the WP#/ACC input. This feature is intended to facilitate factory throughput during system production, but can also be used in the field if desired. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Device programming and erasure are initiated through command sequences. Once a program or erase operation has begun, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy# (RY/BY#) output to determine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four. 2 Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This is achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Suspend/Program Resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation. The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET# pin can be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device. The device reduces power consumption in the standby mode when it detects specific voltage levels on CE# and RESET#, or when addresses have been stable for a specified period of time. The Write Protect (WP#) feature protects the top or bottom two sectors by asserting a logic low on the WP#/ACC pin. The protected sector is still protected even during accelerated programming. The Secured Silicon Sector provides a 128-word/256-byte area for code or data that can be permanently protected. Once this sector is protected, no further changes within the sector can occur. AMD MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection. Am29LV640MT/B 26190C8 February 1, 2007 D A T A S H E E T MIRRORBIT 64 MBIT DEVICE FAMILY Device Sector Architecture Packages VIO RY/BY# WP#, ACC WP# Protection x8 Uniform (64 Kbyte) 48-pin TSOP (std. & rev. pinout), 63-ball FBGA Yes Yes ACC only No WP# LV640MT/B x8/x16 Boot (8 x 8 Kbyte at top & bottom) 48-pin TSOP, 63-ball Fine-pitch BGA, 64-ball Fortified BGA No Yes WP#/ACC pin 2 x 8 Kbyte top or bottom LV640MH/L x8/x16 Uniform (64 Kbyte) 56-pin TSOP (std. & rev. pinout), 64-ball Fortified BGA Yes Yes WP#/ACC pin 1 x 64 Kbyte high or low LV641MH/L x16 Uniform (32 Kword) 48-pin TSOP (std. & rev. pinout) Yes No Separate WP# and ACC pins 1 x 32 Kword top or bottom LV640MU x16 Uniform (32 Kword) 64-ball Fortified BGA, 63-ball Fine-pitch BGA Yes Yes ACC only No WP# LV065MU Bus RELATED DOCUMENTS To download related documents, click on the following links or go to www.amd.com→Flash Memory→Product Information→MirrorBit→Flash Information→Technical Documentation. MirrorBit™ Flash Memory Write Buffer Programming and Page Buffer Read February 1, 2007 26190C8 Implementing a Common Layout for AMD MirrorBit and Intel StrataFlash Memory Devices Migrating from Single-byte to Three-byte Device IDs AMD MirrorBit™ White Paper Am29LV640MT/B 3 D A T A S H E E T TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10 Device Bus Operations . . . . . . . . . . . . . . . . . . . . 11 Table 1. Device Bus Operations .....................................................11 Word/Byte Configuration ........................................................ 11 Requirements for Reading Array Data ................................... 11 Page Mode Read .................................................................... 12 Writing Commands/Command Sequences ............................ 12 Write Buffer ............................................................................. 12 Accelerated Program Operation ............................................. 12 Autoselect Functions .............................................................. 12 Standby Mode ........................................................................ 12 Automatic Sleep Mode ........................................................... 13 RESET#: Hardware Reset Pin ............................................... 13 Output Disable Mode .............................................................. 13 Table 2. Am29LV640MT Top Boot Sector Architecture ..................13 Table 3. Am29LV640MB Bottom Boot Sector Architecture .............16 Autoselect Mode..................................................................... 19 Table 4. Autoselect Codes, (High Voltage Method) .......................19 Sector Group Protection and Unprotection ............................. 20 Table 5. Am29LV640MT Top Boot Sector Protection .....................20 Table 6. Am29LV640MB Bottom Boot Sector Protection ................20 Write Protect (WP#) ................................................................ 21 Temporary Sector Group Unprotect ....................................... 21 Figure 1. Temporary Sector Group Unprotect Operation................ 21 Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 22 Secured Silicon Sector Flash Memory Region ....................... 23 Table 7. Secured Silicon Sector Contents ......................................23 Figure 3. Secured Silicon Sector Protect Verify .............................. 24 Hardware Data Protection ...................................................... 24 Low VCC Write Inhibit ............................................................ 24 Write Pulse “Glitch” Protection ............................................... 24 Logical Inhibit .......................................................................... 24 Power-Up Write Inhibit ............................................................ 24 Common Flash Memory Interface (CFI) . . . . . . . 24 Table 8. CFI Query Identification String .............................. 25 Table 9. System Interface String......................................................25 Table 10. Device Geometry Definition................................. 26 Table 11. Primary Vendor-Specific Extended Query........... 27 Command Definitions . . . . . . . . . . . . . . . . . . . . . 27 Reading Array Data ................................................................ 27 Reset Command ..................................................................... 28 Autoselect Command Sequence ............................................ 28 Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence .............................................................. 28 Word/Byte Program Command Sequence ............................. 28 Unlock Bypass Command Sequence ..................................... 29 Write Buffer Programming ...................................................... 29 Accelerated Program .............................................................. 30 Figure 4. Write Buffer Programming Operation............................... 31 Figure 5. Program Operation .......................................................... 32 Program Suspend/Program Resume Command Sequence ... 32 Figure 6. Program Suspend/Program Resume............................... 33 Chip Erase Command Sequence ........................................... 33 4 Sector Erase Command Sequence ........................................ 33 Figure 7. Erase Operation.............................................................. 34 Erase Suspend/Erase Resume Commands ........................... 35 Command Definitions ............................................................. 36 Table 12. Command Definitions (x16 Mode, BYTE# = VIH) ............ 36 Table 13. Command Definitions (x8 Mode, BYTE# = VIL)............... 37 Write Operation Status . . . . . . . . . . . . . . . . . . . . . 38 DQ7: Data# Polling ................................................................. 38 Figure 8. Data# Polling Algorithm .................................................. 38 RY/BY#: Ready/Busy#............................................................ 39 DQ6: Toggle Bit I .................................................................... 39 Figure 9. Toggle Bit Algorithm........................................................ 40 DQ2: Toggle Bit II ................................................................... 40 Reading Toggle Bits DQ6/DQ2 ............................................... 40 DQ5: Exceeded Timing Limits ................................................ 41 DQ3: Sector Erase Timer ....................................................... 41 DQ1: Write-to-Buffer Abort ..................................................... 41 Table 14. Write Operation Status ................................................... 41 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 42 Figure 10. Maximum Negative Overshoot Waveform ................... 42 Figure 11. Maximum Positive Overshoot Waveform..................... 42 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 42 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 43 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 12. Test Setup.................................................................... 44 Table 15. Test Specifications ......................................................... 44 Key to Switching Waveforms. . . . . . . . . . . . . . . . 44 Figure 13. Input Waveforms and Measurement Levels...................................................................... 44 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 45 Read-Only Operations ........................................................... 45 Figure 14. Read Operation Timings ............................................... 45 Figure 15. Page Read Timings ...................................................... 46 Hardware Reset (RESET#) .................................................... 47 Figure 16. Reset Timings ............................................................... 47 Erase and Program Operations .............................................. 48 Figure 17. Program Operation Timings.......................................... Figure 18. Accelerated Program Timing Diagram.......................... Figure 19. Chip/Sector Erase Operation Timings .......................... Figure 20. Data# Polling Timings (During Embedded Algorithms). Figure 21. Toggle Bit Timings (During Embedded Algorithms)...... Figure 22. DQ2 vs. DQ6................................................................. 49 49 50 51 52 52 Temporary Sector Unprotect .................................................. 53 Figure 23. Temporary Sector Group Unprotect Timing Diagram ... 53 Figure 24. Sector Group Protect and Unprotect Timing Diagram .. 54 Alternate CE# Controlled Erase and Program Operations ..... 55 Figure 25. Alternate CE# Controlled Write (Erase/Program) Operation Timings.......................................................................... 56 Erase And Programming Performance. . . . . . . . 57 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 57 TSOP Pin and BGA Package Capacitance . . . . . 58 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 59 TS 048—48-Pin Standard Pinout Thin Small Outline Package (TSOP) ................................................................................... 59 FBE063—63-Ball Fine-pitch Ball Grid Array (FBGA) 12 x 11 mm Package .............................................................. 60 LAA064—64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm Package .............................................................. 61 Am29LV640MT/B 26190C8 February 1, 2007 D A T A S H E E T Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . 62 February 1, 2007 26190C8 Am29LV640MT/B 5 D A T A S H E E T PRODUCT SELECTOR GUIDE Part Number Am29LV640M VCC = 3.0–3.6 V Speed Option 90R 100R VCC = 2.7–3.6 V 110R 120R 100 110 120 Max. Access Time (ns) 90 100 110 120 Max. CE# Access Time (ns) 90 100 110 120 Max. Page access time (tPACC) 25 30 30 40 30 40 Max. OE# Access Time (ns) 25 30 30 40 30 40 Note: See AC Characteristics on page 45 for full specifications. BLOCK DIAGRAM DQ0–DQ15 (A-1) RY/BY# VCC Sector Switches VSS Erase Voltage Generator Input/Output Buffers RESET# WE# WP#/ACC BYTE# State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic CE# OE# VCC Detector Timer A21–A0 6 Am29LV640MT/B Address Latch STB STB Data Latch Y-Decoder Y-Gating X-Decoder Cell Matrix 26190C8 February 1, 2007 D A T A S H E E T CONNECTION DIAGRAMS A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RESET# A21 WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 A8 B8 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 48-Pin Standard TSOP 63-ball Fine-pitch BGA (FBGA) Top View, Balls Facing Down A7 B7 C7 D7 E7 F7 G7 NC NC A13 A12 A14 A15 A16 H7 J7 C6 D6 E6 F6 G6 H6 J6 K6 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 BYTE# DQ15/A-1 L8 M8 NC* NC* K7 L7 M7 VSS NC* NC* C5 D5 E5 F5 G5 H5 J5 K5 WE# RESET# A21 A19 DQ5 DQ12 VCC DQ4 C4 D4 RY/BY# WP#/ACC A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 E4 F4 G4 H4 J4 K4 A18 A20 DQ2 DQ10 DQ11 DQ3 C3 D3 E3 F3 G3 H3 J3 K3 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A2 C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 NC* A3 A4 A2 A1 A0 CE# OE# VSS NC* NC* L1 M1 NC* NC* A1 B1 * Balls are shorted together via the substrate but not connected to the die. NC* NC* February 1, 2007 26190C8 Am29LV640MT/B 7 D A T A S H E E T CONNECTION DIAGRAMS 64-Ball Fortified BGA (fBGA) Top View, Balls Facing Down A8 B8 C8 D8 E8 F8 G8 H8 NC NC NC NC VSS NC NC NC A7 B7 C7 D7 E7 F7 G7 H7 A13 A12 A14 A15 A16 A6 B6 C6 D6 E6 F6 VSS G6 H6 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 A5 B5 C5 D5 E5 F5 G5 H5 WE# RESET# A21 A19 DQ5 DQ12 VCC DQ4 A4 B4 C4 D4 E4 F4 G4 H4 A18 A20 DQ2 DQ10 DQ11 DQ3 RY/BY# WP#/ACC A3 B3 C3 D3 E3 F3 G3 H3 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A2 B2 C2 D2 E2 F2 G2 H2 A3 A4 A2 A1 A0 CE# OE# VSS A1 B1 C1 D1 E1 F1 G1 H1 NC NC NC NC NC NC NC NC Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP and BGA). The package 8 BYTE# DQ15/A-1 and/or data integrity can be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. Am29LV640MT/B 26190C8 February 1, 2007 D A T A PIN DESCRIPTION A21–A0 S H E E T LOGIC SYMBOL = 22 Address inputs 22 DQ14–DQ0 = 15 Data inputs/outputs A21–A0 DQ15/A-1 = DQ15 (Data input/output, word mode), A-1 (LSB Address input, byte mode) CE# CE# = Chip Enable input OE# OE# = Output Enable input WE# WE# = Write Enable input WP#/ACC WP#/ACC = Hardware Write Protect input/Programming Acceleration input RESET# RESET# = Hardware Reset Pin input RY/BY# = Ready/Busy output BYTE# = Selects 8-bit or 16-bit mode VCC = 3.0 volt-only single power supply (See Product Selector Guide on page 6 for speed options and voltage supply tolerances.) VSS = Device Ground NC = Pin Not Connected Internally February 1, 2007 26190C8 Am29LV640MT/B BYTE# 16 or 8 DQ15–DQ0 (A-1) RY/BY# 9 D A T A S H E E T ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Am29LV640M T 120R PC I TEMPERATURE RANGE F = Industrial (-40°C to +85°C) with Pb-free Package I = Industrial (–40°C to +85°C) PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) PC = 64-Ball Fortified Ball Grid Array 1.0 mm pitch, 13 x 11 mm package (LAA064) WH = 63-Ball Fine Pitch Ball Grid Array 0.80 mm pitch, 12 x 11 mm package (FBE063) SPEED OPTION See Product Selector Guide and Valid Combinations SECTOR ARCHITECTURE AND WP# PROTECTION (WP# = VIL) T = Top boot sector device, top two address sectors protected B = Bottom boot sector device, bottom two address sectors protected DEVICE NUMBER/DESCRIPTION Am29LV640M 64 Megabit (4 M x 16-Bit/8 M x 8-Bit) MirrorBit™ Boot Sector Flash Memory 3.0 Volt-only Read, Program, and Erase Valid Combinations for TSOP Package Speed (ns) VCC Range Am29LV640MT90R, Am29LV640MB90R 90 3.0– 3.6 V Am29LV640MT100, Am29LV640MB100 100 Am29LV640MT110, Am29LV640MB110 110 Am29LV640MT120, Am29LV640MB120 EI EF 100 Am29LV640MT110R, Am29LV640MB110R 110 Am29LV640MT120R, Am29LV640MB120R 120 Am29LV640MT90R Am29LV640MB90R 2.7– 3.6 V 120 Am29LV640MT100R, Am29LV640MB100R Order Number Am29LV640MT100 Am29LV640MB100 Am29LV640MT110 3.0– 3.6 V Am29LV640MB110 Am29LV640MT120 Am29LV640MB120 Valid Combinations Am29LV640MT100R Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am29LV640MB100R Am29LV640MT110R Am29LV640MB110R Am29LV640MT120R Am29LV640MB120R 10 WHI PCI WHI PCI WHI PCI WHI PCI WHI PCI WHI PCI WHI PCI WHI PCI WHI PCI WHI PCI WHI PCI WHI PCI WHI PCI WHI PCI Valid Combinations for BGA Packages Package Order Number Marking L640MT90RI Am29LV640MT90R L640MT90NI L640MB90RI Am29LV640MB90R L640MB90NI L640MT10VI Am29LV640MT100 L640MT10PI L640MB10VI Am29LV640MB100 L640MB10PI L640MT11VI Am29LV640MT110 L640MT11PI L640MB11VI Am29LV640MB110 L640MB11PI L640MT12VI Am29LV640MT120 L640MT12PI L640MB12VI Am29LV640MB120 L640MB12PI L640MT10RI Am29LV640MT100R L640MT10NI L640MB10RI Am29LV640MB100R L640MB10NI L640MT11RI Am29LV640MT110R L640MT11NI L640MB11RI Am29LV640MB110R L640MB11NI L640MT12RI Am29LV640MT120R L640MT12NI L640MB12RI Am29LV640MB120R L640MB12NI Am29LV640MT/B WHF PCF WHF PCF WHF PCF WHF PCF WHF PCF WHF PCF WHF PCF WHF PCF WHF PCF WHF PCF WHF PCF WHF PCF WHF PCF WHF PCF Package Marking L640MT90RF L640MT90NF L640MB90RF L640MB90NF L640MT10VF L640MT10PF L640MB10VF L640MB10PF L640MT11VF L640MT11PF L640MB11VF L640MB11PF L640MT12VF L640MT12PF L640MB12VF L640MB12PF L640MT10RF L640MT10NF L640MB10RF L640MB10NF L640MT11RF L640MT11NF L640MB11RF L640MB11NF L640MT12RF L640MT12NF L640MB12RF L640MB12NF Speed VCC (ns) Range 90 3.0– 3.6 V 100 110 2.7– 3.6 V 120 100 110 3.0– 3.6 V 120 26190C8 February 1, 2007 D A T A S H E E T DEVICE BUS OPERATIONS register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of the Table 1. Device Bus Operations DQ8–DQ15 CE# OE# WE# RESET# WP# ACC Addresses (Note 2) DQ0– DQ7 BYTE# = VIH Read L L H H X X AIN DOUT DOUT Write (Program/Erase) L H L H (Note 3) X AIN (Note 4) (Note 4) Accelerated Program L H L H (Note 3) VHH AIN (Note 4) (Note 4) VCC ± 0.3 V X X VCC ± 0.3 V X H X High-Z High-Z High-Z Output Disable L H H H X X X High-Z High-Z High-Z Reset X X X L X X X High-Z High-Z High-Z Sector Group Protect (Note 2) L H L VID H X SA, A6 =L, A3=L, A2=L, A1=H, A0=L (Note 4) X X Sector Group Unprotect (Note 2) L H L VID H X SA, A6=H, A3=L, A2=L, A1=H, A0=L (Note 4) X X Temporary Sector Group Unprotect X X X VID H X AIN Operation Standby (Note 4) (Note 4) BYTE# = VIL DQ8–DQ14 = High-Z, DQ15 = A-1 High-Z Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A21:A0 in word mode; A21:A-1 in byte mode. Sector addresses are A21:A12 in both modes. 2. The sector protect and sector unprotect functions can also be implemented via programming equipment. See the See Sector Group Protection and Unprotection on page 20. 3. If WP# = VIL, the first or last sector remains protected. If WP# = VIH, the top two or bottom two sectors are protected or unprotected as determined by the method described in Sector Group Protection and Unprotection. All sectors are unprotected when shipped from the factory (The Secured Silicon Sector can be factory protected depending on version ordered.) 4. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2). Word/Byte Configuration The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ0–DQ15 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O February 1, 2007 26190C8 pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. Am29LV640MT/B 11 D A T A The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See See Reading Array Data on page 27 for more information. See the table, Read-Only Operations on page 45 for timing specifications and to Figure 14 for the timing diagram. Refer to the DC Characteristics table for the active current specification on reading array data. Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. The page size of the device is 4 words/8 bytes. The appropriate page is selected by the higher address bits A(max)–A2. Address bits A1–A0 in word mode (A1–A-1 in byte mode) determine the specific word within a page. This is an asynchronous operation; the microprocessor supplies the specific word location. The random or initial page access is equal to tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is deasserted and reasserted for a subsequent access, the access time is t ACC or t CE . Fast page mode accesses are obtained by keeping the “read-page addresses” constant and changing the “intra-read page” addresses. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The Word/Byte Program Command Sequence on page 29 has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 and Table 3 indicates the address space that each sector occupies. 12 S H E E T Refer to the DC Characteristics table for the active current specification for the write mode. AC Characteristics on page 45 contains timing specification tables and timing diagrams for write operations. Write Buffer Write Buffer Programming allows the system to write a maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. See Write Buffer on page 12 for more information. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to normal operation. Note that the WP#/ACC pin must not be at VHH for operations other than accelerated programming, or device damage can result. In addition, no external pullup is necessary since the WP#/ACC pin has internal pullup to VCC. Autoselect Functions If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. See Autoselect Mode on page 19 and Autoselect Command Sequence on page 28 for more information. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device is in the standby mode, but the standby current is greater. The device requires standard access time (tCE) for read access when the de- Am29LV640MT/B 26190C8 February 1, 2007 D A T A vice is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. See the table in DC Characteristics on page 43 for the standby current specification. Automatic Sleep Mode S H E E T device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. To ensure data integrity, reinitiate the operation that was interrupted, once the device is ready to accept another command sequence. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current is greater. The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Refer to the DC Characteristics table for the automatic sleep mode current specification. Refer to the AC Characteristics tables for RESET# parameters and to Figure 16 for the timing diagram. RESET#: Hardware Reset Pin Output Disable Mode The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. Table 2. The RESET# pin can be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. Am29LV640MT Top Boot Sector Architecture Sector Sector Address A21–A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range SA0 0000000xxx 64/32 000000h–00FFFFh 00000h–07FFFh SA1 0000001xxx 64/32 010000h–01FFFFh 08000h–0FFFFh SA2 0000010xxx 64/32 020000h–02FFFFh 10000h–17FFFh SA3 0000011xxx 64/32 030000h–03FFFFh 18000h–1FFFFh SA4 0000100xxx 64/32 040000h–04FFFFh 20000h–27FFFh SA5 0000101xxx 64/32 050000h–05FFFFh 28000h–2FFFFh SA6 0000110xxx 64/32 060000h–06FFFFh 30000h–37FFFh SA7 0000111xxx 64/32 070000h–07FFFFh 38000h–3FFFFh SA8 0001000xxx 64/32 080000h–08FFFFh 40000h–47FFFh SA9 0001001xxx 64/32 090000h–09FFFFh 48000h–4FFFFh SA10 0001010xxx 64/32 0A0000h–0AFFFFh 50000h–57FFFh SA11 0001011xxx 64/32 0B0000h–0BFFFFh 58000h–5FFFFh SA12 0001100xxx 64/32 0C0000h–0CFFFFh 60000h–67FFFh SA13 0001101xxx 64/32 0D0000h–0DFFFFh 68000h–6FFFFh SA14 0001101xxx 64/32 0E0000h–0EFFFFh 70000h–77FFFh SA15 0001111xxx 64/32 0F0000h–0FFFFFh 78000h–7FFFFh SA16 0010000xxx 64/32 100000h–00FFFFh 80000h–87FFFh SA17 0010001xxx 64/32 110000h–11FFFFh 88000h–8FFFFh SA18 0010010xxx 64/32 120000h–12FFFFh 90000h–97FFFh SA19 0010011xxx 64/32 130000h–13FFFFh 98000h–9FFFFh SA20 0010100xxx 64/32 140000h–14FFFFh A0000h–A7FFFh SA21 0010101xxx 64/32 150000h–15FFFFh A8000h–AFFFFh SA22 0010110xxx 64/32 160000h–16FFFFh B0000h–B7FFFh SA23 0010111xxx 64/32 170000h–17FFFFh B8000h–BFFFFh SA24 0011000xxx 64/32 180000h–18FFFFh C0000h–C7FFFh SA25 0011001xxx 64/32 190000h–19FFFFh C8000h–CFFFFh SA26 0011010xxx 64/32 1A0000h–1AFFFFh D0000h–D7FFFh February 1, 2007 26190C8 Am29LV640MT/B 13 D A T A S H E E T Table 2. Am29LV640MT Top Boot Sector Architecture (Continued) 14 Sector Sector Address A21–A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range SA27 0011011xxx SA28 0011000xxx 64/32 1B0000h–1BFFFFh D8000h–DFFFFh 64/32 1C0000h–1CFFFFh SA29 0011101xxx E0000h–E7FFFh 64/32 1D0000h–1DFFFFh E8000h–EFFFFh SA30 0011110xxx 64/32 1E0000h–1EFFFFh F0000h–F7FFFh SA31 0011111xxx 64/32 1F0000h–1FFFFFh F8000h–FFFFFh SA32 0100000xxx 64/32 200000h–20FFFFh F9000h–107FFFh SA33 0100001xxx 64/32 210000h–21FFFFh 108000h–10FFFFh SA34 0100010xxx 64/32 220000h–22FFFFh 110000h–117FFFh SA35 0101011xxx 64/32 230000h–23FFFFh 118000h–11FFFFh SA36 0100100xxx 64/32 240000h–24FFFFh 120000h–127FFFh SA37 0100101xxx 64/32 250000h–25FFFFh 128000h–12FFFFh SA38 0100110xxx 64/32 260000h–26FFFFh 130000h–137FFFh SA39 0100111xxx 64/32 270000h–27FFFFh 138000h–13FFFFh SA40 0101000xxx 64/32 280000h–28FFFFh 140000h–147FFFh SA41 0101001xxx 64/32 290000h–29FFFFh 148000h–14FFFFh SA42 0101010xxx 64/32 2A0000h–2AFFFFh 150000h–157FFFh SA43 0101011xxx 64/32 2B0000h–2BFFFFh 158000h–15FFFFh SA44 0101100xxx 64/32 2C0000h–2CFFFFh 160000h–167FFFh SA45 0101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh SA46 0101110xxx 64/32 2E0000h–2EFFFFh 170000h–177FFFh SA47 0101111xxx 64/32 2F0000h–2FFFFFh 178000h–17FFFFh SA48 0110000xxx 64/32 300000h–30FFFFh 180000h–187FFFh SA49 0110001xxx 64/32 310000h–31FFFFh 188000h–18FFFFh SA50 0110010xxx 64/32 320000h–32FFFFh 190000h–197FFFh SA51 0110011xxx 64/32 330000h–33FFFFh 198000h–19FFFFh SA52 0100100xxx 64/32 340000h–34FFFFh 1A0000h–1A7FFFh SA53 0110101xxx 64/32 350000h–35FFFFh 1A8000h–1AFFFFh SA54 0110110xxx 64/32 360000h–36FFFFh 1B0000h–1B7FFFh SA55 0110111xxx 64/32 370000h–37FFFFh 1B8000h–1BFFFFh SA56 0111000xxx 64/32 380000h–38FFFFh 1C0000h–1C7FFFh SA57 0111001xxx 64/32 390000h–39FFFFh 1C8000h–1CFFFFh SA58 0111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh SA59 0111011xxx 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh SA60 0111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh SA61 0111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh SA62 0111110xxx 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh SA63 0111111xxx 64/32 3F0000h–3FFFFFh 1F8000h–1FFFFFh SA64 1000000xxx 64/32 400000h–40FFFFh 200000h–207FFFh SA65 1000001xxx 64/32 410000h–41FFFFh 208000h–20FFFFh SA66 1000010xxx 64/32 420000h–42FFFFh 210000h–217FFFh SA67 1000011xxx 64/32 430000h–43FFFFh 218000h–21FFFFh SA68 1000100xxx 64/32 440000h–44FFFFh 220000h–227FFFh SA69 1000101xxx 64/32 450000h–45FFFFh 228000h–22FFFFh SA70 1000110xxx 64/32 460000h–46FFFFh 230000h–237FFFh SA71 1000111xxx 64/32 470000h–47FFFFh 238000h–23FFFFh SA72 1001000xxx 64/32 480000h–48FFFFh 240000h–247FFFh SA73 1001001xxx 64/32 490000h–49FFFFh 248000h–24FFFFh SA74 1001010xxx 64/32 4A0000h–4AFFFFh 250000h–257FFFh SA75 1001011xxx 64/32 4B0000h–4BFFFFh 258000h–25FFFFh SA76 1001100xxx 64/32 4C0000h–4CFFFFh 260000h–267FFFh SA77 1001101xxx 64/32 4D0000h–4DFFFFh 268000h–26FFFFh SA78 1001110xxx 64/32 4E0000h–4EFFFFh 270000h–277FFFh SA79 1001111xxx 64/32 4F0000h–4FFFFFh 278000h–27FFFFh SA80 1010000xxx 64/32 500000h–50FFFFh 280000h–28FFFFh SA81 1010001xxx 64/32 510000h–51FFFFh 288000h–28FFFFh Am29LV640MT/B 26190C8 February 1, 2007 D A T A S H E E T Table 2. Am29LV640MT Top Boot Sector Architecture (Continued) Sector Sector Address A21–A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range SA82 1010010xxx 64/32 520000h–52FFFFh 290000h–297FFFh SA83 1010011xxx 64/32 530000h–53FFFFh 298000h–29FFFFh SA84 1010100xxx 64/32 540000h–54FFFFh 2A0000h–2A7FFFh SA85 1010101xxx 64/32 550000h–55FFFFh 2A8000h–2AFFFFh SA86 1010110xxx 64/32 560000h–56FFFFh 2B0000h–2B7FFFh SA87 1010111xxx 64/32 570000h–57FFFFh 2B8000h–2BFFFFh SA88 1011000xxx 64/32 580000h–58FFFFh 2C0000h–2C7FFFh SA89 1011001xxx 64/32 590000h–59FFFFh 2C8000h–2CFFFFh SA90 1011010xxx 64/32 5A0000h–5AFFFFh 2D0000h–2D7FFFh SA91 1011011xxx 64/32 5B0000h–5BFFFFh 2D8000h–2DFFFFh SA92 1011100xxx 64/32 5C0000h–5CFFFFh 2E0000h–2E7FFFh SA93 1011101xxx 64/32 5D0000h–5DFFFFh 2E8000h–2EFFFFh SA94 1011110xxx 64/32 5E0000h–5EFFFFh 2F0000h–2FFFFFh SA95 1011111xxx 64/32 5F0000h–5FFFFFh 2F8000h–2FFFFFh SA96 1100000xxx 64/32 600000h–60FFFFh 300000h–307FFFh SA97 1100001xxx 64/32 610000h–61FFFFh 308000h–30FFFFh SA98 1100010xxx 64/32 620000h–62FFFFh 310000h–317FFFh SA99 1100011xxx 64/32 630000h–63FFFFh 318000h–31FFFFh SA100 1100100xxx 64/32 640000h–64FFFFh 320000h–327FFFh SA101 1100101xxx 64/32 650000h–65FFFFh 328000h–32FFFFh SA102 1100110xxx 64/32 660000h–66FFFFh 330000h–337FFFh SA103 1100111xxx 64/32 670000h–67FFFFh 338000h–33FFFFh SA104 1101000xxx 64/32 680000h–68FFFFh 340000h–347FFFh SA105 1101001xxx 64/32 690000h–69FFFFh 348000h–34FFFFh SA106 1101010xxx 64/32 6A0000h–6AFFFFh 350000h–357FFFh SA107 1101011xxx 64/32 6B0000h–6BFFFFh 358000h–35FFFFh SA108 1101100xxx 64/32 6C0000h–6CFFFFh 360000h–367FFFh SA109 1101101xxx 64/32 6D0000h–6DFFFFh 368000h–36FFFFh SA110 1101110xxx 64/32 6E0000h–6EFFFFh 370000h–377FFFh SA111 1101111xxx 64/32 6F0000h–6FFFFFh 378000h–37FFFFh SA112 1110000xxx 64/32 700000h–70FFFFh 380000h–387FFFh SA113 1110001xxx 64/32 710000h–71FFFFh 388000h–38FFFFh SA114 1110010xxx 64/32 720000h–72FFFFh 390000h–397FFFh SA115 1110011xxx 64/32 730000h–73FFFFh 398000h–39FFFFh SA116 1110100xxx 64/32 740000h–74FFFFh 3A0000h–3A7FFFh SA117 1110101xxx 64/32 750000h–75FFFFh 3A8000h–3AFFFFh SA118 1110110xxx 64/32 760000h–76FFFFh 3B0000h–3B7FFFh SA119 1110111xxx 64/32 770000h–77FFFFh 3B8000h–3BFFFFh SA120 1111000xxx 64/32 780000h–78FFFFh 3C0000h–3C7FFFh SA121 1111001xxx 64/32 790000h–79FFFFh 3C8000h–3CFFFFh SA122 1111010xxx 64/32 7A0000h–7AFFFFh 3D0000h–3D7FFFh SA123 1111011xxx 64/32 7B0000h–7BFFFFh 3D8000h–3DFFFFh SA124 1111100xxx 64/32 7C0000h–7CFFFFh 3E0000h–3E7FFFh SA125 1111101xxx 64/32 7D0000h–7DFFFFh 3E8000h–3EFFFFh SA126 1111110xxx 64/32 7E0000h–7EFFFFh 3F0000h–3F7FFFh SA127 1111111000 8/4 7F0000h–7F1FFFh 3F8000h–3F8FFFh SA128 1111111001 8/4 7F2000h–7F3FFFh 3F9000h–3F9FFFh SA129 1111111010 8/4 7F4000h–7F5FFFh 3FA000h–3FAFFFh SA130 1111111011 8/4 7F6000h–7F7FFFh 3FB000h–3FBFFFh SA131 1111111100 8/4 7F8000h–7F9FFFh 3FC000h–3FCFFFh SA132 1111111101 8/4 7FA000h–7FBFFFh 3FD000h–3FDFFFh SA133 1111111110 8/4 7FC000h–7FDFFFh 3FE000h–3FEFFFh SA134 1111111111 8/4 7FE000h–7FFFFFh 3FF000h–3FFFFFh February 1, 2007 26190C8 Am29LV640MT/B 15 D A T A S H E E T Table 3. Am29LV640MB Bottom Boot Sector Architecture 16 Sector Sector Address A21–A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range SA0 0000000000 8/4 000000h–001FFFh 00000h–00FFFh SA1 0000000001 8/4 002000h–003FFFh 01000h–01FFFh SA2 0000000010 8/4 004000h–005FFFh 02000h–02FFFh SA3 0000000011 8/4 006000h–007FFFh 03000h–03FFFh SA4 0000000100 8/4 008000h–009FFFh 04000h–04FFFh SA5 0000000101 8/4 00A000h–00BFFFh 05000h–05FFFh SA6 0000000110 8/4 00C000h–00DFFFh 06000h–06FFFh SA7 0000000111 8/4 00E000h–00FFFFFh 07000h–07FFFh 08000h–0FFFFh SA8 0000001xxx 64/32 010000h–01FFFFh SA9 0000010xxx 64/32 020000h–02FFFFh 10000h–17FFFh SA10 0000011xxx 64/32 030000h–03FFFFh 18000h–1FFFFh SA11 0000100xxx 64/32 040000h–04FFFFh 20000h–27FFFh SA12 0000101xxx 64/32 050000h–05FFFFh 28000h–2FFFFh SA13 0000110xxx 64/32 060000h–06FFFFh 30000h–37FFFh SA14 0000111xxx 64/32 070000h–07FFFFh 38000h–3FFFFh SA15 0001000xxx 64/32 080000h–08FFFFh 40000h–47FFFh SA16 0001001xxx 64/32 090000h–09FFFFh 48000h–4FFFFh SA17 0001010xxx 64/32 0A0000h–0AFFFFh 50000h–57FFFh SA18 0001011xxx 64/32 0B0000h–0BFFFFh 58000h–5FFFFh SA19 0001100xxx 64/32 0C0000h–0CFFFFh 60000h–67FFFh SA20 0001101xxx 64/32 0D0000h–0DFFFFh 68000h–6FFFFh SA21 0001101xxx 64/32 0E0000h–0EFFFFh 70000h–77FFFh SA22 0001111xxx 64/32 0F0000h–0FFFFFh 78000h–7FFFFh SA23 0010000xxx 64/32 100000h–00FFFFh 80000h–87FFFh SA24 0010001xxx 64/32 110000h–11FFFFh 88000h–8FFFFh SA25 0010010xxx 64/32 120000h–12FFFFh 90000h–97FFFh SA26 0010011xxx 64/32 130000h–13FFFFh 98000h–9FFFFh SA27 0010100xxx 64/32 140000h–14FFFFh A0000h–A7FFFh SA28 0010101xxx 64/32 150000h–15FFFFh A8000h–AFFFFh SA29 0010110xxx 64/32 160000h–16FFFFh B0000h–B7FFFh SA30 0010111xxx 64/32 170000h–17FFFFh B8000h–BFFFFh SA31 0011000xxx 64/32 180000h–18FFFFh C0000h–C7FFFh SA32 0011001xxx 64/32 190000h–19FFFFh C8000h–CFFFFh SA33 0011010xxx 64/32 1A0000h–1AFFFFh D0000h–D7FFFh SA34 0011011xxx 64/32 1B0000h–1BFFFFh D8000h–DFFFFh SA35 0011000xxx 64/32 1C0000h–1CFFFFh E0000h–E7FFFh SA36 0011101xxx 64/32 1D0000h–1DFFFFh E8000h–EFFFFh SA37 0011110xxx 64/32 1E0000h–1EFFFFh F0000h–F7FFFh SA38 0011111xxx 64/32 1F0000h–1FFFFFh F8000h–FFFFFh SA39 0100000xxx 64/32 200000h–20FFFFh F9000h–107FFFh SA40 0100001xxx 64/32 210000h–21FFFFh 108000h–10FFFFh SA41 0100010xxx 64/32 220000h–22FFFFh 110000h–117FFFh SA42 0101011xxx 64/32 230000h–23FFFFh 118000h–11FFFFh SA43 0100100xxx 64/32 240000h–24FFFFh 120000h–127FFFh SA44 0100101xxx 64/32 250000h–25FFFFh 128000h–12FFFFh SA45 0100110xxx 64/32 260000h–26FFFFh 130000h–137FFFh SA46 0100111xxx 64/32 270000h–27FFFFh 138000h–13FFFFh SA47 0101000xxx 64/32 280000h–28FFFFh 140000h–147FFFh SA48 0101001xxx 64/32 290000h–29FFFFh 148000h–14FFFFh SA49 0101010xxx 64/32 2A0000h–2AFFFFh 150000h–157FFFh SA50 0101011xxx 64/32 2B0000h–2BFFFFh 158000h–15FFFFh SA51 0101100xxx 64/32 2C0000h–2CFFFFh 160000h–167FFFh SA52 0101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh SA53 0101110xxx 64/32 2E0000h–2EFFFFh 170000h–177FFFh Am29LV640MT/B 26190C8 February 1, 2007 D A T A Table 3. Sector S H E E T Am29LV640MB Bottom Boot Sector Architecture (Continued) Sector Address A21–A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range 178000h–17FFFFh SA54 0101111xxx 64/32 2F0000h–2FFFFFh SA55 0110000xxx 64/32 300000h–30FFFFh 180000h–187FFFh SA56 0110001xxx 64/32 310000h–31FFFFh 188000h–18FFFFh SA57 0110010xxx 64/32 320000h–32FFFFh 190000h–197FFFh SA58 0110011xxx 64/32 330000h–33FFFFh 198000h–19FFFFh SA59 0100100xxx 64/32 340000h–34FFFFh 1A0000h–1A7FFFh SA60 0110101xxx 64/32 350000h–35FFFFh 1A8000h–1AFFFFh SA61 0110110xxx 64/32 360000h–36FFFFh 1B0000h–1B7FFFh SA62 0110111xxx 64/32 370000h–37FFFFh 1B8000h–1BFFFFh SA63 0111000xxx 64/32 380000h–38FFFFh 1C0000h–1C7FFFh SA64 0111001xxx 64/32 390000h–39FFFFh 1C8000h–1CFFFFh SA65 0111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh SA66 0111011xxx 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh SA67 0111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh SA68 0111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh SA69 0111110xxx 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh SA70 0111111xxx 64/32 3F0000h–3FFFFFh 1F8000h–1FFFFFh SA71 1000000xxx 64/32 400000h–40FFFFh 200000h–207FFFh SA72 1000001xxx 64/32 410000h–41FFFFh 208000h–20FFFFh SA73 1000010xxx 64/32 420000h–42FFFFh 210000h–217FFFh SA74 1000011xxx 64/32 430000h–43FFFFh 218000h–21FFFFh SA75 1000100xxx 64/32 440000h–44FFFFh 220000h–227FFFh SA76 1000101xxx 64/32 450000h–45FFFFh 228000h–22FFFFh SA77 1000110xxx 64/32 460000h–46FFFFh 230000h–237FFFh SA78 1000111xxx 64/32 470000h–47FFFFh 238000h–23FFFFh SA79 1001000xxx 64/32 480000h–48FFFFh 240000h–247FFFh SA80 1001001xxx 64/32 490000h–49FFFFh 248000h–24FFFFh SA81 1001010xxx 64/32 4A0000h–4AFFFFh 250000h–257FFFh SA82 1001011xxx 64/32 4B0000h–4BFFFFh 258000h–25FFFFh SA83 1001100xxx 64/32 4C0000h–4CFFFFh 260000h–267FFFh SA84 1001101xxx 64/32 4D0000h–4DFFFFh 268000h–26FFFFh SA85 1001110xxx 64/32 4E0000h–4EFFFFh 270000h–277FFFh SA86 1001111xxx 64/32 4F0000h–4FFFFFh 278000h–27FFFFh SA87 1010000xxx 64/32 500000h–50FFFFh 280000h–28FFFFh SA88 1010001xxx 64/32 510000h–51FFFFh 288000h–28FFFFh SA89 1010010xxx 64/32 520000h–52FFFFh 290000h–297FFFh SA90 1010011xxx 64/32 530000h–53FFFFh 298000h–29FFFFh SA91 1010100xxx 64/32 540000h–54FFFFh 2A0000h–2A7FFFh SA92 1010101xxx 64/32 550000h–55FFFFh 2A8000h–2AFFFFh SA93 1010110xxx 64/32 560000h–56FFFFh 2B0000h–2B7FFFh SA94 1010111xxx 64/32 570000h–57FFFFh 2B8000h–2BFFFFh SA95 1011000xxx 64/32 580000h–58FFFFh 2C0000h–2C7FFFh SA96 1011001xxx 64/32 590000h–59FFFFh 2C8000h–2CFFFFh SA97 1011010xxx 64/32 5A0000h–5AFFFFh 2D0000h–2D7FFFh SA98 1011011xxx 64/32 5B0000h–5BFFFFh 2D8000h–2DFFFFh SA99 1011100xxx 64/32 5C0000h–5CFFFFh 2E0000h–2E7FFFh SA100 1011101xxx 64/32 5D0000h–5DFFFFh 2E8000h–2EFFFFh SA101 1011110xxx 64/32 5E0000h–5EFFFFh 2F0000h–2FFFFFh SA102 1011111xxx 64/32 5F0000h–5FFFFFh 2F8000h–2FFFFFh SA103 1100000xxx 64/32 600000h–60FFFFh 300000h–307FFFh SA104 1100001xxx 64/32 610000h–61FFFFh 308000h–30FFFFh SA105 1100010xxx 64/32 620000h–62FFFFh 310000h–317FFFh SA106 1100011xxx 64/32 630000h–63FFFFh 318000h–31FFFFh SA107 1100100xxx 64/32 640000h–64FFFFh 320000h–327FFFh SA108 1100101xxx 64/32 650000h–65FFFFh 328000h–32FFFFh February 1, 2007 26190C8 Am29LV640MT/B 17 D A T A Table 3. S H E E T Am29LV640MB Bottom Boot Sector Architecture (Continued) Sector Sector Address A21–A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range SA109 1100110xxx 64/32 660000h–66FFFFh 330000h–337FFFh SA110 1100111xxx 64/32 670000h–67FFFFh 338000h–33FFFFh SA111 1101000xxx 64/32 680000h–68FFFFh 340000h–347FFFh SA112 1101001xxx 64/32 690000h–69FFFFh 348000h–34FFFFh SA113 1101010xxx 64/32 6A0000h–6AFFFFh 350000h–357FFFh SA114 1101011xxx 64/32 6B0000h–6BFFFFh 358000h–35FFFFh SA115 1101100xxx 64/32 6C0000h–6CFFFFh 360000h–367FFFh SA116 1101101xxx 64/32 6D0000h–6DFFFFh 368000h–36FFFFh SA117 1101110xxx 64/32 6E0000h–6EFFFFh 370000h–377FFFh SA118 1101111xxx 64/32 6F0000h–6FFFFFh 378000h–37FFFFh SA119 1110000xxx 64/32 700000h–70FFFFh 380000h–387FFFh SA120 1110001xxx 64/32 710000h–71FFFFh 388000h–38FFFFh SA121 1110010xxx 64/32 720000h–72FFFFh 390000h–397FFFh SA122 1110011xxx 64/32 730000h–73FFFFh 398000h–39FFFFh SA123 1110100xxx 64/32 740000h–74FFFFh 3A0000h–3A7FFFh SA124 1110101xxx 64/32 750000h–75FFFFh 3A8000h–3AFFFFh SA125 1110110xxx 64/32 760000h–76FFFFh 3B0000h–3B7FFFh SA126 1110111xxx 64/32 770000h–77FFFFh 3B8000h–3BFFFFh SA127 1111000xxx 64/32 780000h–78FFFFh 3C0000h–3C7FFFh SA128 1111001xxx 64/32 790000h–79FFFFh 3C8000h–3CFFFFh SA129 1111010xxx 64/32 7A0000h–7AFFFFh 3D0000h–3D7FFFh SA130 1111011xxx 64/32 7B0000h–7BFFFFh 3D8000h–3DFFFFh SA131 1111100xxx 64/32 7C0000h–7CFFFFh 3E0000h–3E7FFFh SA132 1111101xxx 64/32 7D0000h–7DFFFFh 3E8000h–3EFFFFh SA133 1111110xxx 64/32 7E0000h–7EFFFFh 3F0000h–3F7FFFh SA134 1111111000 64/32 7F0000h–7FFFFFh 3F8000h–3FFFFFh Note: The address range is A21:A-1 in byte mode (BYTE# = VIL) or A21:A0 in word mode (BYTE# = VIH) 18 Am29LV640MT/B 26190C8 February 1, 2007 D A T A S H E E T Autoselect Mode sector address must appear on the appropriate highest order address bits (see Tables 2 and 3). Table 4 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment can then read the corresponding identifier code on DQ7–DQ0. The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device programmed with its corresponding programming algorithm. However, the autoselect codes can be accessed in-system through the command register. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 12 and Table 13. This method does not require V ID. See Autoselect Command Sequence on page 28 for more information. When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins A6, A3, A2, A1, and A0 must be set as shown in Table 4. In addition, when verifying sector protection, the Table 4. CE# Manufacturer ID: AMD L Device ID Description OE# WE# L H Autoselect Codes, (High Voltage Method) A21 A14 to to A15 A10 X X A8 to A7 A6 A5 to A4 A3 to A2 A1 A0 VID X L X L L L 00 X 01h L L H 22 X 7Eh H H L 22 X 10h Cycle 1 Cycle 2 L L H X X DQ8 to DQ15 A9 VID X L X Cycle 3 BYTE# BYTE# = VIH = VIL DQ7 to DQ0 H H H 22 X 00 (bottom boot) 01h (top boot) Sector Protection Verification L L H SA X VID X L X L H L X X 01h (protected), 00h (unprotected) Secured Silicon Sector Indicator Bit (DQ7), WP# protects top two address sector L L H X X VID X L X L H H X X 98h (factory locked), 18h (not factory locked) Secured Silicon Sector Indicator Bit (DQ7), WP# protects bottom two address sector L L H X X VID X L X L H H X X 88h (factory locked), 08h (not factory locked) Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. February 1, 2007 26190C8 Am29LV640MT/B 19 D A T A Sector Group Protection and Unprotection The hardware sector group protection feature disables both program and erase operations in any sector group. In this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same time (see Tables 5 and 6). The hardware sector group unprotection feature re-enables both program and erase operations in previously protected sector groups. Sector group protection/unprotection can be implemented via two methods. S H E E T Sector A21–A12 Sector/ Sector Block Size SA80-SA83 10100XXXXX 256 (4x64) Kbytes SA84-SA87 10101XXXXX 256 (4x64) Kbytes SA88-SA91 10110XXXXX 256 (4x64) Kbytes SA92-SA95 10111XXXXX 256 (4x64) Kbytes SA96-SA99 11000XXXXX 256 (4x64) Kbytes SA100-SA103 11001XXXXX 256 (4x64) Kbytes SA104-SA107 11010XXXXX 256 (4x64) Kbytes SA108-SA111 11011XXXXX 256 (4x64) Kbytes SA112-SA115 11100XXXXX 256 (4x64) Kbytes SA116-SA119 11101XXXXX 256 (4x64) Kbytes SA120-SA123 11110XXXXX 256 (4x64) Kbytes SA124-SA126 1111100XXX 1111101XXX 1111110XXX 192 (3x64) Kbytes SA127 1111111000 8 Kbytes SA128 1111111001 8 Kbytes The device is shipped with all sector groups unprotected. AMD offers the option of programming and protecting sector groups at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. SA129 1111111010 8 Kbytes SA130 1111111011 8 Kbytes SA131 1111111100 8 Kbytes SA132 1111111101 8 Kbytes SA133 1111111110 8 Kbytes It is possible to determine whether a sector group is protected or unprotected. See Autoselect Mode on page 19 SA134 1111111111 8 Kbytes Sector protection/unprotection requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 24 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector group unprotect, all unprotected sector groups must first be protected prior to the first sector group unprotect write cycle. Table 5. 20 Table 6. Am29LV640MT Top Boot Sector Protection Am29LV640MB Bottom Boot Sector Protection Sector A21–A12 Sector/ Sector Block Size Sector A21–A12 Sector/ Sector Block Size SA0 0000000000 8 Kbytes SA0-SA3 00000XXXXX 256 (4x64) Kbytes SA1 0000000001 8 Kbytes SA4-SA7 00001XXXXX 256 (4x64) Kbytes SA2 0000000010 8 Kbytes SA8-SA11 00010XXXXX 256 (4x64) Kbytes SA3 0000000011 8 Kbytes SA12-SA15 00011XXXXX 256 (4x64) Kbytes SA4 0000000100 8 Kbytes SA16-SA19 00100XXXXX 256 (4x64) Kbytes SA5 0000000101 8 Kbytes SA20-SA23 00101XXXXX 256 (4x64) Kbytes SA6 0000000110 8 Kbytes SA24-SA27 00110XXXXX 256 (4x64) Kbytes SA7 0000000111 8 Kbytes SA28-SA31 00111XXXXX 256 (4x64) Kbytes SA32-SA35 01000XXXXX 256 (4x64) Kbytes SA8–SA10 0000001XXX, 0000010XXX, 0000011XXX, 192 (3x64) Kbytes SA36-SA39 01001XXXXX 256 (4x64) Kbytes SA11–SA14 00001XXXXX 256 (4x64) Kbytes SA40-SA43 01010XXXXX 256 (4x64) Kbytes SA15–SA18 00010XXXXX 256 (4x64) Kbytes SA44-SA47 01011XXXXX 256 (4x64) Kbytes SA19–SA22 00011XXXXX 256 (4x64) Kbytes SA48-SA51 01100XXXXX 256 (4x64) Kbytes SA23–SA26 00100XXXXX 256 (4x64) Kbytes SA52-SA55 01101XXXXX 256 (4x64) Kbytes SA27-SA30 00101XXXXX 256 (4x64) Kbytes SA56-SA59 01110XXXXX 256 (4x64) Kbytes SA31-SA34 00110XXXXX 256 (4x64) Kbytes SA60-SA63 01111XXXXX 256 (4x64) Kbytes SA35-SA38 00111XXXXX 256 (4x64) Kbytes SA64-SA67 10000XXXXX 256 (4x64) Kbytes SA39-SA42 01000XXXXX 256 (4x64) Kbytes SA68-SA71 10001XXXXX 256 (4x64) Kbytes SA43-SA46 01001XXXXX 256 (4x64) Kbytes SA72-SA75 10010XXXXX 256 (4x64) Kbytes SA47-SA50 01010XXXXX 256 (4x64) Kbytes SA76-SA79 10011XXXXX 256 (4x64) Kbytes SA51-SA54 01011XXXXX 256 (4x64) Kbytes Am29LV640MT/B 26190C8 February 1, 2007 D A T A S H E E T Temporary Sector Group Unprotect Table 6. Am29LV640MB Bottom Boot Sector Protection (Continued) Sector A21–A12 Sector/ Sector Block Size SA55–SA58 01100XXXXX 256 (4x64) Kbytes SA59–SA62 01101XXXXX 256 (4x64) Kbytes SA63–SA66 01110XXXXX 256 (4x64) Kbytes SA67–SA70 01111XXXXX 256 (4x64) Kbytes SA71–SA74 10000XXXXX 256 (4x64) Kbytes SA75–SA78 10001XXXXX 256 (4x64) Kbytes SA79–SA82 10010XXXXX 256 (4x64) Kbytes SA83–SA86 10011XXXXX 256 (4x64) Kbytes SA87–SA90 10100XXXXX 256 (4x64) Kbytes SA91–SA94 10101XXXXX 256 (4x64) Kbytes SA95–SA98 10110XXXXX 256 (4x64) Kbytes SA99–SA102 10111XXXXX 256 (4x64) Kbytes SA103–SA106 11000XXXXX 256 (4x64) Kbytes SA107–SA110 11001XXXXX 256 (4x64) Kbytes SA111–SA114 11010XXXXX 256 (4x64) Kbytes SA115–SA118 11011XXXXX 256 (4x64) Kbytes SA119–SA122 11100XXXXX 256 (4x64) Kbytes SA123–SA126 11101XXXXX 256 (4x64) Kbytes SA127–SA130 11110XXXXX 256 (4x64) Kbytes SA131–SA134 11111XXXXX 256 (4x64) Kbytes (Note: In this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same time (see Table 6). This feature allows temporary unprotection of previously protected sector groups to change data in-system. The Sector Group Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once VID is removed from the RESET# pin, all the previously protected sector groups are protected again. Figure 1 shows the algorithm, and Figure 23 shows the timing diagrams, for this feature. START RESET# = VID (Note 1) Perform Erase or Program Operations RESET# = VIH Write Protect (WP#) The Write Protect function provides a hardware method of protecting the top two or bottom two sectors without using VID. WP# is one of two functions provided by the WP#/ACC input. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the first or last sector independently of whether those sectors were protected or unprotected using the method described in Sector Group Protection and Unprotection. Note that if WP#/ACC is at VIL when the device is in the standby mode, the maximum input load current is increased. See the table in DC Characteristics. Temporary Sector Group Unprotect Completed (Note 2) Notes: 1. All protected sector groups unprotected (If WP# = VIL, the first or last sector remain protected). 2. All previously protected sector groups are protected once again. If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the top or bottom two sectors were previously set to be protected or unprotected using the method described in Sector Group Protection and Unprotection. Note: No external pullup is necessary since the WP#/ACC pin has internal pullup to VCC February 1, 2007 26190C8 Am29LV640MT/B Figure 1. Temporary Sector Group Unprotect Operation 21 D A T A S H E E T START START PLSCNT = 1 RESET# = VID Wait 1 μs Temporary Sector Group Unprotect Mode No PLSCNT = 1 Protect all sector groups: The indicated portion of the sector group protect algorithm must be performed for all unprotected sector groups prior to issuing the first sector group unprotect address RESET# = VID Wait 1 μs First Write Cycle = 60h? First Write Cycle = 60h? Temporary Sector Group Unprotect Mode Yes Yes Set up sector group address No All sector groups protected? Yes Sector Group Protect: Write 60h to sector group address with A6–A0 = 0xx0010 Set up first sector group address Sector Group Unprotect: Write 60h to sector group address with A6–A0 = 1xx0010 Wait 150 µs Verify Sector Group Protect: Write 40h to sector group address with A6–A0 = 0xx0010 Increment PLSCNT No Reset PLSCNT = 1 Read from sector group address with A6–A0 = 0xx0010 Wait 15 ms Verify Sector Group Unprotect: Write 40h to sector group address with A6–A0 = 1xx0010 Increment PLSCNT No No PLSCNT = 25? Read from sector group address with A6–A0 = 1xx0010 Data = 01h? Yes No Yes Device failed Protect another sector group? Yes PLSCNT = 1000? No Yes Remove VID from RESET# Device failed Write reset command Sector Group Protect Algorithm Set up next sector group address No Data = 00h? Yes Last sector group verified? No Yes Sector Group Protect complete Sector Group Unprotect Algorithm Remove VID from RESET# Write reset command Sector Group Unprotect complete Figure 2. 22 In-System Sector Group Protect/Unprotect Algorithms Am29LV640MT/B 26190C8 February 1, 2007 D A T A S H E E T Secured Silicon Sector Flash Memory Region Factory Locked: Secured Silicon Sector Programmed and Protected At the Factory The Secured Silicon Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 128 words/256 bytes in length, and uses a Secured Silicon Sector Indicator Bit (DQ7) to indicate whether or not the Secured Silicon Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. In devices with an ESN, the Secured Silicon Sector is protected when the device is shipped from the factory. The Secured Silicon Sector cannot be modified in any way. See Table 7 for Secured Silicon Sector addressing. AMD offers the device with the Secured Silicon Sector either factory locked or customer lockable. The factory-locked version is always protected when shipped from the factory, and has the Secured Silicon Sector Indicator Bit per manently set to a “1.” The customer-lockable version is shipped with the Secured Silicon Sector unprotected, allowing customers to program the sector after receiving the device. The customer-lockable version also has the Secured Silicon Sector Indicator Bit permanently set to a “0.” Thus, the Secured Silicon Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. The Secured Silicon sector address space in this device is allocated as follows: Table 7. Secured Silicon Sector Contents Secured Silicon Sector Address Range Standard Factory Locked ExpressFlash Factory Locked x16 x8 000000h– 000007h 000000h– 00000Fh ESN ESN or determined by customer 000008h– 00007Fh 000010h– 0000FFh Unavailable Determined by customer Customer Lockable Determined by customer The system accesses the Secured Silicon Sector through a command sequence. See Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence on page 28 After the system has written the Enter Secured Silicon Sector command sequence, it can read the Secured Silicon Sector by using the addresses normally occupied by the first sector (SA0). This mode of operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to sector SA0. Note that the ACC function and unlock bypass modes are not available when the Secured Silicon Sector is enabled. February 1, 2007 26190C8 Customers can opt to have their code programmed by AMD through the AMD ExpressFlash service. The devices are then shipped from AMD’s factory with the Secured Silicon Sector permanently locked. Contact an AMD representative for details on using AMD’s ExpressFlash service. Customer Lockable: Secured Silicon Sector NOT Programmed or Protected At the Factory As an alternative to the factory-locked version, the device can be ordered such that the customer can program and protect the 128-word/256 bytes Secured Silicon sector. The system can program the Secured Silicon Sector using the write-buffer, accelerated and/or unlock bypass methods, in addition to the standard programming command sequence. See Command Definitions on page 27 Programming and protecting the Secured Silicon Sector must be used with caution since, once protected, there is no procedure available for unprotecting the Secured Silicon Sector area and none of the bits in the Secured Silicon Sector memory space can be modified in any way. The Secured Silicon Sector area can be protected using one of the following procedures: ■ Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, except that RESET# can be at either VIH or VID. This allows in-system protection of the Secured Silicon Sector without raising any device pin to a high voltage. Note that this method is only applicable to the Secured Silicon Sector. ■ To verify the protect/unprotect status of the Secured Silicon Sector, follow the algorithm shown in Figure 3. Once the Secured Silicon Sector is programmed, locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence to return to reading and writing within the remainder of the array. Am29LV640MT/B 23 D A T A S H E E T hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. START RESET# = VIH or VID Wait 1 ms Write 60h to any address If data = 00h, SecSi Sector is unprotected. If data = 01h, SecSi Sector is protected. Remove VIH or VID from RESET# Write 40h to SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Read from SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Figure 3. Low VCC Write Inhibit Write reset command When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. SecSi Sector Protect Verify complete Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Secured Silicon Sector Protect Verify Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Tables 12 and 13 for command definitions). In addition, the following Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 8–11. To terminate reading CFI data, the system must write the reset command. 24 The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 8–11. The system must write the reset command to return the device to reading array data. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alternatively, contact an AMD representative for copies of these documents. Am29LV640MT/B 26190C8 February 1, 2007 D A T A Table 8. S H E E T CFI Query Identification String Addresses (x16) Addresses (x8) Data 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h Query Unique ASCII string “QRY” 13h 14h 26h 28h 0002h 0000h Primary OEM Command Set 15h 16h 2Ah 2Ch 0040h 0000h Address for Primary Extended Table 17h 18h 2Eh 30h 0000h 0000h Alternate OEM Command Set (00h = none exists) 19h 1Ah 32h 34h 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) Description Table 9. System Interface String Addresses (x16) Addresses (x8) Data 1Bh 36h 0027h VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Ch 38h 0036h VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Dh 3Ah 0000h VPP Min. voltage (00h = no VPP pin present) 1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP pin present) 1Fh 3Eh 0007h Typical timeout per single byte/word write 2N µs 20h 40h 0007h Typical timeout for Min. size buffer write 2N µs (00h = not supported) 21h 42h 000Ah Typical timeout per individual block erase 2N ms 22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported) 23h 46h 0001h Max. timeout for byte/word write 2N times typical 24h 48h 0005h Max. timeout for buffer write 2N times typical 25h 4Ah 0004h Max. timeout per individual block erase 2N times typical 26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported) February 1, 2007 26190C8 Description Am29LV640MT/B 25 D A T A Table 10. S H E E T Device Geometry Definition Addresses (x16) Addresses (x8) Data 27h 4Eh 0017h Device Size = 2N byte 28h 29h 50h 52h 0002h 0000h Flash Device Interface description (refer to CFI publication 100) 2Ah 2Bh 54h 56h 0005h 0000h Max. number of byte in multi-byte write = 2N (00h = not supported) 2Ch 58h 0002h Number of Erase Block Regions within device (01h = uniform device, 02h = boot device) 2Dh 2Eh 2Fh 30h 5Ah 5Ch 5Eh 60h 007Fh 0000h 0020h 0000h Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 007Eh 0000h 0000h 0001h Erase Block Region 2 Information (refer to CFI publication 100) 35h 36h 37h 38h 6Ah 6Ch 6Eh 70h 0000h 0000h 0000h 0000h Erase Block Region 3 Information (refer to CFI publication 100) 39h 3Ah 3Bh 3Ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h Erase Block Region 4 Information (refer to CFI publication 100) 26 Description Am29LV640MT/B 26190C8 February 1, 2007 D A T A Table 11. S H E E T Primary Vendor-Specific Extended Query Addresses (x16) Addresses (x8) Data 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h Query-unique ASCII string “PRI” 43h 86h 0031h Major version number, ASCII 44h 88h 0033h Minor version number, ASCII 45h 8Ah 0008h Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Description Process Technology (Bits 7-2) 0010b = 0.23 µm MirrorBit 46h 8Ch 0002h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 8Eh 0001h Sector Protect 0 = Not Supported, X = Number of sectors in per group 48h 90h 0001h Sector Temporary Unprotect 00 = Not Supported, 01 = Supported 49h 92h 0004h Sector Protect/Unprotect scheme 04 = 29LV800 mode 4Ah 94h 0000h Simultaneous Operation 00 = Not Supported, X = Number of Sectors in Bank 4Bh 96h 0000h Burst Mode Type 00 = Not Supported, 01 = Supported 4Ch 98h 0001h Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page 4Dh 9Ah 00B5h 4Eh 9Ch 00C5h ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 4Fh 9Eh 0002h/ 0003h 50h A0h 0001h 00h = Uniform Device without WP# protect, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top WP# protect Program Suspend 00h = Not Supported, 01h = Supported COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Tables 12 and 13 define the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence can place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens February 1, 2007 26190C8 first. See AC Characteristics on page 45 for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after Am29LV640MT/B 27 D A T A which the system can read data from any non-erase-suspended sector. After completing a programming operation in the Erase Suspend mode, the system can once again read array data with the same exception. See Erase Suspend/Erase Resume Commands on page 35 for more information. The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the device is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data on page 11 in Device Bus Operations for more information. See the table, Read-Only Operations on page 45 for the read parameters, and Figure 14 for the timing diagram. Reset Command Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command can be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command can be written between the sequence cycles in a program command sequence before programming begins. This resets the device to the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command can be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the device entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend). Note that if DQ1 goes high during a Write Buffer Programming operation, the system must write the 28 S H E E T Write-to-Buffer-Abort Reset command sequence to reset the device for the next operation. Autoselect Command Sequence The autoselect command sequence allows the host system to read several identifier codes at specific addresses: A7:A0 (x16) Identifier Code A6:A-1 (x8) Manufacturer ID 00h 00h Device ID, Cycle 1 01h 02h Device ID, Cycle 2 0Eh 1Ch Device ID, Cycle 3 0Fh 1Eh Secured Silicon Sector Factory Protect 03h 06h Sector Protect Verify (SA)02h (SA)04h Note: The device ID is read over three cycles. SA = Sector Address Tables 12 and 13 show the address and data requirements. This method is an alternative to that shown in Table 4, which is intended for PROM programmers and requires VID on address pin A9. The autoselect command sequence can be written to an address that is either in the read or erase-suspend-read mode. The autoselect command cannot be written while the device is actively programming or erasing. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the autoselect command. The device then enters the autoselect mode. The system can read at any address any number of times without initiating another autoselect command sequence. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the device was previously in Erase Suspend). Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence The Secured Silicon Sector region provides a secured data area containing an 8-word/16-byte random Electronic Serial Number (ESN). The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence. The Exit Secured Silicon Sector command sequence returns the device to normal operation. Tables 12 and 13 show the address and data requirements for both command sequences. See also Secured Silicon Sector Flash Memory Region for further information. Am29LV640MT/B 26190C8 February 1, 2007 D A T A Word/Byte Program Command Sequence Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Tables 12 and 13 show the address and data requirements for the word program command sequence. Note that the autoselect and CFI functions are unavailable when a program operation is in progress. When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. See Write Operation Status on page 38 for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so can cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read shows that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to program words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Tables 12 and 13 show the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands February 1, 2007 26190C8 S H E E T are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h. The second cycle must contain the data 00h. The device then returns to the read mode. Write Buffer Programming Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming occurs. The fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. For example, if the system programs six unique address locations, then 05h should be written to the device. This tells the device how many write buffer addresses are loaded with data and therefore when to expect the Program Buffer to Flash command. The number of locations to program cannot exceed the size of the write buffer or the operation aborts. The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is selected by address bits AMAX–A 4. All subsequent add r e s s / d a t a p a i r s m u s t fa l l w i t h i n t h e selected-write-buffer-page. The system then writes the remaining address/data pairs into the write buffer. Write buffer locations can be loaded in any order. The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple write-buffer pages. This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer page, the operation aborts. Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter is decremented for every data load operation. The host system must therefore account for loading a write-buffer location more than once. The counter decrements for each data load operation, not for each unique write-buffer-address location. Also note, if an address location is loaded more than once into the buffer, the final data loaded for that address is programmed. Once the specified number of write buffer locations have been loaded, the system must then write the Program Buffer to Flash command at the sector address. Any other address and data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last address location loaded into Am29LV640MT/B 29 D A T A the write buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer programming operation can be suspended using the standard program suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command. The Write Buffer Programming Sequence can be aborted in the following ways: ■ Load a value that is greater than the page buffer size during the Number of Locations to Program step. ■ Write to an address in a sector different than the one specified during the Write-Buffer-Load command. ■ Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data loading stage of the operation. ■ Write data other than the Confirm Command after the specified number of data load cycles. 30 S H E E T The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded), DQ6 = toggle, and DQ5=0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the device for the next operation. Note that the full 3-cycle Write-to-Buffer-Abort Reset command sequence is required when using Write-Buffer-Programming features in Unlock Bypass mode. Accelerated Program The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system can then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at VHH for operations other than accelerated programming, or device damage can result. In addition, no external pullup is necessary since the WP#/ACC pin has internal pullup to VCC. Figure 5 illustrates the algorithm for the program operation. See the table, Erase and Program Operations on page 48 in AC Characteristics for parameters, and Figure 17 for timing diagrams. Am29LV640MT/B 26190C8 February 1, 2007 D A T A S H E E T Write “Write to Buffer” command and Sector Address Part of “Write to Buffer” Command Sequence Write number of addresses to program minus 1(WC) and Sector Address Write first address/data Yes WC = 0 ? No Write to a different sector address Abort Write to Buffer Operation? Yes Write to buffer ABORTED. Must write “Write-to-buffer Abort Reset” command sequence to return to read mode. No (Note 1) Write next address/data pair WC = WC - 1 Write program buffer to flash sector address Notes: Read DQ7 - DQ0 at Last Loaded Address When Sector Address is specified, any address in the selected sector is acceptable. However, when loading Write-Buffer address locations with data, all addresses must fall within the selected Write-Buffer Page. 2. DQ7 can change simultaneously with DQ5. Therefore, verify DQ7 . 3. If this flowchart location was reached because DQ5= “1”, then the device FAILED. If this flowchart location was reached because DQ1= “1”, then the Write to Buffer operation was ABORTED. In either case, the proper reset command must write before the device can begin another operation. If DQ1=1, write the Write-Buffer-Programming-Abort-Reset command. if DQ5=1, write the Reset command. 4. See Table 13 for command sequences required for write buffer programming. Yes DQ7 = Data? No 1. No No DQ1 = 1? DQ5 = 1? Yes Yes Read DQ7 - DQ0 with address = Last Loaded Address (Note 2) DQ7 = Data? Yes No (Note 3) FAIL or ABORT Figure 4. February 1, 2007 26190C8 PASS Write Buffer Programming Operation Am29LV640MT/B 31 D A T A S H E E T Program Suspend/Program Resume Command Sequence The Program Suspend command allows the system to interrupt a programming operation or a Write to Buffer programming operation so that data can be read from any non-suspended sector. When the Program Suspend command is written during a programming process, the device halts the program operation within 15 μs maximum (5 μs typical) and updates the status bits. Addresses are not required when writing the Program Suspend command. START Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Yes Increment Address No Last Address? Yes Programming Completed Note: See Table 13 for program command sequence. Figure 5. 32 Program Operation After the programming operation has been suspended, the system can read array data from any non-suspended sector. The Program Suspend command can also be issued during a programming operation while an erase is suspended. In this case, data can be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector area (One-time Program area), then user must use the proper command sequences to enter and exit this region. The system can also write the autoselect command sequence when the device is in the Program Suspend mode. The system can read as many autoselect codes as required. When the device exits the autoselect mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence on page 28 for more information. After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status on page 38 for more information. Am29LV640MT/B 26190C8 February 1, 2007 D A T A The system must write the Program Resume command (address bits are don’t care) to exit the Program Suspend mode and continue the programming operation. Further writes of the Resume command are ignored. Another Program Suspend command can be written after the device has resume programming. Write Program Suspend Command Sequence Figure 7 illustrates the algorithm for the erase operation. See the table, Erase and Program Operations on page 48 in AC Characteristics for parameters, and Figure 19 for timing diagrams. Command is also valid for Erase-suspended-program operations Wait 15 μs Read data as required No Autoselect and SecSi Sector read operations are also allowed Data cannot be read from erase- or program-suspended sectors Done reading? Yes Write address/data XXXh/30h Write Program Resume Command Sequence Device reverts to operation prior to Program Suspend Figure 6. Program Suspend/Program Resume Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Tables 12 and 13 shows the address and data requirements for the chip erase command sequence. Note that the autoselect and CFI functions are unavailable when an erase operation is in progress. February 1, 2007 26190C8 When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See Write Operation Status on page 38 for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Program Operation or Write-to-Buffer Sequence in Progress Write address/data XXXh/B0h S H E E T Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Tables 12 and 13 shows the address and data requirements for the sector erase command sequence. Note that the autoselect and CFI functions are unavailable when an erase operation is in progress. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period, additional sector addresses and sector erase commands can be written. Loading the sector erase buffer can be done in any sequence, and the number of sectors can be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise erasure can begin. Any sector erase address and command following the exceeded time-out might or might not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to the read mode. The system must rewrite the command sequence and any additional addresses and commands. Am29LV640MT/B 33 D A T A S H E E T The system can monitor DQ3 to determine if the sector erase timer has timed out. See DQ3: Sector Erase Timer on page 41. The time-out begins from the rising e d g e o f t h e f i n a l W E # p u l s e in t h e c o m m a n d sequence. START When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by reading DQ7, DQ6, or DQ2 in the erasing sector. See Write Operation Status on page 38 for information on these status bits. Write Erase Command Sequence (Notes 1, 2) Data Poll to Erasing Bank from System Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. No Figure 7 illustrates the algorithm for the erase operation. See the table, Erase and Program Operations on page 48 in AC Characteristics for parameters, and Figure 19 for timing diagrams. Embedded Erase algorithm in progress Data = FFh? Yes Erasure Completed Notes: 1. See Table 12 and Table 13 for erase command sequence. 2. See DQ3: Sector Erase Timer on page 41 for information on the sector erase timer. Figure 7. 34 Am29LV640MT/B Erase Operation 26190C8 February 1, 2007 D A T A S H E E T Erase Suspend/Erase Resume Commands lect Mode on page 19 and Autoselect Command Sequence on page 28 for details. The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. To resume the sector erase operation, the system must write the Erase Resume command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. When the Erase Suspend command is written during the sector erase operation, the device requires a typical of 5 µs (maximum of 20 µs) to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the device enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See Write Operation Status on page 38 for information on these status bits. Note: During an erase operation, this flash device performs multiple internal operations which are invisible to the system. When an erase operation is suspended, any of the internal operations that were not fully completed must be restarted. As such, if this flash device is continually issued suspend/resume commands in rapid succession, erase progress is impeded as a function of the number of suspends. The result is a longer cumulative erase time than without suspends. Note that the additional suspends do not affect device reliability or future performance. In most systems rapid erase/suspend activity occurs only briefly. In such cases, erase performance is not significantly impacted. After an erase-suspended program operation is complete, the device returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard word program operation. See Write Operation Status on page 38 for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. See Autose- February 1, 2007 26190C8 Am29LV640MT/B 35 D A T A S H E E T Command Definitions Table 12. Command Definitions (x16 Mode, BYTE# = VIH) Cycles Bus Cycles (Notes 1–4) Addr Read (Note 5) 1 RA Reset (Note 6) Autoselect (Note 7) Command Sequence (Notes) First Second Data RD Third Fourth Fifth Addr Data Addr Data Addr Data 1 XXX F0 Manufacturer ID 4 555 AA 2AA 55 555 90 X00 0001 Device ID (Note 8) 6 555 AA 2AA 55 555 90 X01 227E Secured Silicon Sector Factory Protect (Note 9) 4 555 AA 2AA 55 555 90 X03 (Note 9) Sector Group Protect Verify (Note 10) 4 555 AA 2AA 55 555 90 (SA)X02 00/01 88 Sixth Addr Data Addr Data X0E 2210 X0F 2200/ 2201 PD Enter Secured Silicon Sector Region 3 555 AA 2AA 55 555 Exit Secured Silicon Sector Region 4 555 AA 2AA 55 555 90 XXX 00 Program 4 555 AA 2AA 55 555 A0 PA PD Write to Buffer (Note 11) 6 555 AA 2AA 55 SA 25 SA WC PA PD WBL Program Buffer to Flash 1 SA 29 Write to Buffer Abort Reset (Note 12) 3 555 AA 2AA 55 555 F0 Unlock Bypass 3 555 AA 2AA 55 555 20 Unlock Bypass Program (Note 13) 2 XXX A0 PA PD Unlock Bypass Reset (Note 14) 2 XXX 90 XXX 00 Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30 Program/Erase Suspend (Note 15) 1 XXX B0 Program/Erase Resume (Note 16) 1 XXX 30 CFI Query (Note 17) 1 55 98 Legend: X = Don’t care RA = Read Address of the memory location to be read. RD = Read Data read from location RA during read operation. PA = Program Address. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Program Data for location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. Notes: 1. See Table 1 for description of bus operations. SA = Sector Address of sector to be verified (in autoselect mode) or erased. Address bits A21–A15 uniquely select any sector. WBL = Write Buffer Location. Address must be within the same write buffer page as PA. WC = Word Count. Number of write buffer locations to load minus 1. bottom two address sectors, the data is 88h for factory locked and 08h for not factor locked. 2. All values are in hexadecimal. 3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 10. The data is 00h for an unprotected sector group and 01h for a protected sector group. 4. During unlock cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. 5. No unlock or command cycles required when device is in read mode. 11. The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum number of cycles in the command sequence is 21, including "Program Buffer to Flash" command. 6. 7. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when the device is in the autoselect mode, or if DQ5 goes high while the device is providing status information. The fourth cycle of the autoselect command sequence is a read cycle. Data bits DQ15–DQ8 are don’t care. Except RD, PD and WC. See Autoselect Command Sequence on page 28 for more information. 8. The device ID must be read in three cycles. The data is 2201h for top boot and 2200h for bottom boot. 9. If WP# protects the top two address sectors, the data is 98h for factory locked and 18h for not factory locked. If WP# protects the 36 12. Command sequence resets device for next command after aborted write-to-buffer operation. 13. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 14. The Unlock Bypass Reset command is required to return to the read mode when the device is in the unlock bypass mode. 15. The system can read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 16. The Erase Resume command is valid only during the Erase Suspend mode. 17. Command is valid when device is ready to read array data or when device is in autoselect mode. Am29LV640MT/B 26190C8 February 1, 2007 D A T A Table 13. Command Definitions (x8 Mode, BYTE# = VIL) Cycles Bus Cycles (Notes 1–4) Addr Read (Note 5) 1 RA Reset (Note 6) Autoselect (Note 7) Command Sequence (Notes) S H E E T First Second Data RD Addr Data Third Addr Fourth Data Addr Fifth Data 1 XXX F0 Manufacturer ID 4 AAA AA 555 55 AAA 90 X00 01 Device ID (Note 8) 6 AAA AA 555 55 AAA 90 X02 7E Secured Silicon Sector Factory Protect (Note 9) 4 AAA AA 555 55 AAA 90 X06 (Note 9) Sector Group Protect Verify (Note 10) 4 AAA AA 555 55 AAA 90 (SA)X04 00/01 Sixth Addr Data Addr Data X1C 10 X1E 00/01 PA PD WBL PD Enter Secured Silicon Sector Region 3 AAA AA 555 55 AAA 88 Exit Secured Silicon Sector Region 4 AAA AA 555 55 AAA 90 XXX 00 Program 4 AAA AA 555 55 AAA A0 PA PD Write to Buffer (Note 11) 6 AAA AA 555 55 SA 25 SA BC Program Buffer to Flash 1 SA 29 Write to Buffer Abort Reset (Note 12) 3 AAA AA 555 55 AAA F0 Unlock Bypass 3 AAA AA 555 55 AAA 20 Unlock Bypass Program (Note 13) 2 XXX A0 PA PD Unlock Bypass Reset (Note 14) 2 XXX 90 XXX 00 Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10 Sector Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 SA 30 Program/Erase Suspend (Note 15) 1 XXX B0 Program/Erase Resume (Note 16) 1 XXX 30 CFI Query (Note 17) 1 AA 98 Legend: X = Don’t care RA = Read Address of the memory location to be read. RD = Read Data read from location RA during read operation. PA = Program Address. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Program Data for location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. SA = Sector Address of sector to be verified (in autoselect mode) or erased. Address bits A21–A15 uniquely select any sector. WBL = Write Buffer Location. Address must be within the same write buffer page as PA. BC = Byte Count. Number of write buffer locations to load minus 1. 10. The data is 00h for an unprotected sector group and 01h for a protected sector group. 3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. During unlock cycles, when lower address bits are 555 or AAAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. 5. No unlock or command cycles required when device is in read mode. 6. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when the device is in the autoselect mode, or if DQ5 goes high while the device is providing status information. 11. The total number of cycles in the command sequence is determined by the number of bytes written to the write buffer. The maximum number of cycles in the command sequence is 37, including "Program Buffer to Flash" command. 12. Command sequence resets device for next command after aborted write-to-buffer operation. 13. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 14. The Unlock Bypass Reset command is required to return to the read mode when the device is in the unlock bypass mode. 7. The fourth cycle of the autoselect command sequence is a read cycle. Data bits DQ15–DQ8 are don’t care. See Autoselect Command Sequence on page 28 for more information. 15. The system can read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 8. The device ID must be read in three cycles. The data is 01h for top boot and 00h for bottom boot 16. The Erase Resume command is valid only during the Erase Suspend mode. 9. If WP# protects the top two address sectors, the data is 98h for factory locked and 18h for not factory locked. If WP# protects the bottom two address sectors, the data is 88h for factory locked and 08h for not factor locked. 17. Command is valid when device is ready to read array data or when device is in autoselect mode. February 1, 2007 26190C8 Am29LV640MT/B 37 D A T A S H E E T WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 14 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed. valid data, the data outputs on DQ0–DQ6 might be still invalid. Valid data on DQ0–DQ7 appears on successive read cycles. Table 14 shows the outputs for Data# Polling on DQ7. Figure 8 shows the Data# Polling algorithm. Figure 20 in AC Characteristics shows the Data# Polling timing diagram. DQ7: Data# Polling START The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to the read mode. Read DQ7–DQ0 Addr = VA DQ7 = Data? No No During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status might not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 can change asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low. That is, the device can change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it can read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has 38 Yes DQ5 = 1? Yes Read DQ7–DQ0 Addr = VA DQ7 = Data? Yes No FAIL PASS Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. Recheck DQ7 even if DQ5 = “1” because DQ7 can change simultaneously with DQ5. Am29LV640MT/B Figure 8. Data# Polling Algorithm 26190C8 February 1, 2007 D A T A RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. Table 14 shows the outputs for RY/BY#. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I can be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system can use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. February 1, 2007 26190C8 S H E E T After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7. See DQ7: Data# Polling on page 38). If a program address falls within a protected sector, DQ6 toggles for approximately 1 μs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 14 shows the outputs for Toggle Bit I on DQ6. Figure 9 shows the toggle bit algorithm. Figure 21 in AC Characteristics shows the toggle bit timing diagrams. Figure 22 shows the differences between DQ2 and DQ6 in graphical form. See also DQ2: Toggle Bit II on page 40. Am29LV640MT/B 39 D A T A S H E E T DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. START Read DQ7–DQ0 DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system can use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 14 to compare outputs for DQ2 and DQ6. Read DQ7–DQ0 Toggle Bit = Toggle? No Yes No Figure 9 shows the toggle bit algorithm in flowchart form, and DQ2: Toggle Bit II on page 40 explains the algor ithm. See also RY/BY#: Ready/Busy# on page 39. Figure 21 shows the toggle bit timing diagram. Figure 22 shows the differences between DQ2 and DQ6 in graphical form. DQ5 = 1? Yes Read DQ7–DQ0 Twice Toggle Bit = Toggle? Reading Toggle Bits DQ6/DQ2 No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit can stop toggling as DQ5 changes to “1.” See DQ6: Toggle Bit I and DQ2: Toggle Bit II for more information. Figure 9. Toggle Bit Algorithm Refer to Figure 9 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high. (See DQ2: Toggle Bit II on page 40.) If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit might have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system can continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it can choose to perform 40 Am29LV640MT/B 26190C8 February 1, 2007 D A T A other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 9). DQ5: Exceeded Timing Limits DQ5 indicates whether the program, erase, or write-to-buffer time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. The device might output a “1” on DQ5 if the system tries to program a “1” to a location that was previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” In all these cases, the system must write the reset command to return the device to the reading the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode). S H E E T switches from a “0” to a “1.” If the time between additional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See also Sector Erase Command Sequence on page 33 . After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device accepts additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 14 shows the status of DQ3 relative to the other status bits. DQ3: Sector Erase Timer DQ1: Write-to-Buffer Abort After writing a sector erase command sequence, the system can read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a “1”. The system must issue the Write-to-Buffer-Abort-Reset command sequence to return the device to reading array data. See Write Buffer Programming on page 29 for more details. Table 14. Standard Mode Program Suspend Mode Erase Suspend Mode Write-toBuffer Write Operation Status DQ7 Status (Note 2) Embedded Program Algorithm DQ7# Embedded Erase Algorithm 0 Program-Suspended Program- Sector Suspend Non-Program Read Suspended Sector Erase-Suspended 1 EraseSector Suspend Non-Erase Suspended Read Sector Erase-Suspend-Program DQ7# (Embedded Program) Busy (Note 3) DQ7# Abort (Note 4) DQ7# DQ6 Toggle Toggle No toggle DQ5 (Note 1) 0 0 DQ3 N/A 1 DQ2 (Note 2) No toggle Toggle DQ1 0 N/A RY/BY# 0 0 Invalid (not allowed) 1 Data 1 0 N/A Toggle N/A Data 1 1 Toggle 0 N/A N/A N/A 0 Toggle Toggle 0 0 N/A N/A N/A N/A 0 1 0 0 Notes: 1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the maximum timing limits. See DQ5: Exceeded Timing Limits for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location. 4. DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation. February 1, 2007 26190C8 Am29LV640MT/B 41 D A T A S H E E T ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied. . . . . . . . . . . . . . –65°C to +125°C Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . . –0.5 V to +4.0 V 20 ns 20 ns +0.8 V –0.5 V –2.0 V VIO . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.0 V 20 ns A9, OE#, ACC, and RESET# (Note 2) . . . . . . . . . . . . . . . . . . . . –0.5 V to +12.5 V Figure 10. Maximum Negative Overshoot Waveform All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. Dur ing voltage transitions, input or I/O pins can overshoot V SS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. See Figure 10. During voltage transitions, input or I/O pins can overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 11. 2. Minimum DC input voltage on pins A9, OE#, ACC, and RESET# is –0.5 V. During voltage transitions, A9, OE#, ACC, and RESET# can overshoot V SS to –2.0 V for periods of up to 20 ns. See Figure 10. Maximum DC input voltage on pin A9, OE#, ACC, and RESET# is +12.5 V which can overshoot to +14.0 V for periods up to 20 ns. 20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns Figure 11. Maximum Positive Overshoot Waveform 3. No more than one output can be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under “Absolute Maximum Ratings” can cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods can affect device reliability. OPERATING RANGES Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C Supply Voltages VCC for full voltage range . . . . . . . . . . . . . . . 2.7–3.6 V VCC for regulated voltage range . . . . . . . . . . 3.0–3.6 V Note: Operating ranges define those limits between which the functionality of the device is guaranteed. 42 Am29LV640MT/B 26190C8 February 1, 2007 D A T A S H E E T DC CHARACTERISTICS CMOS Compatible Parameter Symbol Parameter Description (Notes) Test Conditions ILI Input Load Current (1) VIN = VSS to VCC, VCC = VCC max ILIT A9, ACC Input Load Current VCC = VCC max; A9 = 12.5 V ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ILR Reset Leakage Current VCC = VCC max; RESET= 12.5 V ICC1 VCC Active Read Current (2, 3) CE# = VIL, OE# = VIH, ICC2 VCC Initial Page Read Current (2, 3) ICC3 Min Typ Max Unit ±1.0 µA 35 µA ±1.0 µA 35 µA 5 MHz 15 20 1 MHz 15 20 CE# = VIL, OE# = VIH 30 50 mA VCC Intra-Page Read Current (2, 3) CE# = VIL, OE# = VIH 10 20 mA ICC4 VCC Active Write Current (3, 4) CE# = VIL, OE# = VIH 50 60 mA ICC5 VCC Standby Current (3) CE#, RESET# = VCC ± 0.3 V, WP# = VIH 1 5 µA ICC6 VCC Reset Current (3) RESET# = VSS ± 0.3 V, WP# = VIH 1 5 µA ICC7 Automatic Sleep Mode (3, 5) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V, WP# = VIH 1 5 µA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 1.9 VCC + 0.5 V VID Voltage for Autoselect and Temporary VCC = 2.7 –3.6 V Sector Unprotect 11.5 12.5 V VOL Output Low Voltage 0.15 x VCC V VOH1 VOH2 VLKO Output High Voltage IOL = 4.0 mA, VCC = VCC min mA IOH = –2.0 mA, VCC = VCC min 0.85 VCC V IOH = –100 µA, VCC = VCC min VCC–0.4 V Low VCC Lock-Out Voltage (6) 2.3 2.5 V Notes: 1. On the WP#/ACC pin only, the maximum input load current when WP# = VIL is ± 5.0 µA. 4. ICC active while Embedded Erase or Embedded Program is in progress. 2. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. 3. Maximum ICC specifications are tested with VCC = VCCmax. 6. Not 100% tested. 7. Includes RY/BY# February 1, 2007 26190C8 Am29LV640MT/B 43 D A T A S H E E T TEST CONDITIONS Table 15. 3.3 V Test Condition 2.7 kΩ Device Under Test CL Test Specifications 6.2 kΩ All Speeds Output Load 1 TTL gate Output Load Capacitance, CL (including jig capacitance) 30 pF Input Rise and Fall Times 5 ns 0.0–3.0 V Input timing measurement reference levels (See Note) 1.5 V Output timing measurement reference levels 0.5 VIO V Input Pulse Levels Note: Diodes are IN3064 or equivalent Figure 12. Test Setup Unit Note: If VIO < VCC, the reference level is 0.5 VIO. KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H 3.0 V Input Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) 1.5 V Measurement Level 0.5 VIO V Output 0.0 V Note: If VIO < VCC, the input measurement reference level is 0.5 VIO. Figure 13. Input Waveforms and Measurement Levels 44 Am29LV640MT/B 26190C8 February 1, 2007 D A T A S H E E T AC CHARACTERISTICS Read-Only Operations Parameter Speed Options JEDEC Std. Description Test Setup tAVAV tRC Read Cycle Time (Note 1) tAVQV tACC Address to Output Delay tELQV tCE Chip Enable to Output Delay 90R 100R 100 110R 110, 120R 120 Unit Min 90 100 110 120 ns CE#, OE# = VIL Max 90 100 110 120 ns OE# = VIL Max 90 100 110 120 ns Max 25 30 30 40 30 40 ns 25 30 30 40 30 40 ns tPACC Page Access Time tGLQV tOE Output Enable to Output Delay Max tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 16 ns tGHQZ tDF Output Enable to Output High Z (Note 1) Max 16 ns tAXQX Output Hold Time From tOH Addresses, CE# or OE#, Whichever Occurs First Min 0 ns Min 0 ns Min 10 ns tOEH Output Enable Read Hold Time Toggle and (Note 1) Data# Polling Notes: 1. Not 100% tested. 2. See Figure 12 and Table 15 for test specifications. tRC Addresses Stable Addresses tACC CE# tRH tRH tDF tOE OE# tOEH WE# tCE tOH HIGH Z HIGH Z Output Valid Outputs RESET# RY/BY# 0V Figure 14. February 1, 2007 26190C8 Read Operation Timings Am29LV640MT/B 45 D A T A S H E E T AC CHARACTERISTICS Same Page A21-A2 A1-A0 Aa Ab tPACC tACC Data Bus Qa Ad Ac tPACC Qb tPACC Qc Qd CE# OE# * Figure shows word mode. Addresses are A1–A-1 for byte mode. Figure 15. 46 Page Read Timings Am29LV640MT/B 26190C8 February 1, 2007 D A T A S H E E T AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std. Description All Speed Options Unit tReady RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) Max 20 μs tReady RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH Reset High Time Before Read (See Note) Min 50 ns tRPD RESET# Low to Standby Mode Min 20 μs Note: Not 100% tested. RY/BY# CE#, OE# tRH RESET# tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms tReady RY/BY# tRB CE#, OE# RESET# tRP Figure 16. February 1, 2007 26190C8 Reset Timings Am29LV640MT/B 47 D A T A S H E E T AC CHARACTERISTICS Erase and Program Operations Parameter Speed Options 90R 100, 100R 112, 112R 120, 120R Unit 90 100 110 120 ns JEDEC Std. Description tAVAV tWC Write Cycle Time (Note 1) Min tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tAH Address Hold Time Min 45 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 45 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 ns tWHDL tWPH Write Pulse Width High Min 30 ns Write Buffer Program Operation (Notes 2, 3) Typ 352 µs Per Byte Typ 11 µs Per Word Typ 22 µs Per Byte Typ 8.8 µs Per Word Typ 17.6 µs tWLAX Effective Write Buffer Program Operation (Notes 2, 4) tWHWH1 tWHWH1 Accelerated Effective Write Buffer Program Operation (Notes 2, 4) Byte Single Word/Byte Program Operation (Note 2, 5) µs Word Accelerated Single Word/Byte Programming Operation (Note 2, 5) tWHWH2 100 Typ 100 Byte 90 Typ µs Word 90 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec tVHH VHH Rise and Fall Time (Note 1) Min 250 ns tVCS VCC Setup Time (Note 1) Min 50 µs tBUSY WE# High to RY/BY# Low Max tPOLL Program Valid Before Status Polling (Note 6) Max 90 100 110 4 120 ns µs Notes: 1. Not 100% tested. 5. 2. See Erase And Programming Performance on page 57 for more information. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 6. 3. For 1–16 words/ 1–32 bytes programmed. 4. Effective write buffer specification is based upon a 16-word/ 32-byte write buffer operation. When using the program suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be fully re-applied upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL is not required again prior to reading the status bits upon resuming. 48 Am29LV640MT/B 26190C8 February 1, 2007 D A T A S H E E T AC CHARACTERISTICS Program Command Sequence (last two cycles) tAS tWC Addresses Read Status Data (last two cycles) 555h PA PA PA tAH CE# tCH OE# tPOLL tWP WE# tWPH tCS tDS tDH PD A0h Data tWHWH1 Status tBUSY DOUT tRB RY/BY# VCC tVCS Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode. Figure 17. Program Operation Timings VHH ACC VIL or VIH VIL or VIH tVHH Figure 18. February 1, 2007 26190C8 tVHH Accelerated Program Timing Diagram Am29LV640MT/B 49 D A T A S H E E T AC CHARACTERISTICS Erase Command Sequence (last two cycles) tAS tWC 2AAh Addresses Read Status Data VA SA VA 555h for chip erase tAH CE# tCH OE# tWP WE# tWPH tCS tWHWH2 tDS tDH Data 55h In Progress 30h Complete 10 for Chip Erase tBUSY tRB RY/BY# tVCS VCC Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data. See Write Operation Status on page 38. 2. These waveforms are for the word mode. Figure 19. 50 Chip/Sector Erase Operation Timings Am29LV640MT/B 26190C8 February 1, 2007 D A T A S H E E T AC CHARACTERISTICS tRC Addresses VA tPOLL VA VA tACC tCE CE# tCH tOE OE# tOEH tDF WE# tOH DQ15 and DQ7 DQ14–DQ8, DQ6–DQ0 Complement Complement Status Data Status Data True True Valid Data Valid Data High Z High Z tBUSY RY/BY# Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Figure 20. Data# Polling Timings (During Embedded Algorithms) February 1, 2007 26190C8 Am29LV640MT/B 51 D A T A S H E E T AC CHARACTERISTICS tAHT tAS Addresses tAHT tASO CE# tCEPH tOEH WE# tOEPH OE# tDH DQ6/DQ2 tOE Valid Status Valid Status Valid Status (first read) (second read) (stops toggling) Valid Data Valid Data RY/BY# Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle Figure 21. Enter Embedded Erasing WE# Erase Suspend Erase Toggle Bit Timings (During Embedded Algorithms) Enter Erase Suspend Program Erase Suspend Read Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete DQ6 DQ2 Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system can use OE# or CE# to toggle DQ2 and DQ6. Figure 22. DQ2 vs. DQ6 52 Am29LV640MT/B 26190C8 February 1, 2007 D A T A S H E E T AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description tVIDR VID Rise and Fall Time (See Note) tRSP RESET# Setup Time for Temporary Sector Unprotect All Speed Options Unit Min 500 ns Min 4 µs Note: Not 100% tested. VID RESET# VID VSS, VIL, or VIH VSS, VIL, or VIH tVIDR tVIDR Program or Erase Command Sequence CE# WE# tRRB tRSP RY/BY# Figure 23. February 1, 2007 26190C8 Temporary Sector Group Unprotect Timing Diagram Am29LV640MT/B 53 D A T A S H E E T AC CHARACTERISTICS VID VIH RESET# SA, A6, A1, A0 Valid* Valid* Sector Group Protect or Unprotect Data 60h 60h Valid* Verify 40h Status Sector Group Protect: 150 µs, Sector Group Unprotect: 15 ms 1 µs CE# WE# OE# * For sector group protect, A6–A0 = 0xx0010. For sector group unprotect, A6–A0 = 1xx0010. Figure 24. 54 Sector Group Protect and Unprotect Timing Diagram Am29LV640MT/B 26190C8 February 1, 2007 D A T A S H E E T AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations Parameter Speed Options 90R 100, 100R 112, 112R 120, 120R Unit 90 100 110 120 ns JEDEC Std. Description tAVAV tWC Write Cycle Time (Note 1) Min tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 ns tDVEH tDS Data Setup Time Min 45 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 45 ns tEHEL tCPH CE# Pulse Width High Min 30 ns Write Buffer Program Operation (Notes 2, 3) Typ 352 µs Per Byte Typ 11 µs Per Word Typ 22 µs Per Byte Typ 8.8 µs Per Word Typ 17.6 µs Effective Write Buffer Program Operation (Notes 2, 4) tWHWH1 tWHWH1 Accelerated Effective Write Buffer Program Operation (Notes 2, 4) Byte Single Word/Byte Program Operation (Note 2) Word Accelerated Single Word/Byte Programming Operation (Note 2) tWHWH2 tWHWH2 tRH tPOLL 100 Typ µs 100 Byte 90 Typ Word µs 90 Sector Erase Operation (Note 2) Typ 0.5 sec RESET High Time Before Write (Note 1) Min 50 ns Program Valid Before Status Polling (Note 6) Max 4 µs Notes: 1. Not 100% tested. 2. 3. 4. 5. 6. See Erase And Programming Performance on page 57 for more information. For 1–16 words programmed/1–32 bytes programmed. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. When using the program suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be fully re-applied upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL is not required again prior to reading the status bits upon resuming. February 1, 2007 26190C8 Am29LV640MT/B 55 D A T A S H E E T AC CHARACTERISTICS 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data# Polling Addresses PA tWC tAS tAH tWH WE# tPOLL tGHEL OE# tWHWH1 or 2 tCP CE# tWS tCPH tBUSY tDS tDH DQ7#, DQ15 Data tRH A0 for program 55 for erase DOUT PD for program 30 for sector erase 10 for chip erase RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. 4. Waveforms are for the word mode. Figure 25. 56 Alternate CE# Controlled Write (Erase/Program) Operation Timings Am29LV640MT/B 26190C8 February 1, 2007 D A T A S H E E T ERASE AND PROGRAMMING PERFORMANCE Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.5 15 sec Chip Erase Time 64 128 sec Excludes 00h programming prior to erasure (Note 6) Byte 100 800 µs Word 100 800 µs Byte 90 720 µs Word 90 720 µs 352 1800 µs Per Byte 11 57 µs Per Word 22 113 µs 282 1560 µs Per Byte 8.8 49 µs Per Word 17.6 98 µs Single Word/Byte Program Time (Note 3) Accelerated Single Word/Byte Program Time (Note 3) Total Write Buffer Program Time (Note 4) Effective Write Buffer Program Time (Note 5) Total Accelerated Write Buffer Program Time (Note 4) Effective Accelerated Write Buffer Program Time (Note 4) Excludes system level overhead (Note 7) Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC. Programming specifications assume that all bits are programmed to 00h. 2. Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and including 100,000 program/erase cycles. 3. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 4. For 1-16 words or 1-32 bytes programmed in a single write buffer programming operation. 5. Effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer operation. 6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 7. System-level overhead is the time required to execute the command sequence(s) for the program command. See Tables 12 and 13 for further information on command definitions. 8. The device has a minimum erase and program cycle endurance of 100,000 cycles. LATCHUP CHARACTERISTICS Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V –100 mA +100 mA VCC Current Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. February 1, 2007 26190C8 Am29LV640MT/B 57 D A T A S H E E T TSOP PIN AND BGA PACKAGE CAPACITANCE Parameter Symbol Parameter Description Test Setup CIN Input Capacitance VIN = 0 COUT Output Capacitance VOUT = 0 CIN2 Control Pin Capacitance VIN = 0 Typ Max Unit TSOP 6 7.5 pF Fine-pitch BGA 4.2 5.0 pF TSOP 8.5 12 pF Fine-pitch BGA 5.4 6.5 pF TSOP 7.5 9 pF Fine-pitch BGA 3.9 4.7 pF Test Conditions Min Unit 150°C 10 Years 125°C 20 Years Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Description Minimum Pattern Data Retention Time 58 Am29LV640MT/B 26190C8 February 1, 2007 D A T A S H E E T PHYSICAL DIMENSIONS TS 048—48-Pin Standard Pinout Thin Small Outline Package (TSOP) Dwg rev AA; 10/99 February 1, 2007 26190C8 Am29LV640MT/B 59 D A T A S H E E T PHYSICAL DIMENSIONS FBE063—63-Ball Fine-pitch Ball Grid Array (FBGA) 12 x 11 mm Package Dwg rev AF; 10/99 60 Am29LV640MT/B 26190C8 February 1, 2007 D A T A S H E E T PHYSICAL DIMENSIONS LAA064—64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm Package February 1, 2007 26190C8 Am29LV640MT/B 61 D A T A REVISION SUMMARY Revision A (April 26, 2002) S H E E T Changed text in the third paragraph of CFI to read “reading array data.” Initial release. Revision B+3 (September 19, 2002) Revision B (May 23, 2002) Changed packaging from 64-ball FBGA to 64-ball Fortified BGA. Ordering Information Changed Block Diagram: Moved VIO from RY/BY# to Input/Output Buffers. Revision B+4 (October 15, 2002) Deleted FI from Valid Combinations Table. Connection Diagrams Changed Note about WP#/ACC pin to indicate internal pullup to VCC. Changed from 56-Pin Standard TSOP to 48-Pin Standard TSOP. Revision B+1 (July 31, 2002) Product Selector Guide MIRRORBIT 64 MBIT Device Family Added regulated OPNs. Added 64 Fortified BGA to LV640MU device. Revision C (December 5, 2002) Alternate CE# Controlled Erase and Program Operations Added tRH parameter to table. Secured Silicon Sector Flash Memory Region, and Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence Noted that the ACC function and unlock bypass modes are not available when the Secured Silicon sector is enabled. Erase and Program Operations Added tBUSY parameter to table. Figure 16. Program Operation Timings Byte/Word Program Command Sequence, Sector Erase Command Sequence, and Chip Erase Command Sequence Added RY/BY# to waveform. TSOP and BGA PIN Capacitance Added the FBGA package. Program Suspend/Program Resume Command Sequence Noted that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when a program or erase operation is in progress. Changed 15 μs typical to maximum and added 5 μs typical. Common Flash Memory Interface (CFI) Erase Suspend/Erase Resume Commands Command Definitions Changed typical from 20 μs to 5 μs and added a maximum of 20 μs. Valid Combinations for TSOP Package Changed wording in last sentence of first paragraph from, “...resets the device to reading array data.” to ...”may place the device to an unknown state. A reset command is then required to return the device to reading array data.” Added 100R, 110R, and 120R OPNs. CMOS Compatible Valid Combinations for BGA Package Added ILR parameter to table. Added 100R, 110R, and 120R OPNs. Removed VIL, VIH, VOL, and VOH from table and added V IL1 , V IH1 , V IL2 , V IH2 , VOL , VOH1 , and VOH2 from the CMOS table in the Am29LV640MH/L datasheet. Revision B+2 (August 9, 2002) CMOS Compatible Added Note 8. Special package handling instructions Modified the special handling wording. DC Characteristics table Deleted the IACC specification row. CFI 62 Changed CFI website address. Changed VIH1 and VIH2 minimum to 1.9. Removed typos in notes. AC Characteristics and Read-Only Operations Changed the Chip Enable to Output High Z and Output Enable to Output High Z Speed Options from 30 ns to 16 ns. Am29LV640MT/B 26190C8 February 1, 2007 D A T A S H E E T Word/Byte Configuration Table 12 & Table 13: Command Definitions Changed BYTE# Switching Low to Output High Z Speed Options from 30 ns to 16 ns. Modified the Addr information for both Program/Erase Suspend and Program/Erase Resume from BA to XXX. Customer Lockable: Secured Silicon Sector NOT Programmed or Protected at the factory. Added second bullet, Secured Silicon sector-protect. AC Characteristics - Erase and Program Operations, and Alternate CE# Controlled Erase and Program Operations Revision C+1 (February 16, 2003) Added tPOLL information. Distinctive Characteristics Product Selector Guide AC Characteristics Figures - Program Operation Timings, Data# Polling Timings (During Embedded Algorithms, and Alternate CE# Controlled Write (Erase/Program) Operation Timings Added note 2. Updated figures with tPOLL information. Corrected performance characteristics. Connection Diagrams Revision C+4 (August 19, 2004) Changed pin F1 to NC. Added Max programming specifications. Ordering Information Cover sheet and Title page Corrected Valid Combinations table. Added notation referencing superseding documentation. Added Note. AC Characteristics Revision C+5 (November5, 2004) Removed 93, 93R speed option. Ordering Information and Valid Combinations Added Note Added Pb-Free options Input values in the tWHWH1 and tWHWH2 parameters in the Erase and Program Options table that were previously TBD. Also, added note 5. Input values in the tWHWH1 and tWHWH2 parameters in the Alternate CE# Controlled Erase and Program Options table that were previously TBD. Also, added note 5. Erase and Programming Performance Revision C+6 (December 7, 2004) Coversheet and Title page Added notation referencing superseding documentation. Revision C+7 (December 13, 2005) Global Input values into table that were previously TBD. Added note 3 and 4 Revision C+2 (June 12, 2003) Ordering Information Added 90R speed grade. Erase and Programming Performance Modified table and notes, inserted values for Typical. This product has been retired and is not available for designs. For new and current designs, S29GL064A supersedes Am29LV640MT/B and is the factory-recommended migration path. Please refer to the S29GL064A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. Revision C8 (February 1, 2007) Global Revision C+3 (February 12, 2004) Changed SecSi Sector to Secured Silicon Sector. Erase Suspend/Erase Resume Commands AC Characteristics Added note reference to erase operation. Erase and Program Operations table: Changed tBUSY to a maximum specification. February 1, 2007 26190C8 Am29LV640MT/B 63 D A T A S H E E T Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks Copyright © 2002–2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Copyright © 2006–2007 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners. 64 Am29LV640MT/B 26190C8 February 1, 2007