Ordering number : EN*5041A CMOS LSI LC11011-141 Computer Image Signal Processing Full-Color Gray-Scale Processor Preliminaly Overview Package Dimensions The LC11011-141 is a pseudo gray scale processor for TFT LCD. It allows LCD panels with inputs of three to six bits per RGB to display the equivalent of 16.7 million colors. unit: mm 3151-QFP100E [LC11011-141] Features • Handles 8-bits of input data (256-scale data) for each of the RGB colors. • Operating mode selection of three, four, or six bit driver outputs • Realizes reduced resolution loss (as compared to dithering techniques) by using intra- and inter-frame error diffusion processing. • Supports both 5 V and low voltage (3.3 V) operation. • Operates with arbitrary clock frequencies up to 50 MHz (at 5 V) or up to 30 MHz (at 3.3 V). • Can operate independently of the number of displayed pixels since internal operation is controlled by the horizontal and vertical synchronization signals. SANYO: QFP100E Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Symbol Maximum supply voltage VDD max Input and output voltages VI, VO Conditions Ratings Unit –0.3 to +7.0 V –0.3 to VDD + 0.3 V Operating temperature Topr 0 to +70 °C Storage temperature Tstg –40 to +125 °C Electrical Characteristics: At an operating voltage of 5.0 V Operating Ranges at Ta = 0 to +70°C Ratings Parameter Symbol Conditions min typ 5.0 Supply voltage VDD 4.5 Input voltage VIN 0 Clock frequency fclk max Unit 5.5 V VDD V 50 MHz SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 22896HA (OT)/No. 5041-1/7 LC11011-141 DC Characteristics at Ta = 0 to +70°C, VSS = 0 V, VDD = 4.5 to 5.5 V Ratings Parameter Symbol Conditions High level input voltage VIH CMOS level Low level input voltage VIL CMOS level High level output voltage VOH IOH (–4 mA) Low level output voltage VOL IOL (4 mA) min typ Unit max 0.7 VDD V 0.3 VDD V 2.4 Supply current ICC * Note: * The test conditions are: fCP = 25.175 MHz, VDD = 5.0 V, CL = 15 pF (measured with VGA timing) V 40 0.4 V 70 mA Switching Characteristics at Ta = 0 to +70°C, VSS = 0 V, VDD = 4.5 to 5.5 V, CL = 15 pF Ratings Parameter Symbol Conditions min typ Unit max Dot clock cycle time Tdclk 20 ns Hsync low level pulse width Thpw 2 Tdclk ns Vsync low level pulse width Tvpw 2 Tdclk ns Data setup time Tdsu 5 ns Data hold time Tdhd 5 ns Control signal setup time Tcsu 5 ns Control signal hold time Tchd 5 CLK propagation delay time Ttdhh 2 3 6 ns CLK propagation delay time Ttdll 2 4 7 ns CLKB propagation delay time Ttdhl 2 4 7 ns CLKB propagation delay time Ttdlh 2 4 7 ns Control signal propagation delay time Ttctl 2 Tdclk + 3 2 Tdclk + 6 2 Tdclk + 10 ns Ttdata 2 Tdclk + 3 2 Tdclk + 6 2 Tdclk + 11 ns Data output propagation delay time ns Electrical Characteristics: At an operating voltage of 3.3 V Operating Ranges at Ta = 0 to +70°C Ratings Parameter Symbol Conditions min typ 3.3 Supply voltage VDD 3.0 Input voltage VIN 0 Clock frequency fclk max Unit 3.6 V VDD V 30 MHz DC Characteristics at Ta = 0 to +70°C, VSS = 0 V, VDD = 3.0 to 3.6 V Ratings Parameter Symbol Conditions High level input voltage VIH CMOS level Low level input voltage VIL CMOS level High level output voltage VOH IOH (–2 mA) Low level output voltage VOL IOL (2 mA) min typ max 0.7 VDD Supply current ICC * Note: * The test conditions are: fclk = 25.175 MHz, VDD = 3.3 V, CL = 15 pF (measured with VGA timing) Unit V 0.3 VDD 2.2 V V 30 0.4 V 45 mA No. 5041-2/7 LC11011-141 Switching Characteristics at Ta = 0 to +70°C, VSS = 0 V, VDD = 3.0 to 3.6 V, CL = 15 pF Ratings Parameter Symbol Conditions min typ Unit max Dot clock cycle time Tdclk 33 ns Hsync low level pulse width Thpw 2 Tdclk ns Vsync low level pulse width Tvpw 2 Tdclk ns Data setup time Tdsu 10 ns Data hold time Tdhd 10 ns Control signal setup time Tcsu 10 ns Control signal hold time Tchd 10 CLK propagation delay time Ttdhh 2 5 12 ns CLK propagation delay time Ttdll 2 6 14 ns CLKB propagation delay time Ttdhl 2 6 14 ns CLKB propagation delay time Ttdlh 2 6 14 ns Control signal propagation delay time Ttctl 2 Tdclk + 5 2 Tdclk + 10 2 Tdclk + 22 ns Ttdata 2 Tdclk + 5 2 Tdclk + 10 2 Tdclk + 24 ns Data output propagation delay time ns Pin Assignment No. 5041-3/7 LC11011-141 Block Diagram No. 5041-4/7 LC11011-141 Pin Functions Symbol Pin No. I/O VDD 5, 21, 28, 32, 41, 61, 68, 91 Input Power supply (+5 V) VSS 10, 15, 20, 26, 30, 34, 35, 40, 46,51, 56, 66, 71, 73, 82, 87, 90, 98 Input GND (0 V) NC 24, 76, 77 — MODESEL0 1 Input Function Must be left open. Mode selection signals [0:3] for the gray scale mode. The setting process for the mode selection lines is described below. MODESEL0 is the LSB, and MODESEL3 is the MSB. Note that modes 8, 9, C, D and E are compatible with the LC1001-131 (a product that handles 6-bits of input for each of the RGB signals). Color scale mode 0 1 2 3 4 5 6 7 8 9 A B C D E F L L L L H L L L L H L L H H L L L L H L H L H L L H H L H H H L L L L H H L L H L H L H H H L H L L H H H L H H L H H H H H H H Intra-frame processing Y Y Y Y Y Y Y Y Y Y Inter-frame processing R R Y Y Y N N N Y Y N N N Number of valid input bits 8 8 8 8 8 8 6 6 6 6 6 Number of output bits 3 4 6 4 5 6 3 4 3 4 5 MODESEL0 MODESEL1 MODESEL2 MODESEL3 MODESEL1 2 Input Processing MODESEL2 MODESEL3 3 4 Input Input Y R R R Note: Y = yes, N = no, R = reserved Gray scale modes 0, 8 and C Operating mode for TFT-LCD modules using 3-bit source drivers. Gray scale modes 1 and 9 Operating mode for TFT-LCD modules using 4-bit source drivers. Gray scale mode 3 Operating mode for TFT-LCD modules using 6-bit source drivers. Gray scale modes 5 and D Operating mode for TFT-LCD modules that perform FRC or other inter-frame processing. Gray scale modes 6, 7 and E Operating mode for TFT-LCD modules that perform FRC or other inter-frame processing. Note: Do not use gray scale modes 0, 1, 3, 8 and 9 with LCD modules that perform FRC or other interframe processing. BYPASS 100 Input TEST0 6 Input TEST1 7 Input TEST2 8 Input TEST3 9 Input SCLK 67 Input SRDATA [0:7] 57 to 60, 62 to 65 Input SGDATA [0:7] 78 to 81, 83 to 86 Input SBDATA [0:7] 88, 89, 92 to 97 Input Shsync 69 Input Svsync 70 Input SHDEN 72 Input SCTL0 74 Input SCTL1 75 Input CLKSEL 99 Input CLK 31 Output CLKB 33 Output Input bypass pin. When this pin is low, the LC11011-141 performs no gray scale processing, but rather simply passes the input signals through unchanged. When a low level input on this pin is sampled on the rising edge of the clock, the IC will begin the output of unchanged data two clock cycles later. Test pins [0:3]; left open in normal operation. Display dot clock input. Data is processed according to this clock signal. Input pins for red, green and blue scale data. SRDATA7, SGDATA7, and SBDATA7 are the MSBs. SRDATA0, SGDATA0, and SBDATA0 are the LSBs. Horizontal and vertical synchronization signal inputs. These are the sources for the Hsync and Vsync signals. These are also used to control data processing. These are low level active signals. Horizontal data valid period signal input. Set this pin high during periods when the horizontal data is valid. If this signal is not used, tie it high, and set the input data to zero during the horizontal blanking period. LCD control inputs. Input control signals that must be matched to the data signal timing. These are the sources for the CTL signals. If the CTL [0:1] signals are not used, there is no need to input the SCTL [0:1] signals. CLKSEL is the dot clock output selection. It is used to select the output mode of the dot clock signal output pin. If CLKSEL is low: A signal with the same phase as the SCLK pin is output from the CLK pin. If CLKSEL is high: A signal with the opposite phase from the SCLK pin is output from the CLKB pin. Continued on next page. No. 5041-5/7 LC11011-141 Continued from preceding page. Symbol Pin No. I/O Function Red, green and blue gray scale data output pins. These are delayed by 2 clock cycles with respect to the input data. RDATA7, GDATA7 and BDATA7 are the MSBs. In modes 0, 8, C and F, RDATA5, GDATA5 and BDATA5 are the LSBs. In these modes, RDATA [0:4], GDATA [0:4] and BDATA [0:4] are not used. In modes 1, 5, 9 and D, RDATA4, GDATA4 and BDATA4 are the LSBs. In these modes, RDATA [0:3], GDATA [0:3] and BDATA [0:3] are not used. In modes 6 and E, RDATA3, GDATA3 and BDATA3 are the LSBs. In these modes, RDATA [0:2], GDATA [0:2] and BDATA [0:2] are not used. In modes 3 and 7, RDATA2, GDATA2 and BDATA2 are the LSBs. In these modes, RDATA [0:1], GDATA [0:1] and BDATA [0:1] are not used. RDATA [0:7] 11 to 14, 16 to 19 Output GDATA [0:7] 36 to 39, 42 to 45 Output BDATA [0:7] 47 to 50, 52 to 55 Output Vsync 27 Output Hsync 29 Output Horizontal and vertical synchronization signal outputs. To match the data signal timing these are delayed by two clock cycles with respect to their input signals. HDEN 25 Output Horizontal data valid period signal output CLT0 22 Output CLT1 23 Output LCD control signal outputs. To match the data signal timing these are delayed by two clock cycles with respect to the SCTL [0:1] input signals. Timing Chart No. 5041-6/7 LC11011-141 Continued from preceding page. Usage Note Since this LSI performs spatial modulation using an error diffusion algorithm, patterns that differ from the original images may be displayed for certain display pattern and gray-scale mode combinations. ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1997. Specifications and information herein are subject to change without notice. No. 5041-7/7