Sanyo LC866428B 8-bit single chip microcontroller Datasheet

Ordering number : ENN*6699
CMOS IC
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
8-Bit Single Chip Microcontroller
Preliminary
Overview
The LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B microcontrollers are 8-bit single chip microcontrollers
with the following on-chip functional blocks:
- CPU : Operable at a minimum bus cycle time of 0.5µs (microsecond)
- On-chip ROM Maximum Capacity : 48K bytes
- On-chip RAM Capacity : 1152/768/640/512 bytes
(LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B)
- 16-bit timer /counter (or two 8-bit timers)
- 16-bit timer /PWM (or two 8-bit timers)
- 8-channel × 8-bit AD converter
- Two 8-bit synchronous serial-interface circuits (1-channel × 16bit, 1-channel × 8bit)
- 14-source 10-vectored interrupt system
All of the above functions are fabricated on a single chip.
Ver.1.05
O0499
91400 RM (IM) SK No.6699-1/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
Features
: LC866448B
49152 × 8 bits
: LC866444B
45056 × 8 bits
: LC866440B
40960 × 8 bits
: LC866436B
36864 × 8 bits
: LC866432B
32768 × 8 bits
: LC866428B
28672 × 8 bits
: LC866424B
24576 × 8 bits
: LC866420B
20480 × 8 bits
: LC866416B
16384 × 8 bits
: LC866412B
12288 × 8 bits
: LC866408B
8192 × 8 bits
(2) Random Access Memory (RAM) : LC866448B/44B/40B/36B
1152 × 8 bits
: LC866432B/28B/24B
768 × 8 bits
: LC866420B/16B
640 × 8 bits
: LC866412B/08B
512 × 8 bits
(3) Bus Cycle Time/Instruction Cycle Time
The LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B are constructed to read ROM twice within one
instruction cycle. It has 1.7 times more performance capability within the same instruction cycle compared to our 4-bit
microcomputers (LC66000 series).
Bus cycle time indicates the speed to read ROM.
(1) Read-Only Memory (ROM)
Bus cycle time
Cycle time
Clock divider
System clock oscillation
Oscillation Frequency
Voltage
0.5µs
1µs
1/1
Ceramic resonator oscillation
6MHz
4.5V to 6.0V
2µs
4µs
1/1
Ceramic resonator oscillation
3MHz
2.5V to 6.0V
7.5µs
15µs
1/1
RC resonator oscillation
800kHz
2.5V to 6.0V
183µs
366µs
1/2
Crystal oscillation
32.768kHz
2.5V to 6.0V
(4) Ports
- Input/output ports
: 1 port (8 terminals : port 1)
Input/output programmable in a bit
- 15V withstand Input/Output ports
: 2 ports (12 terminals)
Input/output port programmable in nibble unit
: 1 port (8 terminals : port 0)
(When the N-channel open drain output is selected, the data in a bit can be inputted.)
Input/output port programmable in a bit
: 1 port (4 terminals : port 3)
- Input port
: 2 ports (14 terminals : port 7,8)
- VFD output port
: 38 terminals
Large current output for digit
: 16 terminals
Pull-down resistor option available
- Other function
Input/output port
: 1 port (6 terminals : port E)
Input port
: 2 ports (16 terminals : port C,D)
(5) VFD automatic dislay controller
-Segment/digit output pattern programmable
Any segment/digit combination available
VFD parallel-drive available
- 16-step dimmer function available
(6) AD converter
- 8-channel × 8-bit AD converter
(7) Serial-interface
- 1 channel × 16-bit serial-interface circuits
- 1 channel × 8-bit serial-interface circuits
- LSB first / MSB first function available
- Internal 8-bit baud-rate generator in common with two serial-interface circuits
No.6699-2/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
(8) Timer
- Timer 0
16-bit timer/counter
2-bit prescaler + 8-bit programmable prescaler
Mode 0 : Two 8-bit timers with programmable prescaler
Mode 1 : 8-bit timer with programmable prescaler + 8-bit counter
Mode 2 : 16-bit timer with programmable prescaler
Mode 3 : 16-bit counter
The resolution of Timer is tCYC. (tCYC: cycle time)
- Timer 1
16-bit timer/PWM
Mode 0 : Two 8-bit timers
Mode 1 : 8-bit timer + 8-bit PWM
Mode 2 : 16-bit timer
Mode 3 : Variable-bit PWM (9-16 bits)
In Mode 0 and Mode 1,the resolution of Timer and PWM is tCYC.
In Mode 2 and Mode 3,the resolution of Timer and PWM selectable: tCYC or 1/2 tCYC by program
- Base timer
Every 500ms overflow system for a clock application (using 32.768kHz crystal oscillation for Base timer clock)
Every 976µs, 3.9ms, 15.6ms, 62.5ms overflow system (using 32.768kHz crystal oscillation for Base timer clock)
The Base timer clock selectable; 32.768kHz crystal oscillation, System clock, and programmable prescaler output of
Timer 0
(9) Buzzer output
- The Buzzer sound frequency selectable; 4KHz, 2KHz (using 32.768kHz crystal oscillation for Base
timer clock)
(10) Remote-control receiver circuit (Shares with the P73/INT3/T0IN terminal)
- Noise Rejection function (the time constant of noize rejection filter: 1tCYC/16tCYC/64tCYC)
(tCYC: instruction cycle time)
- Switch Polarity function
(11) Watchdog timer
- The watchdog timer is taken on RC outside
- Watchdog timer operation selectable: interrupt system, system reset
(12) Interrupt system
- 14-source 10-vectored interrupts :
1. External interrupt INT0 (include watchdog timer)
2. External interrupt INT1
3. External interrupt INT2, Timer/counter T0L (Lower 8-bit)
4. External interrupt INT3, Base timer
5. Timer/counter T0H (Upper 8-bit)
6. Timer T1L, Timer T1H
7. Serial-interface SIO0
8. Serial-interface SIO1
9. AD converter
10. VFD automatic display controller, Port 0
- Built-in Interrupt Priority control register
Microcontroller allows 3 levels of interrupt; low level, high level, and highest level of multiplex interrupt. It can
specify a low level or a high level interrupt priority from INT2/T0L through port 0
(i.e. the above interrupt number from three through ten). It can also specify a low level or the highest level interrupt
priority to INT0 and INT1.
No.6699-3/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
(13) Real-time service operation
The Real-Time Service (RTS) functions the 4-byte data-transfer between the Special Function Registers at
acknowledging the interrupt request.
The RTS starts within 1 instruction cycle-time and completes within 5 instructions cycle-time after occurring the
interrupt request.
(14) Subroutine stack levels
- 128 levels (Max.): Stack area included in RAM area
(15) Multiplication and division
16-bit × 8-bit (7 instruction cycle times)
16-bit / 8-bit (7 instruction cycle times)
(16) Three oscillation circuits
- On-chip RC oscillation circuit using for the system clock.
- On-chip CF oscillation circuit using for the system clock.
- On-chip crystal oscillation circuit using for the system clock and for time-base clock.
(17) Standby function
- HALT mode function
The HALT mode is used to reduce power dissipation. In this operation mode, program execution is stopped. This
operation mode can be released by interrupt request signals or the initial system reset request signal.
- HOLD mode function
The HOLD mode is used to freeze all the oscillations;
RC (internal), CF and Crystal oscillations. This mode can be released by the following operations.
• Reset terminal ( RES ) set to Low level
• P70/INT0/T0IN, P71/INT1/T0IN terminals set to assigned level (programmable)
• Input a Port 0 interrupt condition
(18) Factory shipment
• QFP80E delivery form
(19) Development support tools
Evaluation (EVA) chip
: LC866097
EPROM version
: LC86E6449
One time version
: LC86P6449
Emulator
: EVA-86000 + ECB866400 (Evaluation chip board) + POD866400 (POD)
Notice for use
1. Set VDD=4.0V to 6.0V at using S16 to S37 as input port.
2. Follow the under table.
Frequency range of the system clock
Voltage range
Clock Divider
Note
15kHz to 30kHz
30kHz to 6MHz
15kHz to 30kHz
30kHz to 1.5MHz
1.5MHz to 3MHz
Internal RC oscillation
4.5V to 6.0V
1/1
1/1,1/2
1/1
1/1,1/2
1/2
1/1,1/2
1/2
Can not use 1/2 divider
2.5V to 6.0V
4.5V to 6.0V
2.5V to 6.0V
Can not use 1/2 divider
Can not use 1/1 divider
Can not use 1/1 divider
No.6699-4/21
P17/PWM0
P30
P31
P32
P33
P70/INT0
RES
XT1/P74
XT2/P75
VSS1
CF1
CF2
VDD1
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
P71/INT1
P72/INT2/T0IN
P73/INT3/T0IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
S37/PE5
S36/PE4
S35/PE3
S34/PE2
S33/PE1
S32/PE0
S31/PD7
S30/PD6
S29/PD5
S28/PD4
S27/PD3
S26/PD2
S25/PD1
S24/PD0
S23/PC7
S22/PC6
S21/PC5
S20/PC4
S19/PC3
S18/PC2
S17/PC1
S16/PC0
VP
VDD2
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
Pin Assignment
QIP80E
P00
P01
P02
P03
P04
P05
P06
P07
VSS2
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
P16/BUZ
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
S15/T15
S14/T14
S13/T13
S12/T12
S11/T11
S10/T10
S9/T9
S8/T8
S7/T7
S6/T6
S5/T5
S4/T4
S3/T3
S2/T2
S1/T1
S0/T0
Package Dimension
(unit : mm)
3174
SANYO : QIP-80E
No.6699-5/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
System Block Diagram
Interrupt Control
IR
Standby Control
PLA
ROM
RC
Clock
Generator
CF
PC
X’tal
Base Timer
Bus Interface
ACC
SIO0
Port 1
B Register
SIO1
Port 3
C Register
Timer 0
Port 7
ALU
Timer 1
Port 8
ADC
PSW
INT0 to 3
Noise Filtter
RAR
Real Time Service
RAM
RAM
(128 bytes)
Stack Pointer
VFD Controller
Port 0
High voltage Output
Watchdog Timer
No.6699-6/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
Pin description
Pin name
VSS1,2
I/O
-
Function description
Option
Power pin (-) Short-circuit VSS1 to VSS2.
-
VDD1,2
-
Power pin (+) *1
VP
-
Power pin (+) for the VFD output pull-down resistor
Refer to Notes
-
-
PORT0
P00 to P07
I/O
•8-bit input/output port
•Input for port 0 interrupt
•Input/output in nibble units
•Input for HOLD release
•15V withstand at N-channel open drain output
•Pull-up resistor :
Provided/Not provided (each nibble)
•Output form :
CMOS/N-channel open drain (each bit)
PORT1
P10 to P17
I/O
•8-bit input/output port
•Input/output can be specified in a bit unit
•Other pin functions
P10 SIO0 data output
P11 SIO0 data input/bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 data input/bus input/output
P15 SIO1 clock input/output
P16 Buzzer output
P17 Timer 1 output (PWM0 output)
Output form :
CMOS/N-channel open drain (each bit)
PORT3
P30 to P33
I/O
•4-bit input/output port
•Input/output in bit unit
•15V withstand at N-channel open drain output
Output form :
CMOS/N-channel open drain (each bit)
•6-bit input port
•Other pin functions
P70 : INT0 input/HOLD release/N-channel Tr.
output for watchdog timer
P71 : INT1 input/HOLD release input
P72 : INT2 input/timer 0 event input
P73 : INT3 input with noise filter/timer 0 event input
P74 : 32.768kHz crystal oscillation terminal XT1
Pull-up resistor :
Provided/Not provided
(P70,71,72,73)
* P74 , P75 don’t have the pull-up
PORT7
P70
P71 to P75
I/O
I
resistor option.
P75 : 32.768kHz crystal oscillation terminal XT2
•Interrupt received forms, the vector addresses
rising
&
falling
high
level
low
level
vector
rising
falling
INT0
enable
enable disable enable
enable
03H
INT1
enable
enable disable enable
enable
0BH
INT2
enable
enable
enable disable disable
13H
INT3
enable
enable
enable disable disable
1BH
Continue.
No.6699-7/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
Pin name
I/O
Function description
Option
PORT8
P80 to 87
I
•8-bit input port
•Other function
AD input port (8 Port pins)
-
S0/T0 to
S6/T6
O
Output for VFD display controller
segment/timing in common
Pull-down resistor :
Provided/Not provided (each nibble)
S7/T7 to
S15/T15
O
•Output for VFD display controller
segment/timing with internal pull-down resistor in
common
•Internal pull-down resistor output
S16 to S31
I/O
•Output for VFD display controller segment
•Other function
S16 : High voltage input port PC0
S17 : High voltage input port PC1
S18 : High voltage input port PC2
S19 : High voltage input port PC3
S20 : High voltage input port PC4
S21 : High voltage input port PC5
S22 : High voltage input port PC6
S23 : High voltage input port PC7
Pull-down resistor :
Provided/Not provided (each nibble)
S24 : High voltage input port PD0
S25 : High voltage input port PD1
S26 : High voltage input port PD2
S27 : High voltage input port PD3
S28 : High voltage input port PD4
S29 : High voltage input port PD5
S30 : High voltage input port PD6
S31 : High voltage input port PD7
S32 to S37
I/O
•Output for VFD display controller Segment
•Other function
S32 : High voltage I/O port PE0
S33 : High voltage I/O port PE1
S34 : High voltage I/O port PE2
S35 : High voltage I/O port PE3
S36 : High voltage I/O port PE4
S37 : High voltage I/O port PE5
Pull-down resistor :
Provided/Not provided (each nibble)
RES
I
Reset pin
-
XT1/ P74
I
•Input pin for 32.768kHz crystal oscillation
•Other function
P74 for input port
-
XT2/P75
O
•Output pin for 32.768kHz crystal oscillation
•Other function
P75 for input port
•In case of non use,
At using as oscillator, should be left opened.
At using as a port, connect to VDD1.
-
•In case of non use, connect to VDD1.
CF1
I
Input pin for the ceramic resonator oscillation
-
CF2
O
Output pin for the ceramic resonator oscillation
-
* All of port options (except pull-up resistor of port 0) can be specified in bit unit.
No.6699-8/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
*A state of pins at reset
Pin name
Input/output mode
Port 0
Input
Ports 1,3
Input
Input
Ports 70,71,72,73
S0/T0 to S15/T15
S16 to S37
A state of pull-up resistor specified at pull-up option
Fixed pull-up resistor OFF
Programmable pull-up resistor OFF
Fixed pull-up resistor OFF
P channel Transistor OFF
P channel Transistor OFF
[Notes]
When connecting to the power supply, the power pins must be connected like following figure.
In case for the LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
LSI
VDD1
Power
Supply
For back-up
VDD2
(VFD power
pin)
VSS1 VSS2
In case for the LC866432A/28A/24A/20A/16A/12A/08A
LSI
VDD1
Power
Supply
For back-up
VDD2
(VFD power
pin)
VSS1 VSS2
*1 Each of the power pins, VDD1 and VDD2, should be connected the capacitors for reducing the noise into the VDD1 pin.
No.6699-9/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
1. Absolute Maximum Ratings at VSS1=VSS2=0V and Ta=25°C
Parameter
Supply voltage
Input voltage
Output voltage
Input/Output
voltage
Symbol
VDDMAX VDD1,VDD2
VI(1)
VIO(3)
IOPH(1)
•Ports 71,72,73
•Ports 74 ,75
•Port 8
• RES
VP
S0/T0 to S15/T15
•Port 1
•Port 70
•Ports 0, 3 at CMOS
output option
Ports 0, 3 at N-ch open
drain output option
S16 to S37
Ports 0, 1, 3
IOPH(2)
IOPH(3)
ΣIOAH(1)
ΣIOAH(2)
ΣIOAH(3)
IOPL(1)
IOPL(2)
S0/T0 to S15/T15
S16 to S37
Ports 0, 1, 3
S0/T0 to S15/T15
S16 to S37
Ports 0, 1, 3
Port 70
VI(2)
VO
VIO(1)
VIO(2)
High
Peak
level
output
output current
current
Total
output
current
Low
level
output
current
Peak
output
current
Total
output
current
Maximum
power
dissipation
Operating
temperature
range
Storage
temperature
range
Pins
Conditions
VDD1=VDD2
•CMOS output
•At each pins
At each pins
At each pins
The total of all pins
The total of all pins
The total of all pins
At each pins
At each pins
VDD[V]
min.
Ratings
typ.
max.
-0.3
-0.3
+7.0
VDD+0.3
VDD-45
VDD-45
-0.3
VDD+0.3
VDD+0.3
VDD+0.3
-0.3
15
VDD-45
-10
VDD+0.3
unit
V
mA
-30
-15
-30
-55
-115
20
15
ΣIOAL(1) Port 0
ΣIOAL(2) Ports 1,3
The total of all pins
The total of all pins
40
40
Pdmax
Ta=-30 to+70°C
480
mW
°C
QFP80E
Topr
-30
70
Tstg
-55
125
No.6699-10/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
2. Recommended Operating Range at Ta=-30°C to +70°C, VSS1=VSS2=0V
Parameter
Symbol
VDD(1)
Pins
VDD(2)
Hold voltage
VHD
VDD1=VDD2
Pull-down
voltage
Input high
voltage
VP
VP
VIH(1)
Port 0 at CMOS output
VIH(2)
Port 0 at N-ch open drain Output disable
output
VIH(3)
•Port 1
•Ports 72,73
•Port 3 at CMOS
output option
Port 3 at N-ch open
drain output option
VIH(5)
VIH(6)
VIH(7)
VIH(8)
Input low
voltage
VIL(1)
VIL(2)
VIL(3)
VIL(4)
VIL(5)
VIL(6)
VIL(7)
Operation
cycle time
•Port 70
Port input/interrupt
•Port 71
• RES
Port 70
Watchdog timer
•Port 8
•Ports 74 ,75
S16 to S37
Port 0 at CMOS
output option
Port 0 at N-ch open
drain output
•Ports 1,3
•Ports 72,73
•Port 70
Port input/interrupt
•Port 71
• RES
Port 70
Watchdog timer
•Port 8
•Ports 74 ,75
S16 to S37
VDD[V]
0.98µs ≤ tCYC
tCYC ≤ 400µs
3.9µs ≤ tCYC
tCYC ≤ 400µs
RAMs and the
registers hold
voltage at HOLD
mode.
Operating
Supply
voltage
VIH(4)
VDD1=VDD2
Conditions
2.5 to 6.0
Output disable
Output disable
Output disable
Tr. OFF
Output N-channel
Tr. OFF
min.
Ratings
typ.
max.
4.5
6.0
2.5
6.0
2.0
6.0
-35
VDD
2.5 to 6.0 0.33VDD
+1.0
4.0 to 6.0 0.8VDD
2.5 to 4.0 0.75VDD
2.5 to 6.0 0.75VDD
VDD
4.5 to 6.0 0.8VDD
2.5 to 4.0 0.75VDD
2.5 to 6.0 0.75VDD
13.5
13.5
VDD
2.5 to 6.0 0.9VDD
VDD
2.5 to 6.0 0.75VDD
VDD
Output P-channel
Tr. OFF
Output disable
4.0 to 6.0 0.33VDD
+1.0
2.5 to 6.0 VSS
VDD
0.2VDD
Output disable
2.5 to 6.0
VSS
0.25VDD
Output disable
2.5 to 6.0
VSS
0.25VDD
Output N-channel
Tr. OFF
2.5 to 6.0
VSS
0.25VDD
Output N-channel
Tr. OFF
Using as port
2.5 to 6.0
VSS
2.5 to 6.0
VSS
0.8VDD
-1.0
0.25VDD
4.0 to 6.0
VP
0.2VDD
4.5 to 6.0
2.5 to 6.0
0.98
3.9
400
400
tCYC
V
13.5
13.5
VDD
Output N-channel
Tr. OFF
Using as port
Output P-channel
Tr. OFF
unit
µs
Continue.
No.6699-11/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
Parameter
Symbol
Oscillation
FmCF(1)
frequency
range
(Note 1)
FmCF(2)
Oscillation
stabilizing
time period
(Note 1)
Pins
CF1, CF2
CF1, CF2
FmRC
FsXtal
XT1, XT2
tmsCF(1)
CF1, CF2
tmsCF(2)
CF1, CF2
tssXtal
XT1, XT2
Conditions
•6MHz
(ceramic resonator
oscillation)
•Refer to figure 1
•3MHz
(ceramic resonator
oscillation)
•Refer to figure 1
RC oscillation
•32.768kHz
(crystal oscillation)
•Refer to figure 2
•6MHz
(ceramic resonator
oscillation)
Ratings
typ.
min.
4.5 to 6.0
To be
deter-min
ed
6
To be MHz
deter-min
ed
2.5 to 6.0
To be
deter-min
ed
3
To be
deter-min
ed
2.5 to 6.0
2.5 to 6.0
0.3
0.8
32.768
3.0
0..1
3.0
0.1
3.0
0.1
3.0
0.7
0.8
1.4
2.2
4.5 to 6.0
•Refer to figure 3
•3MHz
4.5 to 6.0
(ceramic resonator 2.5 to 6.0
oscillation)
•Refer to figure 3
4.5 to 6.0
•32.768kHz
(crystal oscillation) 2.5 to 6.0
•Refer to figure 3
max.
unit
VDD[V]
kHz
ms
s
(Note 1) The oscillation constant is shown on table 1 and table 2.
No.6699-12/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
3. Electrical Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=0V
Parameter
Input high
current
Symbol
IIH(1)
Ports 0,3 at open
drain output
IIH(2)
•Port 0 without
pull-up MOS Tr.
•Ports 1,3
IIH(3)
•Ports 70,71,72,73
without pull-up
MOS Tr.
•Port 8
RES
Ports 74 ,75
IIH(4)
IIH(5)
IIH(6)
Input low
current
IIL(1)
IIL(2)
IIL(3)
IIL(4)
Output high
voltage
Pins
S16 to S37 without
pull-down resistor
(Ports C,D,E)
•Ports 1,3
•Port 0 without
pull-up MOS Tr.
•Ports 70,71,72,73
without pull-up
MOS Tr.
•Port 8
RES
Ports 74 ,75
VDD[V]
1
2.5 to 6.0
1
VIN=VDD
•Using as port
•VIN=VDD
•Output disable
•VIN=VDD
2.5 to 6.0
2.5 to 6.0
1
1
2.5 to 6.0
1
•Output disable
•Pull-up MOS Tr. OFF.
•VIN=VSS
(including off-leakage
current of the output Tr.)
VIN=VSS
2.5 to 6.0
-1
2.5 to 6.0
-1
2.5 to 6.0
2.5 to 6.0
-1
-1
IOL=0.5mA
2.5 to 6.0
VOH=0.9VDD
4.5 to 6.0
2.5 to 4.5
Pull-up MOS Rpu
Tr. resistor
•Ports 0,1,3
•Ports 70,71,72,73
max.
2.5 to 6.0
VOL(5)
VOL(1) Ports 0,1,3
VOL(2)
VOL(3)
Ratings
typ.
5
VOL(4) Port 70
VOH(1) Ports 0,1,3 of
VOH(2) CMOS output
VOH(3) S0/T0 to S15/T15
VOH(4)
min.
2.5 to 6.0
•Output disable
•VIN=13.5V
(including off-leakage
current of the output Tr.)
•Output disable
•Pull-up MOS Tr. OFF.
•VIN=VDD
(including off-leakage
current of the output Tr.)
VIN=VDD
VIN=VSS
•VIN=VSS
•Using as port
IOH=-1.0mA
IOH=-0.1mA
IOH=-20mA
•IOH=-1mA
•The current of any
unmeasurement pin is not
over 1mA.
IOH=-5mA
The current of any
unmeasurement pin is not
over 1mA.
IOL=10mA
IOL=1.6mA
•IOL=1.0mA
•The current of any
unmeasurement pin is not
over 1mA.
IOL=1mA
VOH(5) S16 to S37
VOH(6)
Output low
voltage
Conditions
unit
µA
V
4.5 to 6.0 VDD-1
2.5 to 6.0 VDD-0.5
4.5 to 6.0 VDD-1.8
2.5 to 6.0 VDD-1
4.5 to 6.0 VDD-1.8
2.5 to 6.0 VDD-1
4.5 to 6.0
4.5 to 6.0
2.5 to 6.0
1.5
0.4
0.4
4.5 to 6.0
0.4
0.4
15
25
40
70
70
150
kΩ
Continue.
No.6699-13/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
Parameter
Output offleak current
Symbol
Pins
Conditions
IOFF(1) S0/T0 to S6/T6,
S16 to S37 without
IOFF(2) pull-down resistor
Resistance of
the low level
hold Tr.
High voltage
pull-down
resistor
Hysteresis
voltage
Rinpd
S16 to S37
Rpd
Pin
capacitance
CP
S0/T0 to S15/T15,
S16 to S37 without
pull-down resistor
•Port 1
•Ports 70,71,72,73
• RES
All pins
VHIS
•Output P-channel Tr. OFF
•VOUT=VSS
•Output P-channel Tr. OFF
•VOUT=VDD-40V
•Output P-channel Tr. OFF
•Using as input ports
•Output P-channel Tr. OFF
•VOUT=3V
•Vp=-30V
Output disable
•f=1MHz
•VIN=VSS for all
unmeasured terminals.
•Ta=25°C
VDD[V]
min.
2.5 to 6.0
-1
2.5 to 6.0
-30
Ratings
typ.
max.
µA
4.0 to 6.0
kΩ
200
5.0
unit
60
100
200
2.5 to 6.0
0.1VDD
V
2.5 to 6.0
10
pF
4. Serial input/output characteristics / Ta=-30°C to +70°C, VSS1=VSS2=0V
Serial output
Serial input
Input clock
Output clock
Serial clock
Parameter
Cycle
Low Level
pulse width
High Level
pulse width
Cycle
Low Level
pulse width
High Level
pulse width
Symbol
Pins
tCKCY(1)
tCKL(1)
SCK0,SCK1
Conditions
Refer to figure 5
VDD[V]
min.
2.5 to 6.0
2
1
tCKH(1)
tCKCY(2)
tCKL(2)
tICK
Data hold time
tCKI
Output delay time
(External clock
using for serial
transfer clock)
tCKO(1)
Output delay time
(Internal clock
using for serial
transfer clock)
tCKO(2)
max.
unit
tCYC
1
SCK0,SCK1
tCKH(2)
Data set-up time
Ratings
typ.
•SI0,SI1
•SB0,SB1
•SO0,SO1
•SB0,SB1
•Use pull-up
resistor (1kΩ) in
the open drain
output.
•Refer to figure 5
2.5 to 6.0
•Data set-up to
SCK0,1
•Data hold from
SCK0,1
•Refer to figure 5
•Use pull-up
resistor (1kΩ) in
the open drain
output.
•Data hold from
SCK0,1
•Refer to figure 5
4.5 to 6.0
0.1
2.5 to 6.0
4.5 to 6.0
2.5 to 6.0
0.4
0.1
0.4
2
1/2tCKCY
1/2tCKCY
µs
4.5 to 6.0
7/12
tCYC
2.5 to 6.0
7/12
tCYC
4.5 to 6.0
1/3
+0.2
+1
tCYC
+0.2
2.5 to 6.0
1/3
tCYC
+1
No.6699-14/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
5. Pulse Input Conditions at Ta=-30°C to +70°C, VSS1=VSS2=0V
Parameter
Symbol
Pins
High/low level
pulse width
tPIH(1)
tPIL(1)
tPIH(2)
tPIL(2)
•INT0, INT1
•INT2/T0IN
INT3/T0IN
(The noise rejection clock
selected to 1/1.)
INT3/T0IN
(The noise rejection clock
selected to 1/16.)
INT3/T0IN
(The noise rejection clock
selected to 1/64.)
RES
tPIH(3)
tPIL(3)
tPIH(4)
tPIL(4)
tPIL(5)
Conditions
VDD[V]
min.
•Interrupt acceptable
•Timer0-countable
•Interrupt acceptable
•Timer0-countable
2.5 to 6.0
1
2.5 to 6.0
2
•Interrupt acceptable
•Timer0-countable
2.5 to 6.0
32
•Interrupt acceptable
•Timer0-countable
2.5 to 6.0
128
Reset acceptable
2.5 to 6.0
200
Ratings
typ. max.
unit
tCYC
µs
6. AD Converter Characteristics at Ta=-30°C to + 70°C, VSS1=VSS2=0V
Parameter
Resolution
Absolute precision
(Note 2)
Conversion time
Analog input
voltage range
Analog port
input current
Symbol
Pins
Conditions
N
ET
IAINH
IAINL
min.
4.5 to 6.0
4.5 to 6.0
tCAD
VAIN
VDD[V]
AD conversion time =
16 × tCYC
(ADCR2=0)
(Note 3)
AD conversion time =
32 × tCYC
(ADCR2=1)
(Note 3)
AN0 to AN7
VAIN=VDD
VAIN=VSS
4.5 to 6.0
Ratings
typ.
max.
8
±1.5
unit
bit
LSB
µs
15.68
(tCYC=
0.98µs)
65.28
(tCYC=
4.08µs)
31.36
(tCYC=
0.98µs)
130.56
(tCYC=
4.08µs)
4.5 to 6.0
VSS
VDD
V
4.5 to 6.0
4.5 to 6.0
1
µA
-1
(Note 2) Absolute precision excepts the quantizing error (±1/2 LSB).
(Note 3) The conversion time means the time from executing the AD conversion instruction to setting the complete digital
conversion value to the register.
No.6699-15/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
7. Current Dissipation Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=0V
Parameter
Current dissipation
during basic
operation
(Note 4)
Symbol
IDDOP(1)
IDDOP(2)
IDDOP(3)
IDDOP(4)
IDDOP(5)
IDDOP(6)
IDDOP(7)
Pins
Conditions
•FmCF=6MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/1 divided
•FmCF=3MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/2 divided
•FmCF=0Hz
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•1/2 divided
•FmCF=0Hz
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
32.768kHz
•Internal RC
oscillation stops
•1/2 divided
Ratings
typ.
max.
4.5 to 6.0
10
25
4.5 to 6.0
2.5 to 4.5
3
1.5
9
5
4.5 to 6.0
0.7
3.4
2.5 to 4.5
0.4
2.8
4.5 to 6.0
35
130
2.5 to 4.5
15
70
VDD[V]
min.
unit
mA
µA
Continue.
No.6699-16/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
Parameter
Symbol
Current dissipation
IDDHALT(1)
in HALT mode
(Note 4)
IDDHALT(2)
IDDHALT(3)
IDDHALT(4)
IDDHALT(5)
IDDHALT(6)
IDDHALT(7)
Current dissipation
IDDHOLD(1)
in HOLD mode
IDDHOLD(2)
(Note 4)
Pins
Conditions
•HALT mode
•FmCF=6MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/1 divided
•HALT mode
•FmCF=3MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/2 divided
•HALT mode
FmCF=0Hz
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•1/2 divided
•HALT mode
FmCF=0Hz
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
crystal oscillation
•Internal RC
oscillation stops
•1/2 divided
HOLD mode
Ratings
typ.
max.
4.5 to 6.0
5
14
4.5 to 6.0
2.2
7
2.5 to 4.5
0.8
4
4.5 to 6.0
400
1600
2.5 to 4.5
200
1300
4.5 to 6.0
25
100
2.5 to 4.5
8
55
4.5 to 6.0
0.05
30
2.5 to 4.5
0.02
20
VDD[V]
min.
unit
mA
µA
(Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored.
No.6699-17/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
Table 1. Ceramic resonator oscillation recommended constant (main-clock)
Oscillation type
Maker
Oscillator
6MHz ceramic resonator oscillation
Murata
CSA6.00MG
CST6.00MGW
KBR-6.0MSB
PBRC6.00A(chip type)
KBR-6.0MKC
PBRC6.00B(chip type)
CSA3.00MG
CST3.00MGW
KBR-3.0MS
Kyocera
3MHz ceramic resonator oscillation
Murata
Kyocera
C1
C2
33pF
33pF
on chip
33pF
33pF
33pF
33pF
on chip
33pF
33pF
on chip
47pF
47pF
* Both C1 and C2 must be use K rank (±10%) and SL characteristics.
Table 2. Crystal oscillation guaranteed constant (sub-clock)
Oscillation type
32.768kHz crystal oscillation
Maker
EPSON
Oscillator
C-002RX
C3
18pF
C4
18pF
Rd
680kΩ
* Both C3 and C4 must be use J rank (±5%) and CH characteristics.
(Not in need of high precision, use K rank (±10%) and SL characteristics.)
(Notes)
• Please place the oscillation-related parts as close to the oscillation pins as possible with the shortest
possible pattern length since the circuit pattern affects the oscillation frequency.
• If you use other oscillators herein, we provide no guarantee for the characteristics.
CF1
CF2
XT1
XT2
Rd
CF
C1
Figure 1
C2
Main-clock circuit
Ceramic resonator oscillation
C3
X’tal
Figure 2
C4
Sub-clock circuit
Crystal oscillation
No.6699-18/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
VDD
VDD limit
Power supply
OV
Reset time
RES
Interrnal RC
resonator
oscillation
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Operation mode
Unfixed
Reset
Instruction
execution mode
OCR6=1
Instruction execution mode
< Reset time and oscillation stabilizing time. >
HOLD release signal
Valid
Interrnal RC
resonator
oscillation
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Operation mode
HOLD
Instruction execution mode
< HOLD release signal and oscillation stabilizing time. >
Figure 3
Oscillation stable time
No.6699-19/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
VDD
RRES
(Note) Fix the value of CRES, RRES that is
sure to reset until 200µs, after Power
supply has been over inferior limit of
supply voltage.
RES
CRES
Figure 4
Reset circuit
0.5VDD
<AC timing point>
tCKCY
tCKL
VDD
tCKH
SCK0
SCK1
1KΩ
tICK
tCKI
SI0
SI1
tCKO
50pF
SO0, SO1
SB0, SB1
<Timing>
Figure 5
tPIL
Figure 6
<Test load>
Serial input / output test condition
tPIH
Pulse input timing condition
No.6699-20/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
memo:
PS No.6699-21/21