Sanyo LC86P6548 8-bit single chip microcontroller with one-time programmable prom Datasheet

Ordering number : ENN*6690
CMOS IC
LC86P6548
8-Bit Single Chip Microcontroller
with One-Time Programmable PROM
Preliminary
Overview
The LC86P6548 is a CMOS 8-bit single chip microcontroller with one-time PROM for the LC866500 series.
This microcontroller has the function and the pin description of the LC866500 series mask ROM version, and 48K-byte
PROM.
Features
(1) Option switching by PROM data
The option function of the LC866500 series can be specified by the PROM data.
LC86P6548 can be checked the function of the trial pieces using the mass production board.
(2) Internal one-time PROM capacity
: 49408 bytes
(3) Internal RAM capacity
: 1152 bytes
Used PROM or RAM capacity are equal ROM or RAM capacity of mask ROM version which applies LC86P6548.
Mask ROM version
PROM capacity
RAM capacity
LC866548
LC866540
LC866532
LC866528
LC866524
49152 bytes
40960 bytes
32768 bytes
28672 bytes
24576 bytes
1152 bytes
1152 bytes
1152 bytes
896 bytes
896 bytes
Programming service
We offers various services at nominal charges. These include the ROM writing, the ROM reading, the package
stamping and the screening. Contact our representative for further information.
Ver.1.03
80696
91400 RM (IM) SK No.6690-1/22
LC86P6548
(4) Operating supply voltage
: 4.5V to 6.0V
(5) Instruction cycle time
: 1.0µs to 366µs
(6) Operating temperature
: -30°C to +70°C
(7) The pin and the package compatible with the LC866500 series mask ROM devices
(8) Applicable mask ROM version
: LC866548/LC866540//LC866532/LC866528/LC866524
Notice for use
LC86P6548 is provided for the first release and small shipping of the LC866500 series.
At using, take notice of the followings.
(1) A point of difference LC86P6548 and LC866500 series
Item
LC86P6548
LC866548/40/32/28/24
Operation after reset
releasing
The option is specified until 3ms after
going to a ‘H’ level to the reset terminal
by dgrees. The program is executed
from 00H of the program counter.
The program is executed from 00H of the
program counter immediately after going to
a ‘H’ level to reset terminal.
Pull-down resistor of
the following pins
•S0/T0 – S6/T6
•S7/T7 – S15/T15
•S16 – S31
•S32 – S47
•S48 – S51
Pull-down resistor
provided/not provided
Not provided
Provided (fixed)
Provided (fixed)
Not provided
Not provided
Pull-down resistor
provided/not provided
Specified by the option
Provided (fixed)
Specified by the option
Specified by the option
Not provided
Power dissipation
Refer to ‘electrical characteristics’ on the semiconductor news.
LC86P6548 uses 256 bytes that is addressed on FF00H to FFFFH in the program memory as the option configuration data
area. This option configuration cannot execute all options which LC866500 series have. Next tables show the options
that correspond and not correspond to LC86P6548.
• A kind of the option corresponding of the LC86P6548
A kind of option
Input/output form of
Input/output ports
Pins, Circuits
Contents of the option
Port 0
*1
3. Pull-up MOS Tr. proveded
4. Pull-up MOS Tr. not provided
*2
*1
1. Input
Output
2. Input
Output
: Programmable pull-up MOS Tr.
: N-channel open drain
: Programmable pull-up MOS Tr.
: CMOS
*1
1. Input
Output
2. Input
Output
: No Programmable pull-up MOS Tr.
: N-channel open drain
: Programmable pull-up MOS Tr.
: CMOS
Port 1
Port 3
*1) Specified in a bit
*2) Specified in nibble unit.
1. N-channel open drain output
2. CMOS output
The port of N-channel open drain output does not have the Pull-up MOS Tr..
No.6690-2/22
LC86P6548
• A kind of the option not corresponding of the LC86P6548
A kind of option
Pins, Circuits
Pull-down resistor of
the high voltage
Withstand output terminals
•S0/T0 to S6/T6
•S16 to S31
•S32 to S47
LC86P6548
Not provided
Provided (fixed)
Not provided
LC866548/40/32/28/24
Specified by the option
Specified by the option
Specified by the option
(2) Option
The option data is created by the option specified program “SU86K.EXE”.
program area by linkage loader “L86K.EXE”.
The created option data is linked to the
(3) ROM space
LC86P6548 and LC866500 series use 256 bytes that is addressed on 0FF00H to 0FFFFH in the program memory as the
option specified data area. These program memory capacity are 49152 bytes that is addressed on 0000H to BFFFH.
0FFFFH
0FF00H
0EFFFH
0DFFFH
0CFFFH
0BFFFH
0AFFFH
9FFFH
8FFFH
7FFFH
6FFFH
5FFFH
4FFFH
3FFFH
2FFFH
1FFFH
0FFFH
0000H
The option
specified area
256 bytes
The option
specified area
The option
specified area
The option
specified area
The option
specified area
Program area
48K bytes
Program area
40K bytes
Program area
32K bytes
Program area
28K bytes
Program area
24K bytes
LC866548
LC866540
LC866532
LC866528
LC866524
(4) Ordering information
1. When ordering the identical mask ROM and PROM devices simultaneously.
Provide an EPROM containing the target memory contents together with the separate order forms for each of the mask
ROM and PROM versions.
2. When ordering a PROM device.
Provide an EPROM containing the target memory contents together with an order form.
No.6690-3/22
LC86P6548
How to use
(1) Specification of option
Programming data for PROM of the LC86P6548 is required.
Debugged evaluation file (EVA file) must be converted to an INTEL-HEX formatted file (HEX file) with file converter
program, EVA2HEX.EXE. The HEX file is used as the programming data for the LC86P6548.
(2) How to program for the PROM
LC86P6548 can be programmed by the EPROM programmer with attachment ; W86EP6548Q.
• Recommended EPROM programmer
Productor
EPROM programmer
Advantest
R4945, R4944, R4943
Andou
AF-9704
AVAL
PKW-1100, PKW-3000
Minato electronics
MODEL 1890A
• “27512 (Vpp=12.5V) Intel high speed programming” mode available. The address must be set to
“0 to 0FFFFH” and a jumper (DASEC) must be set to ‘OFF’ at programming.
(3) How to use the data security function
“Data security” is the disabled function to read the data of the PROM.
The following is the process in order to execute the data security.
1. Set ‘ON’ the jumper of attachment.
2. Program again. Then EPROM programmer displays the error. The error means normally activity of the data
security. It is not a trouble of the EPROM programmer or the LSI.
Notes
• Data security is not executed when the data of all address have ‘FFH’ at the sequence 2 above.
• The programming by a sequential operation “BLANK⇒PROGRAM⇒VERIFY” cannot be executed data security at the
sequence 2 above.
• Set to ‘OFF’ the jumper after executing the data security.
Data security
1 pin mark
of LSI
Not data security
1 pin
W86EP6548Q
No.6690-4/22
P16/BUZZ
P17/PWM0
P30
P31
P32
P33
P34
P35
P36
P37
P70/INT0
RES
XT1/P74
XT2/P75
VSS1
CF1
CF2
VDD1
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
P71/INT1
P72/INT2/T0IN
P72/INT3/T0IN
S0/T0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
S47/PF7
S46/PF6
S45/PF5
S44/PF4
S43/PF3
S42/PF2
S41/PF1
S40/PF0
VDD4
S39/PE7
S38/PE6
S37/PE5
S36/PE4
S35/PE3
S34/PE2
S33/PE1
S32/PE0
S31/PD7
S30/PD6
S29/PD5
S28/PD4
S27/PD3
S26/PD2
S25/PD1
S24/PD0
S23/PC7
S22/PC6
S21/PC5
S20/PC4
VP
LC86P6548
Pin Assignment
S48/PG0
S49/PG1
S50/PG2
S51/PG3
P00
P01
P02
P03
VSS2
VDD2
P04
P05
P06
P07
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
S19/PC3
S18/PC2
S17/PC1
S16/PC0
VDD3
S15/T15
S14/T14
S13/T13
S12/T12
S11/T11
S10/T10
S9/T9
S8/T8
S7/T7
S6/T6
S5/T5
S4/T4
S3/T3
S2/T2
S1/T1
Package Dimension
(unit : mm)
3151
SANYO : QIP-100E
No.6690-5/22
LC86P6548
System Block Diagram
Interrupt Control
IR
Standby Control
RC
A15-A0
D7-D0
TA
CE
OE
DASEC
PROM
Control
Clock
Generator
CF
PLA
PROM(48KB)
X’tal
PC
Base Timer
Bus Interface
ACC
SIO0
Port 1
B Register
SIO1
Port 3
C Register
Timer 0
Port 7
ALU
Timer 1
Port 8
ADC
PSW
INT0-3
Noise Filter
RAR
SIO Automatic
transmission
RAM
RAM
128 bytes
Stack Pointer
Port 0
VFD
Controller
Watchdog Timer
High voltage Output
No.6690-6/22
LC86P6548
LC86P6548 Pin Description
Pin name
VSS1,2
I/O
-
Function description
Option
Power pin (-)
*4
*4
-
PROM mode
-
VDD1,2,3,4
-
Power pin (+)
-
-
VP
-
Power pin (+) for the VFD output pull-down resist
-
-
PORT0
P00 to P07
I/O
•8-bit input/output port
•Input for port 0 interrupt
•Input/output in nibble units
•Input for HOLD release
•15V withstand at N-channel open drain
output
•Pull-up resistor :
Provided/Not provided
(each nibble)
•Output form :
CMOS/N-channel open
drain (each bit)
-
PORT1
P10 to P17
I/O
•8-bit input/output port
•Input/output can be specified in a bit unit
•Other pin functions
P10 SIO0 data output
P11 SIO0 data input/bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 data input/bus input/output
P15 SIO1 clock input/output
P16 Buzzer output
P17 Timer 1 output (PWM0 output)
•Output form :
CMOS/N-channel open
drain (each bit)
Data line
D0 to D7
PORT3
P30 to P37
I/O
•8-bit input/output port
•Input/output in bit unit
•15V withstand at N-channel open drain
output
•Output form :
CMOS/N-channel open
drain (each bit)
-
PORT7
P70 to P73
I/O
P74 to P75
I
•4-bit input/output port
•Input/output in bit unit
•2-bit input port
•Other pin functions
P70 : INT0 input/HOLD release/N-channel Tr.
output for watchdog timer
P71 : INT1 input/HOLD release input
P72 : INT2 input/timer 0 event input
P73 : INT3 input with noise filter/timer 0 event
input
P74 : 32.768kHz crystal oscillation terminal XT1
PROM control
signals
DASEC (*1)
OE (*2)
CE (*3)
‚bE
P75 : 32.768kHz crystal oscillation terminal XT2
•Interrupt received forms, the vector addresses
rising falling rising high
level
&
falling
low vector
level
INT0 enable enable disable enable enable 03H
INT1 enable enable disable enable enable 0BH
INT2 enable enable enable disable disable 13H
INT3 enable enable enable disable disable 1BH
Continue.
No.6690-7/22
LC86P6548
Pin name
PORT8
P80 to 83
P84 to 87
I/O
I
I/O
Function description
Option
PROM mode
•4-bit input port
•Input/output in bit unit
•4-bit input port
•Other function
AD input port (8 port pins)
-
-
S0/T0 to
S6/T6 *6
O
Output for VFD display controller
segment/timing in common
-
-
S7/T7 to
S15/T15
*7
O
•Output for VFD display controller
segment/timing with internal pull-down
resistor in common
•Internal pull-down resistor output
-
TA (*5)
S16 to S31
*8
I/O
•Output for VFD display controller Segment
output
•Other function
S16 : High voltage input port PC0
S17 : High voltage input port PC1
S18 : High voltage input port PC2
S19 : High voltage input port PC3
S20 : High voltage input port PC4
S21 : High voltage input port PC5
S22 : High voltage input port PC6
S23 : High voltage input port PC7
-
•Address input
A15 to A0
-
-
S24 : High voltage input port PD0
S25 : High voltage input port PD1
S26 : High voltage input port PD2
S27 : High voltage input port PD3
S28 : High voltage input port PD4
S29 : High voltage input port PD5
S30 : High voltage input port PD6
S31 : High voltage input port PD7
S32 to S47
*9
I/O
•Output for VFD display controller Segment
•Other function
S32 : High voltage input port PE0
S33 : High voltage input port PE1
S34 : High voltage input port PE2
S35 : High voltage input port PE3
S36 : High voltage input port PE4
S37 : High voltage input port PE5
S38 : High voltage input port PE6
S39 : High voltage input port PE7
S40 : High voltage I/O port PF0
S41 : High voltage I/O port PF1
S42 : High voltage I/O port PF2
S43 : High voltage I/O port PF3
S44 : High voltage I/O port PF4
S45 : High voltage I/O port PF5
S46 : High voltage I/O port PF6
S47 : High voltage I/O port PF7
Continue.
No.6690-8/22
LC86P6548
Pin name
I/O
S48 to S51
*9
I/O
Function description
Option
PROM mode
•Output for VFD display controller Segment
•Other function
S48 : High voltage I/O port PG0
S49 : High voltage I/O port PG1
S50 : High voltage I/O port PG2
S51 : High voltage I/O port PG3
-
-
RES
I
Reset pin
-
-
XT1/ P74
I
•Input pin for 32.768kHz crystal oscillation
•Other function
XT1 : Input port P74
-
-
•Output pin for 32.768kHz crystal oscillation
•Other function
XT2 : Input port P75
In case of non use, connect to VDD1 at using
as port or unconnect at using as oscillation.
-
-
In case of non use, connect to VDD1.
XT2/P75
O
CF1
I
Input pin for the ceramic resonator oscillation
-
-
CF2
O
Output pin for the ceramic resonator oscillation
-
-
♦ All of port options (except pull-up resistor of port 0) can be specified in bit unit.
*1
*2
*3
*4
*5
*6
*7
*8
*9
Memory select input for data security
Output enable input
Chip enable input
Connect like the following figure to reduce noise into a VDD1 terminal.
Shorted the VSS1 terminal to the VSS2 terminal and to make the back-up time long.
TA ! PROM control signal input
S0/T0 to S6/T6 : not provided the pull-down resistor
S7/T7 to S15/T15 : provided the pull-down resistor (fixed)
S16 to S31 : provided the pull-down resistor (fixed)
S32 to S51 : not provided the pull-down resistor
LSI
VDD1
Power
Supply
Back-up capacitor
VDD2
VDD3
VFD
powers
VDD4
VSS1
VSS2
No.6690-9/22
LC86P6548
1. Absolute Maximum Ratings at VSS1=VSS2=0V and Ta=25°C
Parameter
Supply voltage
Symbol
Pins
Conditions
VDDMAX VDD1, VDD2
VDD1=VDD2
=VDD3=VDD4
VI(2)
VDD3, VDD4
•Ports 74 ,75
•Ports 80,81,82,83
•Port 8
• RES
VP
Output voltage
VO(1)
S0/T0 to S15/T15
Input/Output
voltage
VIO(1)
VIO(3)
•Port 1
•Ports 70,71,72,73
•Ports 84,85,86,87
•Ports 0, 3 at CMOS
output option
Ports 0, 3 at N-ch open
drain output option
S16 to S51
IOPH(1)
Ports 0, 1, 3
Input voltage
VI(1)
VIO(2)
High
Peak
level
output
output current
current
Total
output
current
Low
level
output
current
Peak
output
current
Total
output
current
Maximum
power
dissipation
Operating
temperature
range
Storage
temperature
range
IOPH(2)
IOPH(3)
ΣIOAH(1)
ΣIOAH(2)
ΣIOAH(3)
ΣIOAH(4)
ΣIOAH(5)
ΣIOAH(6)
IOPL(1)
IOPL(2)
S0/T0 to S15/T15
S16 to S51
Port 0
Ports 1, 3
S0/T0 to S15/T15
S16 to S27
S28to S39
S40 to S51
Ports 0,1,3
•Ports 70,71,72,73
•Ports 84,85,86,87
ΣIOAL(1) Port 0
ΣIOAL(2) Ports 1,3,70
ΣIOAL(3) •Ports 71,72,73
•Ports 84,85,86,87
Pdmax
QFP100E
Ratings
VDD[V]
min.
max.
-0.3
+7.0
-0.3
VDD+
0.3
VDD-45
VDD+
0.3
VDD+
0.3
VDD+
0.3
VDD-45
-0.3
•CMOS output
•At each pins
At each pins
At each pins
The total of all pins
The total of all pins
The total of all pins
The total of all pins
The total of all pins
The total of all pins
At each pins
At each pins
typ.
-0.3
15
VDD-45
VDD+
0.3
-10
unit
V
mA
-30
-15
-30
-30
-55
-60
-60
-60
20
15
The total of all pins
The total of all pins
The total of all pins
60
50
20
Ta=-30 to+70°C
500
mW
°C
Topr
-30
70
Tstg
-55
125
No.6690-10/22
LC86P6548
2. Recommended Operating Range at Ta=-30°C to +70°C, VSS1=VSS2=0V
Parameter
Symbol
Pins
Conditions
0.98µs ≤ tCYC
tCYC ≤ 400µs
RAMs and the
registers hold
voltage at HOLD
mode.
Operating
VDD(1)
Supply voltage
Hold voltage
VHD
VDD1=VDD2
=VVDD3=VDD4
VDD1=VDD2
Pull-down
Voltage
Input high
voltage
VP
VP
VIH(1)
Port 0 at CMOS output
Output disable
VIH(2)
Port 0 at N-ch open drain
output
•Port 1
•Ports 72,73
•Port 3 at CMOS
output
•Port 3 at N-ch open
drain output
•Port 70
Port input/interrupt
•Port 71
• RES
Port 70
Watchdog timer
•Port 8
•Ports 74 ,75
VIH(3)
VIH(4)
VIH(5)
VIH(6)
VIH(7)
Input low
voltage
VIH(8)
S16 to S51
VIL(1)
Port 0 at CMOS
output option
Port 0 at N-ch open
drain output
•Ports 1,3
•Ports 72,73
•Port 70
Port input/interrupt
•Port 71
• RES
VIL(2)
VIL(3)
VIL(4)
VIL(5)
VIL(6)
VIL(7)
Operation
cycle time
Port 70
Watchdog timer
•Port 8
•Ports 74 ,75
S16 to S51
Ratings
VDD[V]
4.5 to 6.0
min.
typ.
max.
4.5
6.0
2.0
6.0
-35
VDD
VDD
Output disable
4.5 to 6.0 0.33VDD
+1.0
4.5 to 6.0 0.75VDD
Output disable
4.5 to 6.0 0.75VDD
VDD
Output disable
Tr. OFF
Output disable
4.5 to 6.0 0.75VDD
13.5
4.5 to 6.0 0.75VDD
VDD
Output disable
4.5 to 6.0 0.9VDD
VDD
Output disable
4.5 to 6.0 0.75VDD
VDD
Output P-channel
Tr. OFF
Output disable
4.5 to 6.0 0.33VDD
+1.0
4.5 to 6.0 VSS
VDD
0.2VDD
Output disable
4.5 to 6.0
VSS
0.25VDD
Output disable
4.5 to 6.0
VSS
0.25VDD
Output disable
4.5 to 6.0
VSS
0.25VDD
Output disable
4.5 to 6.0
VSS
Output disable
4.5 to 6.0
VSS
0.8VDD
-1.0
0.25VDD
Output P-channel
Tr. OFF
4.5 to 6.0
VP
0.2VDD
4.5 to 6.0
0.98
400
tCYC
unit
V
13.5
µs
Continue.
No.6690-11/22
LC86P6548
Parameter
Symbol
Pins
Conditions
Oscillation
FmCF(1)
frequency
range
(Note 1)
FmCF(2)
CF1, CF2
•6MHz
(ceramic resonator
oscillation)
•Refer to figure 1
•3MHz
(ceramic resonator
oscillation)
•Refer to figure 1
RC oscillation
•32.768kHz
(crystal oscillation)
•Refer to figure 2
•6MHz
(ceramic resonator
Oscillation
stabilizing
time period
(Note 1)
CF1, CF2
FmRC
FsXtal
XT1, XT2
tmsCF(1)
CF1, CF2
Ratings
VDD[V]
min.
typ.
4.5 to 6.0
6
4.5 to 6.0
3
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
0.3
0.8
32.768
max.
unit
MHz
3.0
kHz
ms
oscillation)
tmsCF(2)
CF1, CF2
•Refer to figure 3
•3MHz
(ceramic resonator
4.5 to 6.0
oscillation)
tssXtal
XT1, XT2
•Refer to figure 3
•32.768kHz
(crystal oscillation)
•Refer to figure 3
4.5 to 6.0
s
(Note 1) The oscillation constant is shown on table 1.
No.6690-12/22
LC86P6548
3. Electrical Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=0V
Parameter
Input high
current
Input low
current
Output high
voltage
Symbol
Pins
IIH(1)
Ports 0,3 at open
drain output
IIH(2)
•Ports 1,3
•Port 0 without
pull-up MOS Tr.
IIH(3)
•Ports 70,71,72,73
•Port 8
IIH(4)
IIH(5)
IIH(6)
RES
Ports 74 ,75
•S32 to S51 without
pull-down resistor
•Ports 1,3
•Port 0 without
pull-up MOS Tr.
IIL(1)
IIL(2)
•Ports 70,71,72,73
•Port 8
IIL(3)
IIL(4)
VOH(1)
VOH(2)
VOH(3)
VOH(4)
RES
Ports 74 ,75
Ports 0,1,3 of
CMOS output
S0/T0 to S15/T15
VOH(5) S16 to S51
VOH(6)
Output low
voltage
VOL(1) Ports 0,1,3
VOL(2)
VOL(3) Port 70
VOL(4) •Ports 71,72,73
•Ports 84,85,86,87
Pull-up MOS Rpu
Ports 0,1,3
Tr. resistor
Conditions
•Output disable
•VIN=13.5V
(including off-leakage
current of the output Tr.)
•Output disable
•Pull-up MOS Tr. OFF.
•VIN=VDD
(including off-leakage
current of the output Tr.)
•Output disable
•VIN=VDD
(including off-leakage
current of the output Tr.)
VIN=VDD
VIN=VDD
•Output P-channel Tr. OFF.
•VIN=VDD
•Output disable
•Pull-up MOS Tr. OFF.
•VIN=VSS
(including off-leakage
current of the output Tr.)
•Output disable
•VIN=VSS
(including off-leakage
current of the output Tr.)
VIN=VSS
VIN=VSS
IOH=-1.0mA
IOH=-0.1mA
IOH=-20mA
•IOH=-1.0mA
•The current of any
unmeasurement pin is not
over 1mA.
IOH=-5mA
•IOH=-1.0mA
•The current of any
unmeasurement pins is not
over 1mA.
IOL=10mA
IOL=1.6mA
IOL=1mA
IOL=1.6mA
VOH=0.9VDD
VDD[V]
4.5 to 6.0
min.
Ratings
typ.
max.
5
4.5 to 6.0
1
4.5 to 6.0
1
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
1
1
1
4.5 to 6.0
-1
4.5 to 6.0
-1
4.5 to 6.0
-1
4.5 to 6.0
-1
4.5 to 6.0 VDD-1
4.5 to 6.0 VDD-0.5
4.5 to 6.0 VDD-1.8
4.5 to 6.0 VDD-1
unit
µA
V
4.5 to 6.0 VDD-1.8
4.5 to 6.0 VDD-1
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
1.5
0.4
0.4
0.4
15
40
70
KΩ
Continue.
No.6690-13/22
LC86P6548
Parameter
Output offleakage current
Symbol
Pins
Ratings
Conditions
IOFF(1) •S0/T0 to S6/T6
•S32 to S51
(without pull-down
IOFF(2) resistor)
•Output P-channel
Tr. OFF
•VOUT=VSS
•Output P-channel
Tr. OFF
•VOUT=VDD-40V
•Output P-channel
Tr. OFF
•Using as input ports
•Output P-channel
Tr. OFF
•VOUT=3V
•Vp=-30V
•VSS=GND
•Vp=-30V
Output disable
Resistance of
The low level
Hold Tr.
High voltage
Pull-down
resistor
Rinpd
S16 to S51
Rpd
•S7/T7 to S15/T15
•S16 to S31
VP pull-down
resistor
Hysteresis
voltage
Rvppd
Vp
VHIS
Pin capacitance
CP
•Port 1
•Ports 70,71,72,73,75
• RES
All pins
•f=1MHz
•VIN=VSS for all
unmeasured terminals.
•Ta=25°C
VDD[V]
min.
4.5 to 6.0
-1
4.5 to 6.0
-30
typ.
max.
unit
µA
4.5 to 6.0
200
KΩ
5.0
60
100
200
5.0
60
100
200
4.5 to 6.0
0.1VDD
V
4.5 to 6.0
10
pF
4. Serial Input/Output Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=0V
Serial output
Serial input
Symbol
Pins
tCKCY(1)
tCKL(1)
SCK0,SCK1
tICK
Data hold time
tCKI
Output delay time
(External clock
using for serial
transfer clock)
Output delay time
(Internal clock
using for serial
transfer clock)
tCKO(1)
Input clock
Cycle
Low Level
pulse width
High Level
pulse width
Cycle
Low Level
pulse width
High Level
pulse width
Data set-up time
Output clock
Serial clock
Parameter
Conditions
Refer to figure 5
Ratings
VDD[V]
min.
4.5 to 6.0
2
1
tCKH(1)
tCKCY(2)
tCKL(2)
max.
unit
tCYC
1
SCK0,SCK1
tCKH(2)
tCKO(2)
typ.
•SI0,SI1
•SB0,SB1
•SO0,SO1
•SB0,SB1
•Use pull-up
resistor (1kΩ) in
the open drain
output.
•Refer to figure 5
4.5 to 6.0
•Data set-up to
SCK0,1
•Data hold from
SCK0,1
•Refer to figure 5
4.5 to 6.0
•Use pull-up
resistor (1kΩ) in
the open drain
output.
•Data hold from
SCK0,1
•Refer to figure 5
4.5 to 6.0
2
1/2tCKCY
1/2tCKCY
µs
0.1
0.1
7/12
tCYC
+0.2
1/3
tCYC
+0.2
No.6690-14/22
LC86P6548
5. Pulse Input Conditions at Ta=-30°C to +70°C, VSS1=VSS2=0V
Parameter
Symbol
Pins
High/low level
pulse width
tPIH(1)
tPIL(1)
tPIH(2)
tPIL(2)
•INT0, INT1
•INT2/T0IN
INT3/T0IN
(The noise rejection clock
selected to 1/1.)
INT3/T0IN
(The noise rejection clock
selected to 1/16.)
INT3/T0IN
(The noise rejection clock
selected to 1/64.)
RES
tPIH(3)
tPIL(3)
tPIH(4)
tPIL(4)
tPIL(5)
Conditions
Ratings
VDD[V]
min.
•Interrupt acceptable
•Timer0-countable
•Interrupt acceptable
•Timer0-countable
4.5 to 6.0
1
4.5 to 6.0
2
•Interrupt acceptable
•Timer0-countable
4.5 to 6.0
32
•Interrupt acceptable
•Timer0-countable
4.5 to 6.0
128
Reset acceptable
4.5 to 6.0
200
typ.
max.
unit
tCYC
µs
6. AD Converter Characteristics at Ta=-30°C to + 70°C, VSS1=VSS2=0V
Parameter
Resolution
Absolute precision
(Note 2)
Conversion time
Analog input
voltage range
Analog port
input current
Symbol
Pins
Conditions
N
ET
IAINH
IAINL
min.
4.5 to 6.0
4.5 to 6.0
tCAD
VAIN
Ratings
VDD[V]
AD conversion time =
16 × tCYC
(ADCR2=0)
(Note 3)
AD conversion time =
32 × tCYC
(ADCR2=1)
(Note 3)
AN0 to AN7
VAIN=VDD
VAIN=VSS
typ.
max.
8
±1.5
unit
bit
LSB
µs
4.5 to 6.0 15.68
(tCYC=
0.98µs)
65.28
(tCYC=
4.08µs)
31.36
(tCYC=
0.98 µs)
130.56
(tCYC=
4.08µs)
4.5 to 6.0
VSS
VDD
V
4.5 to 6.0
4.5 to 6.0
1
µA
-1
(Note 2) Absolute precision excepts the quantizing error (±1/2 LSB).
(Note 3) The conversion time means the time from executing the AD conversion instruction to setting the complete digital
conversion value to the register.
No.6690-15/22
LC86P6548
7. Current Dissipation Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=0V
Parameter
Current dissipation
during basic
operation
(Note 4)
Symbol
IDDOP(1)
IDDOP(2)
IDDOP(3)
IDDOP(4)
Pins
Conditions
•FmCF=6MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/1 divided
•FmCF=3MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/2 divided
•FmCF=0Hz
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•1/2 divided
•FmCF=0Hz
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
32.768kHz
•Internal RC
oscillation stops
•1/2 divided
Ratings
VDD[V]
min.
typ.
max.
4.5 to 6.0
14
33
4.5 to 6.0
6
18
4.5 to 6.0
4
13
4.5 to 6.0
3
10
unit
mA
Continue.
No.6690-16/22
LC86P6548
Parameter
Symbol
Current dissipation
IDDHALT(1)
in HALT mode
(Note 4)
IDDHALT(2)
IDDHALT(3)
IDDHALT(4)
Current dissipation
IDDHOLD(1)
in HOLD mode
(Note 4)
Pins
Conditions
•HALT mode
•FmCF=6MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/1 divided
•HALT mode
•FmCF=3MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/2 divided
•HALT mode
FmCF=0Hz
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•1/2 divided
•HALT mode
FmCF=0Hz
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
crystal oscillation
•Internal RC
oscillation stops
•1/2 divided
HOLD mode
Ratings
VDD[V]
min.
typ.
max.
4.5 to 6.0
5
14
4.5 to 6.0
2.2
7
4.5 to 6.0
400
1600
4.5 to 6.0
25
100
4.5 to 6.0
0.05
30
unit
mA
µA
(Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored.
No.6690-17/22
LC86P6548
Table 1. Ceramic resonator oscillation recommended constant (main-clock)
Oscillation type
Maker
6MHz ceramic resonator
oscillation
Murata
3MHz ceramic resonator
oscillation
Oscillator
C1
C2
Kyocera
Murata
Kyocera
* Both C1 and C2 must be use K rank (±10%) and SL characteristics.
Table 2. Crystal oscillation guaranteed constant (sub-clock)
Oscillation type
Maker
Oscillator
C3
C4
Rd
Rf
32.768kHz crystal oscillation
* Both C3 and C4 must be use J rank (±5%) and CH characteristics.
(Not in need of high precision, use K rank (±10%) and SL characteristics.)
(Notes)
• Please place the oscillation-related parts as close to the oscillation pins as possible with the shortest
possible pattern length since the circuit pattern affects the oscillation frequency.
• If you use other oscillators herein, we provide no guarantee for the characteristics.
CF1
CF2
XT1
XT2
Rf
Rd
CF
C1
Figure 1
C2
Main-clock circuit
Ceramic resonator oscillation
X’tal
C3
Figure 2
C4
Sub-clock circuit
Crystal oscillation
No.6690-18/22
LC86P6548
VDD
VDD limit
0V
Power supply
Reset time
RES
Internal RC resonator
oscillation
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Operation mode
Unfixed
Instruction
execution mode
OCR6=1
Reset
Instruction execution mode
<Reset time and oscillation stable time>
HOLD release signal
Valid
Internal RC resonator
oscillation
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Operation mode
HOLD
Instruction execution mode
<HOLD release signal and oscillation stable time>
Figure 3
Oscillation stable time
No.6690-19/22
LC86P6548
VDD
RRES
(Note) Fix the value of CRES, RRES that is
sure to reset until 200µs, after Power
supply has been over inferior limit of
supply voltage.
RES
CRES
Figure 4
Reset circuit
0.5VDD
<AC timing point>
tCKCY
tCKL
VDD
tCKH
SCK0
SCK1
1KΩ
tICK
tCKI
SI0
SI1
tCKO
50pF
SO0, SO1
SB0, SB1
<Timing>
Figure 5
tPIL
Figure 6
Serial input / output test condition
tPIH
Pulse input timing condition
No.6690-20/22
LC86P6548
Notice For Use
• The construction of the one-time programmable microcomputer with a blank built-in PROM makes it impossible for
Sanyo to completely factory-test it before shipping. To probe reliability of the programmed devices, the screening
procedure shown in the following figure should always be followed.
• It is not possible to perform a writing test on the blank PROM.
100% yield, therefore, cannot be guaranteed.
• Keeping the dry packing
The environment must be held at a temperature of 30°C or less and a humidity level of 70% or less.
• After opening the packing
The preparation procedures shown in the following figure should always be followed prior to mounting the packages on
the substrate. After opening the packing, a controlled environment must be maintained until soldering. The
environment must be held at a temperature of 30°C or less and a humidity level of 70% or less. Please solder within 96
hours.
Unused devices should be kept in the dry atmosphere such as inside of desiccator or dry these up before assembling on the
board.
a. Shipping with a blank PROM
(Programming the data by yourself)
b. Shipping with a programmed PROM
(Programming the data by Sanyo)
QFP
QFP
Writing data for
program/Verifying
Mounting
Recommended process of screening
Heat-soak
150±5°C,24 +1 Hr
-0
Reading ascertain of program
VDD=5±0.5V
Mounting
No.6690-21/22
LC86P6548
memo:
PS No.6690-22/22