TI1 LF441MH Lf441 low power jfet input operational amplifier Datasheet

LF441
LF441 Low Power JFET Input Operational Amplifier
Literature Number: SNOSC14A
LF441 Low Power JFET
Input Operational Amplifier
General Description
The LF441 low power operational amplifier provides many
of the same AC characteristics as the industry standard
LM741 while greatly improving the DC characteristics of the
LM741. The amplifier has the same bandwidth, slew rate,
and gain (10 kX load) as the LM741 and only draws one
tenth the supply current of the LM741. In addition, the well
matched high voltage JFET input devices of the LF441 reduce the input bias and offset currents by a factor of 10,000
over the LM741. A combination of careful layout design and
internal trimming guarantees very low input offset voltage
and voltage drift. The LF441 also has a very low equivalent
input noise voltage for a low power amplifier.
The LF441 is pin compatible with the LM741, allowing an
immediate 10 times reduction in power drain in many applications. The LF441 should be used where low power
dissipation and good electrical characteristics are the major
considerations.
Typical Connection
Ordering Information
Features
Y
Y
Y
Y
Y
Y
Y
Y
200 mA (max)
50 pA (max)
0.5 mV (max)
10 mV/§ C (max)
1 MHz
1 V/ms
35 nV/ SHz
0.01 pA/ SHz
1012X
50k (min)
et
Y
1/10 supply current of a LM741
Low input bias current
Low input offset voltage
Low input offset voltage drift
High gain bandwidth
High slew rate
Low noise voltage for low power
Low input noise current
High input impedance
High gain VO e g 10V, RL e 10k
e
Y
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LF441XYZ
X indicates electrical grade
Y indicates temperature range
‘‘M’’ for military,
‘‘C’’ for commercial
Z indicates package type
‘‘H’’ or ‘‘N’’
TL/H/9297 – 1
Connection Diagrams
Dual-In-Line Package
O
Metal Can Package
TL/H/9297 – 2
Top View
Note: Pin 4 connected to case.
Order Number LF441MH/883
See NS Package Number H08A
TL/H/9297 – 4
Top View
Order Number LF441ACN,
LF441CM or LF441CN
See NS Package Number M08A or N08E
BI-FETTM is a trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/H/9297
RRD-B30M115/Printed in U. S. A.
LF441 Low Power JFET Input Operational Amplifier
February 1995
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
LF441A
LF441
Supply Voltage
g 22V
g 18V
Differential Input Voltage
g 38V
g 30V
Continuous
Continuous
N Package
670 mW
670 mW
150§ C
115§ C
130§ C/W
M Package
185§ C/W
165§ C/W
65§ C/W
25§ C/W
(Note 3)
b 65§ C s TA s 150§ C
300§ C
LF441A
LF441
260§ C
260§ C
215§ C
220§ C
215§ C
220§ C
(Note 3)
b 65§ C s TA s 150§ C
260§ C
See AN-450 ‘‘Surface Mounting Methods and Their Effect
on Product Reliability’’ for other methods of soldering surface mount devices.
ESD Tolerance (Note 10)
Rating to be Determined
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DC Electrical Characteristics (Note 4)
Symbol
g 15V
e
Soldering Information
Dual-In-Line Package
Soldering (10 sec.)
Small Outline Package
Vapor Phase (60 sec.)
Infrared (15 sec.)
g 19V
Output Short Circuit
Duration
et
Operating Temp. Range
Storage Temp. Range
Lead Temperature
(Soldering, 10 seconds)
LF441
H Package
Power Dissipation
(Notes 2 and 9)
Tj max
ijA(Typical)
Board Mount in still air
Board Mount in 400 LF/
min air flow
ijC
LF441A
Input Voltage Range
(Note 1)
Parameter
LF441A
Conditions
Min
VOS
Input Offset Voltage
RS e 10 kX, TA e 25§ C
DVOS/DT
Average TC of Input
Offset Voltage
RS e 10 kX (Note 5)
IOS
Input Offset Current
VS e g 15V
(Notes 4 and 6)
LF441
Typ
Max
0.3
0.5
Min
Max
1
5
mV
7.5
mV
Over Temperature
Input Bias Current
VS e g 15V
(Notes 4 and 6)
O
IB
Tj e 25§ C
7
10
10
5
25
5
Tj e 70§ C
1.5
Tj e 125§ C
10
Tj e 25§ C
10
Tj e 70§ C
50
Tj e 25§ C
AVOL
Large Signal Voltage
Gain
VS e g 15V, VO e g 10V,
RL e 10 kX, TA e 25§ C
VO
Output Voltage Swing
VCM
Input Common-Mode
Voltage Range
CMRR
Common-Mode
Rejection Ratio
Over Temperature
50
g 12
g 16
RS s 10 kX
80
2
pA
1.5
nA
10
100
pA
3
nA
nA
100
25
g 13
g 12
25
VS e g 15V, RL e 10 kX
50
20
1012
Input Resistance
mV/§ C
nA
3
Tj e 125§ C
RIN
Units
Typ
1012
X
100
V/mV
15
a 18, b 17
100
g 11
70
V/mV
g 13
a 14, b 12
95
V
V
dB
DC Electrical Characteristics (Note 4) (Continued)
Symbol
Parameter
PSRR
Supply Voltage
Rejection Ratio
IS
Supply Current
LF441A
Conditions
(Note 7)
Min
Typ
80
100
150
LF441
Max
Min
Typ
70
90
200
150
Units
Max
dB
250
mA
AC Electrical Characteristics (Note 4)
Symbol
Parameter
LF441A
Conditions
SR
Slew Rate
GBW
Gain-Bandwidth Product
VS e g 15V, TA e 25§ C
VS e g 15V, TA e 25§ C
en
Equivalent Input Noise Voltage
TA e 25§ C, RS e 100X,
f e 1 kHz
in
Equivalent Input Noise Current
TA e 25§ C, f e 1 kHz
Min
Typ
0.8
0.8
LF441
Max
Units
Min
Typ
Max
1
0.6
1
V/ms
1
0.6
1
MHz
35
35
nV/0Hz
0.01
0.01
pA/0Hz
Note 1: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.
Note 2: For operating at elevated temperature, these devices must be derated based on a thermal resistance of ijA.
e
Note 3: The temperature range is designated by the position just before the package type in the device number. A ‘‘C’’ indicates the commercial temperature range
and an ‘‘M’’ indicates the military temperature range. The military temperature range is available in ‘‘H’’ package only.
Note 4: Unless otherwise specified the specifications apply over the full temperature range and for VS e g 20V for the LF441A and for VS e g 15V for the LF441.
VOS, IB, and IOS are measured at VCM e 0.
Note 5: The LF441A is 100% tested to this specification.
et
Note 6: The input bias currents are junction leakage currents which approximately double for every 10§ C increase in the junction temperature, Tj. Due to limited
production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient
temperature as a result of internal power dissipation, PD. Tj e TA a ijA PD where ijA is the thermal resistance from junction to ambient. Use of a heat sink is
recommended if input bias current is to be kept to a minimum.
Note 7: Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice. From
g 15V to g 5V for the LF441 and from g 20V to g 5V for the LF441A.
Note 8: Refer to RETS441X for LF441MH military specifications.
Note 9: Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate
outside guaranteed limits.
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Note 10: Human body model, 1.5 kX in series with 100 pF.
Typical Performance Characteristics
O
Input Bias Current
Positive Common-Mode
Input Voltage Limit
Input Bias Current
Supply Current
Negative Common-Mode
Input Voltage Limit
Positive Current Limit
TL/H/9297 – 5
3
Typical Performance Characteristics (Continued)
Output Voltage Swing
Output Voltage Swing
Gain Bandwidth
Bode Plot
Slew Rate
et
e
Negative Current Limit
Undistorted Output
Voltage Swing
Open Loop Frequency
Response
Common-Mode
Rejection Ratio
Power Supply
Rejection Ratio
Equivalent Input
Noise Voltage
O
bs
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Distortion vs Frequency
TL/H/9297 – 6
4
Typical Performance Characteristics (Continued)
Open Loop Voltage Gain
Output Impedance
Inverter Settling Time
TL/H/9297 – 7
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et
e
Simplified Schematic
TL/H/9297 – 3
Pulse Response RL e 10 kX, CL e 10 pF
O
Small Signal Inverting
TL/H/9297 – 8
5
Pulse Response RL e 10 kX, CL e 10 pF (Continued)
Small Signal Non-Inverting
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et
Large Signal Inverting
e
TL/H/9297 – 9
TL/H/9297 – 10
O
Large Signal Non-Inverting
TL/H/9297 – 11
6
Application Hints
The amplifier will drive a 10 kX load resistance to g 10V
over the full temperature range.
Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards
in a socket, as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the
internal conductors and result in a destroyed unit.
As with most amplifiers, care should be taken with lead
dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the
input to minimize ‘‘pick-up’’ and maximize the frequency of
the feedback pole by minimizing the capacitance from the
input to ground.
A feedback pole is created when the feedback around any
amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input
to AC ground) set the frequency of this pole. In many instances the frequency of this pole is much greater than the
expected 3 dB frequency, of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately 6 times
the expected 3 dB frequency, a lead capacitor should be
placed from the output to the input of the op amp. The value
of the added capacitor should be such that the RC time
constant of this capacitor and the resistance it parallels is
greater than or equal to the original feedback pole time constant.
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This device is a low power op amp with an internally
trimmed input offset voltage and JFET input devices
(BI-FET II). These JFETs have large reverse breakdown
voltages from gate to source and drain, eliminating the need
for clamps across the inputs. Therefore, large differential
input voltages can easily be accommodated without a large
increase in input current. The maximum differential input
voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the
negative supply as this will cause large currents to flow
which can result in a destroyed unit.
Exceeding the negative common-mode limit on either input
will force the output to a high state, potentially causing a
reversal of phase to the output. Exceeding the negative
common-mode limit on both inputs will force the amplifier
output to a high state. In neither case does a latch occur
since raising the input back within the common-mode range
again puts the input stage and thus the amplifier in a normal
operating mode.
Exceeding the positive common-mode limit on a single input
will not change the phase of the output; however, if both
inputs exceed the limit, the output of the amplifier will be
forced to a high state.
The amplifier will operate with a common-mode input voltage equal to the positive supply; however, the gain bandwidth and slew rate may be decreased in this condition.
When the negative common-mode voltage swings to within
3V of the negative supply, an increase in input offset voltage
may occur.
The amplifier is biased to allow normal circuit operation with
power supplies of g 3V. Supply voltages less than these
may degrade the common-mode rejection and restrict the
output voltage swing.
O
Detailed Schematic
TL/H/9297 – 13
7
8
e
et
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O
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et
e
Physical Dimensions inches (millimeters)
O
Metal Can Package (H)
Order Number LF441MH/883
NS Package Number H08A
Dual-In-Line Package(M)
Order Number LF441CM
NS Package Number M08A
9
e
et
Molded Dual-In-Line Package (N)
Order Number LF441ACN or LF441CN
NS Package Number N08E
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LF441 Low Power JFET Input Operational Amplifier
Physical Dimensions inches (millimeters) (Continued)
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O
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