LatticeECP/EC Family Data Sheet DS1000 Version 02.7, February 2008 LatticeECP/EC Family Data Sheet Introduction May 2005 Data Sheet Features − − − − − − ■ Extensive Density and Package Options • 1.5K to 32.8K LUT4s • 65 to 496 I/Os • Density migration supported ■ sysDSP™ Block (LatticeECP™ Versions) • High performance multiply and accumulate • 4 to 8 blocks − 4 to 8 36x36 multipliers or – 16 to 32 18x18 multipliers or − 32 to 64 9x9 multipliers ■ Embedded and Distributed Memory • 18 Kbits to 498 Kbits sysMEM™ Embedded Block RAM (EBR) • Up to 131 Kbits distributed RAM • Flexible memory resources: − Distributed and block memory ■ Dedicated DDR Memory Support • Implements interface up to DDR400 (200MHz) ■ sysCLOCK™ PLLs • Up to four analog PLLs per device • Clock multiply, divide and phase shifting ■ System Level Support • IEEE Standard 1149.1 Boundary Scan, plus ispTRACY™ internal logic analyzer capability • SPI boot flash interface • 1.2V power supply ■ Low Cost FPGA • Features optimized for mainstream applications • Low cost TQFP and PQFP packaging ■ Flexible I/O Buffer • Programmable sysI/O™ buffer supports wide range of interfaces: Table 1-1. LatticeECP/EC Family Selection Guide Device LVCMOS 3.3/2.5/1.8/1.5/1.2 LVTTL SSTL 3/2 Class I, II, SSTL18 Class I HSTL 18 Class I, II, III, HSTL15 Class I, III PCI LVDS, Bus-LVDS, LVPECL, RSDS LFEC1 LFEC3 LFEC6/ LFECP6 LFEC10/ LFECP10 LFEC15/ LFECP15 LFEC20/ LFECP20 LFEC33/ LFECP33 12 16 24 32 40 44 64 PFU/PFF Rows PFU/PFF Columns 16 24 32 40 48 56 64 PFUs/PFFs 192 384 768 1280 1920 2464 4096 LUTs (K) 1.5 3.1 6.1 10.2 15.4 19.7 32.8 Distributed RAM (Kbits) 6 12 25 41 61 79 131 EBR SRAM (Kbits) 18 55 92 276 350 424 498 EBR SRAM Blocks 2 6 10 30 38 46 54 1 sysDSP Blocks — — 4 5 6 7 8 18x18 Multipliers1 — — 16 20 24 28 32 VCC Voltage (V) 1.2 1.2 1.2 1.2 1.2 1.2 1.2 Number of PLLs 2 2 2 4 4 4 4 67 67 360 360 400 496 Packages and I/O Combinations: 100-pin TQFP (14 x 14 mm) 144-pin TQFP (20 x 20 mm) 97 97 97 208-pin PQFP (28 x 28 mm) 112 145 147 256-ball fpBGA (17 x 17 mm) 484-ball fpBGA (23 x 23 mm) 160 147 195 195 195 224 288 352 672-ball fpBGA (27 x 27 mm) 1. LatticeECP devices only. © 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 Introduction_01.3 Introduction LatticeECP/EC Family Data Sheet Lattice Semiconductor Introduction The LatticeECP/EC family of FPGA devices is optimized to deliver mainstream FPGA features at low cost. For maximum performance and value, the LatticeECP™ (EConomy Plus) FPGA concept combines an efficient FPGA fabric with high-speed dedicated functions. Lattice’s first family to implement this approach is the LatticeECPDSP™ (EConomy Plus DSP) family, providing dedicated high-performance DSP blocks on-chip. The LatticeEC™ (EConomy) family supports all the general purpose features of LatticeECP devices without dedicated function blocks to achieve lower cost solutions. The LatticeECP/EC FPGA fabric, which was designed from the outset with low cost in mind, contains all the critical FPGA elements: LUT-based logic, distributed and embedded memory, PLLs and support for mainstream I/Os. Dedicated DDR memory interface logic is also included to support this memory that is becoming increasingly prevalent in cost-sensitive applications. The ispLEVER® design tool suite from Lattice allows large complex designs to be efficiently implemented using the LatticeECP/EC FPGA family. Synthesis library support for LatticeECP/EC is available for popular logic synthesis tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LatticeECP/EC device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design for timing verification. Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the LatticeECP/EC family. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity. 1-2 LatticeECP/EC Family Data Sheet Architecture May 2007 Data Sheet Architecture Overview The LatticeECP-DSP and LatticeEC architectures contain an array of logic blocks surrounded by Programmable I/ O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM (EBR), as shown in Figures 2-1 and 2-2. In addition, LatticeECP-DSP supports an additional row of DSP blocks, as shown in Figure 2-2. There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional unit without RAM/ROM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM and register functions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks are optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a two-dimensional array. Only one type of block is used per row. The PFU blocks are used on the outside rows. The rest of the core consists of rows of PFF blocks interspersed with rows of PFU blocks. For every three rows of PFF blocks there is a row of PFU blocks. Each PIC block encompasses two PIOs (PIO pairs) with their respective sysI/O interfaces. PIO pairs on the left and right edges of the device can be configured as LVDS transmit/receive pairs. sysMEM EBRs are large dedicated fast memory blocks. They can be configured as RAM or ROM. The PFU, PFF, PIC and EBR Blocks are arranged in a two-dimensional grid with rows and columns as shown in Figure 2-1. The blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool automatically allocates these routing resources. At the end of the rows containing the sysMEM Blocks are the sysCLOCK Phase Locked Loop (PLL) Blocks. These PLLs have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the clocks. The LatticeECP/EC architecture provides up to four PLLs per device. Every device in the family has a JTAG Port with internal Logic Analyzer (ispTRACY) capability. The sysCONFIG™ port which allows for serial or parallel device configuration. The LatticeECP/EC devices use 1.2V as their core voltage. © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 2-1 Architecture_01.9 Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor Figure 2-1. Simplified Block Diagram, LatticeEC Device (Top Level) Programmable I/O Cell (PIC) includes sysIO Interface sysMEM Embedded Block RAM (EBR) JTAG Port sysCONFIG Programming Port (includes dedicated and dual use pins) PFF (PFU without RAM) sysCLOCK PLL Programmable Functional Unit (PFU) Figure 2-2. Simplified Block Diagram, LatticeECP-DSP Device (Top Level) Programmable I/O Cell (PIC) includes sysIO Interface sysMEM Embedded Block RAM (EBR) JTAG Port sysCONFIG Programming Port (includes dedicated and dual use pins) PFF (Fast PFU without RAM/ROM) sysDSP Block sysCLOCK PLL Programmable Functional Unit (PFU) 2-2 Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor PFU and PFF Blocks The core of the LatticeECP/EC devices consists of PFU and PFF blocks. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform Logic, Arithmetic and ROM functions. Except where necessary, the remainder of the data sheet will use the term PFU to refer to both PFU and PFF blocks. Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-3. All the interconnections to and from PFU blocks are from routing. There are 53 inputs and 25 outputs associated with each PFU block. Figure 2-3. PFU Diagram From Routing LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY Slice 0 D FF/ Latch D FF/ Latch LUT4 & CARRY LUT4 & CARRY Slice 1 D FF/ Latch LUT4 & CARRY LUT4 & CARRY Slice 3 Slice 2 D FF/ Latch D FF/ Latch LUT4 & CARRY D FF/ Latch D FF/ Latch D FF/ Latch To Routing Slice Each slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select and wider RAM/ROM functions. Figure 2-4 shows an overview of the internal logic of the slice. The registers in the slice can be configured for positive/negative and edge/level clocks. There are 14 input signals: 13 signals from routing and one from the carry-chain (from adjacent slice or PFU). There are 7 outputs: 6 to routing and one to carry-chain (to adjacent PFU). Table 2-1 lists the signals associated with each slice. 2-3 Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor Figure 2-4. Slice Diagram To / From Different slice / PFU Slice OFX1 A1 B1 C1 D1 From Routing CO LUT4 & CARRY F1 F D SUM Q1 FF/ Latch CI To Routing M1 M0 CO A0 OFX0 LUT Expansion Mux B0 C0 D0 LUT4 & CARRY F0 F SUM OFX0 CI D Q0 FF/ Latch Control Signals CE selected and CLK inverted per LSR slice in routing Interslice signals are not shown To / From Different slice / PFU Table 2-1. Slice Signal Descriptions Function Type Signal Names Description Input Data signal A0, B0, C0, D0 Inputs to LUT4 Input Data signal A1, B1, C1, D1 Inputs to LUT4 Input Multi-purpose M0 Multipurpose Input Input Multi-purpose M1 Multipurpose Input Input Control signal CE Clock Enable Input Control signal LSR Local Set/Reset Input Control signal CLK System Clock Input Inter-PFU signal FCIN Fast Carry In1 Output Data signals F0, F1 LUT4 output register bypass signals Output Data signals Q0, Q1 Register Outputs Output Data signals OFX0 Output of a LUT5 MUX Output Data signals OFX1 Output of a LUT6, LUT7, LUT82 MUX depending on the slice Output Inter-PFU signal FCO For the right most PFU the fast carry chain output1 1. See Figure 2-3 for connection details. 2. Requires two PFUs. 2-4 Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor Modes of Operation Each Slice is capable of four modes of operation: Logic, Ripple, RAM and ROM. The Slice in the PFF is capable of all modes except RAM. Table 2-2 lists the modes and the capability of the Slice blocks. Table 2-2. Slice Modes Logic Ripple RAM ROM PFU Slice LUT 4x2 or LUT 5x1 2-bit Arithmetic Unit SPR16x2 ROM16x1 x 2 PFF Slice LUT 4x2 or LUT 5x1 2-bit Arithmetic Unit N/A ROM16x1 x 2 Logic Mode: In this mode, the LUTs in each Slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16 possible input combinations. Any logic function with four inputs can be generated by programming this lookup table. Since there are two LUT4s per Slice, a LUT5 can be constructed within one Slice. Larger lookup tables such as LUT6, LUT7 and LUT8 can be constructed by concatenating other Slices. Ripple Mode: Ripple mode allows the efficient implementation of small arithmetic functions. In ripple mode, the following functions can be implemented by each Slice: • • • • • • • Addition 2-bit Subtraction 2-bit Add/Subtract 2-bit using dynamic control Up counter 2-bit Down counter 2-bit Ripple mode multiplier building block Comparator functions of A and B inputs - A greater-than-or-equal-to B - A not-equal-to B - A less-than-or-equal-to B Ripple Mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this configuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are generated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating Slices. RAM Mode: In this mode, distributed RAM can be constructed using each LUT block as a 16x1-bit memory. Through the combination of LUTs and Slices, a variety of different memories can be constructed. The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the software will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3 shows the number of Slices required to implement different distributed RAM primitives. Figure 2-5 shows the distributed memory primitive block diagrams. Dual port memories involve the pairing of two Slices, one Slice functions as the read-write port. The other companion Slice supports the read-only port. For more information about using RAM in LatticeECP/EC devices, please see the list of technical documentation at the end of this data sheet. Table 2-3. Number of Slices Required For Implementing Distributed RAM SPR16x2 DPR16x2 1 2 Number of slices Note: SPR = Single Port RAM, DPR = Dual Port RAM 2-5 Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor Figure 2-5. Distributed Memory Primitives SPR16x2 DPR16x2 AD0 AD1 AD2 AD3 WAD0 WAD1 WAD2 WAD3 DO0 DO1 DI0 DI1 WRE DI0 DI1 WCK WRE CK RAD0 RAD1 RAD2 RAD3 RDO0 RDO1 WDO0 WDO1 ROM16x1 AD0 AD1 AD2 AD3 DO0 ROM Mode: The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is accomplished through the programming interface during configuration. PFU Modes of Operation Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the functionality possible at the PFU level. Table 2-4. PFU Modes of Operation Logic Ripple RAM1 ROM LUT 4x8 or MUX 2x1 x 8 2-bit Add x 4 SPR16x2 x 4 DPR16x2 x 2 ROM16x1 x 8 LUT 5x4 or MUX 4x1 x 4 2-bit Sub x 4 SPR16x4 x 2 DPR16x4 x 1 ROM16x2 x 4 LUT 6x 2 or MUX 8x1 x 2 2-bit Counter x 4 SPR16x8 x 1 ROM16x4 x 2 LUT 7x1 or MUX 16x1 x 1 2-bit Comp x 4 ROM16x8 x 1 1. These modes are not available in PFF blocks 2-6 Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor Routing There are many resources provided in the LatticeECP/EC devices to route signals individually or as busses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU). The x1 and x2 connections provide fast and efficient connections in horizontal and vertical directions. The x2 and x6 resources are buffered, the routing of both short and long connections between PFUs. The ispLEVER design tool suite takes the output of the synthesis tool and places and routes the design. Generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the design. Clock Distribution Network The clock inputs are selected from external I/O, the sysCLOCK™ PLLs or routing. These clock inputs are fed through the chip via a clock distribution system. Primary Clock Sources LatticeECP/EC devices derive clocks from three primary sources: PLL outputs, dedicated clock inputs and routing. LatticeECP/EC devices have two to four sysCLOCK PLLs, located on the left and right sides of the device. There are four dedicated clock inputs, one on each side of the device. Figure 2-6 shows the 20 primary clock sources. Figure 2-6. Primary Clock Sources From Routing PLL Input From Routing PLL PLL 20 Primary Clock Sources To Quadrant Clock Selection Clock Input PLL Input Clock Input Clock Input PLL PLL From Routing Clock Input Note: Smaller devices have two PLLs. 2-7 From Routing PLL Input PLL Input Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor Secondary Clock Sources LatticeECP/EC devices have four secondary clock resources per quadrant. The secondary clock branches are tapped at every PFU. These secondary clock networks can also be used for controls and high fanout data. These secondary clocks are derived from four clock input pads and 16 routing signals as shown in Figure 2-7. Figure 2-7. Secondary Clock Sources From Routing From Routing From Routing From Routing From Routing From Routing From Routing From Routing 20 Secondary Clock Sources To Quadrant Clock Selection From Routing From Routing From Routing From Routing From Routing From Routing From Routing From Routing Clock Routing The clock routing structure in LatticeECP/EC devices consists of four Primary Clock lines and a Secondary Clock network per quadrant. The primary clocks are generated from MUXs located in each quadrant. Figure 2-8 shows this clock routing. The four secondary clocks are generated from MUXs located in each quadrant as shown in Figure 2-9. Each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown in Figure 2-10. 2-8 Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor Figure 2-8. Per Quadrant Primary Clock Selection 20 Primary Clock Sources: 12 PLLs + 4 PIOs + 4 Routing1 DCS DCS 4 Primary Clocks (CLK0, CLK1, CLK2, CLK3) per Quadrant 1. Smaller devices have fewer PLL related lines. Figure 2-9. Per Quadrant Secondary Clock Selection 20 Secondary Clock Feedlines : 4 Clock Input Pads + 16 Routing Signals 4 Secondary Clocks per Quadrant Figure 2-10. Slice Clock Selection Primary Clock Secondary Clock Clock to each slice Routing GND sysCLOCK Phase Locked Loops (PLLs) The PLL clock input, from pin or routing, feeds into an input clock divider. There are three sources of feedback signal to the feedback divider: from CLKOP (PLL Internal), from clock net (CLKOP) or from a user clock (PIN or logic). There is a PLL_LOCK signal to indicate that VCO has locked on to the input clock signal. Figure 2-11 shows the sysCLOCK PLL diagram. The setup and hold times of the device can be improved by programming a delay in the feedback or input path of the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either pro- 2-9 Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor grammed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after adjustment and not relock until the tLOCK parameter has been satisfied. Additionally, the phase and duty cycle block allows the user to adjust the phase and duty cycle of the CLKOS output. The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated with it: input clock divider, feedback divider, post scalar divider and secondary clock divider. The input clock divider is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal. The post scalar divider allows the VCO to operate at higher frequencies than the clock output, thereby increasing the frequency range. The secondary divider is used to derive lower frequency outputs. Figure 2-11. PLL Diagram Dynamic Delay Adjustment LOCK CLKI (from routing or external pin) Input Clock Divider (CLKI) Delay Adjust Voltage Controlled VCO Oscillator Post Scalar Divider (CLKOP) Phase/Duty Select CLKOS CLKOP RST Secondary Clock Divider (CLKOK) Feedback Divider (CLKFB) CLKFB from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock (PIN or logic) CLKOK Figure 2-12 shows the available macros for the PLL. Table 2-5 provides signal description of the PLL Block. Figure 2-12. PLL Primitive CLKI CLKFB EPLLB CLKOP LOCK RST CLKOP CLKI CLKOS CLKFB CLKOK DDA MODE DDAIZR DDAILAG DDAIDEL[2:0] 2-10 EHXPLLB LOCK DDAOZR DDAOLAG DDAODEL[2:0] Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor Table 2-5. PLL Signal Descriptions Signal CLKI I/O Description I Clock input from external pin or routing I PLL feedback input from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock (PIN or logic) RST I “1” to reset PLL CLKOS O PLL output clock to clock tree (phase shifted/duty cycle changed) CLKOP O PLL output clock to clock tree (No phase shift) CLKFB CLKOK O PLL output to clock tree through secondary clock divider LOCK O “1” indicates PLL LOCK to CLKI DDAMODE I Dynamic Delay Enable. “1”: Pin control (dynamic), “0”: Fuse Control (static) DDAIZR I Dynamic Delay Zero. “1”: delay = 0, “0”: delay = on DDAILAG I Dynamic Delay Lag/Lead. “1”: Lead, “0”: Lag DDAIDEL[2:0] I Dynamic Delay Input DDAOZR O Dynamic Delay Zero Output DDAOLAG O Dynamic Delay Lag/Lead Output DDAODEL[2:0] O Dynamic Delay Output For more information about the PLL, please see the list of technical documentation at the end of this data sheet. Dynamic Clock Select (DCS) The DCS is a global clock buffer with smart multiplexer functions. It takes two independent input clock sources and outputs a clock signal without any glitches or runt pulses. This is achieved regardless of where the select signal is toggled. There are eight DCS blocks per device, located in pairs at the center of each side. Figure 2-13 illustrates the DCS Block Macro. Figure 2-13. DCS Block Primitive CLK0 CLK1 DCS DCSOUT SEL Figure 2-14 shows timing waveforms of the default DCS operating mode. The DCS block can be programmed to other modes. For more information about the DCS, please see the list of technical documentation at the end of this data sheet. 2-11 Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor Figure 2-14. DCS Waveforms CLK0 CLK1 SEL DCSOUT sysMEM Memory The LatticeECP/EC devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists of a 9Kbit RAM, with dedicated input and output registers. sysMEM Memory Block The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in a variety of depths and widths as shown in Table 2-6. Table 2-6. sysMEM Block Configurations Memory Mode Configurations Single Port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 256 x 36 True Dual Port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 Pseudo Dual Port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 256 x 36 Bus Size Matching All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for each port varies, this mapping scheme applies to each port. RAM Initialization and ROM Operation If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM. 2-12 Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor Memory Cascading Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. Single, Dual and Pseudo-Dual Port Modes Figure 2-15 shows the four basic memory configurations and their input/output names. In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory array. The output data of the memory is optionally registered at the output. Figure 2-15. sysMEM EBR Primitives AD[12:0] DI[35:0] CLK CE RST WE CS[2:0] EBR ADA[12:0] DIA[17:0] CLKA CEA DO[35:0] RSTA WEA CSA[2:0] DOA[17:0] True Dual Port RAM Single Port RAM AD[12:0] CLK CE RST CS[2:0] EBR EBR ADB[12:0] DIB[17:0] CEB CLKB RSTB WEB CSB[2:0] DOB[17:0] ADW[12:0] DI[35:0] CLKW CEW DO[35:0] WE RST CS[2:0] ROM ADR[12:0] EBR DO[35:0] CER CLKR Pseudo-Dual Port RAM The EBR memory supports three forms of write behavior for single port or dual port operation: 1. Normal – data on the output appears only during read cycle. During a write cycle, the data (at the current address) does not appear on the output. This mode is supported for all data widths. 2. Write Through – a copy of the input data appears at the output of the same port during a write cycle. This mode is supported for all data widths. 3. Read-Before-Write – when new data is being written, the old content of the address appears at the output. This mode is supported for x9, x18 and x36 data widths. Memory Core Reset The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchronously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B, respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and associated resets for both ports are as shown in Figure 2-16. 2-13 Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor Figure 2-16. Memory Core Reset Memory Core D SET Q Port A[17:0] LCLR Output Data Latches D SET Q Port B[17:0] LCLR RSTA RSTB GSRN Programmable Disable For further information about sysMEM EBR block, please see the the list of technical documentation at the end of this data sheet. EBR Asynchronous Reset EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-17. The GSR input to the EBR is always asynchronous. Figure 2-17. EBR Asynchronous Reset (Including GSR) Timing Diagram Reset Clock Clock Enable If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after the EBR read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge. If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during device Wake Up must occur before the release of the device I/Os becomes active. These instructions apply to all EBR RAM and ROM implementations. Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled. sysDSP Block The LatticeECP-DSP family provides a sysDSP block, making it ideally suited for low cost, high performance Digital Signal Processing (DSP) applications. Typical functions used in these applications are Finite Impulse Response (FIR) filters; Fast Fourier Transforms (FFT) functions, correlators, Reed-Solomon/Turbo/Convolution encoders and 2-14 Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor decoders. These complex signal processing functions use similar building blocks such as multiply-adders and multiply-accumulators. sysDSP Block Approach Compared to General DSP Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with fixed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by higher clock speeds. The LatticeECP, on the other hand, has many DSP blocks that support different data-widths. This allows the designer to use highly parallel implementations of DSP functions. The designer can optimize the DSP performance vs. area by choosing an appropriate level of parallelism. Figure 2-18 compares the serial and the parallel implementations. Figure 2-18. Comparison of General DSP and LatticeECP-DSP Approaches Operand A Operand A Operand A Operand B Operand A Operand B Operand B Operand B x Single Multiplier x Accumulator Σ M loops x x Multiplier 0 Multiplier 1 Accumulator Function implemented in General purpose DSP Multiplier (k-1) m/k loops Σ Output Function implemented in LatticeECP sysDSP Block Capabilities The sysDSP block in the LatticeECP-DSP family supports four functional elements in three 9, 18 and 36 data path widths. The user selects a function element for a DSP block and then selects the width and type (signed/unsigned) of its operands. The operands in the LatticeECP-DSP family sysDSP Blocks can be either signed or unsigned but not mixed within a function element. Similarly, the operand widths cannot be mixed within a block. The resources in each sysDSP block can be configured to support the following four elements: • • • • MULT MAC MULTADD MULTADDSUM (Multiply) (Multiply, Accumulate) (Multiply, Addition/Subtraction) (Multiply, Addition/Subtraction, Accumulate) The number of elements available in each block depends on the width selected from the three available options x9, x18, and x36. A number of these elements are concatenated for highly parallel implementations of DSP functions. Table 2-1 shows the capabilities of the block. 2-15 Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor Table 2-7. Maximum Number of Elements in a Block Width of Multiply x9 x18 x36 MULT 8 4 1 MAC 2 2 — MULTADD 4 2 — MULTADDSUM 2 1 — Some options are available in four elements. The input register in all the elements can be directly loaded or can be loaded as shift registers from previous operand registers. In addition by selecting “dynamic operation” in the ‘Signed/Unsigned’ options the operands can be switched between signed and unsigned on every cycle. Similarly by selecting ‘Dynamic operation’ in the ‘Add/Sub’ option the Accumulator can be switched between addition and subtraction on every cycle. MULT sysDSP Element This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B, are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers. Figure 2-19 shows the MULT sysDSP element. Figure 2-19. MULT sysDSP Element Shift Register B In Shift Register A In Multiplier m m n n m Input Data Register A n m Multiplier n Input Data Register B x m+n (default) Output Register Multiplicand m+n Output Pipeline Register m n Signed Input Register To Multiplier CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) Shift Register B Out Shift Register A Out MAC sysDSP Element In this case the two operands, A and B, are multiplied and the result is added with the previous accumulated value. This accumulated value is available at the output. The user can enable the input and pipeline registers but the output register is always enabled. The output register is used to store the accumulated value. A registered overflow signal is also available. The overflow conditions are provided later in this document. Figure 2-20 shows the MAC sysDSP element. 2-16 Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor Figure 2-20. MAC sysDSP Element Shift Register B In Shift Register A In m n Accumulator m n n Multiplier m Input Data Register A Input Data Register B x n n Addn Accumsload m+n+16 bits (default) Pipeline Register n SignedAB m+n (default) Input Register Pipeline Register Input Register Pipeline Register To Accumulator Input Register Pipeline Register To Accumulator m+n+16 bits (default) Output Register Multiplier m Output Overflow Register Multiplicand To Accumulator Overflow signal CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) Shift Register B Out Shift Register A Out MULTADD sysDSP Element In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multiplier operation of operands A1 and A2. The user can enable the input, output and pipeline registers. Figure 2-21 shows the MULTADD sysDSP element. Figure 2-21. MULTADD Shift Register B In Shift Register A In Multiplicand A0 m CLK (CLK0,CLK1,CLK2,CLK3) m CE (CE0,CE1,CE2,CE3) Multiplier B0 RST(RST0,RST1,RST2,RST3) m n n Input Data Register A n Multiplier m x n Input Data Register B Pipeline Register m m+n (default) Add/Sub Multiplicand A1 Multiplier B1 m m+n+1 (default) m n Input Data Register A n Signed Addn Shift Register B Out x n Input Data Register B n Multiplier m Pipeline Register m Input Register Pipeline Pipe Register Reg To Add/Sub Input Register Pipeline Pipe Register Reg To Add/Sub Shift Register A Out 2-17 m+n (default) Output Register n Output m+n+1 (default) Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor MULTADDSUM sysDSP Element In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multiplier operation of operands A1 and B1. Additionally the operands A2 and B2 are multiplied and the result is added/ subtracted with the result of the multiplier operation of operands A3 and B3. The result of both addition/subtraction are added in a summation block. The user can enable the input, output and pipeline registers. Figure 2-22 shows the MULTADDSUM sysDSP element. Figure 2-22. MULTADDSUM Shift Register B In Shift Register A In Multiplicand A0 m m CLK (CLK0,CLK1,CLK2,CLK3) m n n CE (CE0,CE1,CE2,CE3) Input Data Register A n n Input Data Register B Multiplier x m+n (default) Pipeline Register m RST(RST0,RST1,RST2,RST3) Add/Sub0 n Multiplicand A1 Multiplier B1 m m m+n (default) m n Input Data Register A n n Input Data Register B Multiplicand A2 n Multiplier m+n+1 x SUM Pipeline Register m m m+n+2 Multiplier B2 m n n Input Data Register A n n Input Data Register B Multiplier x m+n+2 m+n (default) m+n+1 Pipeline Register m Output Add/Sub1 n Multiplicand A3 Multiplier B3 m Output Register Multiplier B0 m n Input Data Register A n Input Data Register B Signed Addn0 Addn1 Shift Register B Out m+n (default) m n m n Multiplier x Pipeline Register m Input Register Pipeline Register To Add/Sub0, Add/Sub1 Input Register Pipeline Register To Add/Sub0 Input Register Pipeline Register To Add/Sub1 Shift Register A Out Clock, Clock Enable and Reset Resources Global Clock, Clock Enable and Reset signals from routing are available to every DSP block. Four Clock, Reset and Clock Enable signals are selected for the sysDSP block. From four clock sources (CLK0, CLK1, CLK2, CLK3) one clock is selected for each input register, pipeline register and output register. Similarly Clock enable (CE) and Reset (RST) are selected from their four respective sources (CE0, CE1, CE2, CE3 and RST0, RST1, RST2, RST3) at each input register, pipeline register and output register. 2-18 Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor Signed and Unsigned with Different Widths The DSP block supports different widths of signed and unsigned multipliers besides x9, x18 and x36 widths. For unsigned operands, unused upper data bits should be filled to create a valid x9, x18 or x36 operand. For signed two’s complement operands, sign extension of the most significant bit should be performed until x9, x18 or x36 width is reached. Table 2-8 provides an example of this. Table 2-8. An Example of Sign Extension Number Unsigned Unsigned 9-bit Unsigned 18-bit Signed Two’s Complement Signed 9-Bits Two’s Complement Signed 18-bits +5 0101 000000101 000000000000000101 0101 000000101 000000000000000101 -6 0110 000000110 000000000000000110 1010 111111010 111111111111111010 OVERFLOW Flag from MAC The sysDSP block provides an overflow output to indicate that the accumulator has overflowed. When two unsigned numbers are added and the result is a smaller number then accumulator roll over is said to occur and overflow signal is indicated. When two positive numbers are added with a negative sum and when two negative numbers are added with a positive sum, then the accumulator “roll-over” is said to have occurred and an overflow signal is indicated. Note when overflow occurs the overflow flag is present for only one cycle. By counting these overflow pulses in FPGA logic, larger accumulators can be constructed. The conditions overflow signals for signed and unsigned operands are listed in Figure 2-23. Figure 2-23. Accumulator Overflow/Underflow Conditions 0101111100 0101111101 0101111110 0101111111 1010000000 1010000001 1010000010 252 253 254 255 256 257 258 000000011 000000010 000000001 000000000 3 2 1 0 111111111 111111110 111111101 511 510 509 Unsigned Operation 0101111100 000000011 000000010 000000001 000000000 111111111 111111110 111111101 252 Overflow signal is generated 0101111101 253 0101111110 254 for one cycle when this 0101111111 255 boundary is crossed 1010000000 256 1010000001 255 1010000010 254 Signed Operation 2-19 +3 +2 +1 0 -1 -2 -3 Carry signal is generated for one cycle when this boundary is crossed Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor IPexpress™ The user can access the sysDSP block via the IPexpress configuration tool, included with the ispLEVER design tool suite. IPexpress has options to configure each DSP module (or group of modules) or through direct HDL instantiation. Additionally Lattice has partnered Mathworks to support instantiation in the Simulink tool, which is a Graphical Simulation Environment. Simulink works with ispLEVER and dramatically shortens the DSP design cycle in Lattice FPGAs. Optimized DSP Functions Lattice provides a library of optimized DSP IP functions. Some of the IPs planned for LatticeECP DSP are: Bit Correlators, Fast Fourier Transform, Finite Impulse Response (FIR) Filter, Reed-Solomon Encoder/ Decoder, Turbo Encoder/Decoders and Convolutional Encoder/Decoder. Please contact Lattice to obtain the latest list of available DSP IPs. Resources Available in the LatticeECP Family Table 2-9 shows the maximum number of multipliers for each member of the LatticeECP family. Table 2-10 shows the maximum available EBR RAM Blocks in each of the LatticeECP family. EBR blocks, together with Distributed RAM can be used to store variables locally for the fast DSP operations. Table 2-9. Number of DSP Blocks in LatticeECP Family Device DSP Block 9x9 Multiplier 18x18 Multiplier 36x36 Multiplier LFECP6 4 32 16 4 LFECP10 5 40 20 5 LFECP15 6 48 24 6 LFECP20 7 56 28 7 LFECP33 8 64 32 8 Device EBR SRAM Block Total EBR SRAM (Kbits) Table 2-10. Embedded SRAM in LatticeECP Family LFECP6 10 92 LFECP10 30 276 LFECP15 38 350 LFECP20 46 424 LFECP33 54 498 DSP Performance of the LatticeECP Family Table 2-11 lists the maximum performance in millions of MAC operations per second (MMAC) for each member of the LatticeECP family. Table 2-11. DSP Block Performance of LatticeECP Family Device DSP Block DSP Performance MMAC LFECP6 4 3680 LFECP10 5 4600 LFECP15 6 5520 LFECP20 7 6440 LFECP33 8 7360 2-20 Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor For further information about the sysDSP block, please see the list of technical information at the end of this data sheet. Programmable I/O Cells (PIC) Each PIC contains two PIOs connected to their respective sysI/O Buffers which are then connected to the PADs as shown in Figure 2-24. The PIO Block supplies the output data (DO) and the Tri-state control signal (TO) to sysI/O buffer, and receives input from the buffer. Figure 2-24. PIC Diagram PIO A TD D0 D1 DDRCLK TD OPOS1 ONEG1 IOLT0 Tristate Register Block (2 Flip Flops) D0 D1 DDRCLK OPOS0 ONEG0 PADA "T" IOLD0 Output Register Block (2 Flip Flops) INCK INDD INFF IPOS0 IPOS1 INCK INDD INFF IPOS0 IPOS1 Control Muxes CLK CE LSR GSRN DQS DDRCLKPOL CLKO CEO LSR GSR CLKI CEI sysIO Buffer DI Input Register Block (5 Flip Flops) PADB "C" PIO B Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-25. The PAD Labels “T” and “C” distinguish the two PIOs. Only the PIO pairs on the left and right edges of the device can be configured as LVDS transmit/receive pairs. One of every 16 PIOs contains a delay element to facilitate the generation of DQS signals. The DQS signal feeds the DQS bus which spans the set of 16 PIOs. Figure 2-25 shows the assignment of DQS pins in each set of 16 PIOs. The exact DQS pins are shown in a dual function in the Logic Signal Connections table at the end of this data sheet. Additional detail is provided in the Signal Descriptions table at the end of this data sheet. The DQS signal from the bus is used to strobe the DDR data from the memory into input register blocks. This interface is designed for memories that support one DQS strobe per eight bits of data. 2-21 Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor Table 2-12. PIO Signal List Name CE0, CE1 Type Control from the core Description Clock enables for input and output block FFs. CLK0, CLK1 Control from the core System clocks for input and output blocks. LSR Control from the core Local Set/Reset. GSRN Control from routing Global Set/Reset (active low). INCK Input to the core Input to Primary Clock Network or PLL reference inputs. DQS Input to PIO DQS signal from logic (routing) to PIO. INDD Input to the core Unregistered data input to core. INFF Input to the core Registered input on positive edge of the clock (CLK0). IPOS0, IPOS1 Input to the core DDRX registered inputs to the core. ONEG0 Control from the core Output signals from the core for SDR and DDR operation. OPOS0, Control from the core Output signals from the core for DDR operation OPOS1 ONEG1 Tristate control from the core Signals to Tristate Register block for DDR operation. TD Tristate control from the core Tristate signal from the core used in SDR operation. DDRCLKPOL Control from clock polarity bus Controls the polarity of the clock (CLK0) that feed the DDR input block. Figure 2-25. DQS Routing PIO A PADA "T" PIO B PADB "C" PIO A PADA "T" LVDS Pair LVDS Pair PIO B PADB "C" PIO A PADA "T" LVDS Pair PADB "C" PIO B PIO A PADA "T" LVDS Pair PADB "C" PIO B DQS PIO A sysIO Buffer Delay PIO B PIO A Assigned DQS Pin PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PIO B PADB "C" PIO A PADA "T" LVDS Pair PIO B PADB "C" PIO A PADA "T" PIO B LVDS Pair PADB "C" PIO The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic block. These blocks contain registers for both single data rate (SDR) and double data rate (DDR) operation along with the necessary clock and selection logic. Programmable delay lines used to shift incoming clock and data signals are also included in these blocks. 2-22 Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor Input Register Block The input register block contains delay elements and registers that can be used to condition signals before they are passed to the device core. Figure 2-26 shows the diagram of the input register block. Input signals are fed from the sysI/O buffer to the input register block (as signal DI). If desired the input signal can bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and in selected blocks the input to the DQS delay block. If one of the bypass options is not chosen, the signal first passes through an optional delay block. This delay, if selected, reduces input-register hold-time requirement when using a global clock. The input block allows two modes of operation. In the single data rate (SDR) the data is registered, by one of the registers in the single data rate sync register block, with the system clock. In the DDR Mode two registers are used to sample the data on the positive and negative edges of the DQS signal creating two data streams, D0 and D2. These two data streams are synchronized with the system clock before entering the core. Further discussion on this topic is in the DDR Memory section of this data sheet. Figure 2-27 shows the input register waveforms for DDR operation and Figure 2-28 shows the design tool primitives. The SDR/SYNC registers have reset and clock enable available. The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures adequate timing when data is transferred from the DQS to system clock domain. For further discussion on this topic, see the DDR Memory section of this data sheet. Figure 2-26. Input Register Diagram DI (From sysIO Buffer) INCK INDD Delay Block Fixed Delay SDR & Sync Registers DDR Registers D0 D Q D D-Type /LATCH Q D-Type D2 D Q D1 D-Type DQS Delayed (From DQS Bus) CLK0 (From Routing) DDRCLKPOL (From DDR Polarity Control Bus) 2-23 D Q D-Type D Q D-Type /LATCH To Routing IPOS0 IPOS1 Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor Figure 2-27. Input Register DDR Waveforms DI (In DDR Mode) A B C D F E DQS DQS Delayed D0 B D D2 A C Figure 2-28. INDDRXB Primitive D ECLK LSR SCLK QA IDDRXB QB CE DDRCLKPOL Output Register Block The output register block provides the ability to register signals from the core of the device before they are passed to the sysI/O buffers. The block contains a register for SDR operation that is combined with an additional latch for DDR operation. Figure 2-29 shows the diagram of the Output Register Block. In SDR mode, ONEG0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured a Dtype or latch. In DDR mode, ONEG0 is fed into one register on the positive edge of the clock and OPOS0 is latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0). Figure 2-30 shows the design tool DDR primitives. The SDR output register has reset and clock enable available. The additional register for DDR operation does not have reset or clock enable available. 2-24 Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor Figure 2-29. Output Register Block OUTDDN Q D D-Type /LATCH ONEG0 0 0 DO 1 From Routing To sysIO Buffer 1 OPOS0 Q D Latch LE* CLK1 Programmed Control *Latch is transparent when input is low. Figure 2-30. ODDRXB Primitive DA DB CLK ODDRXB Q LSR Tristate Register Block The tristate register block provides the ability to register tri-state control signals from the core of the device before they are passed to the sysI/O buffers. The block contains a register for SDR operation and an additional latch for DDR operation. Figure 2-31 shows the diagram of the Tristate Register Block. In SDR mode, ONEG1 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured a Dtype or latch. In DDR mode, ONEG1 is fed into one register on the positive edge of the clock and OPOS1 is latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0). 2-25 Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor Figure 2-31. Tristate Register Block TD OUTDDN Q D D-Type /LATCH ONEG1 0 0 From Routing TO 1 To sysIO Buffer 1 OPOS1 D Q Latch LE* CLK1 Programmed Control *Latch is transparent when input is low. Control Logic Block The control logic block allows the selection and modification of control signals for use in the PIO block. A clock is selected from one of the clock signals provided from the general purpose routing and a DQS signal provided from the programmable DQS pin. The clock can optionally be inverted. The clock enable and local reset signals are selected from the routing and optionally inverted. The global tristate signal is passed through this block. DDR Memory Support Implementing high performance DDR memory interfaces requires dedicated DDR register structures in the input (for read operations) and in the output (for write operations). As indicated in the PIO Logic section, the LatticeEC devices provide this capability. In addition to these registers, the LatticeEC devices contain two elements to simplify the design of input structures for read operations: the DQS delay block and polarity control logic. DLL Calibrated DQS Delay Block Source Synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at the input register. For most interfaces a PLL is used for this adjustment. However in DDR memories the clock (referred to as DQS) is not free running so this approach cannot be used. The DQS Delay block provides the required clock alignment for DDR memory interfaces. The DQS signal (selected PIOs only) feeds from the PAD through a DQS delay element to a dedicated DQS routing resource. The DQS signal also feeds polarity control logic, which controls the polarity of the clock to the sync registers in the input register blocks. Figures 2-32 and 2-33 show how the DQS transition signals are routed to the PIOs. The temperature, voltage and process variations of the DQS delay block are compensated by a set of calibration (6-bit bus) signals from two DLLs on opposite sides of the device. Each DLL compensates DQS Delays in its half of the device as shown in Figure 2-33. The DLL loop is compensated for temperature, voltage and process variations by the system clock and feedback loop. 2-26 Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor Figure 2-32. DQS Local Bus. PIO Delay Control Bus Polarity Control Bus DQS Bus DQS GSR CLKI CEI DQS DDR Datain PAD sysIO Buffer Input Register Block ( 5 Flip Flops) To Sync. Reg. DI To DDR Reg. PIO DQS Strobe PAD sysIO Buffer Polarity Control Logic DI DQS DQSDEL Calibration Bus from DLL Figure 2-33. DLL Calibration Bus and DQS/DQS Transition Distribution Delay Control Bus Polarity Control Bus DQS Bus DLL DLL 2-27 Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor Polarity Control Logic In a typical DDR Memory interface design, the phase relation between the incoming delayed DQS strobe and the internal system Clock (during the READ cycle) is unknown. The LatticeECP/EC family contains dedicated circuits to transfer data between these domains. To prevent setup and hold violations at the domain transfer between DQS (delayed) and the system Clock a clock polarity selector is used. This changes the edge on which the data is registered in the synchronizing registers in the input register block. This requires evaluation at the start of each READ cycle for the correct clock polarity. Prior to the READ operation in DDR memories DQS is in tristate (pulled by termination). The DDR memory device drives DQS low at the start of the preamble state. A dedicated circuit detects this transition. This signal is used to control the polarity of the clock to the synchronizing registers. sysI/O Buffer Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the periphery of the device in eight groups referred to as Banks. The sysI/O buffers allow users to implement the wide variety of standards that are found in today’s systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL. sysI/O Buffer Banks LatticeECP/EC devices have eight sysI/O buffer banks; each is capable of supporting multiple I/O standards. Each sysI/O bank has its own I/O supply voltage (VCCIO), and two voltage references VREF1 and VREF2 resources allowing each bank to be completely independent from each other. Figure 2-34 shows the eight banks and their associated supplies. In the LatticeECP/EC devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS, PCI and PCIX) are powered using VCCIO. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as fixed threshold input independent of VCCIO. In addition to the bank VCCIO supplies, the LatticeECP/EC devices have a VCC core logic power supply, and a VCCAUX supply that power all differential and referenced buffers. Each bank can support up to two separate VREF voltages, VREF1 and VREF2 that set the threshold for the referenced input buffers. In the LatticeECP/EC devices, some dedicated I/O pins in a bank can be configured to be a reference voltage supply pin. Each I/O is individually configurable based on the bank’s supply and reference voltages. 2-28 Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor Figure 2-34. LatticeECP/EC Banks TOP Bank 7 Bank 1 VCCIO2 Bank 2 VREF1(2) VREF2(2) GND VCCIO6 VCCIO3 V REF1(6) VREF1(3) Bank 6 V REF2(6) Bank 3 GND RIGHT LEFT GND VREF2(1) VREF1(1) VCCIO1 VREF2(7) GND VREF2(0) VREF1(7) VREF1(0) VCCIO0 Bank 0 VCCIO7 VREF2(3) GND GND GND VREF2(4) VREF1(4) VCCIO4 Bank 4 GND VREF1(5) VREF2(5) VCCIO5 Bank 5 BOTTOM LatticeECP/EC devices contain two types of sysI/O buffer pairs. 1. Top and Bottom sysI/O Buffer Pairs (Single-Ended Outputs Only) The sysI/O buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). The referenced input buffer can also be configured as a differential input. The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer. Only the I/Os on the top and bottom banks have programmable PCI clamps. These I/O banks also support hot socketing with IDK less than 1mA. Note that the PCI clamp is enabled after VCC, VCCAUX and VCCIO are at valid operating levels and the device has been configured. 2. Left and Right sysI/O Buffer Pairs (Differential and Single-Ended Outputs) The sysI/O buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. The referenced input buffer can also be configured as a differential input. In these banks the two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive side of the differential I/O, and the comp (complementary) pad is associated with the negative side of the differential I/O. Only the left and right banks have LVDS differential output drivers. See the IDK specification for I/O leakage current during power-up. 2-29 Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor Typical I/O Behavior During Power-up The internal power-on-reset (POR) signal is deactivated when VCC and VCCAUX have reached satisfactory levels. After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure that all other VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that are critical to the application. For more information about controlling the output logic state with valid input logic levels during power-up in LatticeECP/EC devices, see the list of technical documentation at the end of this data sheet. The VCC and VCCAUX supply the power to the FPGA core fabric, whereas the VCCIO supplies power to the I/O buffers. In order to simplify system design while providing consistent and predictable I/O behavior, it is recommended that the I/O buffers be powered-up prior to the FPGA core fabric. VCCIO supplies should be powered-up before or together with the VCC and VCCAUX supplies. Supported Standards The LatticeECP/EC sysI/O buffer supports both single-ended and differential standards. Single-ended standards can be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 1.2, 1.5, 1.8, 2.5 and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain. Other single-ended standards supported include SSTL and HSTL. Differential standards supported include LVDS, BLVDS, LVPECL, RSDS, differential SSTL and differential HSTL. Tables 2-13 and 2-14 show the I/O standards (together with their supply and reference voltages) supported by the LatticeECP/EC devices. For further information about utilizing the sysI/O buffer to support a variety of standards please see the the list of technical information at the end of this data sheet. Table 2-13. Supported Input Standards Input Standard VREF (Nom.) VCCIO1 (Nom.) Single Ended Interfaces LVTTL — — LVCMOS332 — — LVCMOS252 — — LVCMOS18 — 1.8 LVCMOS15 — 1.5 LVCMOS122 — — PCI — 3.3 HSTL18 Class I, II 0.9 — HSTL18 Class III 1.08 — HSTL15 Class I 0.75 — HSTL15 Class III 0.9 — SSTL3 Class I, II 1.5 — SSTL2 Class I, II 1.25 — SSTL18 Class I 0.9 — Differential SSTL18 Class I — — Differential SSTL2 Class I, II — — Differential SSTL3 Class I, II — — Differential HSTL15 Class I, III — — Differential HSTL18 Class I, II, III — — LVDS, LVPECL, BLVDS, RSDS — — Differential Interfaces 1. When not specified VCCIO can be set anywhere in the valid operating range. 2. JTAG inputs do not have a fixed threshold option and always follow VCCJ. 2-30 Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor Table 2-14. Supported Output Standards Output Standard Drive VCCIO (Nom.) 4mA, 8mA, 12mA, 16mA, 20mA 3.3 LVCMOS33 4mA, 8mA, 12mA 16mA, 20mA 3.3 LVCMOS25 4mA, 8mA, 12mA, 16mA, 20mA 2.5 LVCMOS18 4mA, 8mA, 12mA, 16mA 1.8 LVCMOS15 4mA, 8mA 1.5 Single-ended Interfaces LVTTL LVCMOS12 2mA, 6mA 1.2 LVCMOS33, Open Drain 4mA, 8mA, 12mA 16mA, 20mA — LVCMOS25, Open Drain 4mA, 8mA, 12mA 16mA, 20mA — LVCMOS18, Open Drain 4mA, 8mA, 12mA 16mA — LVCMOS15, Open Drain 4mA, 8mA — LVCMOS12, Open Drain 2mA, 6mA — PCI33 N/A 3.3 HSTL18 Class I, II, III N/A 1.8 HSTL15 Class I, III N/A 1.5 SSTL3 Class I, II N/A 3.3 SSTL2 Class I, II N/A 2.5 SSTL18 Class I N/A 1.8 N/A 3.3 Differential Interfaces Differential SSTL3, Class I, II Differential SSTL2, Class I, II N/A 2.5 Differential SSTL18, Class I N/A 1.8 Differential HSTL18, Class I, II, III N/A 1.8 Differential HSTL15, Class I, III N/A 1.5 LVDS N/A 2.5 BLVDS1 N/A 2.5 LVPECL1 N/A 3.3 RSDS1 N/A 2.5 1. Emulated with external resistors. Hot Socketing The LatticeECP/EC devices have been carefully designed to ensure predictable behavior during power-up and power-down. Power supplies can be sequenced in any order. During power up and power-down sequences, the I/Os remain in tristate until the power supply voltage is high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled within specified limits, this allows for easy integration with the rest of the system. These capabilities make the LatticeECP/EC ideal for many multiple power supply and hot-swap applications. Configuration and Testing The following section describes the configuration and testing features of the LatticeECP/EC devices. IEEE 1149.1-Compliant Boundary Scan Testability All LatticeECP/EC devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to 2-31 Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage VCCJ and can operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards. For more details on boundary scan test, please see information regarding additional technical documentation at the end of this data sheet. Device Configuration All LatticeECP/EC devices contain two possible ports that can be used for device configuration. The test access port (TAP), which supports bit-wide configuration, and the sysCONFIG port that supports both byte-wide and serial configuration. The TAP supports both the IEEE Std. 1149.1 Boundary Scan specification and the IEEE Std. 1532 In-System Configuration specification. The sysCONFIG port is a 20-pin interface with six of the I/Os used as dedicated pins and the rest being dual-use pins (please refer to TN1053 for more information about using the dual-use pins as general purpose I/O). There are four configuration options for LatticeECP/EC devices: 1. Industry standard SPI memories. 2. Industry standard byte wide flash and ispMACH 4000 for control/addressing. 3. Configuration from system microprocessor via the configuration bus or TAP. 4. Industry standard FPGA board memory. On power-up, the FPGA SRAM is ready to be configured with the sysCONFIG port active. The IEEE 1149.1 serial mode can be activated any time after power-up by sending the appropriate command through the TAP port. Once a configuration port is selected, that port is locked and another configuration port cannot be activated until the next power-up sequence. For more information about device configuration, please see the list of technical documentation at the end of this data sheet. Internal Logic Analyzer Capability (ispTRACY) All LatticeECP/EC devices support an internal logic analyzer diagnostic feature. The diagnostic features provide capabilities similar to an external logic analyzer, such as programmable event and trigger condition and deep trace memory. This feature is enabled by Lattice’s ispTRACY. The ispTRACY utility is added into the user design at compile time. For more information about ispTRACY, please see information regarding additional technical documentation at the end of this data sheet. External Resistor LatticeECP/EC devices require a single external, 10K ohm +/- 1% value between the XRES pin and ground. Device configuration will not be completed if this resistor is missing. There is no boundary scan register on the external resistor pad. 2-32 Architecture LatticeECP/EC Family Data Sheet Lattice Semiconductor Oscillator Every LatticeECP/EC device has an internal CMOS oscillator which is used to derive a master clock for configuration. The oscillator and the master clock run continuously. The default value of the master clock is 2.5MHz. Table 215 lists all the available Master Clock frequencies. When a different Master Clock is selected during the design process, the following sequence takes place: 1. User selects a different Master Clock frequency. 2. During configuration the device starts with the default (2.5MHz) Master Clock frequency. 3. The clock configuration settings are contained in the early configuration bit stream. 4. The Master Clock frequency changes to the selected frequency once the clock configuration bits are received. For further information about the use of this oscillator for configuration, please see the list of technical documentation at the end of this data sheet. Table 2-15. Selectable Master Clock (CCLK) Frequencies During Configuration CCLK (MHz) CCLK (MHz) CCLK (MHz) 2.5* 13 45 4.3 15 51 5.4 20 55 6.9 26 60 8.1 30 130 9.2 34 — 10.0 41 — Density Shifting The LatticeECP/EC family has been designed to ensure that different density devices in the same package have the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration from lower density parts to higher density parts. In many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a lower density device. However, the exact details of the final resource utilization will impact the likely success in each case. 2-33 LatticeECP/EC Family Data Sheet DC and Switching Characteristics February 2008 Data Sheet Absolute Maximum Ratings1, 2, 3 Supply Voltage VCC . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V Supply Voltage VCCAUX . . . . . . . . . . . . . . . . -0.5 to 3.75V Supply Voltage VCCJ . . . . . . . . . . . . . . . . . . -0.5 to 3.75V Output Supply Voltage VCCIO . . . . . . . . . . . -0.5 to 3.75V Dedicated Input Voltage Applied4 . . . . . . . . -0.5 to 4.25V I/O Tristate Voltage Applied 4 . . . . . . . . . . . . -0.5 to 3.75V Storage Temperature (Ambient) . . . . . . . . . -65 to 150°C Junction Temp. (Tj). . . . . . . . . . . . . . . . . . . . . . . . +125°C 1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. Compliance with the Lattice Thermal Management document is required. 3. All voltages referenced to GND. 4. Overshoot and undershoot of -2V to (VIHMAX + 2) volts is permitted for a duration of <20ns. Recommended Operating Conditions Symbol VCC VCCAUX 3 VCCPLL 1, 2 Min. Max. Units Core Supply Voltage Parameter 1.14 1.26 V Auxiliary Supply Voltage 3.135 3.465 V PLL Supply Voltage for ECP/EC33 1.14 1.26 V I/O Driver Supply Voltage 1.140 3.465 V VCCJ1 Supply Voltage for IEEE 1149.1 Test Access Port 1.140 3.465 V tJCOM Junction Commercial Operation 0 85 °C tJIND Junction Industrial Operation -40 100 °C VCCIO 1. If VCCIO or VCCJ is set to 1.2V, they must be connected to the same power supply as VCC. If VCCIO or VCCJ is set to 3.3V, they must be connected to the same power supply as VCCAUX. 2. See recommended voltages by I/O standard in subsequent table. 3. VCCAUX ramp rate must not exceed 3mV/µs for commercial and 0.6 mV/µs for industrial device operations during power up when transitioning between 0.8V and 1.8V. Hot Socketing Specifications1, 2, 3, 4 Symbol Parameter Condition Min. Typ. Max. Units Top and Bottom General Purpose sysI/Os (Banks 0, 1, 4 and 5), JTAG and Dedicated sysCONFIG Pins IDK_TB Input or I/O Leakage Current 0 ≤ VIN ≤ VIH (MAX.) — — +/-1000 µA VIN ≤ VCCIO — — +/-1000 µA VIN > VCCIO — 35 — mA Left and Right General Purpose sysI/Os (Banks 2, 3, 6 and 7) IDK_LR 1. 2. 3. 4. Input or I/O Leakage Current Insensitive to sequence of VCC, VCCAUX and VCCIO. However, assumes monotonic rise/fall rates for VCC, VCCAUX and VCCIO. 0 ≤ VCC ≤ VCC (MAX), 0 ≤ VCCIO ≤ VCCIO (MAX) or 0 ≤ VCCAUX ≤ VCCAUX (MAX). IDK is additive to IPU, IPW or IBH. LVCMOS and LVTTL only. © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 3-1 DC and Switching_01.9 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor DC Electrical Characteristics Over Recommended Operating Conditions Symbol IIL, IIH 1 Parameter Condition Min. Typ. Max. Units Input or I/O Leakage 0 ≤ VIN ≤ (VCCIO - 0.2V) — — 10 µA IIH1, 3 Input or I/O High Leakage (VCCIO - 0.2V) ≤ VIH ≤ 3.6V — — 40 µA IPU I/O Active Pull-up Current 0 ≤ VIN ≤ 0.7 VCCIO -30 — -150 µA IPD I/O Active Pull-down Current VIL (MAX) ≤ VIN ≤ VIH (MAX) 30 — 150 µA IBHLS Bus Hold Low sustaining current VIN = VIL (MAX) 30 — — µA IBHHS Bus Hold High sustaining current VIN = 0.7VCCIO -30 — — µA IBHLO Bus Hold Low Overdrive current 0 ≤ VIN ≤ VIH (MAX) — — 150 µA IBHLH Bus Hold High Overdrive current 0 ≤ VIN ≤ VIH (MAX) — — -150 µA VBHT Bus Hold trip Points 0 ≤ VIN ≤ VIH (MAX) C1 I/O Capacitance VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, VCC = 1.2V, VIO = 0 to VIH (MAX) C2 Dedicated Input Capacitance2 VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, VCC = 1.2V, VIO = 0 to VIH (MAX) 2 VIL (MAX) — VIH (MIN) V — 8 — pf — 6 — pf 1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Bus maintenance circuits are disabled. 2. TA 25oC, f = 1.0MHz 3. For top and bottom general purpose I/O pins, when VIH is higher than VCCIO, a transient current typically of 30ns in duration or less with a peak current of 6mA can occur on the high-to-low transition. For left and right I/O banks, VIH must be less than or equal to VCCIO. 3-2 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor Supply Current (Standby)1, 2, 3, 4 Over Recommended Operating Conditions Symbol ICC Typ.5 Units LFEC1 6 mA LFEC3 10 mA LFECP6/LFEC6 15 mA LFECP10/LFEC10 25 mA LFECP15/LFEC15 35 mA LFECP20/LFEC20 60 mA LFECP33/LFEC33 85 mA 15 mA Parameter Core Power Supply Current Device ICCAUX Auxiliary Power Supply Current ICCPLL PLL Power Supply Current 5 mA ICCIO Bank Power Supply Current6 2 mA ICCJ VCCJ Power Supply Current 5 mA 1. 2. 3. 4. 5. 6. For further information about supply current, please see the list of technical documentation at the end of this data sheet. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND. Frequency 0MHz. Pattern represents a “blank” configuration data file. TJ=25oC, power supplies at nominal voltage. Per bank. 3-3 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor Initialization Supply Current1, 2, 3, 4, 5, 6 Over Recommended Operating Conditions Symbol ICC ICCAUX ICCPLL ICCIO ICCJ 1. 2. 3. 4. 5. 6. 7. Typ.6 Units LFEC1 25 mA LFEC3 40 mA LFECP6/LFEC6 50 mA LFECP10/LFEC10 60 mA LFECP15/LFEC15 70 mA LFECP20/LFEC20 150 mA LFECP33/LFEC33 220 mA LFEC1 30 mA LFEC3 30 mA LFECP6/LFEC6 30 mA LFECP10/LFEC10 35 mA LFECP15/LFEC15 35 mA LFECP20/LFEC20 40 mA LFECP33/LFEC33 40 mA Parameter Devices Core Power Supply Current Auxiliary Power Supply Current PLL Power Supply Current 7 Bank Power Supply Current 12 mA LFEC1 4 mA LFEC3 5 mA LFECP6/LFEC6 6 mA LFECP10/LFEC10 6 mA LFECP15/LFEC15 7 mA LFECP20/LFEC20 8 mA LFECP33/LFEC33 8 mA 20 mA VCCJ Power Supply Current Until DONE signal is active. For further information about supply current, please see the list of technical documentation at the end of this data sheet. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND. Frequency 0MHz. Pattern represents typical design with 65% logic, 55% EBR, 10% routing utilization. TJ=25oC, power supplies at nominal voltage. Per bank. 3-4 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor sysI/O Recommended Operating Conditions VCCIO Standard VREF (V) Min. Typ. Max. Min. Typ. Max. LVCMOS 3.3 3.135 3.3 3.465 — — — LVCMOS 2.5 2.375 2.5 2.625 — — — LVCMOS 1.8 1.71 1.8 1.89 — — — LVCMOS 1.5 1.425 1.5 1.575 — — — LVCMOS 1.2 1.14 1.2 1.26 — — — LVTTL 3.135 3.3 3.465 — — — PCI 3.135 3.3 3.465 — — — SSTL18 Class I 1.71 1.8 1.89 0.833 0.90 0.969 SSTL2 Class I, II 2.375 2.5 2.625 1.15 1.25 1.35 SSTL3 Class I, II 3.135 3.3 3.465 1.3 1.5 1.7 HSTL15 Class I 1.425 1.5 1.575 0.68 0.75 0.9 HSTL15 Class III 1.425 1.5 1.575 — 0.9 — HSTL 18 Class I, II 1.71 1.8 1.89 — 0.9 — HSTL 18 Class III 1.71 1.8 1.89 — 1.08 — LVDS 2.375 2.5 2.625 — — — LVPECL1 3.135 3.3 3.465 — — — BLVDS1 2.375 2.5 2.625 — — — RSDS1 2.375 2.5 2.625 — — — 1. Outputs are implemented with the addition of external resistors. VCCIO applies to outputs only. 3-5 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor sysI/O Single-Ended DC Electrical Characteristics Input/Output Standard LVCMOS 3.3 LVTTL LVCMOS 2.5 LVCMOS 1.8 LVCMOS 1.5 VIL VIH Min. (V) Max. (V) Min. (V) -0.3 0.8 2.0 -0.3 -0.3 -0.3 -0.3 LVCMOS 1.2 -0.3 0.8 0.7 0.35VCCIO 0.35VCCIO 0.35VCC 2.0 1.7 0.65VCCIO 0.65VCCIO VOH Min. (V) IOL1 (mA) IOH1 (mA) 0.4 VCCIO - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 VCCIO - 0.2 0.1 -0.1 0.4 VCCIO - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 VCCIO - 0.2 0.1 -0.1 VCCIO - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 VOL Max. (V) Max. (V) 3.6 3.6 3.6 3.6 3.6 0.65VCC 3.6 0.4 0.2 VCCIO - 0.2 0.1 -0.1 0.4 VCCIO - 0.4 16, 12, 8, 4 -16, -12, -8, -4 0.2 VCCIO - 0.2 0.1 -0.1 0.4 VCCIO - 0.4 8, 4 -8, -4 0.2 VCCIO - 0.2 0.1 -0.1 0.4 VCCIO - 0.4 6, 2 -6, -2 0.2 VCCIO - 0.2 0.1 -0.1 PCI -0.3 0.3VCCIO 0.5VCCIO 3.6 0.1VCCIO 0.9VCCIO 1.5 -0.5 SSTL3 class I -0.3 VREF - 0.2 VREF + 0.2 3.6 0.7 VCCIO - 1.1 8 -8 SSTL3 class II -0.3 VREF - 0.2 VREF + 0.2 3.6 0.5 VCCIO - 0.9 16 -16 SSTL2 class I -0.3 VREF - 0.18 VREF + 0.18 3.6 0.54 VCCIO - 0.62 7.6 -7.6 SSTL2 class II -0.3 VREF - 0.18 VREF + 0.18 3.6 0.35 VCCIO - 0.43 15.2 -15.2 SSTL18 class I -0.3 VREF - 0.125 VREF + 0.125 3.6 0.4 VCCIO - 0.4 6.7 -6.7 HSTL15 class I -0.3 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCIO - 0.4 8 -8 HSTL15 class III -0.3 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCIO - 0.4 24 -8 HSTL18 class I -0.3 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCIO - 0.4 9.6 -9.6 HSTL18 class II -0.3 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCIO - 0.4 16 -16 HSTL18 class III -0.3 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCIO - 0.4 24 -8 1. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as shown in the logic signal connections table shall not exceed n * 8mA. Where n is the number of I/Os between bank GND connections or between the last GND in a bank and the end of a bank. 3-6 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor sysI/O Differential Electrical Characteristics LVDS Over Recommended Operating Conditions Parameter Symbol Parameter Description Test Conditions VINP, VINM Input voltage VTHD Differential input threshold VCM Input common mode voltage IIN Input current Power on or power off VOH Output high voltage for VOP or VOM VOL Output low voltage for VOP or VOM VOD Output voltage differential ΔVOD Change in VOD between high and low VOS Output voltage offset ΔVOS Change in VOS between H and L IOSD Output short circuit current Min. Typ. Max. Units 0 — 2.4 V +/-100 — — mV 100mV ≤ VTHD VTHD/2 1.2 1.8 V 200mV ≤ VTHD VTHD/2 1.2 1.9 V 350mV ≤ VTHD VTHD/2 1.2 2.0 V — — +/-10 µA RT = 100 Ohm — 1.38 1.60 V RT = 100 Ohm 0.9V 1.03 — V (VOP - VOM), RT = 100 Ohm 250 350 450 mV — — 50 mV 1.125 1.25 1.375 V — — 50 mV — — 6 mA (VOP + VOM)/2, RT = 100 Ohm VOD = 0V Driver outputs shorted 3-7 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor Differential HSTL and SSTL Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allowable single-ended output classes (class I and class II) are supported in this mode. LVDS25E The top and bottom side of LatticeECP/EC devices support LVDS outputs via emulated complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-1 is one possible solution for point-to-point signals. Figure 3-1. LVDS25E Output Termination Example Bourns CAT16-LV4F12 VCCIO = 2.5V (±5%) RS=165 ohms (±1%) VCCIO = 2.5V (±5%) RS=165 ohms (±1%) RD = 140 ohms (±1%) + - RD = 100 ohms (±1%) Transmission line, Zo = 100 ohm differential ON-chip OFF-chip OFF-chip ON-chip Table 3-1. LVDS25E DC Conditions Typical Units VOH Parameter Output high voltage Description 1.42 V VOL Output low voltage 1.08 V VOD Output differential voltage 0.35 V VCM Output common mode voltage 1.25 V ZBACK Back impedance 100 Ω 3-8 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor BLVDS The LatticeECP/EC devices support BLVDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one possible solution for bi-directional multi-point differential signals. Figure 3-2. BLVDS Multi-point Output Example Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential 2.5V 2.5V 80 45-90 ohms 45-90 ohms 80 2.5V 2.5V 80 80 ... 2.5V + 2.5V - 80 80 + - 2.5V + 80 + - 2.5V - Table 3-2. BLVDS DC Conditions1 Over Recommended Operating Conditions Typical Parameter Description Zo = 45 Zo = 90 Units 100 100 ohm ZOUT Output impedance RTLEFT Left end termination 45 90 ohm RTRIGHT Right end termination 45 90 ohm VOH Output high voltage 1.375 1.48 V VOL Output low voltage 1.125 1.02 V VOD Output differential voltage 0.25 0.46 V VCM Output common mode voltage 1.25 1.25 V IDC DC output current 11.2 10.2 mA 1. For input buffer, see LVDS table. 3-9 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor LVPECL The LatticeECP/EC devices support differential LVPECL standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for point-to-point signals. Figure 3-3. Differential LVPECL 3.3V 100 ohms + 100 ohms ~150 ohms 3.3V - 100 ohms Transmission line, Zo = 100 ohm differential Off-chip Table 3-3. LVPECL DC Conditions1 Over Recommended Operating Conditions Parameter Description Typical Units 100 ohm ZOUT Output impedance RP Driver parallel resistor 150 ohm RT Receiver termination 100 ohm VOH Output high voltage 2.03 V VOL Output low voltage 1.27 V VOD Output differential voltage 0.76 V VCM Output common mode voltage 1.65 V ZBACK Back impedance 85.7 ohm IDC DC output current 12.7 mA 1. For input buffer, see LVDS table. For further information about LVPECL, BLVDS and other differential interfaces please see the list of technical information at the end of this data sheet. 3-10 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor RSDS The LatticeECP/EC devices support differential RSDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS standard implementation. Use LVDS25E mode with suggested resistors for RSDS operation. Resistor values in Figure 3-4 are industry standard values for 1% resistors. Figure 3-4. RSDS (Reduced Swing Differential Standard) VCCIO = 2.5V 294 Zo = 100 + VCCIO = 2.5V 121 100 294 On-chip Off-chip Emulated RSDS Buffer Table 3-4. RSDS DC Conditions Parameter Description Typical Units ZOUT Output impedance 20 ohm RS Driver series resistor 294 ohm RP Driver parallel resistor 121 ohm RT Receiver termination 100 ohm VOH Output high voltage 1.35 V VOL Output low voltage 1.15 V VOD Output differential voltage 0.20 V VCM Output common mode voltage 1.25 V ZBACK Back impedance 101.5 ohm IDC DC output current 3.66 mA 3-11 - DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor Typical Building Block Function Performance Pin-to-Pin Performance (LVCMOS25 12mA Drive) Function -5 Timing Units 16-bit decoder 5.5 ns 32-bit decoder 6.9 ns Basic Functions 64-bit decoder 7.1 ns 4:1 MUX 4.3 ns 8:1 MUX 4.7 ns 16:1 MUX 5.0 ns 32:1 MUX 5.5 ns -5 Timing Units 16 bit decoder 410 MHz 32 bit decoder 283 MHz Register-to-Register Performance1 Function Basic Functions 64 bit decoder 272 MHz 4:1 MUX 613 MHz 8:1 MUX 565 MHz 16:1 MUX 526 MHz 32:1 MUX 442 MHz 8-bit adder 363 MHz 16-bit adder 353 MHz 64-bit adder 196 MHz 16-bit counter 414 MHz 32-bit counter 317 MHz 64-bit counter 216 MHz 64-bit accumulator 178 MHz 256x36 Single Port RAM 280 MHz 512x18 True-Dual Port RAM 280 MHz 16x2 Single Port RAM 460 MHz 64x2 Single Port RAM 375 MHz 128x4 Single Port RAM 294 MHz 32x2 Pseudo-Dual Port RAM 392 MHz 64x4 Pseudo-Dual Port RAM 332 MHz 9x9 Pipelined Multiply/Accumulate 242 MHz 18x18 Pipelined Multiply/Accumulate 238 MHz 36x36 Pipelined Multiply 235 MHz Embedded Memory Functions Distributed Memory Functions DSP Function2 1. These timing numbers were generated using the ispLEVER design tool. Exact performance may vary with design and tool version. The tool uses internal parameters that have been characterized but are not tested on every device. 2. Applies to LatticeECP devices only. Timing v.G 0.30 3-12 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor Derating Timing Tables Logic Timing provided in the following sections of the data sheet and the ispLEVER design tools are worst-case numbers in the operating range. Actual delays at nominal temperature and voltage for best-case process, can be much better than the values given in the tables. To calculate logic timing numbers at a particular temperature and voltage multiply the noted numbers with the derating factors provided below. The junction temperature for the FPGA depends on the power dissipation by the device, the package thermal characteristics (ΘJA), and the ambient temperature, as calculated with the following equation: TJMAX = TAMAX + (Power * ΘJA) The user must determine this temperature and then use it to determine the derating factor based on the following derating tables: TJ °C. Table 3-5. Delay Derating Table for Internal Blocks Power Supply Voltage TJ °C Commercial TJ °C Industrial 1.14V 1.2V 1.26V — -40 0.82 0.77 0.71 — -25 0.82 0.76 0.71 0 20 0.89 0.83 0.78 25 45 0.93 0.87 0.81 85 105 1.00 0.94 0.89 3-13 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor LatticeECP/EC External Switching Characteristics Over Recommended Operating Conditions -5 Parameter Description Device Min. -4 -3 Max. Min. Max. Min. Max. Units General I/O Pin Parameters (Using Primary Clock without PLL)1 Clock to Output - PIO Output Register tCO7 tSU Clock to Data Setup - PIO Input Register 7 Clock to Data Hold - PIO Input Register tH7 tSU_DEL tH_DEL 7 7 fMAX_IO2 Clock to Data Setup - PIO Input Register with Data Input Delay Clock to Data Hold - PIO Input Register with Input Data Delay Clock Frequency of I/O and PFU Register LFEC1 — 5.09 — 6.11 — 7.13 ns LFEC3 — 5.71 — 6.85 — 7.99 ns LFEC6 — 5.60 — 6.72 — 7.84 ns LFEC10 — 5.47 — 6.57 — 7.66 ns LFEC15 — 5.67 — 6.81 — 7.94 ns LFEC20 — 5.89 — 7.07 — 8.25 ns LFEC33 — 6.19 — 7.42 — 8.66 ns LFEC1 -0.08 — -0.10 — -0.12 — ns LFEC3 -0.70 — -0.84 — -0.98 — ns LFEC6 -0.63 — -0.76 — -0.89 — ns LFEC10 -0.43 — -0.52 — -0.61 — ns LFEC15 -0.70 — -0.84 — -0.98 — ns LFEC20 -0.88 — -1.06 — -1.24 — ns LFEC33 -1.12 — -1.34 — -1.56 — ns LFEC1 2.19 — 2.62 — 3.06 — ns LFEC3 2.80 — 3.36 — 3.92 — ns LFEC6 2.69 — 3.23 — 3.77 — ns LFEC10 2.56 — 3.08 — 3.59 — ns LFEC15 2.76 — 3.32 — 3.87 — ns LFEC20 2.99 — 3.58 — 4.18 — ns LFEC33 3.28 — 3.93 — 4.59 — ns LFEC1 3.36 — 4.03 — 4.70 — ns LFEC3 2.74 — 3.29 — 3.84 — ns LFEC6 2.81 — 3.37 — 3.93 — ns LFEC10 3.01 — 3.61 — 4.21 — ns LFEC15 2.74 — 3.29 — 3.83 — ns LFEC20 2.56 — 3.07 — 3.58 — ns LFEC33 2.32 — 2.79 — 3.25 — ns LFEC1 -1.31 — -1.57 — -1.83 — ns LFEC3 -0.70 — -0.83 — -0.97 — ns LFEC6 -0.80 — -0.96 — -1.12 — ns LFEC10 -0.93 — -1.12 — -1.30 — ns LFEC15 -0.73 — -0.88 — -1.02 — ns LFEC20 -0.51 — -0.61 — -0.71 — ns LFEC33 -0.22 — -0.26 — -0.30 — ns — 420 — 378 — 340 Mhz All DDR I/O Pin Parameters3, 4, 5 tDVADQ Data Valid After DQS (DDR Read) All — 0.19 — 0.19 — 0.19 UI tDVEDQ Data Hold After DQS (DDR Read) All 0.67 — 0.67 — 0.67 — UI 3-14 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor LatticeECP/EC External Switching Characteristics (Continued) Over Recommended Operating Conditions -5 Parameter Description Device -4 -3 Min. Max. Min. Max. Min. Max. Units tDQVBS Data Valid Before DQS All 0.20 — 0.20 — 0.20 — UI tDQVAS Data Valid After DQS All 0.20 — 0.20 — 0.20 — UI fMAX_DDR DDR Clock Frequency All 95 200 95 166 95 133 MHz Primary and Secondary Clock6 fMAX_PRI2 Frequency for Primary Clock Tree All — 420 — 378 — 340 MHz tW_PRI Clock Pulse Width for Primary Clock All 1.19 — 1.19 — 1.19 — ns tSKEW_PRI Primary Clock Skew within an I/O Bank All — 250 — 300 — 350 ps 1. 2. 3. 4. 5. 6. 7. General timing numbers based on LVCMOS2.5V, 12 mA. Loading of 0 pF. Using LVDS I/O standard. DDR timing numbers based on SSTL I/O. DDR specifications are characterized but not tested. UI is average bit period. Based on a single primary clock. These timing numbers were generated using ispLEVER design tool. Exact performance may vary with design and tool version. The tool uses internal parameters that have been characterized but are not tested on every device. Timing v.G 0.30 Figure 3-5. DDR Timings DQ and DQS Read Timings DQS DQ tDVADQ tDVEDQ DQ and DQS Write Timings DQS DQ tDQVBS tDQVAS 3-15 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor LatticeECP/EC Internal Switching Characteristics Over Recommended Operating Conditions -5 Parameter Description -4 -3 Min. Max. Min. Max. Min. Max. Units PFU/PFF Logic Mode Timing tLUT4_PFU LUT4 Delay (A to D Inputs to F Output) — 0.25 — 0.31 — 0.36 ns tLUT6_PFU LUT6 Delay (A to D Inputs to OFX Output) — 0.40 — 0.48 — 0.56 ns tLSR_PFU Set/Reset to Output of PFU — 0.81 — 0.98 — 1.14 ns tSUM_PFU Clock to Mux (M0,M1) Input Setup Time 0.12 — 0.14 — 0.16 — ns tHM_PFU Clock to Mux (M0,M1) Input Hold Time -0.05 — -0.06 — -0.06 — ns tSUD_PFU Clock to D Input Setup Time 0.12 — 0.14 — 0.16 — ns tHD_PFU Clock to D Input Hold time -0.03 — -0.03 — -0.04 — ns tCK2Q_PFU Clock to Q Delay, D-type Register Configuration — 0.36 — 0.44 — 0.51 ns tLE2Q_PFU Clock to Q Delay Latch Configuration — 0.48 — 0.58 — 0.68 ns tLD2Q_PFU D to Q Throughput Delay when Latch is Enabled — 0.50 — 0.60 — 0.69 ns 0.36 — 0.44 — 0.51 ns PFU Dual Port Memory Mode Timing tCORAM_PFU Clock to Output — tSUDATA_PFU Data Setup Time -0.20 — -0.24 — -0.28 — ns tHDATA_PFU Data Hold Time 0.26 — 0.31 — 0.36 — ns tSUADDR_PFU Address Setup Time -0.51 — -0.62 — -0.72 — ns tHADDR_PFU Address Hold Time 0.64 — 0.77 — 0.90 — ns tSUWREN_PFU Write/Read Enable Setup Time -0.24 — -0.29 — -0.34 — ns tHWREN_PFU Write/Read Enable Hold Time 0.30 — 0.36 — 0.42 — ns PIC Timing PIO Input/Output Buffer Timing tIN_PIO Input Buffer Delay — 0.56 — 0.67 — 0.78 ns tOUT_PIO Output Buffer Delay — 1.92 — 2.31 — 2.69 ns — 1.08 — 1.26 — ns IOLOGIC Input/Output Timing tSUI_PIO Input Register Setup Time (Data Before Clock) 0.90 tHI_PIO Input Register Hold Time (Data after Clock) 0.62 — 0.74 — 0.87 — ns tCOO_PIO Output Register Clock to Output Delay — 0.33 — 0.40 — 0.46 ns tSUCE_PIO Input Register Clock Enable Setup Time -0.10 — -0.12 — -0.14 — ns tHCE_PIO Input Register Clock Enable Hold Time 0.12 — 0.14 — 0.17 — ns tSULSR_PIO Set/Reset Setup Time 0.18 — 0.21 — 0.25 — ns tHLSR_PIO Set/Reset Hold Time -0.15 — -0.18 — -0.21 — ns — 3.64 — 4.37 — 5.10 ns EBR Timing tCO_EBR Clock to Output from Address or Data tCOO_EBR Clock to Output from EBR output Register tSUDATA_EBR Setup Data to EBR Memory tHDATA_EBR tSUADDR_EBR tHADDR_EBR tSUWREN_EBR tHWREN_EBR — 0.74 — 0.88 — 1.03 ns -0.29 — -0.35 — -0.41 — ns Hold Data to EBR Memory 0.37 — 0.44 — 0.52 — ns Setup Address to EBR Memory -0.29 — -0.35 — -0.41 — ns Hold Address to EBR Memory 0.37 — 0.45 — 0.52 — ns Setup Write/Read Enable to EBR Memory -0.18 — -0.22 — -0.26 — ns Hold Write/Read Enable to EBR Memory 0.23 — 0.28 — 0.33 — ns 3-16 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor LatticeECP/EC Internal Switching Characteristics (Continued) Over Recommended Operating Conditions -5 Parameter Description -4 -3 Min. Max. Min. Max. Min. Max. Units tSUCE_EBR Clock Enable Setup Time to EBR Output Register 0.18 — 0.21 — 0.25 — ns tHCE_EBR Clock Enable Hold Time to EBR Output Register -0.14 — -0.17 — -0.20 — ns tRSTO_EBR Reset To Output Delay Time from EBR Output Register — 1.47 — 1.76 — 2.05 ns PLL Parameters tRSTREC Reset Recovery to Rising Clock 1.00 — 1.00 — 1.00 — ns tRSTSU Reset Signal Setup Time 1.00 — 1.00 — 1.00 — ns DSP Block Timing2, 3 tSUI_DSP Input Register Setup Time -0.38 — -0.30 — -0.23 — ns tHI_DSP Input Register Hold Time 0.71 — 0.86 — 1.00 — ns tSUP_DSP Pipeline Register Setup Time 3.31 — 3.98 — 4.64 — ns tHP_DSP Pipeline Register Hold Time 0.71 — 0.86 — 1.00 — ns tSUO_DSP4 Output Register Setup Time 5.54 — 6.64 — 7.75 — ns Output Register Hold Time tHO_DSP 4 tCOI_DSP4 4 0.71 — 0.86 — 1.00 — ns Input Register Clock to Output Time — 7.50 — 9.00 — 10.50 ns Pipeline Register Clock to Output Time — 4.66 — 5.60 — 6.53 ns tCOO_DSP Output Register Clock to Output Time — 1.47 — 1.77 — 2.06 ns tSUADSUB AdSub Input Register Setup Time -0.38 — -0.30 — -0.23 — ns tHADSUB AdSub Input Register Hold Time 0.71 — 0.86 — 1.00 — ns tCOP_DSP 1. Internal parameters are characterized but not tested on every device. 2. These parameters apply to LatticeECP devices only. 3. DSP Block is configured in Multiply Add/Sub 18 x 18 Mode. 4. These parameters include the Adder Subtractor block in the path. Timing v.G 0.30 3-17 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor Timing Diagrams PFU Timing Diagrams Figure 3-6. Slice Single/Dual Port Write Cycle Timing CK WRE AD[3:0] AD DI[1:0] D DO[1:0] Old Data D Figure 3-7. Slice Single /Dual Port Read Cycle Timing WRE AD[3:0] AD DO[1:0] Old Data D 3-18 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor EBR Memory Timing Diagrams Figure 3-8. Read/Write Mode (Normal) CLKA CSA WEA A0 ADA A1 A0 A1 A0 tSU tH DIA D0 D1 tCO_EBR tCO_EBR D0 DOA tCO_EBR D1 D0 Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock. Figure 3-9. Read/Write Mode with Input and Output Registers CLKA CSA WEA ADA A0 tSU DIA A1 A0 A1 A0 tH D0 D1 tCOO_EBR DOA (Regs) Mem(n) data from previous read output is only updated during a read cycle 3-19 tCOO_EBR D0 D1 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor Figure 3-10. Read Before Write (SP Read/Write on Port A, Input Registers Only) CLKA CSA WEA ADA A0 tSU DIA A1 A0 A1 A0 D3 D1 tH D2 D1 D0 tACCESS old A0 Data DOA tACCESS tACCESS old A1 Data tACCESS tACCESS D0 D1 D2 Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock. Figure 3-11. Write Through (SP Read/Write On Port A, Input Registers Only) CLKA CSA WEA Three consecutive writes to A0 ADA A0 tSU DIA A1 tH D0 D2 D1 tACCESS DOA A0 Data from Prev Read or Write tACCESS D0 D3 D4 tACCESS D1 tACCESS D2 D3 D4 Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock. 3-20 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor LatticeECP/EC Family Timing Adders1, 2, 3 Over Recommended Operating Conditions Buffer Type Description -5 -4 -3 Units Input Adjusters LVDS25 LVDS 0.41 0.50 0.58 ns BLVDS25 BLVDS 0.41 0.50 0.58 ns LVPECL33 LVPECL 0.50 0.60 0.70 ns HSTL18_I HSTL_18 class I 0.41 0.49 0.57 ns HSTL18_II HSTL_18 class II 0.41 0.49 0.57 ns HSTL18_III HSTL_18 class III 0.41 0.49 0.57 ns HSTL18D_I Differential HSTL 18 class I 0.37 0.44 0.52 ns HSTL18D_II Differential HSTL 18 class II 0.37 0.44 0.52 ns HSTL18D_III Differential HSTL 18 class III 0.37 0.44 0.52 ns HSTL15_I HSTL_15 class I 0.40 0.48 0.56 ns HSTL15_III HSTL_15 class III 0.40 0.48 0.56 ns HSTL15D_I Differential HSTL 15 class I 0.37 0.44 0.51 ns HSTL15D_III Differential HSTL 15 class III 0.37 0.44 0.51 ns SSTL33_I SSTL_3 class I 0.46 0.55 0.64 ns SSTL33_II SSTL_3 class II 0.46 0.55 0.64 ns SSTL33D_I Differential SSTL_3 class I 0.39 0.47 0.55 ns SSTL33D_II Differential SSTL_3 class II 0.39 0.47 0.55 ns SSTL25_I SSTL_2 class I 0.43 0.51 0.60 ns SSTL25_II SSTL_2 class II 0.43 0.51 0.60 ns SSTL25D_I Differential SSTL_2 class I 0.38 0.45 0.53 ns SSTL25D_II Differential SSTL_2 class II 0.38 0.45 0.53 ns SSTL18_I SSTL_18 class I 0.40 0.48 0.56 ns SSTL18D_I Differential SSTL_18 class I 0.37 0.44 0.51 ns LVTTL33 LVTTL 0.07 0.09 0.10 ns LVCMOS33 LVCMOS 3.3 0.07 0.09 0.10 ns LVCMOS25 LVCMOS 2.5 0.00 0.00 0.00 ns LVCMOS18 LVCMOS 1.8 0.07 0.09 0.10 ns LVCMOS15 LVCMOS 1.5 0.24 0.29 0.33 ns LVCMOS12 LVCMOS 1.2 1.27 1.52 1.77 ns PCI33 PCI 0.07 0.09 0.10 ns Output Adjusters LVDS25E LVDS 2.5 E 0.12 0.14 0.17 ns LVDS25 LVDS 2.5 -0.44 -0.53 -0.62 ns BLVDS25 BLVDS 2.5 0.33 0.40 0.46 ns LVPECL33 LVPECL 3.3 0.20 0.24 0.28 ns HSTL18_I HSTL_18 class I -0.10 -0.12 -0.14 ns HSTL18_II HSTL_18 class II 0.06 0.07 0.08 ns HSTL18_III HSTL_18 class III 0.15 0.19 0.22 ns HSTL18D_I Differential HSTL 18 class I -0.10 -0.12 -0.14 ns HSTL18D_II Differential HSTL 18 class II 0.06 0.07 0.08 ns HSTL18D_III Differential HSTL 18 class III 0.15 0.19 0.22 ns HSTL15_I HSTL_15 class I 0.08 0.10 0.11 ns 3-21 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor LatticeECP/EC Family Timing Adders1, 2, 3 (Continued) Over Recommended Operating Conditions Buffer Type -5 -4 -3 Units HSTL_15 class II 0.10 0.12 0.14 ns HSTL15_III HSTL_15 class III 0.10 0.12 0.14 ns HSTL15D_I Differential HSTL 15 class I 0.08 0.10 0.11 ns HSTL15_II Description HSTL15D_III Differential HSTL 15 class III 0.10 0.12 0.14 ns SSTL33_I SSTL_3 class I -0.05 -0.06 -0.07 ns SSTL33_II SSTL_3 class II 0.40 0.48 0.56 ns SSTL33D_I Differential SSTL_3 class I -0.05 -0.06 -0.07 ns SSTL33D_II Differential SSTL_3 class II 0.40 0.48 0.56 ns SSTL25_I SSTL_2 class I 0.05 0.07 0.08 ns SSTL25_II SSTL_2 class II 0.25 0.30 0.35 ns SSTL25D_I Differential SSTL_2 class I 0.05 0.07 0.08 ns SSTL25D_II Differential SSTL_2 class II 0.25 0.30 0.35 ns SSTL18_I SSTL_1.8 class I 0.01 0.01 0.01 ns SSTL18D_I Differential SSTL_1.8 class I 0.01 0.01 0.01 ns LVTTL33_4mA LVTTL 4mA drive 0.09 0.11 0.13 ns LVTTL33_8mA LVTTL 8mA drive 0.07 0.08 0.09 ns LVTTL33_12mA LVTTL 12mA drive -0.03 -0.04 -0.05 ns LVTTL33_16mA LVTTL 16mA drive 0.36 0.43 0.51 ns LVTTL33_20mA LVTTL 20mA drive 0.28 0.33 0.39 ns LVCMOS33_4mA LVCMOS 3.3 4mA drive 0.09 0.11 0.13 ns LVCMOS33_8mA LVCMOS 3.3 8mA drive 0.07 0.08 0.09 ns LVCMOS33_12mA LVCMOS 3.3 12mA drive -0.03 -0.04 -0.05 ns LVCMOS33_16mA LVCMOS 3.3 16mA drive 0.36 0.43 0.51 ns LVCMOS33_20mA LVCMOS 3.3 20mA drive 0.28 0.33 0.39 ns LVCMOS25_4mA LVCMOS 2.5 4mA drive 0.18 0.21 0.25 ns LVCMOS25_8mA LVCMOS 2.5 8mA drive 0.10 0.12 0.14 ns LVCMOS25_12mA LVCMOS 2.5 12mA drive 0.00 0.00 0.00 ns LVCMOS25_16mA LVCMOS 2.5 16mA drive 0.22 0.26 0.31 ns LVCMOS25_20mA LVCMOS 2.5 20mA drive 0.14 0.16 0.19 ns LVCMOS18_4mA LVCMOS 1.8 4mA drive 0.15 0.18 0.21 ns LVCMOS18_8mA LVCMOS 1.8 8mA drive 0.06 0.08 0.09 ns LVCMOS18_12mA LVCMOS 1.8 12mA drive 0.01 0.01 0.01 ns LVCMOS18_16mA LVCMOS 1.8 16mA drive 0.16 0.19 0.22 ns LVCMOS15_4mA LVCMOS 1.5 4mA drive 0.26 0.31 0.36 ns LVCMOS15_8mA LVCMOS 1.5 8mA drive 0.04 0.04 0.05 ns LVCMOS12_2mA LVCMOS 1.2 2mA drive 0.36 0.43 0.50 ns LVCMOS12_6mA LVCMOS 1.2 6mA drive 0.08 0.10 0.11 ns LVCMOS12_4mA LVCMOS 1.2 4mA drive 0.36 0.43 0.50 ns PCI33 PCI33 1.05 1.26 1.46 ns 1. Timing adders are characterized but not tested on every device. 2. LVCMOS timing measured with the load specified in Switching Test Conditions table of this document. 3. All other standards according to the appropriate specification. Timing v.G 0.30 3-22 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor sysCLOCK PLL Timing Over Recommended Operating Conditions Parameter Description Conditions Min. Typ. Max. Units fIN Input Clock Frequency (CLKI, CLKFB) 25 — 420 MHz fOUT Output Clock Frequency (CLKOP, CLKOS) 25 — 420 MHz fOUT2 K-Divider Output Frequency (CLKOK) 0.195 — 210 MHz fVCO PLL VCO Frequency 420 — 840 MHz fPFD Phase Detector Input Frequency 25 — — MHz Default Duty Cycle Elected3 45 50 55 % — — 0.05 UI fOUT >= 100MHz — — +/- 125 ps fOUT < 100MHz — — 0.02 UIPP Divider ratio = integer — — +/- 200 ps AC Characteristics tDT Output Clock Duty Cycle tPH4 Output Phase Accuracy tOPJIT1 Output Clock Period Jitter tSK Input Clock to Output Clock Skew 3 tW Output Clock Pulse Width tLOCK2 PLL Lock-in Time At 90% or 10% 1 — — ns — — 150 µs tPA Programmable Delay Unit tIPJIT Input Clock Period Jitter 100 250 450 ps — — +/- 200 ps tFBKDLY External Feedback Delay tHI Input Clock High Time 90% to 90% — — 10 ns 0.5 — — ns tLO Input Clock Low Time 10% to 10% 0.5 — — ns tRST RST Pulse Width 10 — — ns 1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock. 2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment. 3. Using LVDS output buffers. 4. Relative to CLKOP. Timing v.G 0.30 3-23 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor LatticeECP/EC sysCONFIG Port Timing Specifications Over Recommended Operating Conditions Parameter Description Min. Typ. Max. Units — ns sysCONFIG Byte Data Flow tSUCBDI Byte D[0:7] Setup Time to CCLK 7 tHCBDI Byte D[0:7] Hold Time to CCLK 1 — ns tCODO Clock to Dout in Flowthrough Mode — 12 ns tSUCS CS[0:1] Setup Time to CCLK 7 — ns tHCS CS[0:1] Hold Time to CCLK 1 — ns tSUWD Write Signal Setup Time to CCLK 7 — ns tHWD Write Signal Hold Time to CCLK 1 — ns tDCB CCLK to BUSY Delay Time — 12 ns tCORD Clock to Out for Read Data — 12 ns 6 — ns sysCONFIG Byte Slave Clocking tBSCH Byte Slave Clock Minimum High Pulse tBSCL Byte Slave Clock Minimum Low Pulse 9 — ns tBSCYC Byte Slave Clock Cycle Time 15 — ns tSUSCDI Din Setup time to CCLK Slave Mode 7 — ns tHSCDI Din Hold Time to CCLK Slave Mode 1 — ns tCODO Clock to Dout in Flowthrough Mode — 12 ns sysCONFIG Serial (Bit) Data Flow tSUMCDI Din Setup time to CCLK Master Mode 7 — ns tHMCDI Din Hold Time to CCLK Master Mode 1 — ns sysCONFIG Serial Slave Clocking tSSCH Serial Slave Clock Minimum High Pulse 6 — ns tSSCL Serial Slave Clock Minimum Low Pulse 6 — ns sysCONFIG POR, Initialization and Wake Up tICFG Minimum Vcc to INIT High — 50 ms tVMC Time from tICFG to Valid Master Clock — 2 us tPRGMRJ Program Pin Pulse Rejection — 8 ns tPRGM PROGRAMN Low Time to Start Configuration 25 — ns tDINIT INIT Low Time — 1 ms tDPPINIT Delay Time from PROGRAMN Low to INIT Low — 37 ns tDINITD Delay Time from PROGRAMN Low to DONE Low — 37 ns tIODISS User I/O Disable from PROGRAMN Low — 35 ns tIOENSS User I/O Enabled Time from CCLK Edge During Wake Up Sequence — 25 ns tMWC Additional Wake Master Clock Signals after Done Pin High 120 — cycles tSUCFG CFG to INITN Setup Time 100 — ns tHCFG CFG to INITN Hold Time 100 — ns sysCONFIG SPI Port tCFGX Init High to CCLK Low — 80 ns tCSSPI Init High to CSSPIN Low — 2 us tCSCCLK CCLK Low Before CSSPIN Low 0 - ns tSOCDO CCLK Low to Output Valid — 15 ns 3-24 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor LatticeECP/EC sysCONFIG Port Timing Specifications (Continued) Over Recommended Operating Conditions Parameter Description Min. Max. Units 300 Typ. — ns 300+3cyc 600+6cyc ns — 25 MHz tSOE CSSPIN Active Setup Time tCSPID CSSPIN Low to First Clock Edge Setup Time fMAXSPI Max Frequency for SPI tSUSPI SOSPI Data Setup Time Before CCLK 7 — ns tHSPI SOSPI Data Hold Time After CCLK 1 — ns Timing v.G 0.30 Master Clock Min. Typ. Max. Units 2.5MHz Clock Mode 1.75 2.5 3.25 MHz 5 MHz 3.78 5.4 7.02 MHz 10 MHz 7 10 13 MHz 15 MHz 10.5 15 19.5 MHz 20 MHz 14 20 26 MHz 25 MHz 18.2 26 33.8 MHz 30 MHz 21 30 39 MHz 35 MHz 23.8 34 44.2 MHz 40 MHz 28.7 41 53.3 MHz 45 MHz 31.5 45 58.5 MHz 50 MHz 35.7 51 66.3 MHz 55 MHz 38.5 55 71.5 MHz 60 MHz 42 60 78 MHz Duty Cycle 40 — 60 % Timing v.G 0.30 3-25 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor Figure 3-12. sysCONFIG Parallel Port Read Cycle tBSCL tBSCYC tBSCH CCLK 1 t SUCS tHCS tSUWD t HWD CS1N CSN WRITEN tDCB BUSY t CORD D[0:7] Byte 0 Byte 1 Byte 2 Byte n 1. In Master Parallel Mode the FPGA provides CCLK. In Slave Parallel Mode the external device provides CCLK. Figure 3-13. sysCONFIG Parallel Port Write Cycle tBSCYC tBSCL CCLK tBSCH 1 t SUCS tHCS CS1N CSN t SUWD t HWD WRITEN tDCB BUSY t HCBDI tSUCBDI D[0:7] Byte 0 Byte 1 Byte 2 Byte n 1. In Master Parallel Mode the FPGA provides CCLK. In Slave Parallel Mode the external device provides CCLK. 3-26 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor Figure 3-14. sysCONFIG Master Serial Port Timing CCLK (output) t HMCDI tSUMCDI DIN t CODO DOUT Figure 3-15. sysCONFIG Slave Serial Port Timing tSSCL tSSCH CCLK (input) tHSCDI t SUSCDI DIN t CODO DOUT Figure 3-16. Power-On-Reset (POR) Timing VCC/VCCAUX 1 tICFG INITN DONE t VMC CCLK 2 tHCFG t SUCFG CFG[2:0] 3 Valid 1. Time taken from VCC or VCCAUX, whichever is the last to reach its VMIN. 2. Device is in a Master Mode. 3. The CFG pins are normally static (hard wired). 3-27 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor Figure 3-17. Configuration from PROGRAMN Timing t PRGMRJ PROGRAMN t DPPINIT tDINIT INITN tDINITD DONE CCLK tHCFG tSUCFG CFG[2:0] Valid tIODISS USER I/O 1. The CFG pins are normally static (hard wired) Figure 3-18. Wake-Up Timing PROGRAMN INITN Wake-Up DONE tMWC CCLK tIOENSS USER I/O Figure 3-19. sysCONFIG SPI Port Sequence Capture CFGx Capture OPCODE Clock 127 Clock 128 tICFG VCC tPRGM PROGRAMN tDINITD DONE tDPPINIT INITN CSSPIN CCLK tDINIT tCSSPI tCSPID tCFGX tCSCCLK 0 2 3 4 5 6 7 tSOCDO tSOE SISPI/BUSY 1 D7 D6 D5 D4 D3 D2 D1 D0 D7/SPID0 0 XXX 3-28 Valid Bitstream DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor JTAG Port Timing Specifications Over Recommended Operating Conditions Symbol Parameter Min Max Units fMAX TCK clock frequency — 25 MHz tBTCP TCK [BSCAN] clock pulse width 40 — ns tBTCPH TCK [BSCAN] clock pulse width high 20 — ns tBTCPL TCK [BSCAN] clock pulse width low 20 — ns tBTS TCK [BSCAN] setup time 8 — ns tBTH TCK [BSCAN] hold time 10 — ns tBTRF TCK [BSCAN] rise/fall time 50 — mV/ns tBTCO TAP controller falling edge of clock to valid output — 10 ns tBTCODIS TAP controller falling edge of clock to valid disable — 10 ns tBTCOEN TAP controller falling edge of clock to valid enable — 10 ns tBTCRS BSCAN test capture register setup time 8 — ns tBTCRH BSCAN test capture register hold time 25 — ns tBUTCO BSCAN test update register, falling edge of clock to valid output — 25 ns tBTUODIS BSCAN test update register, falling edge of clock to valid disable — 25 ns tBTUPOEN BSCAN test update register, falling edge of clock to valid enable — 25 ns Timing v.G 0.30 Figure 3-20. JTAG Port Timing Waveforms TMS TDI tBTS tBTCPH tBTH tBTCP tBTCPL TCK tBTCO tBTCOEN TDO Valid Data tBTCRS Data to be captured from I/O tBTCODIS Valid Data tBTCRH Data Captured tBTUPOEN tBUTCO Data to be driven out to I/O Valid Data 3-29 tBTUODIS Valid Data DC and Switching Characteristics LatticeECP/EC Family Data Sheet Lattice Semiconductor Switching Test Conditions Figure 3-21 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 3-6. Figure 3-21. Output Test Load, LVTTL and LVCMOS Standards VT R1 DUT Test Point CL* *CL Includes Test Fixture and Probe Capacitance Table 3-6. Test Fixture Required Components, Non-Terminated Interfaces Test Condition LVTTL and other LVCMOS settings (L -> H, H -> L) R1 ∞ CL 0pF Timing Ref. LVCMOS 3.3 = 1.5V — LVCMOS 2.5 = VCCIO/2 — LVCMOS 1.8 = VCCIO/2 — LVCMOS 1.5 = VCCIO/2 — LVCMOS 1.2 = VCCIO/2 LVCMOS 2.5 I/O (Z -> H) LVCMOS 2.5 I/O (Z -> L) LVCMOS 2.5 I/O (H -> Z) 188Ω LVCMOS 2.5 I/O (L -> Z) 0pF — VCCIO/2 VOL VCCIO/2 VOH VOH - 0.15 VOL VOL + 0.15 VOH Note: Output test conditions for all other interfaces are determined by the respective standards. 3-30 VT LatticeECP/EC Family Data Sheet Pinout Information November 2007 Data Sheet Signal Descriptions Signal Name I/O Description General Purpose [Edge] indicates the edge of the device on which the pad is located. Valid edge designations are L (Left), B (Bottom), R (Right), T (Top). [Row/Column Number] indicates the PFU row or the column of the device on which the PIC exists. When Edge is T (Top) or (Bottom), only need to specify Row Number. When Edge is L (Left) or R (Right), only need to specify Column Number. P[Edge] [Row/Column Number*]_[A/B] I/O [A/B] indicates the PIO within the PIC to which the pad is connected. Some of these user-programmable pins are shared with special function pins. These pin when not used as special purpose pins can be programmed as I/Os for user logic. During configuration the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after configuration. GSRN NC I — Global RESET signal (active low). Any I/O pin can be GSRN. No connect. GND — Ground. Dedicated pins. VCC — Power supply pins for core logic. Dedicated pins. VCCAUX — Auxiliary power supply pin. It powers all the differential and referenced input buffers. Dedicated pins. VCCIOx — Power supply pins for I/O bank x. Dedicated pins. VREF1_x, VREF2_x — Reference supply pins for I/O bank x. Pre-determined pins in each bank are assigned as VREF inputs. When not used, they may be used as I/O pins. XRES — 10K ohm +/-1% resistor must be connected between this pad and ground. VCCPLL — Power supply pin for PLL. Applicable to ECP/EC33 device. PLL and Clock Functions (Used as user programmable I/O pins when not in use for PLL or clock pins) [LOC][num]_PLL[T, C]_IN_A I Reference clock (PLL) input pads: ULM, LLM, URM, LRM, num = row from center, T = true and C = complement, index A,B,C...at each side. [LOC][num]_PLL[T, C]_FB_A I Optional feedback (PLL) input pads: ULM, LLM, URM, LRM, num = row from center, T = true and C = complement, index A,B,C...at each side. PCLK[T, C]_[n:0]_[3:0] I Primary Clock pads, T = true and C = complement, n per side, indexed by bank and 0,1,2,3 within bank. [LOC]DQS[num] I DQS input pads: T (Top), R (Right), B (Bottom), L (Left), DQS, num = ball function number. Any pad can be configured to be output. TMS I Test Mode Select input, used to control the 1149.1 state machine. Pull-up is enabled during configuration. TCK I Test Clock input pin, used to clock the 1149.1 state machine. No pull-up enabled. Test and Programming (Dedicated pins) © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 4-1 Pinout Information_02.5 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor Signal Descriptions (Cont.) Signal Name TDI I/O I Description Test Data in pin. Used to load data into device using 1149.1 state machine. After power-up, this TAP port can be activated for configuration by sending appropriate command. (Note: once a configuration port is selected it is locked. Another configuration port cannot be selected until the power-up sequence). Pull-up is enabled during configuration. TDO O Output pin. Test Data out pin used to shift data out of device using 1149.1. VCCJ — VCCJ - The power supply pin for JTAG Test Access Port. Configuration Pads (used during sysCONFIG) CFG[2:0] INITN I Mode pins used to specify configuration modes values latched on rising edge of INITN. During configuration, a pull-up is enabled. These are dedicated pins. I/O Open Drain pin. Indicates the FPGA is ready to be configured. During configuration, a pull-up is enabled. It is a dedicated pin. I Initiates configuration sequence when asserted low. This pin always has an active pull-up. This is a dedicated pin. DONE I/O Open Drain pin. Indicates that the configuration sequence is complete, and the startup sequence is in progress. This is a dedicated pin. CCLK I/O Configuration Clock for configuring an FPGA in sysCONFIG mode. BUSY/SISPI I/O Read control command in SPI3 or SPIX mode. PROGRAMN CSN I sysCONFIG chip select (Active low). During configuration, a pull-up is enabled. CS1N I sysCONFIG chip select (Active low). During configuration, a pull-up is enabled. WRITEN I Write Data on Parallel port (Active low). D[7:0]/SPID[0:7] I/O sysCONFIG Port Data I/O. DOUT/CSON O DI/CSSPIN Input for serial configuration data (clocked with CCLK) when using sysCONI/O FIG port. During configuration, a pull-up is enabled. Output when used in SPI/SPIX modes. Output for serial configuration data (rising edge of CCLK) when using sysCONFIG port. 4-2 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin PICs Associated with DQS Strobe P[Edge] [n-4] P[Edge] [n-3] P[Edge] [n-2] P[Edge] [n-1] P[Edge] [n] P[Edge] [n+1] P[Edge] [n+2] P[Edge] [n+3] PIO Within PIC DDR Strobe (DQS) and Data (DQ) Pins A DQ B DQ A DQ B DQ A DQ B DQ A DQ B DQ A [Edge]DQSn B DQ A DQ B DQ A DQ B DQ A DQ B DQ Notes: 1. “n” is a Row/Column PIC number 2. The DDR interface is designed for memories that support one DQS strobe per eight bits of data. In some packages, all the potential DDR data (DQ) pins may not be available. 3. PIC numbering definitions are provided in the “Signal Names” column of the Signal Descriptions table. 4-3 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor Pin Information Summary LFEC1 Pin Type LFEC3 LFECP6/EC6 LFECP/EC10 100- 144- 208- 100- 144- 208- 256- 144- 208- 256- 484- 208- 256- 484TQFP TQFP PQFP TQFP TQFP PQFP fpBGA TQFP PQFP fpBGA fpBGA PQFP fpBGA fpBGA Single Ended User I/O 67 97 112 67 97 145 160 97 147 195 224 147 195 288 Differential Pair User I/O 29 46 56 29 46 72 80 46 72 97 112 72 97 144 Dedicated 13 13 13 13 13 13 13 13 13 13 13 13 13 13 Muxed 48 48 48 48 48 48 48 48 48 48 48 56 56 56 TAP 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Dedicated (total without supplies) 80 110 160 80 110 160 208 110 160 208 373 160 208 373 VCC 2 3 3 2 3 3 10 4 4 10 20 6 10 20 VCCAUX 2 2 2 4 4 4 4 2 4 2 12 4 2 12 VCCPLL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bank0 1 2 2 1 2 3 2 2 3 2 4 3 2 4 Bank1 1 2 2 1 2 2 2 2 2 2 4 2 2 4 Bank2 1 1 1 2 2 2 2 1 2 2 4 2 2 4 Bank3 1 2 2 1 2 2 2 2 2 2 4 2 2 4 Bank4 1 2 2 1 2 2 2 2 2 2 4 2 2 4 Bank5 1 2 2 1 2 2 2 2 3 2 4 3 2 4 Bank6 1 2 2 1 2 2 2 2 2 2 4 2 2 4 Bank7 1 1 1 2 2 2 2 1 2 2 4 2 2 4 GND, GND0-GND7 8 13 13 8 13 16 20 14 18 20 44 20 20 44 NC 0 2 51 0 2 9 35 0 4 0 139 0 0 75 Bank 0 11/5 14/7 16/8 11/5 14/7 26/13 32/16 14/7 26/13 32/16 32/16 26/13 32/16 48/24 Bank 1 11/5 13/6 16/8 11/5 13/6 16/8 16/8 13/6 17/8 Bank 2 3/1 8/4 8/4 3/1 8/4 14/7 16/8 8/4 Bank 3 8/4 13/6 16/8 8/4 13/6 16/8 16/8 13/6 Bank 4 12/4 14/6 16/8 12/4 14/6 16/8 16/8 14/6 Bank 5 9/4 13/6 16/8 9/4 13/6 26/13 32/16 13/6 26/13 32/16 32/16 26/13 32/16 48/24 Bank 6 5/2 14/7 16/8 5/2 14/7 16/8 16/8 14/7 16/8 32/16 32/16 16/8 32/16 32/16 Bank 7 8/4 8/4 8/4 8/4 8/4 15/7 16/8 8/4 15/7 16/8 16/8 15/7 16/8 32/16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Configuration VCCIO Single Ended/ Differential I/O Pair per Bank VCCJ 18/9 32/16 17/8 14/7 16/8 16/8 16/8 32/16 32/16 17/8 17/8 32/16 18/9 32/16 14/7 16/8 32/16 16/8 32/16 32/16 17/8 17/8 32/16 Note: During configuration the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after configuration. 4-4 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor Pin Information Summary (Cont.) LFECP/EC15 Pin Type Single Ended User I/O Differential Pair User I/O LFECP20/EC20 LFECP/EC33 256-fpBGA 484-fpBGA 484-fpBGA 672-fpBGA 484-fpBGA 672-fpBGA 195 352 360 400 360 496 97 176 180 200 180 248 Dedicated 13 13 13 13 13 13 Muxed 56 56 56 56 56 56 5 5 5 5 5 5 Dedicated (total without supplies) 208 373 373 509 373 509 VCC 10 20 20 32 16 28 VCCAUX 2 12 12 20 12 20 VCCPLL 0 0 0 0 4 4 Bank0 2 4 4 6 4 6 Bank1 2 4 4 6 4 6 Bank2 2 4 4 6 4 6 Bank3 2 4 4 6 4 6 Bank4 2 4 4 6 4 6 Bank5 2 4 4 6 4 6 Bank6 2 4 4 6 4 6 Bank7 2 4 4 6 4 6 Configuration TAP VCCIO GND, GND0-GND7 20 44 44 63 44 63 NC 0 11 3 96 3 0 Single Ended/ Differential I/O Pair per Bank VCCJ Bank0 32/16 48/24 48/24 64/32 48/24 64/32 Bank1 18/9 48/24 48/24 48/24 48/24 64/32 Bank2 16/8 40/20 40/20 40/20 40/20 56/28 Bank3 32/16 40/20 44/22 48/24 44/22 64/32 Bank4 17/8 48/24 48/24 48/24 48/24 64/32 Bank5 32/16 48/24 48/24 64/32 48/24 64/32 Bank6 32/16 40/20 44/22 48/24 44/22 64/32 Bank7 16/8 40/20 40/20 40/20 40/20 56/28 1 1 1 1 1 1 Note: During configuration the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after configuration. 4-5 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor Power Supply and NC Connections Signals 100 TQFP 144 TQFP 208 PQFP 256 fpBGA VCC 12, 64 EC1, EC3: 13, 92, 99 EC1, EC3: 26, 128, 135 E12, E5, E8, M12, M5, ECP/EC6: 11, 13, 92, 99 ECP/EC6: 24, 26, 128, M9, F6, F11, L11, L6 135 ECP/EC10: 5, 24, 26, 128, 135, 152 VCCIO0 100 136, 143 EC1: 187, 208 EC3, ECP/EC6, ECP/ EC10: 187, 197, 208 F7, F8 VCCIO1 86 110, 125 157, 176 F9, F10 VCCIO2 73 108 EC1: 155 EC3, ECP/EC6, ECP/ EC10: 145, 155 G11, H11 VCCIO3 56 73, 84 106, 120 J11, K11 VCCIO4 38 55, 71 85, 104 L9, L10 VCCIO5 26 38, 44 EC1: 53, 74 EC2, ECP/EC6, ECP/ EC10: 53, 64, 74 L7, L8 VCCIO6 24 24, 36 37, 51 J6, K6 VCCIO7 2 1 EC1: 2 EC3, ECP/EC6, ECP/ EC10: 2, 13 G6, H6 VCCJ 18 19 32 L4 VCCAUX 37, 87 54, 126 EC1: 84, 177 EC3, ECP/EC6, ECP/ EC10: 22, 84, 136, 177 B15, R2 VCCPLL — — — — A1, A16, G10, G7, G8, G9, H10, H7, H8, H9, J10, J7, J8, J9, K10, K7, K8, K9, T1, T16 EC3: G5, H5, F2, F1, H4, H3, G2, G1, J4, J3, J5, K5, H2, H1, J2, J1, R12, H16, H15, G16, G15, K12, J12, J14, J15, F16, F15, J13, H13, H14, G14, E16, E15, B13, C13 ECP/EC10: None ECP/EC15: None GND, GND0-GND7 1, 14, 25, 35, 51, 68, 74, EC1, EC3: 15, 28, 37, 89 52, 63, 72, 80, 96, 98, 109, 117, 128, 144 ECP/EC6: 12, 15, 28, 37, 52, 63, 72, 80, 96, 98, 109, 117, 128, 144 EC1: 1, 28, 41, 52, 82, 93, 105, 116, 132, 134, 156, 168, 179 EC3: 1, 28, 41, 52, 72, 82, 93, 105, 116, 132, 134, 138, 156, 168, 179, 189 ECP/EC6: 1, 18, 25, 28, 41, 52, 72, 82, 93, 105, 116, 132, 134, 138, 156, 168, 179, 189 ECP/EC10: 1, 6, 18, 25, 28, 41, 52, 72, 82, 93, 105, 116, 132, 134, 138, 151, 156, 168, 179, 189 NC — EC1: 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 18, 22, 24, 25, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 72, 103, 136, 138, 144, 145, 146, 147, 148, 149, 150, 151, 152, 158, 189, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207 EC3: 5, 6, 18, 24, 25, 103, 151, 152, 158 ECP/EC6: 5, 6, 151, 152 ECP/EC10: None EC1, EC3: 11, 12 ECP6/EC6: None 4-6 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor Power Supply and NC Connections (Cont.) Signals 484 fpBGA 672 fpBGA VCC J16, J7, K16, K17, K6, K7, L17, L6, M17, M6, N16, H10, H11, H16, H17, H18, H19, H8, H9, J18, J9, N17, N6, N7, P16, P7, J6, J17, P6, P17 K8, L19, M19, N7, R20, R7, T19, V18, V8, V9, W10, W11, W16, W17, W18, W19, W8, W9, K19, L8, U19, U8 VCCIO0 G11, H10, H11, H9 H12, H13, J10, J11, J12, J13 VCCIO1 G12, H12, H13, H14 H14, H15, J14, J15, J16, J17 VCCIO2 J15, K15, L15, L16 K17, K18, L18, M18, N18, N19 VCCIO3 M15, M16, N15, P15 P18, P19, R18, R19, T18, U18 VCCIO4 R12, R13, R14, T12 V14, V15, V16, V17, W14, W15 VCCIO5 R10, R11, R9, T11 V10, V11, V12, V13, W12, W13 VCCIO6 M7, M8, N8, P8 P8, P9, R8, R9, T9, U9 VCCIO7 J8, K8, L7, L8 K9, L9, M8, M9, N8, N9 VCCJ U2 U6 VCCAUX G15, G16, G7, G8, H16, H7, R16, R7, T15, T16, T7, T8 G13, H20, H7, J19, J8, K7, L20, M20, M7, N20, P20, P7, T20, T7, T8, V19, V7, W20, Y13, Y7 VCCPLL ECP/EC20: None ECP/EC33: J6, J17, P6, P17 ECP/EC20: None ECP/EC33: K19, L8, U19, U8 GND, GND0-GND7 A1, A22, AB1, AB22, H15, H8, J10, J11, J12, J13, J14, J9, K10, K11, K12, K13, K14, K9, L10, L11, L12, L13, L14, L9, M10, M11, M12, M13, M14, M9, N10, N11, N12, N13, N14, N9, P10, P11, P12, P13, P14, P9, R15, R8 K10, K11, K12, K13, K14, K15, K16, L10, L11, L12, L13, L14, L15, L16, L17, M10, M11, M12, M13, M14, M15, M16, M17, N10, N11, N12, N13, N14, N15, N16, N17, P10, P11, P12, P13, P14, P15, P16, P17, R10, R11, R12, R13, R14, R15, R16, R17, T10, T11, T12, T13, T14, T15, T16, T17, U10, U11, U12, U13, U14, U15, U16, U17 NC ECP/EC6: C3, B2, E5, F5, D3, C2, F4, G4, E3, D2, B1, C1, F3, E2, G5, H6, G3, H4, J5, H5, F2, F1, E1, D1, R6, P5, P3, P4, R1, R2, R5, R4, T1, T2, R3, T3, V7, T6, V8, U7, W5, U6, AA3, AB3, Y6, V6, AA5, W6, Y5, Y4, AA4, AB4, W16, U15, V16, U16, Y17, V17, AB20, AA19, Y16, W17, AA20, Y19, Y18, W18, T17, U17, T18, R17, R19, R18, U22, T22, R21, R22, P20, N20, P19, P18, E21, D22, G21, G20, J18, H19, J19, H20, H17, H18, D21, C22, G19, G18, F20, F19, E20, D20, C21, C20, F18, E18, B22, B21, G17, F17, D18, C18, C19, B20, D17, C16, B19, A20, E17, C17, F16, E16, F15, D16, A4, B4, C4, C5, D6, B5, E6, C6, A3, B3, F6, D5, F7, E8, G6, E7, A2, AB2, A21 ECP/EC10: G5, H6, G3, H4, J5, H5, F2, F1, R6, P5, P3, P4, R2, R1, R5, R4, T1, T2, R3, T3, W16, U15, V16, U16, Y17, V17, AB20, AA19, Y16, W17, AA20, Y19, Y18, W18, T17, U17, T18, R17, R19, R18, U22, T22, R21, R22, P20, N20, P19, P18, G21, G20, J18, H19, J19, H20, H17, H18, G17, F17, D18, C18, C19, B20, D17, C16, B19, A20, E17, C17, F16, E16, F15, D16, A2, AB2, A21 ECP/EC15: T1, T2, R3, T3, T18, R17, R19, R18, A2, AB2, A21 ECP/EC20: A2, AB2, A21 ECP/EC33: A2, AB2, A21 ECP/EC20: E5, D5, F4, F5, C3, D3, C2, B2, H6, J7, G5, H5, H3, J3, H2, J2, AA2, AA3, W5, Y5, Y6, W7, AA4, AB3, AC2, AC3, AA5, AB5, AD3, AD2, AE1, AD1, AD19, AD20, AC19, AB19, AD21, AC20, AF25, AE25, AB21, AB20, AE24, AD23, AD22, AC21, AC22, AB22, AD24, AD25, AE26, AD26, Y20, Y19, AA23, AA22, AB23, AB24, Y21, AA21, Y23, Y22, AA24, Y24, J21, J22, J23, H22, G26, F26, E26, E25, F24, F23, E24, D24, E22, F22, E21, D22, G20, F20, D21, C21, C23, C22, B23, C24, D20, E19, B25, B24, B26, A25, C20, C19 ECP/EC33: None 4-7 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFEC1, LFEC3 Logic Signal Connections: 100 TQFP LFEC1 Pin Number Pin Function 1* GND0 GND7 2 Bank LVDS LFEC3 Dual Function Pin Function Bank LVDS Dual Function - GND0 GND7 - VCCIO7 7 VCCIO7 7 3 PL2A 7 T VREF2_7 PL2A 7 T VREF2_7 4 PL2B 7 C VREF1_7 PL2B 7 C VREF1_7 5 PL3A 7 T PL7A 7 T 6 PL3B 7 C PL7B 7 C 7 PL4A 7 T PL8A 7 T 8 PL4B 7 C PL8B 7 C 9 PL5A 7 T PCLKT7_0 PL9A 7 T PCLKT7_0 C PCLKC7_0 C PCLKC7_0 LUM0_PLLT_IN_A 10 PL5B 7 PL9B 7 11 XRES 6 XRES 6 12 VCC - VCC - 13 TCK 6 TCK 6 14 GND - GND - 15 TDI 6 TDI 6 16 TMS 6 TMS 6 17 TDO 6 TDO 6 18 VCCJ 6 19 PL7A 6 T 20 PL7B 6 21 PL8A 6 22 PL8B 6 23 PL14A 6 24 VCCIO6 25* GND5 GND6 26 VCCJ 6 LLM0_PLLT_IN_A PL11A 6 T C LLM0_PLLC_IN_A PL11B 6 C LUM0_PLLC_IN_A T LLM0_PLLT_FB_A PL12A 6 T LUM0_PLLT_FB_A C LLM0_PLLC_FB_A PL12B 6 C LUM0_PLLC_FB_A VREF1_6 PL18A 6 6 VCCIO6 6 - GND5 GND6 - VCCIO5 5 VCCIO5 5 27 PB2A 5 T PB10A 5 T 28 PB2B 5 C PB10B 5 C 29 PB3A 5 T PB11A 5 T 30 PB3B 5 C PB11B 5 C 31 PB6A 5 32 PB8A 5 T 33 PB8B 5 34 PB9A 5 35 GND5 5 36 PB9B 5 37 VCCAUX - VCCAUX - 38 VCCIO4 4 VCCIO4 4 39 PB10A 4 T WRITEN PB18A 40 PB10B 4 C CS1N PB18B VREF1_6 BDQS6 PB14A 5 VREF2_5 PB16A 5 T C VREF1_5 PB16B 5 C VREF1_5 T PCLKT5_0 PB17A 5 T PCLKT5_0 GND5 5 C PCLKC5_0 PB17B 5 C PCLKC5_0 4 T WRITEN 4 C CS1N 4-8 BDQS14 VREF2_5 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFEC1, LFEC3 Logic Signal Connections: 100 TQFP (Cont.) LFEC1 LFEC3 Pin Number Pin Function Bank LVDS Dual Function Pin Function Bank LVDS Dual Function 41 PB11A 4 T VREF1_4 PB19A 4 T VREF1_4 42 PB11B 4 C CSN PB19B 4 C 43 PB12B 4 D0/SPID7 PB20B 4 44 PB13A 4 T D2/SPID5 PB21A 4 T D2/SPID5 45 PB13B 4 C D1/SPID6 PB21B 4 C D1/SPID6 46 PB14A 4 T BDQS14 PB22A 4 T BDQS22 47 PB14B 4 C D3/SPID4 PB22B 4 C D3/SPID4 48 PB15B 4 D4/SPID3 PB23B 4 D4/SPID3 49 PB16B 4 D5/SPID2 PB24B 4 D5/SPID2 50 PB17B 4 D6/SPID1 PB25B 4 D6/SPID1 51* GND3 GND4 - GND3 GND4 - 52 PR10B 3 PR14B 3 53 PR10A 54 PR9B 55 PR9A 3 56 VCCIO3 3 57 PR8B 3 C 58 PR8A 3 T 59 PR7B 3 C 60 PR7A 3 T 61 CFG2 62 CFG1 63 64 65 66 C RLM0_PLLC_FB_A 3 T RLM0_PLLT_FB_A PR14A 3 C RLM0_PLLC_IN_A PR13B T RLM0_PLLT_IN_A CSN D0/SPID7 C RLM0_PLLC_FB_A 3 T RLM0_PLLT_FB_A 3 C RLM0_PLLC_IN_A T RLM0_PLLT_IN_A PR13A 3 VCCIO3 3 DI/CSSPIN PR12B 3 C DI/CSSPIN DOUT/CSON PR12A 3 T DOUT/CSON BUSY/SISPI PR11B 3 C BUSY/SISPI D7/SPID0 PR11A 3 T D7/SPID0 3 CFG2 3 3 CFG1 3 CFG0 3 CFG0 3 VCC - VCC - PROGRAMN 3 PROGRAMN 3 CCLK 3 CCLK 3 67 INITN 3 INITN 3 68 GND - GND - 69 DONE 3 DONE 3 70 PR5B 2 C PCLKC2_0 PR9B 2 C PCLKC2_0 71 PR5A 2 T PCLKT2_0 PR9A 2 T PCLKT2_0 72 PR2B 2 VREF1_2 PR2B 2 73 VCCIO2 2 VCCIO2 2 74 GND2 2 GND2 2 75 PT17B 1 C PT25B 1 C 76 PT17A 1 T PT25A 1 T 77 PT14B 1 C PT22B 1 C 78 PT14A 1 T PT22A 1 T 79 PT13A 1 PT21A 1 80 PT12B 1 C PT20B 1 C 81 PT12A 1 T PT20A 1 T TDQS14 4-9 VREF1_2 TDQS22 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFEC1, LFEC3 Logic Signal Connections: 100 TQFP (Cont.) LFEC1 LFEC3 Pin Number Pin Function Bank LVDS Dual Function Pin Function Bank LVDS Dual Function 82 PT11B 1 C VREF2_1 PT19B 1 C VREF2_1 83 PT11A 1 T VREF1_1 VREF1_1 84 PT10B 1 C 85 PT10A 1 T 86 VCCIO1 1 87 VCCAUX - 88 PT9B 0 89 GND0 0 90 PT9A 91 92 PT19A 1 T PT18B 1 C PT18A 1 T VCCIO1 1 VCCAUX - C PCLKC0_0 PT17B 0 GND0 0 0 T PCLKT0_0 PT17A PT8B 0 C VREF1_0 PT8A 0 T VREF2_0 93 PT7B 0 94 PT6B 0 95 PT6A 0 T 96 PT4B 0 C 97 PT4A 0 T PT12A 0 T 98 PT2B 0 C PT10B 0 C 99 PT2A 0 T PT10A 0 T 100 VCCIO0 0 VCCIO0 0 C TDQS6 *Double bonded to the pin. 4-10 C PCLKC0_0 0 T PCLKT0_0 PT16B 0 C VREF1_0 PT16A 0 T VREF2_0 PT15B 0 PT14B 0 C PT14A 0 T PT12B 0 C TDQS14 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFEC1, LFEC3, LFECP/EC6 Logic Signal Connections: 144 TQFP LFEC1 Pin Number Pin Function Bank LVDS 1 VCCIO7 7 2 PL2A 7 T 3 PL2B 7 C 4 PL3A 7 5 PL3B 6 PL4A 7 LFEC3 Dual Function Pin Function Bank LVDS VCCIO7 7 VREF2_7 PL2A 7 T VREF1_7 PL2B 7 C T PL7A 7 7 C PL7B 7 T PL8A PL4B 7 C 8 PL5A 7 T 9 PL5B 7 C 10 XRES 11 NC 12 13 LFECP6/EC6 Dual Function Pin Function Bank LVDS Dual Function VCCIO7 7 VREF2_7 PL2A 7 T VREF2_7 VREF1_7 PL2B 7 C VREF1_7 T PL7A 7 T 7 C PL7B 7 C 7 T PL8A 7 T PL8B 7 C PL8B 7 C PCLKT7_0 PL9A 7 T PCLKT7_0 PL9A 7 T PCLKT7_0 PCLKC7_0 PL9B 7 C PCLKC7_0 PL9B 7 C PCLKC7_0 6 XRES 6 XRES 6 - NC - VCC - NC - NC - GND - VCC - VCC - VCC - 14 TCK 6 TCK 6 TCK 6 15 GND - GND - GND - 16 TDI 6 TDI 6 TDI 6 17 TMS 6 TMS 6 TMS 6 18 TDO 6 TDO 6 TDO 6 19 VCCJ 6 VCCJ 6 VCCJ 6 20 PL7A 6 T LLM0_PLLT_IN_A PL11A 6 T LLM0_PLLT_IN_A PL20A 6 T LLM0_PLLT_IN_A 21 PL7B 6 C LLM0_PLLC_IN_A PL11B 6 C LLM0_PLLC_IN_A PL20B 6 C LLM0_PLLC_IN_A 22 PL8A 6 T LLM0_PLLT_FB_A PL12A 6 T LLM0_PLLT_FB_A PL21A 6 T LLM0_PLLT_FB_A 23 PL8B 6 C LLM0_PLLC_FB_A PL12B 6 C LLM0_PLLC_FB_A PL21B 6 C LLM0_PLLC_FB_A 24 VCCIO6 6 VCCIO6 6 VCCIO6 6 25 PL9A 6 T PL13A 6 T PL22A 6 T 26 PL9B 6 C PL13B 6 C PL22B 6 C 27 PL10A 6 T PL14A 6 T PL23A 6 T 28 GND6 6 GND6 6 GND6 6 29 PL10B 6 C PL14B 6 C PL23B 6 30 PL11A 6 T PL15A 6 T PL24A 6 T 31 PL11B 6 C PL15B 6 C PL24B 6 C 32 PL12A 6 T PL16A 6 T PL25A 6 T 33 PL12B 6 C PL16B 6 C PL25B 6 C 34 PL14A 6 T VREF1_6 PL18A 6 T VREF1_6 PL27A 6 T VREF1_6 35 PL14B 6 C VREF2_6 PL18B 6 C VREF2_6 PL27B 6 C VREF2_6 36 VCCIO6 6 VCCIO6 6 VCCIO6 6 37* GND5 GND6 - GND5 GND6 - GND5 GND6 - 38 VCCIO5 5 VCCIO5 5 VCCIO5 5 39 PB2A 5 T PB10A 5 T PB10A 5 T 40 PB2B 5 C PB10B 5 C PB10B 5 C 41 PB3A 5 T PB11A 5 T PB11A 5 T 42 PB3B 5 C PB11B 5 C PB11B 5 C 43 PB5B 5 PB13B 5 PB13B 5 44 VCCIO5 5 VCCIO5 5 VCCIO5 5 45 PB6A 5 T PB14A 5 T PB14A 5 T 46 PB6B 5 C PB14B 5 C PB14B 5 C 47 PB7A 5 T PB15A 5 T PB15A 5 T 48 PB7B 5 C PB15B 5 C PB15B 5 C 49 PB8A 5 T PB16A 5 T PB16A 5 T LDQS11 BDQS6 VREF2_5 4-11 LDQS15 BDQS14 VREF2_5 C LDQS24 BDQS14 VREF2_5 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFEC1, LFEC3, LFECP/EC6 Logic Signal Connections: 144 TQFP (Cont.) LFEC1 Pin Number Pin Function Bank LVDS LFEC3 Dual Function Pin Function Bank LVDS LFECP6/EC6 Dual Function Pin Function Bank LVDS Dual Function 50 PB8B 5 C VREF1_5 PB16B 5 C VREF1_5 PB16B 5 C VREF1_5 51 PB9A 5 T PCLKT5_0 PB17A 5 T PCLKT5_0 PB17A 5 T PCLKT5_0 52 GND5 5 GND5 5 GND5 5 53 PB9B 5 C PCLKC5_0 PB17B 5 C PCLKC5_0 PB17B 5 C PCLKC5_0 54 VCCAUX - VCCAUX - VCCAUX - 55 VCCIO4 4 VCCIO4 4 VCCIO4 4 56 PB10A 4 T WRITEN PB18A 4 T WRITEN PB18A 4 T WRITEN 57 PB10B 4 C CS1N PB18B 4 C CS1N PB18B 4 C CS1N 58 PB11A 4 T VREF1_4 PB19A 4 T VREF1_4 PB19A 4 T VREF1_4 59 PB11B 4 C CSN PB19B 4 C CSN PB19B 4 C CSN 60 PB12A 4 T VREF2_4 PB20A 4 T VREF2_4 PB20A 4 T VREF2_4 61 PB12B 4 C D0/SPID7 PB20B 4 C D0/SPID7 PB20B 4 C D0/SPID7 62 PB13A 4 T D2/SPID5 PB21A 4 T D2/SPID5 PB21A 4 T D2/SPID5 GND4 4 D1/SPID6 63 GND4 4 GND4 4 64 PB13B 4 C D1/SPID6 PB21B 4 C D1/SPID6 PB21B 4 C 65 PB14A 4 T BDQS14 PB22A 4 T BDQS22 PB22A 4 T BDQS22 66 PB14B 4 C D3/SPID4 PB22B 4 C D3/SPID4 PB22B 4 C D3/SPID4 67 PB15A 4 T 68 PB15B 4 C 69 PB16B 70 PB23A 4 T D4/SPID3 PB23B 4 C PB23A 4 T D4/SPID3 PB23B 4 C 4 D5/SPID2 PB24B 4 D5/SPID2 PB24B 4 PB17B 4 D6/SPID1 D5/SPID2 PB25B 4 D6/SPID1 PB25B 4 71 VCCIO4 D6/SPID1 4 VCCIO4 4 VCCIO4 4 72* GND3 GND4 - GND3 GND4 - GND3 GND4 - 73 VCCIO3 3 74 PR14A 3 75 PR12B 3 76 PR12A 77 PR11B 78 PR11A 3 T 79 PR10B 3 C VCCIO3 3 PR18A 3 C PR16B 3 3 T PR16A 3 C PR15B RDQS11 PR15A 3 T RLM0_PLLC_FB_A PR14B 3 C VREF1_3 D4/SPID3 VCCIO3 3 PR27A 3 C PR25B 3 3 T PR25A 3 T 3 C PR24B 3 C RDQS15 PR24A 3 T RDQS24 RLM0_PLLC_FB_A PR23B 3 C RLM0_PLLC_FB_A GND3 3 VREF1_3 VREF1_3 C 80 GND3 3 GND3 3 81 PR10A 3 T RLM0_PLLT_FB_A PR14A 3 T RLM0_PLLT_FB_A PR23A 3 T RLM0_PLLT_FB_A 82 PR9B 3 C RLM0_PLLC_IN_A PR13B 3 C RLM0_PLLC_IN_A PR22B 3 C RLM0_PLLC_IN_A 83 PR9A 3 T RLM0_PLLT_IN_A PR13A 3 T RLM0_PLLT_IN_A PR22A 3 T RLM0_PLLT_IN_A 84 VCCIO3 3 VCCIO3 3 VCCIO3 3 85 PR8B 3 C DI/CSSPIN PR12B 3 C DI/CSSPIN PR21B 3 C DI/CSSPIN 86 PR8A 3 T DOUT/CSON PR12A 3 T DOUT/CSON PR21A 3 T DOUT/CSON 87 PR7B 3 C BUSY/SISPI PR11B 3 C BUSY/SISPI PR20B 3 C BUSY/SISPI 88 PR7A 3 T D7/SPID0 PR11A 3 T D7/SPID0 PR20A 3 T D7/SPID0 89 CFG2 3 CFG2 3 CFG2 3 90 CFG1 3 CFG1 3 CFG1 3 91 CFG0 3 CFG0 3 CFG0 3 92 VCC - VCC - VCC - 93 PROGRAMN 3 PROGRAMN 3 PROGRAMN 3 94 CCLK 3 CCLK 3 CCLK 3 95 INITN 3 INITN 3 INITN 3 96 GND - GND - GND - 97 DONE 3 DONE 3 DONE 3 98 GND - GND - GND - 4-12 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFEC1, LFEC3, LFECP/EC6 Logic Signal Connections: 144 TQFP (Cont.) LFEC1 Pin Number Pin Function Bank LVDS LFEC3 Dual Function Pin Function Bank LVDS LFECP6/EC6 Dual Function Pin Function Bank LVDS VCC - VCC - 100 PR5B 2 C 101 PR5A 2 T PCLKC2_0 PR9B 2 C PCLKC2_0 PR9B 2 C PCLKC2_0 PCLKT2_0 PR9A 2 T PCLKT2_0 PR9A 2 T 102 PR4B 2 PCLKT2_0 C PR8B 2 C PR8B 2 C 103 PR4A 104 PR3B 2 T PR8A 2 T PR8A 2 T 2 C PR7B 2 C PR7B 2 C 105 PR3A 2 T 106 PR2B 2 C VREF1_2 PR7A 2 T PR7A 2 T PR2B 2 C VREF1_2 PR2B 2 C 107 PR2A 2 T VREF2_2 VREF1_2 PR2A 2 T VREF2_2 PR2A 2 T VREF2_2 108 VCCIO2 109* GND1 GND2 2 VCCIO2 2 VCCIO2 2 - GND1 GND2 - GND1 GND2 - 110 VCCIO1 1 VCCIO1 1 VCCIO1 1 111 PT17B 1 C PT25B 1 C PT25B 1 C 112 PT17A 1 T PT25A 1 T PT25A 1 T 113 PT15A 1 PT23A 1 PT23A 1 114 PT14B 1 C PT22B 1 C PT22B 1 115 PT14A 1 T PT22A 1 T PT22A 1 T 116 PT13B 1 C PT21B 1 C PT21B 1 C 117 GND1 1 GND1 1 GND1 1 118 PT13A 1 T PT21A 1 T PT21A 1 T 119 PT12B 1 C PT20B 1 C PT20B 1 C 120 PT12A 1 T PT20A 1 T PT20A 1 T 121 PT11B 1 C VREF2_1 PT19B 1 C VREF2_1 PT19B 1 C VREF2_1 122 PT11A 1 T VREF1_1 PT19A 1 T VREF1_1 PT19A 1 T VREF1_1 123 PT10B 1 C PT18B 1 C PT18B 1 C 124 PT10A 1 T PT18A 1 T PT18A 1 T 125 VCCIO1 1 VCCIO1 1 VCCIO1 1 126 VCCAUX - 127 PT9B 0 128 GND0 0 129 PT9A 0 T 130 PT8B 0 C 131 PT8A 0 T 132 PT7B 0 C 133 PT7A 0 T 134 PT6B 0 C 135 PT6A 0 T 136 VCCIO0 0 137 PT5B 0 C PT13B 0 C PT13B 0 138 PT5A 0 T PT13A 0 T PT13A 0 T 139 PT4B 0 C PT12B 0 C PT12B 0 C 140 PT4A 0 T PT12A 0 T PT12A 0 T 141 PT2B 0 C PT10B 0 C PT10B 0 C 142 PT2A 0 T PT10A 0 T PT10A 0 T 143 VCCIO0 0 VCCIO0 0 VCCIO0 0 144* GND0 GND7 - GND0 GND7 - GND0 GND7 - C TDQS14 VCC Dual Function 99 VCCAUX - PT17B 0 GND0 0 PCLKT0_0 PT17A 0 T VREF1_0 PT16B 0 C VREF2_0 PT16A 0 T PT15B 0 C PT15A 0 T PT14B 0 C PT14A 0 T VCCIO0 0 PCLKC0_0 TDQS6 *Double bonded to the pin. 4-13 C TDQS22 - VCCAUX - PT17B 0 GND0 0 PCLKT0_0 PT17A VREF1_0 PT16B VREF2_0 PT16A PCLKC0_0 TDQS14 C TDQS22 C PCLKC0_0 0 T PCLKT0_0 0 C VREF1_0 0 T VREF2_0 PT15B 0 C PT15A 0 T PT14B 0 C PT14A 0 T VCCIO0 0 C TDQS14 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFEC1, LFEC3 Logic Signal Connections: 208 PQFP LFEC1 Pin Number Pin Function 1* GND0 GND7 2 Bank LVDS LFEC3 Dual Function Pin Function Bank - GND0 GND7 LVDS Dual Function - VCCIO7 7 VCCIO7 7 3 PL2A 7 T VREF2_7 PL2A 7 T VREF2_7 4 PL2B 7 C VREF1_7 PL2B 7 C VREF1_7 5 NC - NC - 6 NC - NC - 7 NC - PL3B 7 8 NC - PL4A 7 T 9 NC - PL4B 7 C 10 NC - PL5A 7 T 11 NC - PL5B 7 C 12 NC - PL6A 7 T 13 NC - VCCIO7 7 14 NC - PL6B 7 15 PL3A 7 T PL7A 7 T 16 PL3B 7 C PL7B 7 C 17 PL4A 7 T PL8A 7 T 18 NC - NC - 19 PL4B 7 C PL8B 7 C 20 PL5A 7 T PCLKT7_0 PL9A 7 T PCLKT7_0 21 PL5B 7 C PCLKC7_0 PL9B 7 C PCLKC7_0 22 NC - VCCAUX - 23 XRES 6 XRES 6 24 NC - NC - 25 NC - NC - 26 VCC - VCC - 27 TCK 6 TCK 6 28 GND - GND - 29 TDI 6 TDI 6 30 TMS 6 TMS 6 LDQS6 C 31 TDO 6 TDO 6 32 VCCJ 6 VCCJ 6 33 PL7A 6 T LLM0_PLLT_IN_A PL11A 6 T LLM0_PLLT_IN_A 34 PL7B 6 C LLM0_PLLC_IN_A PL11B 6 C LLM0_PLLC_IN_A 35 PL8A 6 T LLM0_PLLT_FB_A PL12A 6 T LLM0_PLLT_FB_A 36 PL8B 6 C LLM0_PLLC_FB_A PL12B 6 C LLM0_PLLC_FB_A 37 VCCIO6 6 VCCIO6 6 38 PL9A 6 T PL13A 6 T 39 PL9B 6 C PL13B 6 C 40 PL10A 6 T PL14A 6 T GND6 6 C PL14B 6 41 GND6 6 42 PL10B 6 4-14 C Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFEC1, LFEC3 Logic Signal Connections: 208 PQFP (Cont.) LFEC1 LFEC3 Pin Number Pin Function Bank LVDS Dual Function Pin Function Bank LVDS Dual Function 43 PL11A 44 PL11B 6 T LDQS11 PL15A 6 C PL15B 6 T LDQS15 6 C 45 PL12A 46 PL12B 6 T PL16A 6 T 6 C PL16B 6 C 47 PL13A 48 PL13B 6 T PL17A 6 T 6 C PL17B 6 C 49 PL14A 6 T VREF1_6 PL18A 6 T VREF1_6 50 PL14B 6 C VREF2_6 PL18B 6 C VREF2_6 51 VCCIO6 6 VCCIO6 6 52* GND5 GND6 - GND5 GND6 - 53 VCCIO5 5 VCCIO5 5 54 NC - PB2A 5 T 55 NC - PB2B 5 C 56 NC - PB3A 5 T 57 NC - PB3B 5 C 58 NC - PB4A 5 T 59 NC - PB4B 5 C 60 NC - PB5A 5 T 61 NC - PB5B 5 C 62 NC - PB6A 5 T 63 NC - PB6B 5 C 64 NC - VCCIO5 5 65 PB2A 5 T PB10A 5 T 66 PB2B 5 C PB10B 5 C 67 PB3A 5 T PB11A 5 T 68 PB3B 5 C PB11B 5 C 69 PB4A 5 T PB12A 5 T 70 PB4B 5 C PB12B 5 C 71 PB5A 5 T PB13A 5 T GND5 5 C PB13B 5 72 NC - 73 PB5B 5 74 VCCIO5 5 75 PB6A 5 T 76 PB6B 5 77 PB7A 5 78 PB7B 5 C 79 PB8A 5 T 80 PB8B 5 81 PB9A 5 82 GND5 5 83 PB9B 5 84 VCCAUX - C VCCIO5 5 PB14A 5 T C PB14B 5 C T PB15A 5 T BDQS6 BDQS6 BDQS14 PB15B 5 C VREF2_5 PB16A 5 T C VREF1_5 PB16B 5 C VREF1_5 T PCLKT5_0 PB17A 5 T PCLKT5_0 GND5 5 C PCLKC5_0 PB17B 5 C PCLKC5_0 VCCAUX - 4-15 VREF2_5 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFEC1, LFEC3 Logic Signal Connections: 208 PQFP (Cont.) LFEC1 Pin Number Pin Function Bank 85 VCCIO4 4 86 PB10A 87 88 LFEC3 LVDS Dual Function Pin Function Bank LVDS Dual Function VCCIO4 4 4 T WRITEN PB18A 4 T WRITEN PB10B 4 C CS1N PB11A 4 T VREF1_4 PB18B 4 C CS1N PB19A 4 T VREF1_4 89 PB11B 4 C 90 PB12A 4 T CSN PB19B 4 C CSN VREF2_4 PB20A 4 T VREF2_4 91 PB12B 4 C 92 PB13A 4 T D0/SPID7 PB20B 4 C D0/SPID7 D2/SPID5 PB21A 4 T D2/SPID5 C GND4 4 D1/SPID6 PB21B 4 C D1/SPID6 93 GND4 4 94 PB13B 4 95 PB14A 4 T BDQS14 PB22A 4 T BDQS22 96 PB14B 4 C D3/SPID4 PB22B 4 C D3/SPID4 97 PB15A 4 T PB23A 4 T 98 PB15B 4 C PB23B 4 C PB24A 4 T PB24B 4 C PB25A 4 T PB25B 4 C D6/SPID1 C VREF2_3 VREF1_3 99 PB16A 4 T 100 PB16B 4 C 101 PB17A 4 T 102 PB17B 4 C D4/SPID3 D5/SPID2 D6/SPID1 103 NC - NC - 104 VCCIO4 4 VCCIO4 4 105* GND3 GND4 - GND3 GND4 - 106 VCCIO3 3 107 PR14B 3 108 PR14A 109 PR13B 110 PR13A 111 PR12B 112 PR12A 113 PR11B 114 PR11A 3 T 115 PR10B 3 C VCCIO3 3 PR18B 3 D4/SPID3 D5/SPID2 C VREF2_3 3 T VREF1_3 PR18A 3 T 3 C PR17B 3 C 3 T PR17A 3 T 3 C PR16B 3 C 3 T PR16A 3 T 3 C PR15B 3 C RDQS11 PR15A 3 T RDQS15 RLM0_PLLC_FB_A PR14B 3 C RLM0_PLLC_FB_A 116 GND3 3 GND3 3 117 PR10A 3 T RLM0_PLLT_FB_A PR14A 3 T RLM0_PLLT_FB_A 118 PR9B 3 C RLM0_PLLC_IN_A PR13B 3 C RLM0_PLLC_IN_A 119 PR9A 3 T RLM0_PLLT_IN_A PR13A 3 T RLM0_PLLT_IN_A 120 VCCIO3 3 121 PR8B 3 C DI/CSSPIN C DI/CSSPIN 122 PR8A 3 T DOUT/CSON PR12A 3 T DOUT/CSON 123 PR7B 3 C BUSY/SISPI PR11B 3 C BUSY/SISPI 124 PR7A 3 T D7/SPID0 PR11A 3 T D7/SPID0 125 CFG2 3 CFG2 3 126 CFG1 3 CFG1 3 4-16 VCCIO3 3 PR12B 3 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFEC1, LFEC3 Logic Signal Connections: 208 PQFP (Cont.) LFEC1 Pin Number Pin Function Bank 127 CFG0 128 VCC 129 130 LVDS LFEC3 Pin Function Bank 3 CFG0 3 - VCC - PROGRAMN 3 PROGRAMN 3 CCLK 3 CCLK 3 131 INITN 3 INITN 3 132 GND - GND - 133 DONE 3 DONE 3 134 GND - GND - 135 VCC - VCC - 136 NC - VCCAUX - 137 PR5B 2 PR9B 2 138 NC - GND2 2 139 PR5A 2 T PR9A 140 PR4B 2 C PR8B 141 PR4A 2 T PR8A 2 T 142 PR3B 2 C PR7B 2 C 143 PR3A 2 T PR7A 2 T 144 NC - PR6B 2 C 145 NC - VCCIO2 2 146 NC - PR6A 2 T 147 NC - PR5B 2 C 148 NC - PR5A 2 T 149 NC - PR4B 2 C 150 NC - PR4A 2 T 151 NC - NC - 152 NC - NC - 153 PR2B 2 C VREF1_2 PR2B 2 C VREF1_2 154 PR2A 2 T VREF2_2 PR2A 2 T VREF2_2 155 VCCIO2 2 VCCIO2 2 156* GND1 GND2 - GND1 GND2 - 157 VCCIO1 1 VCCIO1 1 C 158 NC - 159 PT17B 1 160 PT17A 161 PT16B 162 PT16A 163 PT15B 164 PT15A 165 PT14B 166 PT14A 1 T 167 PT13B 1 C 168 GND1 1 Dual Function PCLKC2_0 PCLKT2_0 LVDS Dual Function C PCLKC2_0 2 T PCLKT2_0 2 C NC - C PT25B 1 1 T PT25A 1 T 1 C PT24B 1 C 1 T PT24A 1 T 1 C PT23B 1 C 1 T PT23A 1 T 1 C PT22B 1 C TDQS14 4-17 RDQS6 C PT22A 1 T PT21B 1 C GND1 1 TDQS22 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFEC1, LFEC3 Logic Signal Connections: 208 PQFP (Cont.) LFEC1 LVDS LFEC3 Pin Number Pin Function Bank Dual Function Pin Function Bank 169 PT13A 1 170 PT12B 1 171 PT12A 1 T 172 PT11B 1 C VREF2_1 173 PT11A 1 T VREF1_1 174 PT10B 1 C 175 PT10A 1 T 176 VCCIO1 1 177 VCCAUX - 178 PT9B 0 179 GND0 0 180 PT9A 181 182 LVDS T PT21A 1 T C PT20B 1 C PT20A 1 T PT19B 1 C VREF2_1 VREF1_1 PT19A 1 T PT18B 1 C PT18A 1 T VCCIO1 1 VCCAUX - C PCLKC0_0 PT17B 0 GND0 0 0 T PCLKT0_0 PT17A PT8B 0 C VREF1_0 PT8A 0 T VREF2_0 183 PT7B 0 184 PT7A 0 185 PT6B 0 C 186 PT6A 0 T 187 VCCIO0 0 188 PT5B 0 Dual Function C PCLKC0_0 0 T PCLKT0_0 PT16B 0 C VREF1_0 PT16A 0 T VREF2_0 C PT15B 0 C T PT15A 0 T PT14B 0 C PT14A 0 T TDQS6 VCCIO0 0 C PT13B 0 C 189 NC - GND0 0 190 PT5A 0 T PT13A 0 T 191 PT4B 0 C PT12B 0 C 192 PT4A 0 T PT12A 0 T 193 PT3B 0 C PT11B 0 C 194 PT3A 0 T PT11A 0 T 195 PT2B 0 C PT10B 0 C 196 PT2A 0 T PT10A 0 T 197 NC - VCCIO0 0 198 NC - PT6B 0 199 NC - PT6A 0 T 200 NC - PT5B 0 C 201 NC - PT5A 0 T 202 NC - PT4B 0 C 203 NC - PT4A 0 T 204 NC - PT3B 0 C 205 NC - PT3A 0 T 206 NC - PT2B 0 C T 207 NC - PT2A 0 208 VCCIO0 0 VCCIO0 0 * Double bonded to the pin. 4-18 TDQS14 C TDQS6 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC6, LFECP/EC10 Logic Signal Connections: 208 PQFP LFECP6/LFEC6 Pin Number Pin Function 1* GND0 GND7 2 Bank LVDS LFECP10/LFEC10 Dual Function Pin Function Bank - GND0 GND7 LVDS Dual Function - VCCIO7 7 VCCIO7 7 3 PL2A 7 T VREF2_7 PL2A 4 PL2B 7 C VREF1_7 PL2B 7 T VREF2_7 7 C VREF1_7 5 NC - VCC - 6 NC - GND - 7 PL3B 7 PL12B 7 8 PL4A 7 T PL13A 7 T 9 PL4B 7 C PL13B 7 C 10 PL5A 7 T PL14A 7 T 11 PL5B 7 C PL14B 7 C 12 PL6A 7 T PL15A 7 T 13 VCCIO7 7 14 PL6B 7 15 PL7A 16 PL7B 17 18 19 PL8B 7 C 20 PL9A 7 T PCLKT7_0 21 PL9B 7 C PCLKC7_0 22 VCCAUX - 23 XRES 6 XRES 6 24 VCC - VCC - 25 GND - GND - 26 VCC - VCC - 27 TCK 6 TCK 6 28 GND - GND - 29 TDI 6 TDI 6 30 TMS 6 TMS 6 LDQS6 LDQS15 VCCIO7 7 C PL15B 7 7 T PL16A 7 T 7 C PL16B 7 C PL8A 7 T PL17A 7 T GND7 7 GND7 7 PL17B 7 C PL18A 7 T PCLKT7_0 PL18B 7 C PCLKC7_0 VCCAUX - C 31 TDO 6 TDO 6 32 VCCJ 6 VCCJ 6 33 PL20A 6 T LLM0_PLLT_IN_A PL29A 6 T LLM0_PLLT_IN_A 34 PL20B 6 C LLM0_PLLC_IN_A PL29B 6 C LLM0_PLLC_IN_A 35 PL21A 6 T LLM0_PLLT_FB_A PL30A 6 T LLM0_PLLT_FB_A 36 PL21B 6 C LLM0_PLLC_FB_A PL30B 6 C LLM0_PLLC_FB_A 37 VCCIO6 6 VCCIO6 6 38 PL22A 6 T PL31A 6 T 39 PL22B 6 C PL31B 6 C 40 PL23A 6 T PL32A 6 T GND6 6 C PL32B 6 41 GND6 6 42 PL23B 6 4-19 C Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC6, LFECP/EC10 Logic Signal Connections: 208 PQFP (Cont.) LFECP6/LFEC6 LFECP10/LFEC10 Pin Number Pin Function Bank LVDS Dual Function 43 PL24A 44 PL24B 6 T LDQS24 PL33A 6 C PL33B 45 PL25A 46 PL25B 6 T PL34A 6 T 6 C PL34B 6 C 47 PL26A 48 PL26B 6 T PL35A 6 T 6 C PL35B 6 C 49 PL27A 6 T VREF1_6 PL36A 6 T VREF1_6 50 PL27B 6 C VREF2_6 PL36B 6 C VREF2_6 51 VCCIO6 6 VCCIO6 6 52* GND5 GND6 - GND5 GND6 - 53 VCCIO5 5 VCCIO5 5 54 PB2A 5 T PB2A 5 T 55 PB2B 5 C PB2B 5 C 56 PB3A 5 T PB3A 5 T 57 PB3B 5 C PB3B 5 C 58 PB4A 5 T PB4A 5 T 59 PB4B 5 C PB4B 5 C 60 PB5A 5 T PB5A 5 T 61 PB5B 5 C PB5B 5 C 62 PB6A 5 T 63 PB6B 5 C 64 VCCIO5 5 VCCIO5 5 65 PB10A 5 T PB18A 5 T 66 PB10B 5 C PB18B 5 C 67 PB11A 5 T PB19A 5 T 68 PB11B 5 C PB19B 5 C 69 PB12A 5 T PB20A 5 T 70 PB12B 5 C PB20B 5 C 71 PB13A 5 T PB21A 5 T GND5 5 C PB21B 5 72 GND5 5 73 PB13B 5 74 VCCIO5 5 75 PB14A 5 T 76 PB14B 5 77 PB15A 5 78 PB15B 5 C 79 PB16A 5 T 80 PB16B 5 81 PB17A 5 82 GND5 5 83 PB17B 5 84 VCCAUX - BDQS6 Pin Function Bank LVDS Dual Function 6 T LDQS33 6 C PB6A 5 T PB6B 5 C C VCCIO5 5 PB22A 5 T C PB22B 5 C T PB23A 5 T BDQS14 BDQS6 BDQS22 PB23B 5 C VREF2_5 PB24A 5 T C VREF1_5 PB24B 5 C VREF1_5 T PCLKT5_0 PB25A 5 T PCLKT5_0 GND5 5 C PCLKC5_0 PB25B 5 C PCLKC5_0 VCCAUX - 4-20 VREF2_5 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC6, LFECP/EC10 Logic Signal Connections: 208 PQFP (Cont.) LFECP6/LFEC6 Pin Number Pin Function Bank 85 VCCIO4 4 86 PB18A 87 88 LFECP10/LFEC10 LVDS Dual Function Pin Function Bank LVDS Dual Function VCCIO4 4 4 T WRITEN PB26A 4 T WRITEN PB18B 4 C CS1N PB19A 4 T VREF1_4 PB26B 4 C CS1N PB27A 4 T VREF1_4 89 PB19B 4 C 90 PB20A 4 T CSN PB27B 4 C CSN VREF2_4 PB28A 4 T VREF2_4 91 PB20B 4 C 92 PB21A 4 T D0/SPID7 PB28B 4 C D0/SPID7 D2/SPID5 PB29A 4 T D2/SPID5 C GND4 4 D1/SPID6 PB29B 4 C D1/SPID6 93 GND4 4 94 PB21B 4 95 PB22A 4 T BDQS22 PB30A 4 T BDQS30 96 PB22B 4 C D3/SPID4 PB30B 4 C D3/SPID4 97 PB23A 4 T PB31A 4 T 98 PB23B 4 C PB31B 4 C PB32A 4 T PB32B 4 C PB33A 4 T PB33B 4 C D6/SPID1 C VREF2_3 VREF1_3 D4/SPID3 99 PB24A 4 T 100 PB24B 4 C 101 PB25A 4 T 102 PB25B 4 C 103 PB33A 4 PB41A 4 104 VCCIO4 4 VCCIO4 4 105* GND3 GND4 - GND3 GND4 - 106 VCCIO3 3 107 PR27B 3 108 PR27A 109 PR26B 110 PR26A 111 PR25B 112 PR25A 113 PR24B 114 PR24A 3 T 115 PR23B 3 C D5/SPID2 D6/SPID1 VCCIO3 3 PR36B 3 D4/SPID3 D5/SPID2 C VREF2_3 3 T VREF1_3 PR36A 3 T 3 C PR35B 3 C 3 T PR35A 3 T 3 C PR34B 3 C 3 T PR34A 3 T 3 C PR33B 3 C RDQS24 PR33A 3 T RDQS33 RLM0_PLLC_FB_A PR32B 3 C RLM0_PLLC_FB_A 116 GND3 3 GND3 3 117 PR23A 3 T RLM0_PLLT_FB_A PR32A 3 T RLM0_PLLT_FB_A 118 PR22B 3 C RLM0_PLLC_IN_A PR31B 3 C RLM0_PLLC_IN_A 119 PR22A 3 T RLM0_PLLT_IN_A PR31A 3 T RLM0_PLLT_IN_A 120 VCCIO3 3 121 PR21B 3 C DI/CSSPIN C DI/CSSPIN 122 PR21A 3 T DOUT/CSON PR30A 3 T DOUT/CSON 123 PR20B 3 C BUSY/SISPI PR29B 3 C BUSY/SISPI 124 PR20A 3 T D7/SPID0 PR29A 3 T D7/SPID0 125 CFG2 3 CFG2 3 126 CFG1 3 CFG1 3 4-21 VCCIO3 3 PR30B 3 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC6, LFECP/EC10 Logic Signal Connections: 208 PQFP (Cont.) LFECP6/LFEC6 Pin Number Pin Function Bank 127 CFG0 128 VCC 129 130 LVDS LFECP10/LFEC10 Pin Function Bank 3 CFG0 3 - VCC - PROGRAMN 3 PROGRAMN 3 CCLK 3 CCLK 3 131 INITN 3 INITN 3 132 GND - GND - 133 DONE 3 DONE 3 134 GND - GND - 135 VCC - VCC - 136 VCCAUX - VCCAUX - 137 PR9B 2 138 GND2 2 139 PR9A 2 T PR18A 140 PR8B 2 C PR17B 141 PR8A 2 T PR17A 2 T 142 PR7B 2 C PR16B 2 C 143 PR7A 2 T PR16A 2 T 144 PR6B 2 C PR15B 2 C 145 VCCIO2 2 146 PR6A 2 T 147 PR5B 2 148 PR5A 2 149 PR4B 150 PR4A 151 NC - GND - 152 NC - VCC - 153 PR2B 2 C VREF1_2 PR2B 2 C VREF1_2 154 PR2A 2 T VREF2_2 PR2A 2 T VREF2_2 155 VCCIO2 2 VCCIO2 2 156* GND1 GND2 - GND1 GND2 - 157 VCCIO1 1 VCCIO1 1 158 PT33A 1 159 PT25B 1 160 PT25A 161 PT24B 162 PT24A 163 PT23B 164 PT23A 165 PT22B 166 PT22A 1 T 167 PT21B 1 C 168 GND1 1 C Dual Function PCLKC2_0 PCLKT2_0 LVDS Dual Function C PCLKC2_0 2 T PCLKT2_0 2 C PR18B 2 GND2 2 VCCIO2 2 PR15A 2 T C PR14B 2 C T PR14A 2 T 2 C PR13B 2 C 2 T PR13A 2 T RDQS6 PT41A 1 C PT33B 1 1 T PT33A 1 T 1 C PT32B 1 C 1 T PT32A 1 T 1 C PT31B 1 C 1 T PT31A 1 T 1 C PT30B 1 C TDQS22 4-22 RDQS15 C PT30A 1 T PT29B 1 C GND1 1 TDQS30 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC6, LFECP/EC10 Logic Signal Connections: 208 PQFP (Cont.) LFECP6/LFEC6 LVDS LFECP10/LFEC10 Pin Number Pin Function Bank Dual Function Pin Function Bank 169 PT21A 1 170 PT20B 1 171 PT20A 1 T 172 PT19B 1 C VREF2_1 173 PT19A 1 T VREF1_1 174 PT18B 1 C 175 PT18A 1 T 176 VCCIO1 1 177 VCCAUX - 178 PT17B 0 179 GND0 0 180 PT17A 181 182 LVDS T PT29A 1 T C PT28B 1 C PT28A 1 T PT27B 1 C VREF2_1 VREF1_1 PT27A 1 T PT26B 1 C PT26A 1 T VCCIO1 1 VCCAUX - C PCLKC0_0 PT25B 0 GND0 0 0 T PCLKT0_0 PT25A PT16B 0 C VREF1_0 PT16A 0 T VREF2_0 183 PT15B 0 184 PT15A 0 185 PT14B 0 C 186 PT14A 0 T 187 VCCIO0 0 188 PT13B 0 189 GND0 0 190 PT13A 191 192 Dual Function C PCLKC0_0 0 T PCLKT0_0 PT24B 0 C VREF1_0 PT24A 0 T VREF2_0 C PT23B 0 C T PT23A 0 T PT22B 0 C PT22A 0 T TDQS14 VCCIO0 0 C PT21B 0 GND0 0 0 T PT21A 0 T PT12B 0 C PT20B 0 C PT12A 0 T PT20A 0 T 193 PT11B 0 C PT19B 0 C 194 PT11A 0 T PT19A 0 T 195 PT10B 0 C PT18B 0 C 196 PT10A 0 T PT18A 0 T 197 VCCIO0 0 198 PT6B 0 199 PT6A 0 T PT6A 0 T 200 PT5B 0 C PT5B 0 C 201 PT5A 0 T PT5A 0 T 202 PT4B 0 C PT4B 0 C 203 PT4A 0 T PT4A 0 T 204 PT3B 0 C PT3B 0 C 205 PT3A 0 T PT3A 0 T 206 PT2B 0 C PT2B 0 C 207 PT2A 0 T PT2A 0 T 208 VCCIO0 0 VCCIO0 0 C TDQS6 *Double bonded to the pin. 4-23 VCCIO0 0 PT6B 0 TDQS22 C C TDQS6 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA LFEC3 LFECP6/LFEC6 Ball Number Ball Function Bank GND GND7 7 D4 PL2A 7 T VREF2_7 PL2A 7 T VREF2_7 D3 PL2B 7 C VREF1_7 PL2B 7 C VREF1_7 C3 PL3A 7 T PL3A 7 T C2 PL3B 7 C PL3B 7 C LVDS Dual Function Ball Function Bank GND7 7 LVDS Dual Function B1 PL4A 7 T PL4A 7 T C1 PL4B 7 C PL4B 7 C E3 PL5A 7 T PL5A 7 T E4 PL5B 7 C PL5B 7 C F4 PL6A 7 T PL6A 7 T F5 PL6B 7 C PL6B 7 C G4 PL7A 7 T PL7A 7 T G3 PL7B 7 C PL7B 7 C D2 PL8A 7 T PL8A 7 T D1 PL8B 7 C PL8B 7 C E1 PL9A 7 T PL9A 7 T PCLKT7_0 GND GND7 7 GND7 7 C PCLKC7_0 C LDQS6 PCLKT7_0 E2 PL9B 7 PL9B 7 F3 XRES 6 PCLKC7_0 XRES 6 G5 NC - PL11A 6 T H5 NC - PL11B 6 C F2 NC - PL12A 6 T F1 NC - PL12B 6 C H4 NC - PL13A 6 T H3 NC - PL13B 6 C G2 NC - PL14A 6 T - - - GND6 6 G1 NC - PL14B 6 C J4 NC - PL15A 6 T J3 NC - PL15B 6 C J5 NC - PL16A 6 T K5 NC - PL16B 6 C H2 NC - PL17A 6 T H1 NC - PL17B 6 C J2 NC - PL18A 6 T - - - GND6 6 J1 NC - PL18B 6 K4 TCK 6 TCK 6 K3 TDI 6 TDI 6 L3 TMS 6 TMS 6 L5 TDO 6 TDO 6 L4 VCCJ 6 VCCJ 6 4-24 C LDQS6 LDQS15 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA (Cont.) LFEC3 LFECP6/LFEC6 Ball Number Ball Function Bank K2 PL11A 6 T LLM0_PLLT_IN_A PL20A 6 T LLM0_PLLT_IN_A K1 PL11B 6 C LLM0_PLLC_IN_A PL20B 6 C LLM0_PLLC_IN_A L2 PL12A 6 T LLM0_PLLT_FB_A PL21A 6 T LLM0_PLLT_FB_A L1 PL12B 6 C LLM0_PLLC_FB_A PL21B 6 C LLM0_PLLC_FB_A M2 PL13A 6 T PL22A 6 T M1 PL13B 6 C PL22B 6 C T PL23A 6 T GND6 6 PL23B 6 C PL24A 6 T LVDS N1 PL14A 6 GND GND6 6 N2 PL14B 6 C M4 PL15A 6 T Dual Function LDQS15 Ball Function Bank LVDS M3 PL15B 6 C PL24B 6 C P1 PL16A 6 T PL25A 6 T R1 PL16B 6 C PL25B 6 C P2 PL17A 6 T PL26A 6 T Dual Function LDQS24 P3 PL17B 6 C PL26B 6 C N3 PL18A 6 T VREF1_6 PL27A 6 T VREF1_6 C VREF2_6 PL27B 6 C VREF2_6 GND6 6 N4 PL18B 6 GND GND6 6 GND GND5 5 P4 PB2A 5 T GND5 5 PB2A 5 T N5 PB2B 5 C PB2B 5 C P5 PB3A 5 T PB3A 5 T P6 PB3B 5 C PB3B 5 C R4 PB4A 5 T PB4A 5 T R3 PB4B 5 C PB4B 5 C T2 PB5A 5 T PB5A 5 T PB5B 5 C PB6A 5 T T3 PB5B 5 C R5 PB6A 5 T R6 PB6B 5 C PB6B 5 C T4 PB7A 5 T PB7A 5 T BDQS6 T5 PB7B 5 C PB7B 5 C N6 PB8A 5 T PB8A 5 T M6 PB8B 5 C PB8B 5 C T6 PB9A 5 T PB9A 5 T GND GND5 5 T7 PB9B 5 GND5 5 C PB9B 5 C P7 PB10A 5 T PB10A 5 T N7 PB10B 5 C PB10B 5 C R7 PB11A 5 T PB11A 5 T R8 PB11B 5 C PB11B 5 C M7 PB12A 5 T PB12A 5 T M8 PB12B 5 C PB12B 5 C T8 PB13A 5 T PB13A 5 T 4-25 BDQS6 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA (Cont.) Ball Number LFEC3 Ball Function Bank GND GND5 5 T9 PB13B 5 LVDS LFECP6/LFEC6 Dual Function C BDQS14 Ball Function Bank GND5 5 PB13B 5 LVDS Dual Function C P8 PB14A 5 T PB14A 5 T N8 PB14B 5 C PB14B 5 C R9 PB15A 5 T PB15A 5 T R10 PB15B 5 C PB15B 5 C BDQS14 P9 PB16A 5 T VREF2_5 PB16A 5 T VREF2_5 N9 PB16B 5 C VREF1_5 PB16B 5 C VREF1_5 T PCLKT5_0 PB17A 5 T PCLKT5_0 GND5 5 T10 PB17A 5 GND GND5 5 T11 PB17B 5 C PCLKC5_0 PB17B 5 C PCLKC5_0 T12 PB18A 4 T WRITEN PB18A 4 T WRITEN T13 PB18B 4 C CS1N PB18B 4 C CS1N P10 PB19A 4 T VREF1_4 PB19A 4 T VREF1_4 N10 PB19B 4 C CSN PB19B 4 C CSN T14 PB20A 4 T VREF2_4 PB20A 4 T VREF2_4 T15 PB20B 4 C D0/SPID7 PB20B 4 C D0/SPID7 M10 PB21A 4 T D2/SPID5 PB21A 4 T D2/SPID5 GND4 4 C D1/SPID6 PB21B 4 C D1/SPID6 GND GND4 4 M11 PB21B 4 R11 PB22A 4 T BDQS22 PB22A 4 T BDQS22 P11 PB22B 4 C D3/SPID4 PB22B 4 C D3/SPID4 R13 PB23A 4 T PB23A 4 T R14 PB23B 4 C PB23B 4 C P12 PB24A 4 T PB24A 4 T P13 PB24B 4 C PB24B 4 C N11 PB25A 4 T PB25A 4 T - - - GND4 4 N12 PB25B 4 PB25B 4 R12 NC - PB26A 4 GND GND4 4 GND4 4 - - - GND4 4 GND3 3 PR27B 3 GND GND3 3 N13 PR18B 3 N14 PR18A P14 PR17B C D4/SPID3 D5/SPID2 D6/SPID1 D4/SPID3 D5/SPID2 C D6/SPID1 C VREF2_3 VREF1_3 C VREF2_3 3 T VREF1_3 PR27A 3 T 3 C PR26B 3 C P15 PR17A 3 T PR26A 3 T R15 PR16B 3 C PR25B 3 C R16 PR16A 3 T PR25A 3 T M13 PR15B 3 C PR24B 3 C M14 PR15A 3 T RDQS15 PR24A 3 T RDQS24 P16 PR14B 3 C RLM0_PLLC_FB_A PR23B 3 C RLM0_PLLC_FB_A GND GND3 3 GND3 3 4-26 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA (Cont.) LFEC3 Ball Number Ball Function Bank N16 PR14A N15 PR13B M15 PR13A M16 PR12B LFECP6/LFEC6 LVDS Dual Function Ball Function 3 T RLM0_PLLT_FB_A PR23A 3 C RLM0_PLLC_IN_A PR22B 3 T RLM0_PLLT_IN_A PR22A 3 C DI/CSSPIN PR21B Bank LVDS Dual Function 3 T RLM0_PLLT_FB_A 3 C RLM0_PLLC_IN_A 3 T RLM0_PLLT_IN_A 3 C DI/CSSPIN L16 PR12A 3 T DOUT/CSON PR21A 3 T DOUT/CSON K16 PR11B 3 C BUSY/SISPI PR20B 3 C BUSY/SISPI T D7/SPID0 T D7/SPID0 J16 PR11A 3 PR20A 3 L12 CFG2 3 CFG2 3 L14 CFG1 3 CFG1 3 L13 CFG0 3 CFG0 3 K13 PROGRAMN 3 PROGRAMN 3 L15 CCLK 3 CCLK 3 K15 INITN 3 INITN 3 K14 DONE 3 DONE 3 - - GND3 3 H16 NC - PR18B 3 H15 NC - PR18A 3 T G16 NC - PR17B 3 C C G15 NC - PR17A 3 T K12 NC - PR16B 3 C J12 NC - PR16A 3 T J14 NC - PR15B 3 C J15 NC - PR15A 3 T F16 NC - PR14B 3 C - - - GND3 3 F15 NC - PR14A 3 T J13 NC - PR13B 3 C H13 NC - PR13A 3 T RDQS15 H14 NC - PR12B 3 C G14 NC - PR12A 3 T E16 NC - PR11B 3 C E15 NC - PR11A 3 T PR9B 2 C PCLKC2_0 PCLKT2_0 H12 PR9B 2 GND GND2 2 C PCLKC2_0 G12 PR9A 2 T PR9A 2 T G13 PR8B 2 C PR8B 2 C F13 PR8A 2 T PR8A 2 T F12 PR7B 2 C PR7B 2 C GND2 PCLKT2_0 E13 PR7A 2 T PR7A 2 T D16 PR6B 2 C PR6B 2 C D15 PR6A 2 T PR6A 2 T F14 PR5B 2 C PR5B 2 C E14 PR5A 2 T PR5A 2 T RDQS6 4-27 RDQS6 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA (Cont.) LFEC3 Ball Number Ball Function Bank LVDS C16 PR4B 2 B16 PR4A 2 C15 PR3B C14 PR3A D14 D13 LFECP6/LFEC6 Dual Function Ball Function Bank LVDS C PR4B 2 C T PR4A 2 T 2 C PR3B 2 C 2 T PR3A 2 T PR2B 2 C VREF1_2 PR2B 2 C VREF1_2 PR2A 2 T VREF2_2 PR2A 2 T VREF2_2 GND GND2 2 GND2 2 GND GND1 1 GND1 1 - - - GND1 1 B13 NC - PT26B 1 C13 NC - C12 PT25B 1 C PT26A 1 T C PT25B 1 C - - - GND1 1 D12 PT25A 1 T PT25A 1 T A15 PT24B 1 C PT24B 1 C B14 PT24A 1 T PT24A 1 T D11 PT23B 1 C PT23B 1 C C11 PT23A 1 T PT23A 1 T E10 PT22B 1 C PT22B 1 C E11 PT22A 1 T PT22A 1 T C PT21B 1 C GND1 1 TDQS22 Dual Function TDQS22 A14 PT21B 1 GND GND1 1 A13 PT21A 1 T PT21A 1 T D10 PT20B 1 C PT20B 1 C PT20A 1 T PT19B 1 C VREF2_1 VREF1_1 C10 PT20A 1 T A12 PT19B 1 C VREF2_1 B12 PT19A 1 T VREF1_1 A11 PT18B 1 C B11 PT18A 1 T A10 PT17B 0 C PCLKC0_0 PT19A 1 T PT18B 1 C PT18A 1 T PT17B 0 C PCLKC0_0 GND GND0 0 GND0 0 B10 PT17A 0 T PCLKT0_0 PT17A 0 T PCLKT0_0 C9 PT16B 0 C VREF1_0 PT16B 0 C VREF1_0 B9 PT16A 0 T VREF2_0 PT16A 0 T VREF2_0 E9 PT15B 0 C PT15B 0 C D9 PT15A 0 T PT15A 0 T D8 PT14B 0 C PT14B 0 C C8 PT14A 0 T PT14A 0 T C PT13B 0 C GND0 0 TDQS14 A9 PT13B 0 GND GND0 0 A8 PT13A 0 T PT13A 0 T B8 PT12B 0 C PT12B 0 C B7 PT12A 0 T PT12A 0 T 4-28 TDQS14 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA (Cont.) LFEC3 Ball Number Ball Function Bank LVDS D7 PT11B 0 C7 PT11A 0 A7 PT10B A6 PT10A LFECP6/LFEC6 Ball Function Bank LVDS C PT11B 0 C T PT11A 0 T 0 C PT10B 0 C 0 T PT10A 0 T C C E7 PT9B 0 GND GND0 0 E6 PT9A 0 D6 PT8B 0 Dual Function PT9B 0 GND0 0 T PT9A 0 T C PT8B 0 C C6 PT8A 0 T PT8A 0 T B6 PT7B 0 C PT7B 0 C B5 PT7A 0 T PT7A 0 T A5 PT6B 0 C PT6B 0 C A4 PT6A 0 T PT6A 0 T A3 PT5B 0 C PT5B 0 C A2 PT5A 0 T PT5A 0 T B2 PT4B 0 C PT4B 0 C TDQS6 B3 PT4A 0 T PT4A 0 T D5 PT3B 0 C PT3B 0 C C5 PT3A 0 T PT3A 0 T C4 PT2B 0 C PT2B 0 C T T B4 PT2A 0 PT2A 0 GND GND0 0 GND0 0 A1 GND - GND - A16 GND - GND - G10 GND - GND - G7 GND - GND - G8 GND - GND - G9 GND - GND - H10 GND - GND - H7 GND - GND - H8 GND - GND - H9 GND - GND - J10 GND - GND - J7 GND - GND - J8 GND - GND - J9 GND - GND - K10 GND - GND - K7 GND - GND - K8 GND - GND - K9 GND - GND - T1 GND - GND - T16 GND - GND - E12 VCC - VCC - 4-29 Dual Function TDQS6 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA (Cont.) LFEC3 Ball Number Ball Function Bank E5 VCC E8 VCC M12 M5 LVDS LFECP6/LFEC6 Dual Function Ball Function Bank - VCC - - VCC - VCC - VCC - VCC - VCC - M9 VCC - VCC - B15 VCCAUX - VCCAUX - R2 VCCAUX - VCCAUX - F7 VCCIO0 0 VCCIO0 0 F8 VCCIO0 0 VCCIO0 0 F10 VCCIO1 1 VCCIO1 1 F9 VCCIO1 1 VCCIO1 1 G11 VCCIO2 2 VCCIO2 2 H11 VCCIO2 2 VCCIO2 2 J11 VCCIO3 3 VCCIO3 3 K11 VCCIO3 3 VCCIO3 3 L10 VCCIO4 4 VCCIO4 4 L9 VCCIO4 4 VCCIO4 4 L7 VCCIO5 5 VCCIO5 5 L8 VCCIO5 5 VCCIO5 5 J6 VCCIO6 6 VCCIO6 6 K6 VCCIO6 6 VCCIO6 6 G6 VCCIO7 7 VCCIO7 7 H6 VCCIO7 7 VCCIO7 7 F6 VCC - VCC - F11 VCC - VCC - L11 VCC - VCC - L6 VCC - VCC - 4-30 LVDS Dual Function Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA LFECP10/LFEC10 Ball Number Ball Function GND GND7 7 D4 PL2A Bank LFECP15/LFEC15 LVDS Dual Function 7 T VREF2_7 C VREF1_7 D3 PL2B 7 GND GND7 7 C3 PL12A 7 T Ball Function Bank LVDS Dual Function GND7 7 PL2A 7 T VREF2_7 C VREF1_7 PL2B 7 GND7 7 PL16A 7 T C2 PL12B 7 C PL16B 7 C B1 PL13A 7 T PL17A 7 T C1 PL13B 7 C PL17B 7 C E3 PL14A 7 T PL18A 7 T GND GND7 7 GND7 7 - - - GND7 7 E4 PL14B 7 C PL18B 7 C F4 PL15A 7 T PL19A 7 T LDQS15 F5 PL15B 7 C PL19B 7 C G4 PL16A 7 T PL20A 7 T G3 PL16B 7 C PL20B 7 C D2 PL17A 7 T PL21A 7 T LDQS19 D1 PL17B 7 C PL21B 7 C E1 PL18A 7 T PCLKT7_0 PL22A 7 T PCLKT7_0 GND7 7 C PCLKC7_0 PL22B 7 C PCLKC7_0 GND GND7 7 E2 PL18B 7 F3 XRES 6 XRES 6 G5 PL20A 6 T PL24A 6 T H5 PL20B 6 C PL24B 6 C F2 PL21A 6 T PL25A 6 T F1 PL21B 6 C PL25B 6 C H4 PL22A 6 T PL26A 6 T H3 PL22B 6 C PL26B 6 C G2 PL23A 6 T PL27A 6 T GND6 6 C PL27B 6 GND GND6 6 G1 PL23B 6 J4 PL24A 6 T PL28A 6 T J3 PL24B 6 C PL28B 6 C LDQS24 C J5 PL25A 6 T PL29A 6 T K5 PL25B 6 C PL29B 6 C H2 PL26A 6 T PL30A 6 T H1 PL26B 6 C PL30B 6 C T PL31A 6 T GND6 6 J2 PL27A 6 GND GND6 6 J1 PL27B 6 PL31B 6 K4 TCK 6 C TCK 6 K3 TDI 6 TDI 6 4-31 C LDQS28 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA LFECP10/LFEC10 LFECP15/LFEC15 Ball Number Ball Function L3 TMS 6 TMS 6 L5 TDO 6 TDO 6 Bank LVDS L4 VCCJ 6 K2 PL29A 6 T K1 PL29B 6 L2 PL30A 6 L1 PL30B M2 PL31A Dual Function Ball Function Bank LVDS Dual Function LLM0_PLLT_IN_A VCCJ 6 LLM0_PLLT_IN_A PL37A 6 T C LLM0_PLLC_IN_A PL37B 6 C LLM0_PLLC_IN_A T LLM0_PLLT_FB_A PL38A 6 T LLM0_PLLT_FB_A 6 C LLM0_PLLC_FB_A PL38B 6 C LLM0_PLLC_FB_A 6 T PL39A 6 T M1 PL31B 6 C PL39B 6 C N1 PL32A 6 T PL40A 6 T GND GND6 6 GND6 6 - - - GND6 6 N2 PL32B 6 C PL40B 6 C M4 PL33A 6 T PL41A 6 T LDQS33 M3 PL33B 6 C PL41B 6 C P1 PL34A 6 T PL42A 6 T R1 PL34B 6 C PL42B 6 C P2 PL35A 6 T PL43A 6 T LDQS41 P3 PL35B 6 C PL43B 6 C N3 PL36A 6 T VREF1_6 PL44A 6 T VREF1_6 C VREF2_6 C VREF2_6 N4 PL36B 6 PL44B 6 GND GND6 6 GND6 6 GND GND5 5 GND5 5 GND GND5 5 GND5 5 P4 PB10A 5 T PB10A 5 T N5 PB10B 5 C PB10B 5 C P5 PB11A 5 T PB11A 5 T P6 PB11B 5 C PB11B 5 C R4 PB12A 5 T PB12A 5 T R3 PB12B 5 C PB12B 5 C T2 PB13A 5 T PB13A 5 T GND GND5 5 GND5 5 PB13B 5 C PB14A 5 T T3 PB13B 5 C R5 PB14A 5 T R6 PB14B 5 C PB14B 5 C T4 PB15A 5 T PB15A 5 T BDQS14 T5 PB15B 5 C PB15B 5 C N6 PB16A 5 T PB16A 5 T M6 PB16B 5 C PB16B 5 C T6 PB17A 5 T PB17A 5 T GND GND5 5 GND5 5 T7 PB17B 5 C PB17B 5 C P7 PB18A 5 T PB18A 5 T 4-32 BDQS14 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA LFECP10/LFEC10 Ball Number Ball Function Bank LVDS N7 PB18B 5 R7 PB19A 5 LFECP15/LFEC15 Dual Function Ball Function Bank LVDS C PB18B 5 C T PB19A 5 T R8 PB19B 5 C PB19B 5 C M7 PB20A 5 T PB20A 5 T M8 PB20B 5 C PB20B 5 C T8 PB21A 5 T PB21A 5 T GND5 5 C PB21B 5 GND GND5 5 T9 PB21B 5 BDQS22 Dual Function C P8 PB22A 5 T PB22A 5 T N8 PB22B 5 C PB22B 5 C R9 PB23A 5 T PB23A 5 T R10 PB23B 5 C PB23B 5 C BDQS22 P9 PB24A 5 T VREF2_5 PB24A 5 T VREF2_5 N9 PB24B 5 C VREF1_5 PB24B 5 C VREF1_5 T PCLKT5_0 PB25A 5 T PCLKT5_0 GND5 5 T10 PB25A 5 GND GND5 5 T11 PB25B 5 C PCLKC5_0 PB25B 5 C PCLKC5_0 T12 PB26A 4 T WRITEN PB26A 4 T WRITEN T13 PB26B 4 C CS1N PB26B 4 C CS1N P10 PB27A 4 T VREF1_4 PB27A 4 T VREF1_4 N10 PB27B 4 C CSN PB27B 4 C CSN T14 PB28A 4 T VREF2_4 PB28A 4 T VREF2_4 T15 PB28B 4 C D0/SPID7 PB28B 4 C D0/SPID7 M10 PB29A 4 T D2/SPID5 PB29A 4 T D2/SPID5 GND4 4 C D1/SPID6 PB29B 4 C D1/SPID6 GND GND4 4 M11 PB29B 4 R11 PB30A 4 T BDQS30 PB30A 4 T BDQS30 P11 PB30B 4 C D3/SPID4 PB30B 4 C D3/SPID4 R13 PB31A 4 T PB31A 4 T R14 PB31B 4 C PB31B 4 C P12 PB32A 4 T PB32A 4 T P13 PB32B 4 C PB32B 4 C T PB33A 4 T GND4 4 D4/SPID3 D5/SPID2 N11 PB33A 4 GND GND4 4 N12 PB33B 4 PB33B 4 R12 PB34A 4 PB34A 4 GND GND4 4 GND4 4 GND GND4 4 GND4 4 - - - GND4 4 - - - GND4 4 C D6/SPID1 D4/SPID3 D5/SPID2 C D6/SPID1 GND GND3 3 GND3 3 N13 PR36B 3 C VREF2_3 PR44B 3 C VREF2_3 N14 PR36A 3 T VREF1_3 PR44A 3 T VREF1_3 4-33 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA LFECP10/LFEC10 Ball Number Ball Function Bank LVDS P14 PR35B 3 P15 PR35A 3 R15 PR34B R16 PR34A M13 M14 LFECP15/LFEC15 Dual Function Ball Function Bank LVDS Dual Function C PR43B 3 C T PR43A 3 T 3 C PR42B 3 C 3 T PR42A 3 T PR33B 3 C PR41B 3 C PR33A 3 T RDQS33 PR41A 3 T RDQS41 C RLM0_PLLC_FB_A PR40B 3 C RLM0_PLLC_FB_A GND3 3 P16 PR32B 3 GND GND3 3 N16 PR32A 3 T RLM0_PLLT_FB_A PR40A 3 T RLM0_PLLT_FB_A N15 PR31B 3 C RLM0_PLLC_IN_A PR39B 3 C RLM0_PLLC_IN_A M15 PR31A 3 T RLM0_PLLT_IN_A PR39A 3 T RLM0_PLLT_IN_A M16 PR30B 3 C DI/CSSPIN PR38B 3 C DI/CSSPIN L16 PR30A 3 T DOUT/CSON PR38A 3 T DOUT/CSON K16 PR29B 3 C BUSY/SISPI PR37B 3 C BUSY/SISPI T D7/SPID0 T D7/SPID0 J16 PR29A 3 PR37A 3 L12 CFG2 3 CFG2 3 L14 CFG1 3 CFG1 3 L13 CFG0 3 CFG0 3 K13 PROGRAMN 3 PROGRAMN 3 L15 CCLK 3 CCLK 3 K15 INITN 3 INITN 3 K14 DONE 3 DONE 3 GND GND3 3 H16 PR27B 3 GND3 3 C PR31B 3 C - - - GND3 3 H15 PR27A 3 T PR31A 3 T G16 PR26B 3 C PR30B 3 C G15 PR26A 3 T PR30A 3 T K12 PR25B 3 C PR29B 3 C J12 PR25A 3 T PR29A 3 T J14 PR24B 3 C PR28B 3 C J15 PR24A 3 T PR28A 3 T F16 PR23B 3 C PR27B 3 C GND GND3 3 GND3 3 RDQS24 F15 PR23A 3 T PR27A 3 T J13 PR22B 3 C PR26B 3 C H13 PR22A 3 T PR26A 3 T H14 PR21B 3 C PR25B 3 C G14 PR21A 3 T PR25A 3 T E16 PR20B 3 C PR24B 3 C PR24A 3 T PR22B 2 C GND2 2 E15 PR20A 3 T H12 PR18B 2 C GND GND2 2 PCLKC2_0 4-34 RDQS28 PCLKC2_0 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA LFECP10/LFEC10 Ball Number Ball Function Bank G12 PR18A G13 PR17B F13 PR17A F12 PR16B LFECP15/LFEC15 LVDS Dual Function Ball Function Bank LVDS Dual Function 2 T PCLKT2_0 PR22A 2 C PR21B 2 T PCLKT2_0 2 C 2 T PR21A 2 T 2 C PR20B 2 C E13 PR16A 2 T PR20A 2 T D16 PR15B 2 C PR19B 2 C D15 PR15A 2 T PR19A 2 T F14 PR14B 2 C PR18B 2 C RDQS19 GND GND2 2 GND2 2 E14 PR14A 2 T PR18A 2 T C16 PR13B 2 C PR17B 2 C B16 PR13A 2 T PR17A 2 T C15 PR12B 2 C PR16B 2 C C14 PR12A 2 T PR16A 2 T GND GND2 2 GND2 2 - - - GND2 2 D14 PR2B 2 C VREF1_2 PR2B 2 C VREF1_2 D13 PR2A 2 T VREF2_2 PR2A 2 T VREF2_2 GND GND2 2 GND2 2 GND GND1 1 GND1 1 GND GND1 1 GND1 1 - - - GND1 1 - - - B13 PT34B 1 GND1 1 C PT34B 1 C13 PT34A C12 PT33B 1 T PT34A 1 T 1 C PT33B 1 C GND GND1 1 D12 PT33A GND1 1 1 T PT33A 1 T A15 B14 PT32B 1 C PT32B 1 C PT32A 1 T PT32A 1 T D11 PT31B 1 C PT31B 1 C C11 PT31A 1 T PT31A 1 T E10 PT30B 1 C PT30B 1 C E11 PT30A 1 T PT30A 1 T C PT29B 1 C GND1 1 TDQS30 C TDQS30 A14 PT29B 1 GND GND1 1 A13 PT29A 1 T PT29A 1 T D10 PT28B 1 C PT28B 1 C PT28A 1 T PT27B 1 C VREF2_1 VREF1_1 C10 PT28A 1 T A12 PT27B 1 C VREF2_1 B12 PT27A 1 T VREF1_1 PT27A 1 T A11 PT26B 1 C PT26B 1 C B11 PT26A 1 T PT26A 1 T 4-35 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA LFECP10/LFEC10 LFECP15/LFEC15 Ball Number Ball Function Bank LVDS Dual Function Ball Function C PCLKC0_0 Bank LVDS Dual Function PT25B 0 C PCLKC0_0 GND0 0 A10 PT25B 0 GND GND0 0 B10 PT25A 0 T PCLKT0_0 PT25A 0 T PCLKT0_0 C9 PT24B 0 C VREF1_0 PT24B 0 C VREF1_0 B9 PT24A 0 T VREF2_0 PT24A 0 T VREF2_0 E9 PT23B 0 C PT23B 0 C D9 PT23A 0 T PT23A 0 T D8 PT22B 0 C PT22B 0 C C8 PT22A 0 T PT22A 0 T A9 PT21B 0 C TDQS22 PT21B 0 C GND GND0 0 GND0 0 A8 PT21A 0 T PT21A 0 T B8 PT20B 0 C PT20B 0 C B7 PT20A 0 T PT20A 0 T D7 PT19B 0 C PT19B 0 C C7 PT19A 0 T PT19A 0 T A7 PT18B 0 C PT18B 0 C A6 PT18A 0 T PT18A 0 T C PT17B 0 C GND0 0 E7 PT17B 0 GND GND0 0 E6 PT17A 0 T PT17A 0 T D6 PT16B 0 C PT16B 0 C C6 PT16A 0 T PT16A 0 T B6 PT15B 0 C PT15B 0 C B5 PT15A 0 T PT15A 0 T A5 PT14B 0 C PT14B 0 C A4 PT14A 0 T PT14A 0 T A3 PT13B 0 C PT13B 0 C TDQS14 - GND0 0 GND0 0 A2 PT13A 0 T PT13A 0 T B2 PT12B 0 C PT12B 0 C B3 PT12A 0 T PT12A 0 T D5 PT11B 0 C PT11B 0 C C5 PT11A 0 T PT11A 0 T C4 PT10B 0 C PT10B 0 C B4 PT10A 0 T PT10A 0 T GND GND0 0 GND0 0 GND GND0 0 GND0 0 A1 GND - GND - A16 GND - GND - G10 GND - GND - G7 GND - GND - G8 GND - GND - 4-36 TDQS22 TDQS14 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA LFECP10/LFEC10 Ball Number Ball Function Bank LVDS LFECP15/LFEC15 Dual Function Ball Function Bank G9 GND - GND - H10 GND - GND - H7 GND - GND - H8 GND - GND - H9 GND - GND - J10 GND - GND - J7 GND - GND - J8 GND - GND - J9 GND - GND - K10 GND - GND - K7 GND - GND - K8 GND - GND - K9 GND - GND - T1 GND - GND - T16 GND - GND - E12 VCC - VCC - E5 VCC - VCC - E8 VCC - VCC - M12 VCC - VCC - M5 VCC - VCC - M9 VCC - VCC - B15 VCCAUX - VCCAUX - R2 VCCAUX - VCCAUX - F7 VCCIO0 0 VCCIO0 0 F8 VCCIO0 0 VCCIO0 0 F10 VCCIO1 1 VCCIO1 1 F9 VCCIO1 1 VCCIO1 1 G11 VCCIO2 2 VCCIO2 2 H11 VCCIO2 2 VCCIO2 2 J11 VCCIO3 3 VCCIO3 3 K11 VCCIO3 3 VCCIO3 3 L10 VCCIO4 4 VCCIO4 4 L9 VCCIO4 4 VCCIO4 4 L7 VCCIO5 5 VCCIO5 5 L8 VCCIO5 5 VCCIO5 5 J6 VCCIO6 6 VCCIO6 6 K6 VCCIO6 6 VCCIO6 6 G6 VCCIO7 7 VCCIO7 7 H6 VCCIO7 7 VCCIO7 7 F6 VCC - VCC - F11 VCC - VCC - L11 VCC - VCC - L6 VCC - VCC - 4-37 LVDS Dual Function Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA LFECP6/LFEC6 LFECP10/LFEC10 Ball Number Ball Function GND GND7 7 D4 PL2A 7 T VREF2_7 E4 PL2B 7 C VREF1_7 C3 NC - C3 PL3A 7 B2 NC - B2 PL3B 7 E5 NC - E5 PL4A 7 F5 NC - F5 PL4B 7 D3 NC - D3 PL5A 7 C2 NC - C2 PL5B 7 Bank LVDS Dual Function LFECP/LFEC15 Ball Number Ball Function Ball Number Ball Function GND GND7 7 D4 PL2A 7 T VREF2_7 GND GND7 D4 PL2A E4 PL2B 7 C VREF1_7 7 T VREF2_7 E4 PL2B 7 C VREF1_7 T C3 PL3A 7 T C B2 PL3B 7 C T E5 PL4A 7 T C F5 PL4B 7 C T D3 PL5A 7 T C C2 PL5B 7 C Bank LVDS F4 NC - F4 PL6A 7 T G4 NC - G4 PL6B 7 C Dual Function LDQS6 Bank LVDS Dual Function 7 F4 PL6A 7 T G4 PL6B 7 C E3 NC - E3 PL7A 7 T E3 PL7A 7 T D2 NC - D2 PL7B 7 C D2 PL7B 7 C LDQS6 B1 NC - B1 PL8A 7 T LUM0_PLLT_IN_A B1 PL8A 7 T LUM0_PLLT_IN_A C1 NC - C1 PL8B 7 C LUM0_PLLC_IN_A C1 PL8B 7 C LUM0_PLLC_IN_A T LUM0_PLLT_FB_A T LUM0_PLLT_FB_A LUM0_PLLC_FB_A F3 NC - F3 PL9A 7 GND - - GND GND7 7 E2 NC - E2 PL9B 7 G5 NC - G5 NC - C LUM0_PLLC_FB_A F3 PL9A 7 GND GND7 7 E2 PL9B 7 C G5 PL11A 7 T C H6 NC - H6 NC - H6 PL11B 7 G3 NC - G3 NC - G3 PL12A 7 T H4 NC - H4 NC - H4 PL12B 7 C J5 NC - J5 NC - J5 PL13A 7 T H5 NC - H5 NC - H5 PL13B 7 C F2 NC - F2 NC - F2 PL14A 7 T GND - - GND - - GND GND7 7 F1 NC - F1 NC - F1 PL14B 7 E1 NC - E1 PL11A 7 T E1 PL15A 7 C T D1 NC - D1 PL11B 7 C D1 PL15B 7 C H3 PL3A 7 T H3 PL12A 7 T H3 PL16A 7 T G2 PL3B 7 C G2 PL12B 7 C G2 PL16B 7 C H2 PL4A 7 T H2 PL13A 7 T H2 PL17A 7 T G1 PL4B 7 C G1 PL13B 7 C G1 PL17B 7 C T T T J4 PL5A 7 GND - - J4 PL14A 7 GND GND7 7 J3 PL5B 7 C J2 PL6A 7 T J3 PL14B 7 C J2 PL15A 7 T H1 PL6B 7 C H1 PL15B 7 K4 PL7A K5 PL7B 7 T K4 PL16A 7 C K5 PL16B K3 PL8A K2 PL8B 7 T K3 PL17A 7 C K2 PL17B T J1 PL9A 7 GND GND7 7 K1 PL9B 7 L3 XRES 6 L4 PL11A 6 L5 PL11B 6 L2 PL12A 6 L1 PL12B 6 LDQS6 PL18A 7 GND7 7 J3 PL18B 7 J2 PL19A 7 T C H1 PL19B 7 C 7 T K4 PL20A 7 T 7 C K5 PL20B 7 C 7 T K3 PL21A 7 T 7 C K2 PL21B 7 C T T PCLKT7_0 C PCLKC7_0 J1 PL18A 7 GND GND7 7 K1 PL18B 7 L3 XRES 6 T L4 PL20A 6 C L5 PL20B 6 T L2 PL21A 6 C L1 PL21B 6 C PCLKT7_0 J4 GND PCLKC7_0 LDQS15 J1 PL22A 7 GND GND7 7 K1 PL22B 7 L3 XRES 6 T L4 PL24A 6 T C L5 PL24B 6 C T L2 PL25A 6 T C L1 PL25B 6 C C 4-38 PCLKT7_0 C PCLKC7_0 LDQS19 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Number Ball Function M4 PL13A 6 M5 PL13B 6 T LFECP10/LFEC10 Ball Number Ball Function T M4 PL22A 6 C M5 PL22B 6 T Bank LVDS M1 PL14A 6 GND GND6 6 M2 PL14B 6 C N3 PL15A 6 T M3 PL15B 6 N5 PL16A N4 PL16B N1 PL17A N2 PL17B Dual Function Ball Number Ball Function T M4 PL26A 6 T C M5 PL26B 6 C T Bank LVDS M1 PL23A 6 GND GND6 6 M2 PL23B 6 C N3 PL24A 6 T C M3 PL24B 6 6 T N5 PL25A 6 C N4 PL25B 6 T N1 PL26A 6 C N2 PL26B T P1 PL18A 6 GND GND6 6 LDQS15 C LFECP/LFEC15 Dual Function Bank LVDS M1 PL27A 6 GND GND6 6 M2 PL27B 6 N3 PL28A 6 T C M3 PL28B 6 C 6 T N5 PL29A 6 T 6 C N4 PL29B 6 C 6 T N1 PL30A 6 T 6 C N2 PL30B 6 C T P1 PL31A 6 T GND GND6 6 P1 PL27A 6 GND GND6 6 LDQS24 C C P2 PL18B 6 P2 PL27B 6 P2 PL31B 6 R6 NC - R6 NC - R6 PL32A 6 T P5 NC - P5 NC - P5 PL32B 6 C P3 NC - P3 NC - P3 PL33A 6 T P4 NC - P4 NC - P4 PL33B 6 C R1 NC - R1 NC - R1 PL34A 6 T R2 NC - R2 NC - R2 PL34B 6 C T R5 NC - R5 NC - R5 PL35A 6 GND - - - - - GND GND6 6 R4 NC - R4 NC - R4 PL35B 6 T1 NC - T1 NC - T1 NC - T2 NC - T2 NC - T2 NC - R3 NC - R3 NC - R3 NC - Dual Function LDQS28 C C T3 NC - T3 NC - T3 NC - T5 TCK 6 T5 TCK 6 T5 TCK 6 U5 TDI 6 U5 TDI 6 U5 TDI 6 T4 TMS 6 T4 TMS 6 T4 TMS 6 U1 TDO 6 U1 TDO 6 U1 TDO 6 U2 VCCJ 6 U2 VCCJ 6 U2 VCCJ 6 V1 PL20A 6 T LLM0_PLLT_IN_A V1 PL29A 6 T LLM0_PLLT_IN_A V1 PL37A 6 T LLM0_PLLT_IN_A V2 PL20B 6 C LLM0_PLLC_IN_A V2 PL29B 6 C LLM0_PLLC_IN_A V2 PL37B 6 C LLM0_PLLC_IN_A U3 PL21A 6 T LLM0_PLLT_FB_A U3 PL30A 6 T LLM0_PLLT_FB_A U3 PL38A 6 T LLM0_PLLT_FB_A V3 PL21B 6 C LLM0_PLLC_FB_A V3 PL30B 6 C LLM0_PLLC_FB_A V3 PL38B 6 C LLM0_PLLC_FB_A U4 PL22A 6 T U4 PL31A 6 T U4 PL39A 6 T V5 PL22B 6 C V5 PL31B 6 C V5 PL39B 6 C T T T W1 PL23A 6 GND GND6 6 W1 PL32A 6 GND GND6 6 W2 PL23B 6 C Y1 PL24A 6 T W2 PL32B 6 C Y1 PL33A 6 T Y2 PL24B 6 C Y2 PL33B 6 AA1 PL25A AA2 PL25B 6 T AA1 PL34A 6 C AA2 PL34B W4 PL26A V4 PL26B 6 T W4 PL35A 6 C V4 PL35B W3 PL27A 6 T Y3 PL27B 6 C VREF1_6 W3 PL36A 6 T VREF2_6 Y3 PL36B 6 C GND GND6 6 GND GND6 6 LDQS24 W1 PL40A 6 GND GND6 6 W2 PL40B 6 Y1 PL41A 6 T C Y2 PL41B 6 C 6 T AA1 PL42A 6 T 6 C AA2 PL42B 6 C 6 T W4 PL43A 6 T 6 C V4 PL43B 6 C VREF1_6 W3 PL44A 6 T VREF1_6 VREF2_6 Y3 PL44B 6 C VREF2_6 GND GND6 6 4-39 LDQS33 C LDQS41 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Number Ball Function GND GND5 V7 NC T6 LFECP10/LFEC10 Ball Number Ball Function 5 GND GND5 5 - V7 PB2A 5 T NC - T6 PB2B 5 C Bank LVDS Dual Function Bank LVDS LFECP/LFEC15 Dual Function Ball Number Ball Function GND GND5 5 V7 PB2A 5 T T6 PB2B 5 C Bank LVDS V8 NC - V8 PB3A 5 T V8 PB3A 5 T U7 NC - U7 PB3B 5 C U7 PB3B 5 C W5 NC - W5 PB4A 5 T W5 PB4A 5 T U6 NC - U6 PB4B 5 C U6 PB4B 5 C AA3 NC - AA3 PB5A 5 T AA3 PB5A 5 T AB3 NC - AB3 PB5B 5 C AB3 PB5B 5 C Y6 NC - Y6 PB6A 5 T Y6 PB6A 5 T V6 NC - V6 PB6B 5 C V6 PB6B 5 C AA5 NC - AA5 PB7A 5 T AA5 PB7A 5 T W6 NC - W6 PB7B 5 C W6 PB7B 5 C Y5 NC - Y5 PB8A 5 T Y5 PB8A 5 T Y4 NC - Y4 PB8B 5 C Y4 PB8B 5 C AA4 NC - AA4 PB9A 5 T AA4 PB9A 5 T GND - - GND GND5 5 GND GND5 5 BDQS6 AB4 NC - AB4 PB9B 5 C AB4 PB9B 5 Y7 PB2A 5 T Y7 PB10A 5 T Y7 PB10A 5 T W8 PB2B 5 C W8 PB10B 5 C W8 PB10B 5 C W7 PB3A 5 T W7 PB11A 5 T W7 PB11A 5 T U8 PB3B 5 C U8 PB11B 5 C U8 PB11B 5 C W9 PB4A 5 T W9 PB12A 5 T W9 PB12A 5 T U9 PB4B 5 C U9 PB12B 5 C U9 PB12B 5 C T Y8 PB13A 5 T Y8 PB13A 5 T GND GND5 5 GND GND5 5 Y8 PB5A 5 GND - - Y9 PB5B 5 C V9 PB6A 5 T T9 PB6B 5 W10 PB7A U10 PB7B V10 PB8A T10 PB8B Y9 PB13B 5 C V9 PB14A 5 T C T9 PB14B 5 5 T W10 PB15A 5 C U10 PB15B 5 T V10 PB16A 5 C T10 PB16B T AA6 PB17A 5 T GND GND5 5 AA6 PB9A 5 GND GND5 5 BDQS6 Y9 PB13B 5 PB14A 5 C T C T9 PB14B 5 C 5 T W10 PB15A 5 T 5 C U10 PB15B 5 C 5 T V10 PB16A 5 T 5 C T10 PB16B 5 C AA6 PB17A 5 T GND GND5 5 AB5 PB9B 5 C AB5 PB17B 5 C AB5 PB17B 5 AA8 PB10A 5 T AA8 PB18A 5 T AA8 PB18A 5 T AA7 PB10B 5 C AA7 PB18B 5 C AA7 PB18B 5 C AB6 PB11A 5 T AB6 PB19A 5 T AB6 PB19A 5 T AB7 PB11B 5 C AB7 PB19B 5 C AB7 PB19B 5 C Y10 PB12A 5 T Y10 PB20A 5 T Y10 PB20A 5 T PB12B 5 C W11 PB20B 5 C W11 PB20B 5 C T T AB8 PB21A 5 T GND GND5 5 AB8 PB13A 5 GND5 5 AB9 PB13B 5 C AA10 PB14A 5 T AA9 PB14B 5 C BDQS14 AB8 PB21A 5 GND GND5 5 AB9 PB21B 5 C AA10 PB22A 5 T AA9 PB22B 5 C BDQS22 AB9 PB21B 5 AA10 PB22A 5 C T AA9 PB22B 5 C Y11 PB15A 5 T Y11 PB23A 5 T Y11 PB23A 5 T AA11 PB15B 5 C AA11 PB23B 5 C AA11 PB23B 5 C V11 PB16A 5 T V11 PB24A 5 T V11 PB24A 5 T VREF2_5 4-40 VREF2_5 BDQS14 C W11 GND BDQS6 C V9 BDQS14 Dual Function BDQS22 VREF2_5 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Number Ball Function Bank LVDS LFECP10/LFEC10 Dual Function Ball Number Ball Function Bank LVDS LFECP/LFEC15 Dual Function Ball Number Ball Function Bank LVDS Dual Function V12 PB16B 5 C VREF1_5 V12 PB24B 5 C VREF1_5 V12 PB24B 5 C VREF1_5 AB10 PB17A 5 T PCLKT5_0 AB10 PB25A 5 T PCLKT5_0 AB10 PB25A 5 T PCLKT5_0 GND GND5 5 GND GND5 5 GND GND5 5 AB11 PB17B 5 C PCLKC5_0 AB11 PB25B 5 C PCLKC5_0 AB11 PB25B 5 C PCLKC5_0 Y12 PB18A 4 T WRITEN Y12 PB26A 4 T WRITEN Y12 PB26A 4 T WRITEN U11 PB18B 4 C CS1N U11 PB26B 4 C CS1N U11 PB26B 4 C CS1N W12 PB19A 4 T VREF1_4 W12 PB27A 4 T VREF1_4 W12 PB27A 4 T VREF1_4 U12 PB19B 4 C CSN U12 PB27B 4 C CSN U12 PB27B 4 C CSN W13 PB20A 4 T VREF2_4 W13 PB28A 4 T VREF2_4 W13 PB28A 4 T VREF2_4 U13 PB20B 4 C D0/SPID7 U13 PB28B 4 C D0/SPID7 U13 PB28B 4 C D0/SPID7 AA12 PB21A 4 T D2/SPID5 AA12 PB29A 4 T D2/SPID5 AA12 PB29A 4 T D2/SPID5 GND GND4 4 GND GND4 4 GND GND4 4 AB12 PB21B 4 C D1/SPID6 AB12 PB29B 4 C D1/SPID6 AB12 PB29B 4 C D1/SPID6 T13 PB22A 4 T BDQS22 T13 PB30A 4 T BDQS30 T13 PB30A 4 T BDQS30 V13 PB22B 4 C D3/SPID4 V13 PB30B 4 C D3/SPID4 V13 PB30B 4 C D3/SPID4 W14 PB23A 4 T W14 PB31A 4 T W14 PB31A 4 T U14 PB23B 4 C U14 PB31B 4 C U14 PB31B 4 C Y13 PB24A 4 T Y13 PB32A 4 T Y13 PB32A 4 T V14 PB24B 4 C AA13 PB25A 4 T GND GND4 4 AB13 PB25B 4 C AA14 PB26A 4 Y14 PB26B Y15 PB27A W15 D4/SPID3 D5/SPID2 V14 PB32B 4 C AA13 PB33A 4 T D4/SPID3 D5/SPID2 V14 PB32B 4 C AA13 PB33A 4 T 4 GND GND4 4 AB13 PB33B 4 C T AA14 PB34A 4 T 4 C Y14 PB34B 4 C Y14 4 T Y15 PB35A 4 T Y15 PB27B 4 C W15 PB35B 4 C W15 V15 PB28A 4 T V15 PB36A 4 T T14 PB28B 4 C T14 PB36B 4 C AB14 PB29A 4 T AB14 PB37A 4 T GND GND4 4 GND GND4 4 AB15 PB29B 4 C AB15 PB37B 4 C AB16 PB30A 4 T AB16 PB38A 4 T AA15 PB30B 4 C AA15 PB38B 4 AB17 PB31A 4 T AB17 PB39A AA16 PB31B 4 C AA16 PB39B AB18 PB32A 4 T AB18 PB40A AA17 PB32B 4 C AA17 PB40B AB19 PB33A 4 T AB19 GND - - GND AA18 PB33B 4 W16 NC - U15 NC - C D6/SPID1 BDQS30 D6/SPID1 GND GND4 AB13 PB33B 4 C AA14 PB34A 4 T PB34B 4 C PB35A 4 T PB35B 4 C V15 PB36A 4 T T14 PB36B 4 C AB14 PB37A 4 T GND GND4 4 AB15 PB37B 4 AB16 PB38A 4 T C AA15 PB38B 4 C 4 T AB17 PB39A 4 T 4 C AA16 PB39B 4 C 4 T AB18 PB40A 4 T 4 C AA17 PB40B 4 C PB41A 4 T AB19 PB41A 4 T - - GND GND4 4 AA18 PB41B 4 AA18 PB41B 4 W16 NC - W16 PB42A 4 T U15 NC - U15 PB42B 4 C C BDQS38 D5/SPID2 D6/SPID1 C BDQS38 C V16 NC - V16 NC - V16 PB43A 4 T U16 NC - U16 NC - U16 PB43B 4 C Y17 NC - Y17 NC - Y17 PB44A 4 T V17 NC - V17 NC - V17 PB44B 4 C AB20 NC - AB20 NC - AB20 PB45A 4 T GND - - GND - - GND GND4 4 AA19 NC - AA19 NC - AA19 PB45B 4 C Y16 NC - Y16 NC - Y16 PB46A 4 T 4-41 D4/SPID3 BDQS46 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Number Ball Function Bank LVDS LFECP10/LFEC10 Dual Function Ball Number Ball Function Bank LVDS LFECP/LFEC15 Dual Function Ball Number Ball Function Bank LVDS W17 NC - W17 NC - W17 PB46B 4 AA20 NC - AA20 NC - AA20 PB47A 4 T Y19 NC - Y19 NC - Y19 PB47B 4 C Y18 NC - Y18 NC - Y18 PB48A 4 T W18 NC - W18 NC - W18 PB48B 4 C Dual Function C T17 NC - T17 NC - T17 PB49A 4 T U17 NC - U17 NC - U17 PB49B 4 C GND GND4 4 GND GND4 4 GND GND4 4 GND GND3 3 GND GND3 3 GND GND3 3 W20 PR27B 3 C VREF2_3 W20 PR36B 3 C VREF2_3 W20 PR44B 3 C VREF2_3 Y20 PR27A 3 T VREF1_3 Y20 PR36A 3 T VREF1_3 Y20 PR44A 3 T VREF1_3 AA21 PR26B 3 C AA21 PR35B 3 C AA21 PR43B 3 C AB21 PR26A 3 T AB21 PR35A 3 T AB21 PR43A 3 T W19 PR25B 3 C W19 PR34B 3 C W19 PR42B 3 C V19 PR25A 3 T V19 PR34A 3 T V19 PR42A 3 T Y21 PR24B 3 C Y21 PR33B 3 C Y21 PR41B 3 C AA22 PR24A 3 T RDQS24 AA22 PR33A 3 T RDQS33 AA22 PR41A 3 T RDQS41 V20 PR23B 3 C RLM0_PLLC_FB_A V20 PR32B 3 C RLM0_PLLC_FB_A V20 PR40B 3 C RLM0_PLLC_FB_A GND GND3 3 GND GND3 3 GND GND3 3 U20 PR23A 3 T RLM0_PLLT_FB_A U20 PR32A 3 T RLM0_PLLT_FB_A U20 PR40A 3 T RLM0_PLLT_FB_A W21 PR22B 3 C RLM0_PLLC_IN_A W21 PR31B 3 C RLM0_PLLC_IN_A W21 PR39B 3 C RLM0_PLLC_IN_A Y22 PR22A 3 T RLM0_PLLT_IN_A Y22 PR31A 3 T RLM0_PLLT_IN_A Y22 PR39A 3 T RLM0_PLLT_IN_A V21 PR21B 3 C DI/CSSPIN V21 PR30B 3 C DI/CSSPIN V21 PR38B 3 C DI/CSSPIN W22 PR21A 3 T DOUT/CSON W22 PR30A 3 T DOUT/CSON W22 PR38A 3 T DOUT/CSON U21 PR20B 3 C BUSY/SISPI U21 PR29B 3 C BUSY/SISPI U21 PR37B 3 C BUSY/SISPI V22 PR20A 3 T D7/SPID0 V22 PR29A 3 T D7/SPID0 V22 PR37A 3 T D7/SPID0 T19 CFG2 3 T19 CFG2 3 T19 CFG2 3 U19 CFG1 3 U19 CFG1 3 U19 CFG1 3 U18 CFG0 3 U18 CFG0 3 U18 CFG0 3 V18 PROGRAMN 3 V18 PROGRAMN 3 V18 PROGRAMN 3 T20 CCLK 3 T20 CCLK 3 T20 CCLK 3 T21 INITN 3 T21 INITN 3 T21 INITN 3 R20 DONE 3 R20 DONE 3 R20 DONE 3 T18 NC - T18 NC - T18 NC - R17 NC - R17 NC - R17 NC - R19 NC - R19 NC - R19 NC - R18 NC - R18 NC - R18 NC - U22 NC - U22 NC - U22 PR35B 3 GND - - GND - - GND GND3 3 C T22 NC - T22 NC - T22 PR35A 3 T R21 NC - R21 NC - R21 PR34B 3 C R22 NC - R22 NC - R22 PR34A 3 T P20 NC - P20 NC - P20 PR33B 3 C N20 NC - N20 NC - N20 PR33A 3 T P19 NC - P19 NC - P19 PR32B 3 C P18 PR32A 3 T P21 PR31B 3 C P18 NC - P21 PR18B 3 GND GND3 3 P22 PR18A 3 T N21 PR17B 3 C C P18 NC - P21 PR27B 3 GND GND3 3 GND GND3 3 P22 PR27A 3 T P22 PR31A 3 T N21 PR26B 3 C N21 PR30B 3 C C 4-42 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Number Ball Function N22 PR17A 3 N19 PR16B 3 LFECP10/LFEC10 Ball Number Ball Function T N22 PR26A 3 C N19 PR25B 3 Bank LVDS Dual Function LFECP/LFEC15 Ball Number Ball Function T N22 PR30A 3 T C N19 PR29B 3 C Bank LVDS Dual Function Bank LVDS N18 PR16A 3 T N18 PR25A 3 T N18 PR29A 3 T M21 PR15B 3 C M21 PR24B 3 C M21 PR28B 3 C L20 PR15A 3 T L20 PR24A 3 T L20 PR28A 3 T L21 PR14B 3 C L21 PR23B 3 C L21 PR27B 3 C GND GND3 3 GND GND3 3 GND GND3 3 M20 PR14A 3 T M20 PR23A 3 T M20 PR27A 3 T M18 PR13B 3 C M18 PR22B 3 C M18 PR26B 3 C M19 PR13A 3 T M19 PR22A 3 T M19 PR26A 3 T M22 PR12B 3 C M22 PR21B 3 C M22 PR25B 3 C RDQS15 RDQS24 Dual Function RDQS28 L22 PR12A 3 T L22 PR21A 3 T L22 PR25A 3 T K22 PR11B 3 C K22 PR20B 3 C K22 PR24B 3 C K21 PR11A 3 T K21 PR20A 3 T K21 PR24A 3 T J22 PR9B 2 C J22 PR18B 2 C J22 PR22B 2 C PCLKC2_0 GND GND2 2 GND GND2 2 GND GND2 2 PCLKT2_0 PCLKC2_0 J21 PR9A 2 T J21 PR18A 2 T J21 PR22A 2 T H22 PR8B 2 C H22 PR17B 2 C H22 PR21B 2 C H21 PR8A 2 T H21 PR17A 2 T H21 PR21A 2 T L19 PR7B 2 C L19 PR16B 2 C L19 PR20B 2 C L18 PR7A 2 T L18 PR16A 2 T L18 PR20A 2 T K20 PR6B 2 C K20 PR15B 2 C K20 PR19B 2 C J20 PR6A 2 T K19 PR5B 2 C PCLKT2_0 PCLKC2_0 RDQS6 J20 PR15A 2 T K19 PR14B 2 C PCLKT2_0 RDQS15 J20 PR19A 2 T K19 PR18B 2 C GND - - GND GND2 2 GND GND2 2 K18 PR5A 2 T K18 PR14A 2 T K18 PR18A 2 T G22 PR4B 2 C G22 PR13B 2 C G22 PR17B 2 C F22 PR4A 2 T F22 PR13A 2 T F22 PR17A 2 T F21 PR3B 2 C F21 PR12B 2 C F21 PR16B 2 C E22 PR3A 2 T E21 NC - E22 PR12A 2 T E22 PR16A 2 T E21 PR11B 2 C E21 PR15B 2 C T D22 NC - D22 PR11A 2 D22 PR15A 2 T G21 NC - G21 NC - G21 PR14B 2 C RDQS19 G20 NC - G20 NC - GND GND2 2 GND - - - - - G20 PR14A 2 T J18 NC - J18 NC - J18 PR13B 2 C H19 NC - H19 NC - H19 PR13A 2 T J19 NC - J19 NC - J19 PR12B 2 C H20 NC - H20 NC - H20 PR12A 2 T H17 NC - H17 NC - H17 PR11B 2 C H18 NC - H18 NC - H18 PR11A 2 T D21 NC - D21 PR9B 2 D21 PR9B 2 C RUM0_PLLC_FB_A GND - - GND GND2 2 GND GND2 2 C RUM0_PLLC_FB_A C22 NC - C22 PR9A 2 T RUM0_PLLT_FB_A C22 PR9A 2 T RUM0_PLLT_FB_A G19 NC - G19 PR8B 2 C RUM0_PLLC_IN_A G19 PR8B 2 C RUM0_PLLC_IN_A G18 NC - G18 PR8A 2 T RUM0_PLLT_IN_A G18 PR8A 2 T RUM0_PLLT_IN_A F20 NC - F20 PR7B 2 C F20 PR7B 2 C F19 NC - F19 PR7A 2 T F19 PR7A 2 T E20 NC - E20 PR6B 2 C E20 PR6B 2 C D20 NC - D20 PR6A 2 T D20 PR6A 2 T 4-43 RDQS6 RDQS6 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Number Ball Function C21 NC C20 NC F18 LFECP10/LFEC10 LFECP/LFEC15 Ball Number Ball Function - C21 PR5B 2 C C21 PR5B 2 - C20 PR5A 2 T C20 PR5A 2 T NC - F18 PR4B 2 C F18 PR4B 2 C E18 NC - E18 PR4A 2 T E18 PR4A 2 T B22 NC - B22 PR3B 2 C B22 PR3B 2 C Bank LVDS Dual Function Bank LVDS Dual Function Ball Number Ball Function Bank LVDS Dual Function C B21 NC - B21 PR3A 2 T B21 PR3A 2 T E19 PR2B 2 C VREF1_2 E19 PR2B 2 C VREF1_2 E19 PR2B 2 C VREF1_2 D19 PR2A 2 T VREF2_2 D19 PR2A 2 T VREF2_2 D19 PR2A 2 T VREF2_2 GND GND2 2 GND GND2 2 GND GND2 2 GND GND1 1 GND GND1 1 GND GND1 1 G17 NC - G17 NC - G17 PT49B 1 F17 NC - F17 NC - F17 PT49A 1 T D18 NC - D18 NC - D18 PT48B 1 C C18 NC - C18 NC - C18 PT48A 1 T C19 NC - C19 NC - C19 PT47B 1 C C B20 NC - B20 NC - B20 PT47A 1 T D17 NC - D17 NC - D17 PT46B 1 C C16 NC - C16 NC - C16 PT46A 1 T B19 NC - B19 NC - B19 PT45B 1 C GND - - GND - - GND GND1 1 A20 NC - A20 NC - A20 PT45A 1 T E17 NC - E17 NC - E17 PT44B 1 C C17 NC - C17 NC - C17 PT44A 1 T F16 NC - F16 NC - F16 PT43B 1 C E16 NC - E16 NC - E16 PT43A 1 T F15 NC - F15 NC - F15 PT42B 1 C D16 PT42A 1 T B18 PT41B 1 C D16 NC - B18 PT33B 1 C D16 NC - B18 PT41B 1 C GND - - GND - - GND GND1 1 A19 PT33A 1 T A19 PT41A 1 T A19 PT41A 1 T B17 PT32B 1 C B17 PT40B 1 C B17 PT40B 1 C A18 PT32A 1 T A18 PT40A 1 T A18 PT40A 1 T B16 PT31B 1 C B16 PT39B 1 C B16 PT39B 1 C A17 PT31A 1 T A17 PT39A 1 T A17 PT39A 1 T B15 PT30B 1 C B15 PT38B 1 C B15 PT38B 1 C A16 PT30A 1 T A16 PT38A 1 T A16 PT38A 1 T A15 PT29B 1 C A15 PT37B 1 C A15 PT37B 1 C GND GND1 1 GND GND1 1 GND GND1 1 A14 PT29A 1 T A14 PT37A 1 T A14 PT37A 1 T G14 PT28B 1 C G14 PT36B 1 C G14 PT36B 1 C TDQS30 TDQS38 E15 PT28A 1 T E15 PT36A 1 T E15 PT36A 1 T D15 PT27B 1 C D15 PT35B 1 C D15 PT35B 1 C C15 PT27A 1 T C15 PT35A 1 T C15 PT35A 1 T C14 PT26B 1 C C14 PT34B 1 C C14 PT34B 1 C B14 PT26A 1 T B14 PT34A 1 T B14 PT34A 1 T A13 PT25B 1 C A13 PT33B 1 C A13 PT33B 1 C GND GND1 1 GND GND1 1 GND GND1 1 B13 PT25A 1 T B13 PT33A 1 T B13 PT33A 1 T E14 PT24B 1 C E14 PT32B 1 C E14 PT32B 1 C C13 PT24A 1 T C13 PT32A 1 T C13 PT32A 1 T 4-44 TDQS46 TDQS38 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Number Ball Function Bank LVDS LFECP10/LFEC10 Dual Function Ball Number Ball Function Bank LVDS LFECP/LFEC15 Dual Function Ball Number Ball Function Bank LVDS Dual Function F14 PT23B 1 C F14 PT31B 1 C F14 PT31B 1 D14 PT23A 1 T D14 PT31A 1 T D14 PT31A 1 T E13 PT22B 1 C E13 PT30B 1 C E13 PT30B 1 C G13 PT22A 1 T G13 PT30A 1 T G13 PT30A 1 T A12 PT21B 1 C A12 PT29B 1 C A12 PT29B 1 C GND GND1 1 GND GND1 1 GND GND1 1 B12 PT21A 1 T B12 PT29A 1 T B12 PT29A 1 T F13 PT20B 1 C F13 PT28B 1 C F13 PT28B 1 C D13 PT20A 1 T D13 PT28A 1 T D13 PT28A 1 T F12 PT19B 1 C VREF2_1 F12 PT27B 1 C VREF2_1 F12 PT27B 1 C VREF2_1 D12 PT19A 1 T VREF1_1 D12 PT27A 1 T VREF1_1 D12 PT27A 1 T VREF1_1 C TDQS22 TDQS30 C TDQS30 F11 PT18B 1 C F11 PT26B 1 C F11 PT26B 1 C12 PT18A 1 T C12 PT26A 1 T C12 PT26A 1 T A11 PT17B 0 C A11 PT25B 0 C A11 PT25B 0 C PCLKC0_0 GND GND0 0 GND GND0 0 GND GND0 0 A10 PT17A 0 T PCLKT0_0 A10 PT25A 0 T PCLKT0_0 A10 PT25A 0 T PCLKT0_0 E12 PT16B 0 C VREF1_0 E12 PT24B 0 C VREF1_0 E12 PT24B 0 C VREF1_0 E11 PT16A 0 T VREF2_0 E11 PT24A 0 T VREF2_0 E11 PT24A 0 T VREF2_0 B11 PT15B 0 C B11 PT23B 0 C B11 PT23B 0 C C11 PT15A 0 T C11 PT23A 0 T C11 PT23A 0 T B9 PT14B 0 C B9 PT22B 0 C B9 PT22B 0 C B10 PT14A 0 T B10 PT22A 0 T B10 PT22A 0 T A9 PT13B 0 C A9 PT21B 0 C A9 PT21B 0 C GND GND0 0 GND GND0 0 GND GND0 0 A8 PT13A 0 T A8 PT21A 0 T A8 PT21A 0 T D11 PT12B 0 C D11 PT20B 0 C D11 PT20B 0 C C10 PT12A 0 T C10 PT20A 0 T C10 PT20A 0 T A7 PT11B 0 C A7 PT19B 0 C A7 PT19B 0 C A6 PT11A 0 T A6 PT19A 0 T A6 PT19A 0 T B7 PT10B 0 C B7 PT18B 0 C B7 PT18B 0 C B8 PT10A 0 T B8 PT18A 0 T B8 PT18A 0 T A5 PT9B 0 C A5 PT17B 0 C A5 PT17B 0 C GND GND0 0 GND GND0 0 GND GND0 0 B6 PT9A 0 T B6 PT17A 0 T B6 PT17A 0 T G10 PT8B 0 C G10 PT16B 0 C G10 PT16B 0 C E10 PT8A 0 T E10 PT16A 0 T E10 PT16A 0 T F10 PT7B 0 C F10 PT15B 0 C F10 PT15B 0 C PCLKC0_0 TDQS14 PCLKC0_0 TDQS22 D10 PT7A 0 T D10 PT15A 0 T D10 PT15A 0 T G9 PT6B 0 C G9 PT14B 0 C G9 PT14B 0 C E9 PT6A 0 T E9 PT14A 0 T E9 PT14A 0 T C9 PT5B 0 C C9 PT13B 0 C C9 PT13B 0 C TDQS6 TDQS14 GND - - GND GND0 0 GND GND0 0 C8 PT5A 0 T C8 PT13A 0 T C8 PT13A 0 T F9 PT4B 0 C F9 PT12B 0 C F9 PT12B 0 C D9 PT4A 0 T D9 PT12A 0 T D9 PT12A 0 T F8 PT3B 0 C F8 PT11B 0 C F8 PT11B 0 C D7 PT3A 0 T D7 PT11A 0 T D7 PT11A 0 T D8 PT2B 0 C D8 PT10B 0 C D8 PT10B 0 C T C7 PT10A 0 T C7 PT10A 0 T GND GND0 0 GND GND0 0 C7 PT2A 0 GND GND0 0 4-45 TDQS22 TDQS14 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Number Ball Function A4 NC B4 NC C4 LFECP10/LFEC10 LFECP/LFEC15 Ball Number Ball Function - A4 PT9B 0 C A4 PT9B 0 - B4 PT9A 0 T B4 PT9A 0 T NC - C4 PT8B 0 C C4 PT8B 0 C C5 NC - C5 PT8A 0 T C5 PT8A 0 T D6 NC - D6 PT7B 0 C D6 PT7B 0 C B5 NC - B5 PT7A 0 T B5 PT7A 0 T E6 NC - E6 PT6B 0 C E6 PT6B 0 C C6 NC - C6 PT6A 0 T C6 PT6A 0 T A3 NC - A3 PT5B 0 C A3 PT5B 0 C B3 NC - B3 PT5A 0 T B3 PT5A 0 T F6 NC - F6 PT4B 0 C F6 PT4B 0 C D5 NC - D5 PT4A 0 T D5 PT4A 0 T F7 NC - F7 PT3B 0 C F7 PT3B 0 C Bank LVDS Dual Function Bank LVDS Dual Function TDQS6 Ball Number Ball Function Bank LVDS C E8 NC - E8 PT3A 0 T E8 PT3A 0 T G6 NC - G6 PT2B 0 C G6 PT2B 0 C T T E7 NC - E7 PT2A 0 GND - - GND GND0 0 E7 PT2A 0 GND GND0 0 - A1 GND - A1 GND - A1 GND A22 GND - A22 GND - A22 GND - AB1 GND - AB1 GND - AB1 GND - AB22 GND - AB22 GND - AB22 GND H15 GND - H15 GND - H15 GND - H8 GND - H8 GND - H8 GND - J10 GND - J10 GND - J10 GND - J11 GND - J11 GND - J11 GND - J12 GND - J12 GND - J12 GND - J13 GND - J13 GND - J13 GND - J14 GND - J14 GND - J14 GND - J9 GND - J9 GND - J9 GND - K10 GND - K10 GND - K10 GND - K11 GND - K11 GND - K11 GND - K12 GND - K12 GND - K12 GND - K13 GND - K13 GND - K13 GND - K14 GND - K14 GND - K14 GND - K9 GND - K9 GND - K9 GND - L10 GND - L10 GND - L10 GND - L11 GND - L11 GND - L11 GND - L12 GND - L12 GND - L12 GND - L13 GND - L13 GND - L13 GND - L14 GND - L14 GND - L14 GND - L9 GND - L9 GND - L9 GND - M10 GND - M10 GND - M10 GND - M11 GND - M11 GND - M11 GND - M12 GND - M12 GND - M12 GND - M13 GND - M13 GND - M13 GND - M14 GND - M14 GND - M14 GND - M9 GND - M9 GND - M9 GND - N10 GND - N10 GND - N10 GND - N11 GND - N11 GND - N11 GND - N12 GND - N12 GND - N12 GND - 4-46 Dual Function TDQS6 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Number Ball Function N13 GND N14 GND N9 LFECP10/LFEC10 Ball Number Ball Function - N13 GND - N14 GND GND - N9 P10 GND - P11 GND - P12 GND P13 LFECP/LFEC15 Ball Number Ball Function - N13 GND - N14 GND - GND - N9 GND - P10 GND - P10 GND - P11 GND - P11 GND - - P12 GND - P12 GND - GND - P13 GND - P13 GND - P14 GND - P14 GND - P14 GND - P9 GND - P9 GND - P9 GND - R15 GND - R15 GND - R15 GND - R8 GND - R8 GND - R8 GND - J16 VCC - J16 VCC - J16 VCC - J7 VCC - J7 VCC - J7 VCC - K16 VCC - K16 VCC - K16 VCC - K17 VCC - K17 VCC - K17 VCC - K6 VCC - K6 VCC - K6 VCC - K7 VCC - K7 VCC - K7 VCC - L17 VCC - L17 VCC - L17 VCC - L6 VCC - L6 VCC - L6 VCC - M17 VCC - M17 VCC - M17 VCC - M6 VCC - M6 VCC - M6 VCC - N16 VCC - N16 VCC - N16 VCC - N17 VCC - N17 VCC - N17 VCC - N6 VCC - N6 VCC - N6 VCC - Bank LVDS Dual Function Bank LVDS Dual Function Bank LVDS - N7 VCC - N7 VCC - N7 VCC - P16 VCC - P16 VCC - P16 VCC - P7 VCC - P7 VCC - P7 VCC - G11 VCCIO0 0 G11 VCCIO0 0 G11 VCCIO0 0 H10 VCCIO0 0 H10 VCCIO0 0 H10 VCCIO0 0 H11 VCCIO0 0 H11 VCCIO0 0 H11 VCCIO0 0 H9 VCCIO0 0 H9 VCCIO0 0 H9 VCCIO0 0 G12 VCCIO1 1 G12 VCCIO1 1 G12 VCCIO1 1 H12 VCCIO1 1 H12 VCCIO1 1 H12 VCCIO1 1 H13 VCCIO1 1 H13 VCCIO1 1 H13 VCCIO1 1 H14 VCCIO1 1 H14 VCCIO1 1 H14 VCCIO1 1 J15 VCCIO2 2 J15 VCCIO2 2 J15 VCCIO2 2 K15 VCCIO2 2 K15 VCCIO2 2 K15 VCCIO2 2 L15 VCCIO2 2 L15 VCCIO2 2 L15 VCCIO2 2 L16 VCCIO2 2 L16 VCCIO2 2 L16 VCCIO2 2 M15 VCCIO3 3 M15 VCCIO3 3 M15 VCCIO3 3 M16 VCCIO3 3 M16 VCCIO3 3 M16 VCCIO3 3 N15 VCCIO3 3 N15 VCCIO3 3 N15 VCCIO3 3 P15 VCCIO3 3 P15 VCCIO3 3 P15 VCCIO3 3 R12 VCCIO4 4 R12 VCCIO4 4 R12 VCCIO4 4 R13 VCCIO4 4 R13 VCCIO4 4 R13 VCCIO4 4 R14 VCCIO4 4 R14 VCCIO4 4 R14 VCCIO4 4 T12 VCCIO4 4 T12 VCCIO4 4 T12 VCCIO4 4 R10 VCCIO5 5 R10 VCCIO5 5 R10 VCCIO5 5 R11 VCCIO5 5 R11 VCCIO5 5 R11 VCCIO5 5 R9 VCCIO5 5 R9 VCCIO5 5 R9 VCCIO5 5 4-47 Dual Function Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections: 484 fpBGA (Cont.) LFECP6/LFEC6 Ball Number Ball Function Bank LVDS LFECP10/LFEC10 Dual Function Ball Number Ball Function Bank LVDS LFECP/LFEC15 Dual Function Ball Number Ball Function Bank LVDS T11 VCCIO5 5 T11 VCCIO5 5 T11 VCCIO5 5 M7 VCCIO6 6 M7 VCCIO6 6 M7 VCCIO6 6 M8 VCCIO6 6 M8 VCCIO6 6 M8 VCCIO6 6 N8 VCCIO6 6 N8 VCCIO6 6 N8 VCCIO6 6 P8 VCCIO6 6 P8 VCCIO6 6 P8 VCCIO6 6 J8 VCCIO7 7 J8 VCCIO7 7 J8 VCCIO7 7 K8 VCCIO7 7 K8 VCCIO7 7 K8 VCCIO7 7 L7 VCCIO7 7 L7 VCCIO7 7 L7 VCCIO7 7 L8 VCCIO7 7 L8 VCCIO7 7 L8 VCCIO7 7 G15 VCCAUX - G15 VCCAUX - G15 VCCAUX - G16 VCCAUX - G16 VCCAUX - G16 VCCAUX - G7 VCCAUX - G7 VCCAUX - G7 VCCAUX - G8 VCCAUX - G8 VCCAUX - G8 VCCAUX - H16 VCCAUX - H16 VCCAUX - H16 VCCAUX - H7 VCCAUX - H7 VCCAUX - H7 VCCAUX - R16 VCCAUX - R16 VCCAUX - R16 VCCAUX - R7 VCCAUX - R7 VCCAUX - R7 VCCAUX - T15 VCCAUX - T15 VCCAUX - T15 VCCAUX - T16 VCCAUX - T16 VCCAUX - T16 VCCAUX - T7 VCCAUX - T7 VCCAUX - T7 VCCAUX - T8 VCCAUX - T8 VCCAUX - T8 VCCAUX - J6 VCC - J6 VCC - J6 VCC - J17 VCC - J17 VCC - J17 VCC - P6 VCC - P6 VCC - P6 VCC - P17 VCC - P17 VCC - P17 VCC - A2 NC - A2 NC - A2 NC - AB2 NC - AB2 NC - AB2 NC - A21 NC - A21 NC - A21 NC - 4-48 Dual Function Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number Ball Function Bank LVDS LFECP/LFEC33 Dual Function Ball Number Ball Function Bank LVDS Dual Function GND GND7 7 GND GND7 7 D4 PL2A 7 T VREF2_7 D4 PL2A 7 T VREF2_7 E4 PL2B 7 C VREF1_7 E4 PL2B 7 C VREF1_7 GND - - GND GND7 7 C3 PL3A 7 T C3 PL10A 7 T B2 PL3B 7 C B2 PL10B 7 C E5 PL4A 7 T E5 PL11A 7 T F5 PL4B 7 C F5 PL11B 7 C D3 PL5A 7 T D3 PL12A 7 T C2 PL5B 7 C C2 PL12B 7 C GND - - GND GND7 7 F4 PL14A 7 T G4 PL14B 7 C F4 PL6A 7 T G4 PL6B 7 C LDQS6 LDQS14 E3 PL7A 7 T E3 PL15A 7 T D2 PL7B 7 C D2 PL15B 7 C B1 PL8A 7 T LUM0_PLLT_IN_A B1 PL16A 7 T C1 PL8B 7 C LUM0_PLLC_IN_A C1 PL16B 7 C LUM0_PLLC_IN_A F3 PL9A 7 T LUM0_PLLT_FB_A F3 PL17A 7 T LUM0_PLLT_FB_A GND GND7 7 GND GND7 7 E2 PL17B 7 C LUM0_PLLC_FB_A GND GND7 7 LDQS23 E2 PL9B 7 GND - - C LUM0_PLLC_FB_A G5 PL11A 7 T G5 PL23A 7 T H6 PL11B 7 C H6 PL23B 7 C G3 PL12A 7 T G3 PL24A 7 T C H4 PL12B 7 C H4 PL24B 7 J5 PL13A 7 T J5 PL25A 7 T H5 PL13B 7 C H5 PL25B 7 C F2 PL14A 7 T T GND GND7 7 F2 PL26A 7 GND GND7 7 F1 PL14B 7 C F1 PL26B 7 E1 PL15A 7 T E1 PL27A 7 T D1 PL15B 7 C D1 PL27B 7 C C H3 PL16A 7 T H3 PL28A 7 T G2 PL16B 7 C G2 PL28B 7 C H2 PL17A 7 T H2 PL29A 7 T G1 PL17B 7 C G1 PL29B 7 C J4 PL18A 7 T J4 PL30A 7 T GND GND7 7 J3 PL18B 7 C J2 PL19A 7 T LDQS19 GND GND7 7 J3 PL30B 7 C J2 PL31A 7 T C H1 PL19B 7 C H1 PL31B 7 K4 PL20A 7 T K4 PL32A 7 T K5 PL20B 7 C K5 PL32B 7 C K3 PL21A 7 T K3 PL33A 7 T 4-49 LUM0_PLLT_IN_A LDQS31 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number Ball Function Bank LVDS K2 PL21B 7 C T J1 PL22A 7 GND GND7 7 K1 PL22B 7 C LFECP/LFEC33 Dual Function Ball Number Ball Function Bank LVDS PCLKT7_0 PCLKC7_0 PL33B 7 C T PCLKT7_0 C PCLKC7_0 J1 PL34A 7 GND GND7 7 K1 PL34B 7 L3 XRES 6 L3 XRES 6 L4 PL24A 6 T L4 PL36A 6 T L5 PL24B 6 C L5 PL36B 6 C L2 PL25A 6 T L2 PL37A 6 T L1 PL25B 6 C L1 PL37B 6 C M4 PL26A 6 T M4 PL38A 6 T M5 PL26B 6 C M5 PL38B 6 C M1 PL27A 6 T M1 PL39A 6 T GND GND6 6 M2 PL27B 6 C N3 PL28A 6 T M3 PL28B 6 N5 PL29A 6 N4 PL29B N1 PL30A N2 GND GND6 6 M2 PL39B 6 C N3 PL40A 6 T C M3 PL40B 6 C T N5 PL41A 6 T 6 C N4 PL41B 6 C 6 T N1 PL42A 6 T PL30B 6 C N2 PL42B 6 C T T P1 PL31A 6 GND GND6 6 P2 PL31B 6 LDQS28 P1 PL43A 6 GND GND6 6 C P2 PL43B 6 PL32A 6 T R6 PL44A 6 T P5 PL32B 6 C P5 PL44B 6 C P3 PL33A 6 T P3 PL45A 6 T P4 PL33B 6 C P4 PL45B 6 C R1 PL34A 6 T R1 PL46A 6 T R2 PL34B 6 C R2 PL46B 6 C R5 PL35A 6 T R5 PL47A 6 T GND GND6 6 GND GND6 6 R4 PL47B 6 C T1 PL48A 6 T C PL35B 6 C T1 PL36A 6 T LDQS36 LDQS40 C R6 R4 Dual Function K2 LDQS48 T2 PL36B 6 C T2 PL48B 6 R3 PL37A 6 T R3 PL49A 6 T T3 PL37B 6 C T3 PL49B 6 C GND GND6 6 GND GND6 6 T5 TCK 6 T5 TCK 6 U5 TDI 6 U5 TDI 6 T4 TMS 6 T4 TMS 6 U1 TDO 6 U1 TDO 6 U2 VCCJ 6 U2 VCCJ 6 V1 PL41A 6 T LLM0_PLLT_IN_A V1 PL53A 6 T LLM0_PLLT_IN_A V2 PL41B 6 C LLM0_PLLC_IN_A V2 PL53B 6 C LLM0_PLLC_IN_A 4-50 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number Ball Function Bank LVDS LFECP/LFEC33 Dual Function Ball Number Ball Function Bank LVDS U3 PL42A 6 T LLM0_PLLT_FB_A LLM0_PLLC_FB_A PL54A 6 T LLM0_PLLT_FB_A LLM0_PLLC_FB_A V3 PL42B 6 C V3 PL54B 6 C U4 PL43A 6 T U4 PL55A 6 T V5 PL43B 6 C V5 PL55B 6 C T T W1 PL44A 6 GND GND6 6 W2 PL44B 6 Y1 PL45A 6 T Y2 PL45B 6 C AA1 PL46A 6 T AA1 PL58A 6 T AA2 PL46B 6 C AA2 PL58B 6 C W4 PL47A 6 T W4 PL59A 6 T C C LDQS45 Dual Function U3 W1 PL56A 6 GND GND6 6 W2 PL56B 6 C Y1 PL57A 6 T Y2 PL57B 6 C LDQS57 V4 PL47B 6 C V4 PL59B 6 W3 PL48A 6 T VREF1_6 W3 PL68A 6 T VREF1_6 Y3 PL48B 6 C VREF2_6 Y3 PL68B 6 C VREF2_6 GND GND6 6 GND GND6 6 GND GND5 5 GND GND6 6 GND - GND GND6 6 GND - GND GND5 5 GND GND5 5 GND GND5 5 V7 PB10A 5 T V7 PB10A 5 T T6 PB10B 5 C T6 PB10B 5 C V8 PB11A 5 T V8 PB11A 5 T U7 PB11B 5 C U7 PB11B 5 C W5 PB12A 5 T W5 PB12A 5 T U6 PB12B 5 C U6 PB12B 5 C AA3 PB13A 5 T AA3 PB13A 5 T GND GND5 5 GND GND5 5 AB3 PB13B 5 C AB3 PB13B 5 Y6 PB14A 5 T Y6 PB14A 5 T V6 PB14B 5 C V6 PB14B 5 C AA5 PB15A 5 T AA5 PB15A 5 T W6 PB15B 5 C W6 PB15B 5 C Y5 PB16A 5 T Y5 PB16A 5 T Y4 PB16B 5 C Y4 PB16B 5 C AA4 PB17A 5 T AA4 PB17A 5 T BDQS14 C GND GND5 5 GND GND5 5 AB4 PB17B 5 C AB4 PB17B 5 C Y7 PB18A 5 T Y7 PB18A 5 T W8 PB18B 5 C W8 PB18B 5 C W7 PB19A 5 T W7 PB19A 5 T C U8 PB19B 5 C U8 PB19B 5 W9 PB20A 5 T W9 PB20A 5 T U9 PB20B 5 C U9 PB20B 5 C 4-51 BDQS14 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number Y8 Ball Function Bank LVDS PB21A 5 LFECP/LFEC33 Dual Function Ball Number Ball Function Bank LVDS T GND GND5 5 Y9 PB21B 5 C V9 PB22A 5 T Y8 BDQS22 PB21A 5 GND GND5 5 Y9 PB21B 5 C V9 PB22A 5 T C T9 PB22B 5 C T9 PB22B 5 W10 PB23A 5 T W10 PB23A 5 T U10 PB23B 5 C U10 PB23B 5 C V10 PB24A 5 T V10 PB24A 5 T T10 PB24B 5 C T10 PB24B 5 C T T AA6 PB25A 5 GND GND5 5 AB5 PB25B 5 AA8 PB26A 5 T AA8 PB26A 5 T AA7 PB26B 5 C AA7 PB26B 5 C AB6 PB27A 5 T AB6 PB27A 5 T AB7 PB27B 5 C AB7 PB27B 5 C Y10 PB28A 5 T Y10 PB28A 5 T W11 PB28B 5 C W11 PB28B 5 C AB8 PB29A 5 T AB8 PB29A 5 T GND GND5 5 GND GND5 5 C AB9 PB29B 5 C AA10 PB30A 5 T AA9 PB30B 5 C BDQS30 AA6 PB25A 5 GND GND5 5 AB5 PB25B 5 Dual Function T BDQS22 C AB9 PB29B 5 AA10 PB30A 5 C T AA9 PB30B 5 C BDQS30 Y11 PB31A 5 T Y11 PB31A 5 T AA11 PB31B 5 C AA11 PB31B 5 C V11 PB32A 5 T VREF2_5 V11 PB32A 5 T VREF2_5 V12 PB32B 5 C VREF1_5 V12 PB32B 5 C VREF1_5 AB10 PB33A 5 T PCLKT5_0 AB10 PB33A 5 T PCLKT5_0 GND GND5 5 GND GND5 5 AB11 PB33B 5 C PCLKC5_0 AB11 PB33B 5 C PCLKC5_0 Y12 PB34A 4 T WRITEN Y12 PB34A 4 T WRITEN U11 PB34B 4 C CS1N U11 PB34B 4 C CS1N W12 PB35A 4 T VREF1_4 W12 PB35A 4 T VREF1_4 U12 PB35B 4 C CSN U12 PB35B 4 C CSN W13 PB36A 4 T VREF2_4 W13 PB36A 4 T VREF2_4 U13 PB36B 4 C D0/SPID7 U13 PB36B 4 C D0/SPID7 AA12 PB37A 4 T D2/SPID5 AA12 PB37A 4 T D2/SPID5 GND GND4 4 GND GND4 4 AB12 PB37B 4 AB12 PB37B 4 C D1/SPID6 C D1/SPID6 T13 PB38A 4 T BDQS38 T13 PB38A 4 T BDQS38 V13 PB38B 4 C D3/SPID4 V13 PB38B 4 C D3/SPID4 W14 PB39A 4 T U14 PB39B 4 C Y13 PB40A 4 T D4/SPID3 4-52 W14 PB39A 4 T U14 PB39B 4 C Y13 PB40A 4 T D4/SPID3 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number Ball Function Bank LVDS V14 PB40B AA13 GND LFECP/LFEC33 Dual Function Ball Number Ball Function Bank LVDS 4 C PB41A 4 T GND4 4 AB13 PB41B 4 AA14 PB42A 4 T AA14 PB42A 4 T Y14 PB42B 4 C Y14 PB42B 4 C Y15 PB43A 4 T Y15 PB43A 4 T W15 PB43B 4 C W15 PB43B 4 C V15 PB44A 4 T V15 PB44A 4 T C D5/SPID2 D6/SPID1 V14 PB40B 4 C AA13 GND PB41A 4 T GND4 4 AB13 PB41B 4 C T14 PB44B 4 C T14 PB44B 4 C AB14 PB45A 4 T AB14 PB45A 4 T GND GND4 4 GND GND4 4 AB15 PB45B 4 C AB15 PB45B 4 AB16 PB46A 4 T AB16 PB46A 4 T AA15 PB46B 4 C AA15 PB46B 4 C AB17 PB47A 4 T AB17 PB47A 4 T AA16 PB47B 4 C AA16 PB47B 4 C AB18 PB48A 4 T AB18 PB48A 4 T AA17 PB48B 4 C AA17 PB48B 4 C AB19 PB49A 4 T AB19 PB49A 4 T BDQS46 GND GND4 4 GND GND4 4 PB49B 4 C AA18 PB49B 4 C W16 PB50A 4 T W16 PB50A 4 T U15 PB50B 4 C U15 PB50B 4 C V16 PB51A 4 T V16 PB51A 4 T C U16 PB51B 4 C U16 PB51B 4 Y17 PB52A 4 T Y17 PB52A 4 T V17 PB52B 4 C V17 PB52B 4 C AB20 PB53A 4 T AB20 PB53A 4 T GND GND4 4 GND GND4 4 AA19 PB53B 4 AA19 PB53B 4 BDQS54 Y16 PB54A 4 T Y16 PB54A 4 T PB54B 4 C W17 PB54B 4 C AA20 PB55A 4 T AA20 PB55A 4 T Y19 PB55B 4 C Y19 PB55B 4 C Y18 PB56A 4 T Y18 PB56A 4 T W18 PB56B 4 C W18 PB56B 4 C T17 PB57A 4 T T17 PB57A 4 T U17 PB57B 4 C U17 PB57B 4 C - - GND GND4 4 GND GND4 4 GND GND4 4 GND GND3 3 GND GND4 4 GND - - GND GND3 3 W20 PR48B 3 W20 PR68B 3 C VREF2_3 4-53 D6/SPID1 BDQS46 C W17 GND D5/SPID2 C AA18 C Dual Function C BDQS54 VREF2_3 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number Ball Function Bank LVDS Y20 PR48A 3 GND - GND - AA21 PR47B 3 AB21 PR47A W19 PR46B V19 T LFECP/LFEC33 Dual Function Ball Number Ball Function Bank LVDS VREF1_3 Y20 PR68A 3 - GND GND3 3 - GND GND3 3 C AA21 PR59B 3 3 T AB21 PR59A 3 T 3 C W19 PR58B 3 C PR46A 3 T V19 PR58A 3 T Y21 PR45B 3 C AA22 PR45A 3 T RDQS45 C RLM0_PLLC_IN_A V20 PR44B 3 GND GND3 3 U20 PR44A 3 T W21 PR43B 3 Y22 PR43A 3 V21 PR42B 3 T Dual Function VREF1_3 C Y21 PR57B 3 C AA22 PR57A 3 T RDQS57 C RLM0_PLLC_IN_A V20 PR56B 3 GND GND3 3 RLM0_PLLT_IN_A U20 PR56A 3 T RLM0_PLLT_IN_A C RLM0_PLLC_FB_A W21 PR55B 3 C RLM0_PLLC_FB_A T RLM0_PLLT_FB_A Y22 PR55A 3 T RLM0_PLLT_FB_A C DI/CSSPIN V21 PR54B 3 C DI/CSSPIN W22 PR42A 3 T DOUT/CSON W22 PR54A 3 T DOUT/CSON U21 PR41B 3 C BUSY/SISPI U21 PR53B 3 C BUSY/SISPI V22 PR41A 3 T D7/SPID0 V22 PR53A 3 T D7/SPID0 T19 CFG2 3 T19 CFG2 3 U19 CFG1 3 U19 CFG1 3 U18 CFG0 3 U18 CFG0 3 V18 PROGRAMN 3 V18 PROGRAMN 3 T20 CCLK 3 T20 CCLK 3 T21 INITN 3 T21 INITN 3 R20 DONE 3 R20 DONE 3 GND GND3 3 GND GND3 3 T18 PR37B 3 C T18 PR49B 3 C R17 PR37A 3 T R17 PR49A 3 T R19 PR36B 3 C R19 PR48B 3 C R18 PR36A 3 T R18 PR48A 3 T U22 PR35B 3 C U22 PR47B 3 C GND GND3 3 GND GND3 3 T22 PR35A 3 T T22 PR47A 3 T R21 PR34B 3 C R21 PR46B 3 C R22 PR34A 3 T R22 PR46A 3 T P20 PR33B 3 C P20 PR45B 3 C N20 PR33A 3 T N20 PR45A 3 T P19 PR32B 3 C P19 PR44B 3 C P18 PR32A 3 T P18 PR44A 3 T C P21 PR43B 3 C GND GND3 3 P21 PR31B 3 GND GND3 3 RDQS36 P22 PR31A 3 T P22 PR43A 3 T N21 PR30B 3 C N21 PR42B 3 C N22 PR30A 3 T N22 PR42A 3 T 4-54 RDQS48 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number Ball Function Bank LVDS N19 PR29B 3 LFECP/LFEC33 Dual Function Ball Number Ball Function Bank LVDS C N19 PR41B 3 N18 PR29A 3 T N18 PR41A 3 T M21 PR28B 3 C M21 PR40B 3 C L20 PR28A 3 T L20 PR40A 3 T C C L21 PR27B 3 GND GND3 3 M20 PR27A 3 M18 PR26B M19 PR26A M22 L22 RDQS28 L21 PR39B 3 GND GND3 3 T M20 PR39A 3 T 3 C M18 PR38B 3 C 3 T M19 PR38A 3 T PR25B 3 C M22 PR37B 3 C PR25A 3 T L22 PR37A 3 T K22 PR24B 3 C K22 PR36B 3 C K21 PR24A 3 T J22 PR22B 2 C GND GND2 2 PCLKC2_0 PCLKT2_0 RDQS40 K21 PR36A 3 T J22 PR34B 2 C PCLKC2_0 GND GND2 2 PCLKT2_0 J21 PR22A 2 T J21 PR34A 2 T H22 PR21B 2 C H22 PR33B 2 C H21 PR21A 2 T H21 PR33A 2 T L19 PR20B 2 C L19 PR32B 2 C L18 PR20A 2 T L18 PR32A 2 T K20 PR19B 2 C C J20 PR19A 2 T K19 PR18B 2 C RDQS19 Dual Function C K20 PR31B 2 J20 PR31A 2 T K19 PR30B 2 C GND GND2 2 GND GND2 2 K18 PR18A 2 T K18 PR30A 2 T G22 PR17B 2 C G22 PR29B 2 C F22 PR17A 2 T F22 PR29A 2 T F21 PR16B 2 C F21 PR28B 2 C E22 PR16A 2 T E22 PR28A 2 T E21 PR15B 2 C E21 PR27B 2 C D22 PR15A 2 T D22 PR27A 2 T G21 PR14B 2 C G21 PR26B 2 C G20 PR14A 2 T G20 PR26A 2 T GND GND2 2 GND GND2 2 J18 PR13B 2 C J18 PR25B 2 C H19 PR13A 2 T H19 PR25A 2 T C J19 PR12B 2 C J19 PR24B 2 H20 PR12A 2 T H20 PR24A 2 T H17 PR11B 2 C H17 PR23B 2 C H18 PR11A 2 T D21 PR9B 2 C GND GND2 GND - C22 PR9A 2 RDQS31 H18 PR23A 2 T RDQS23 D21 PR17B 2 C RUM0_PLLC_FB_A 2 GND GND2 2 - GND GND2 2 C22 PR17A 2 T RUM0_PLLT_FB_A T RUM0_PLLC_FB_A RUM0_PLLT_FB_A 4-55 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number Ball Function Bank LVDS G19 PR8B 2 G18 PR8A F20 PR7B F19 LFECP/LFEC33 Dual Function Ball Number Ball Function Bank LVDS C RUM0_PLLC_IN_A G19 PR16B 2 2 T RUM0_PLLT_IN_A G18 PR16A 2 C F20 PR15B PR7A 2 T F19 PR15A E20 PR6B 2 C D20 PR6A 2 T C21 PR5B 2 C GND - - C20 PR5A 2 T RDQS6 RUM0_PLLC_IN_A 2 T RUM0_PLLT_IN_A 2 C 2 T C E20 PR14B 2 D20 PR14A 2 T C21 PR13B 2 C GND GND2 2 C20 PR13A 2 T C F18 PR4B 2 C F18 PR12B 2 E18 PR4A 2 T E18 PR12A 2 T B22 PR3B 2 C B22 PR11B 2 C T T B21 PR3A 2 GND - - E19 PR2B 2 C VREF1_2 T VREF2_2 B21 PR11A 2 GND2 2 E19 PR2B 2 C VREF1_2 T VREF2_2 D19 PR2A 2 D19 PR2A 2 GND2 2 GND GND2 2 GND GND1 1 GND GND1 1 GND - - GND GND1 1 G17 PT57B 1 G17 PT57B 1 C GND - - GND GND1 1 F17 PT57A 1 T F17 PT57A 1 T D18 PT56B 1 C D18 PT56B 1 C C18 PT56A 1 T C18 PT56A 1 T C19 PT55B 1 C C19 PT55B 1 C B20 PT55A 1 T B20 PT55A 1 T D17 PT54B 1 C D17 PT54B 1 C C16 PT54A 1 T C16 PT54A 1 T C C B19 PT53B 1 GND GND1 1 A20 PT53A 1 T TDQS54 B19 PT53B 1 GND GND1 1 A20 PT53A 1 T E17 PT52B 1 C E17 PT52B 1 C C17 PT52A 1 T C17 PT52A 1 T C F16 PT51B 1 C F16 PT51B 1 E16 PT51A 1 T E16 PT51A 1 T F15 PT50B 1 C F15 PT50B 1 C D16 PT50A 1 T D16 PT50A 1 T B18 PT49B 1 C B18 PT49B 1 C GND GND1 1 GND GND1 1 A19 PT49A 1 T A19 PT49A 1 T B17 PT48B 1 C B17 PT48B 1 C A18 PT48A 1 T A18 PT48A 1 T B16 PT47B 1 C B16 PT47B 1 C A17 PT47A 1 T A17 PT47A 1 T 4-56 RDQS14 GND GND C Dual Function C TDQS54 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number Ball Function Bank LVDS B15 PT46B 1 A16 PT46A 1 T A15 PT45B 1 C GND GND1 1 LFECP/LFEC33 Dual Function Ball Number Ball Function Bank LVDS C TDQS46 B15 PT46B 1 A16 PT46A 1 T A15 PT45B 1 C GND GND1 1 A14 PT45A 1 T A14 PT45A 1 T G14 PT44B 1 C G14 PT44B 1 C E15 PT44A 1 T E15 PT44A 1 T D15 PT43B 1 C D15 PT43B 1 C C15 PT43A 1 T C15 PT43A 1 T C14 PT42B 1 C C14 PT42B 1 C B14 PT42A 1 T B14 PT42A 1 T A13 PT41B 1 C A13 PT41B 1 C GND GND1 1 GND GND1 1 B13 PT41A 1 T B13 PT41A 1 T E14 PT40B 1 C E14 PT40B 1 C C13 PT40A 1 T C13 PT40A 1 T F14 PT39B 1 C F14 PT39B 1 C D14 PT39A 1 T D14 PT39A 1 T E13 PT38B 1 C E13 PT38B 1 C G13 PT38A 1 T G13 PT38A 1 T C C A12 PT37B 1 GND GND1 1 B12 PT37A 1 T TDQS38 Dual Function C A12 PT37B 1 GND GND1 1 B12 PT37A 1 T F13 PT36B 1 C F13 PT36B 1 C D13 PT36A 1 T D13 PT36A 1 T TDQS46 TDQS38 F12 PT35B 1 C VREF2_1 F12 PT35B 1 C VREF2_1 D12 PT35A 1 T VREF1_1 D12 PT35A 1 T VREF1_1 F11 PT34B 1 C F11 PT34B 1 C C12 PT34A 1 T A11 PT33B 0 C GND GND0 0 A10 PT33A 0 T PCLKT0_0 A10 PT33A E12 PT32B 0 C VREF1_0 E12 PT32B E11 PT32A 0 T VREF2_0 E11 PT32A B11 PT31B 0 C B11 PT31B C11 PT31A 0 T C11 PCLKC0_0 C12 PT34A 1 T A11 PT33B 0 C PCLKC0_0 GND GND0 0 0 T PCLKT0_0 0 C VREF1_0 0 T VREF2_0 0 C PT31A 0 T C B9 PT30B 0 C B10 PT30A 0 T A9 PT29B 0 C GND GND0 0 GND GND0 0 A8 PT29A 0 T A8 PT29A 0 T D11 PT28B 0 C D11 PT28B 0 C C10 PT28A 0 T C10 PT28A 0 T A7 PT27B 0 C A7 PT27B 0 C TDQS30 4-57 B9 PT30B 0 B10 PT30A 0 T A9 PT29B 0 C TDQS30 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number Ball Function Bank LVDS LFECP/LFEC33 Dual Function Ball Number Ball Function Bank LVDS A6 PT27A 0 T A6 PT27A 0 T B7 PT26B 0 C B7 PT26B 0 C B8 PT26A 0 T B8 PT26A 0 T A5 PT25B 0 C A5 PT25B 0 C GND GND0 0 GND GND0 0 B6 PT25A 0 T B6 PT25A 0 T G10 PT24B 0 C G10 PT24B 0 C E10 PT24A 0 T E10 PT24A 0 T F10 PT23B 0 C F10 PT23B 0 C D10 PT23A 0 T D10 PT23A 0 T G9 PT22B 0 C G9 PT22B 0 C E9 PT22A 0 T E9 PT22A 0 T C C C9 PT21B 0 GND GND0 0 C8 PT21A 0 T TDQS22 C9 PT21B 0 GND GND0 0 C8 PT21A 0 T F9 PT20B 0 C F9 PT20B 0 C D9 PT20A 0 T D9 PT20A 0 T C F8 PT19B 0 C F8 PT19B 0 D7 PT19A 0 T D7 PT19A 0 T D8 PT18B 0 C D8 PT18B 0 C T T C7 PT18A 0 GND GND0 0 A4 PT17B 0 C C7 PT18A 0 GND GND0 0 A4 PT17B 0 B4 PT17A 0 T B4 PT17A 0 T PT16B 0 C C4 PT16B 0 C C5 PT16A 0 T C5 PT16A 0 T D6 PT15B 0 C D6 PT15B 0 C B5 PT15A 0 T B5 PT15A 0 T C E6 PT14B 0 C PT14A 0 T A3 PT13B 0 C GND GND0 0 B3 PT13A 0 T TDQS14 E6 PT14B 0 C6 PT14A 0 T A3 PT13B 0 C GND GND0 0 B3 PT13A 0 T C F6 PT12B 0 C F6 PT12B 0 D5 PT12A 0 T D5 PT12A 0 T F7 PT11B 0 C F7 PT11B 0 C E8 PT11A 0 T E8 PT11A 0 T G6 PT10B 0 C G6 PT10B 0 C E7 PT10A 0 T E7 PT10A 0 T GND GND0 0 GND GND0 0 GND GND0 0 GND GND0 0 - A1 GND - A1 GND A22 GND - A22 GND - AB1 GND - AB1 GND - 4-58 TDQS22 C C4 C6 Dual Function TDQS14 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number Ball Function Bank LVDS LFECP/LFEC33 Dual Function Ball Number Ball Function Bank LVDS AB22 GND - AB22 GND - H15 GND - H15 GND - H8 GND - H8 GND - J10 GND - J10 GND - J11 GND - J11 GND - J12 GND - J12 GND - J13 GND - J13 GND - J14 GND - J14 GND - J9 GND - J9 GND - K10 GND - K10 GND - K11 GND - K11 GND - K12 GND - K12 GND - K13 GND - K13 GND - K14 GND - K14 GND - K9 GND - K9 GND - L10 GND - L10 GND - L11 GND - L11 GND - L12 GND - L12 GND - L13 GND - L13 GND - L14 GND - L14 GND - L9 GND - L9 GND - M10 GND - M10 GND - M11 GND - M11 GND - M12 GND - M12 GND - M13 GND - M13 GND - M14 GND - M14 GND - M9 GND - M9 GND - N10 GND - N10 GND - N11 GND - N11 GND - N12 GND - N12 GND - N13 GND - N13 GND - N14 GND - N14 GND - N9 GND - N9 GND - P10 GND - P10 GND - P11 GND - P11 GND - P12 GND - P12 GND - P13 GND - P13 GND - P14 GND - P14 GND - P9 GND - P9 GND - R15 GND - R15 GND - R8 GND - R8 GND - J16 VCC - J16 VCC - J7 VCC - J7 VCC - K16 VCC - K16 VCC - 4-59 Dual Function Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number Ball Function Bank LVDS LFECP/LFEC33 Dual Function Ball Number Ball Function Bank LVDS K17 VCC - K17 VCC - K6 VCC - K6 VCC - K7 VCC - K7 VCC - L17 VCC - L17 VCC - L6 VCC - L6 VCC - M17 VCC - M17 VCC - M6 VCC - M6 VCC - N16 VCC - N16 VCC - N17 VCC - N17 VCC - N6 VCC - N6 VCC - N7 VCC - N7 VCC - P16 VCC - P16 VCC - P7 VCC - P7 VCC - G11 VCCIO0 0 G11 VCCIO0 0 H10 VCCIO0 0 H10 VCCIO0 0 H11 VCCIO0 0 H11 VCCIO0 0 H9 VCCIO0 0 H9 VCCIO0 0 G12 VCCIO1 1 G12 VCCIO1 1 H12 VCCIO1 1 H12 VCCIO1 1 H13 VCCIO1 1 H13 VCCIO1 1 H14 VCCIO1 1 H14 VCCIO1 1 J15 VCCIO2 2 J15 VCCIO2 2 K15 VCCIO2 2 K15 VCCIO2 2 L15 VCCIO2 2 L15 VCCIO2 2 L16 VCCIO2 2 L16 VCCIO2 2 M15 VCCIO3 3 M15 VCCIO3 3 M16 VCCIO3 3 M16 VCCIO3 3 N15 VCCIO3 3 N15 VCCIO3 3 P15 VCCIO3 3 P15 VCCIO3 3 R12 VCCIO4 4 R12 VCCIO4 4 R13 VCCIO4 4 R13 VCCIO4 4 R14 VCCIO4 4 R14 VCCIO4 4 T12 VCCIO4 4 T12 VCCIO4 4 R10 VCCIO5 5 R10 VCCIO5 5 R11 VCCIO5 5 R11 VCCIO5 5 R9 VCCIO5 5 R9 VCCIO5 5 T11 VCCIO5 5 T11 VCCIO5 5 M7 VCCIO6 6 M7 VCCIO6 6 M8 VCCIO6 6 M8 VCCIO6 6 N8 VCCIO6 6 N8 VCCIO6 6 P8 VCCIO6 6 P8 VCCIO6 6 J8 VCCIO7 7 J8 VCCIO7 7 K8 VCCIO7 7 K8 VCCIO7 7 L7 VCCIO7 7 L7 VCCIO7 7 4-60 Dual Function Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA LFECP20/LFEC20 Ball Number Ball Function Bank LVDS LFECP/LFEC33 Dual Function Ball Number Ball Function Bank LVDS L8 VCCIO7 7 L8 VCCIO7 7 G15 VCCAUX - G15 VCCAUX - G16 VCCAUX - G16 VCCAUX - G7 VCCAUX - G7 VCCAUX - G8 VCCAUX - G8 VCCAUX H16 VCCAUX - H16 VCCAUX - H7 VCCAUX - H7 VCCAUX - R16 VCCAUX - R16 VCCAUX - R7 VCCAUX - R7 VCCAUX - T15 VCCAUX - T15 VCCAUX - T16 VCCAUX - T16 VCCAUX - T7 VCCAUX - T7 VCCAUX - T8 VCCAUX - T8 VCCAUX - J6 VCC1 - J6 VCCPLL - J17 VCC1 - J17 VCCPLL - P6 VCC 1 - P6 VCCPLL - P17 VCC1 - P17 VCCPLL - A2 NC - A2 NC - AB2 NC - AB2 NC - A21 NC - A21 NC - 1. Tied to VCCPLL. 4-61 Dual Function Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA LFEC20/LFECP20 LFECP/EC33 Ball Number Ball Function GND GND7 7 E3 PL2A 7 T VREF2_7 E4 PL2B 7 C VREF1_7 E4 E5 NC - E5 D5 NC - D5 F4 NC - F4 Bank LVDS Dual Function Ball Number Ball Function LVDS Dual Function GND GND7 7 E3 PL2A 7 T VREF2_7 PL2B 7 C VREF1_7 PL6A 7 T LDQS6 PL6B 7 C PL7A 7 T Bank F5 NC - F5 PL7B 7 C C3 NC - C3 PL8A 7 T D3 NC - D3 PL8B 7 C C2 NC - C2 PL9A 7 T - - - GND GND7 7 B2 NC - B2 PL9B 7 C B1 PL3A 7 T B1 PL10A 7 T C1 PL3B 7 C C1 PL10B 7 C F3 PL4A 7 T F3 PL11A 7 T G3 PL4B 7 C G3 PL11B 7 C D2 PL5A 7 T D2 PL12A 7 T E2 PL5B 7 C E2 PL12B 7 C - - - D1 PL6A 7 T GND GND7 7 D1 PL14A 7 T E1 PL6B 7 F2 PL7A 7 C E1 PL14B 7 C T F2 PL15A 7 T G2 PL7B 7 C F6 PL8A 7 T LDQS6 G2 PL15B 7 C LUM0_PLLT_IN_A F6 PL16A 7 T LDQS14 LUM0_PLLT_IN_A G6 PL8B 7 C LUM0_PLLC_IN_A G6 PL16B 7 C LUM0_PLLC_IN_A H4 PL9A 7 T LUM0_PLLT_FB_A H4 PL17A 7 T LUM0_PLLT_FB_A GND GND7 7 GND GND7 7 G4 PL9B 7 C LUM0_PLLC_FB_A G4 PL17B 7 C LUM0_PLLC_FB_A H6 NC - H6 PL19A 7 T J7 NC - J7 PL19B 7 C G5 NC - G5 PL20A 7 T H5 NC - H5 PL20B 7 C H3 NC - H3 PL21A 7 T J3 NC - J3 PL21B 7 C H2 NC - H2 PL22A 7 T - - - GND GND7 7 J2 NC - J4 PL11A 7 T J2 PL22B 7 C J4 PL23A 7 T J5 PL11B 7 C J5 PL23B 7 C K4 PL12A 7 T K4 PL24A 7 T K5 PL12B 7 C K5 PL24B 7 C J6 PL13A 7 T J6 PL25A 7 T 4-62 LDQS23 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number Ball Function K6 PL13B 7 C T Bank LVDS F1 PL14A 7 GND GND7 7 G1 PL14B 7 H1 PL15A 7 LFECP/EC33 Dual Function Ball Number Ball Function Bank LVDS K6 PL25B 7 C T F1 PL26A 7 GND GND7 7 C G1 PL26B 7 C T H1 PL27A 7 T J1 PL15B 7 C J1 PL27B 7 C K2 PL16A 7 T K2 PL28A 7 T K1 PL16B 7 C K1 PL28B 7 C K3 PL17A 7 T K3 PL29A 7 T L3 PL17B 7 C L3 PL29B 7 C L2 PL18A 7 T L2 PL30A 7 T GND GND7 7 L1 PL18B 7 M3 PL19A 7 T M4 PL19B 7 C M1 PL20A 7 T M1 PL32A 7 T M2 PL20B 7 C M2 PL32B 7 C L4 PL21A 7 T L4 PL33A 7 T L5 PL21B 7 C L5 PL33B 7 C T T PCLKT7_0 C PCLKC7_0 C LDQS19 GND7 7 L1 PL30B 7 C M3 PL31A 7 T M4 PL31B 7 C N2 PL22A 7 GND GND7 7 N1 PL22B 7 N3 XRES 6 P1 PL24A 6 T P1 PL36A 6 T P2 PL24B 6 C P2 PL36B 6 C L7 PL25A 6 T L7 PL37A 6 T L6 PL25B 6 C L6 PL37B 6 C N4 PL26A 6 T N4 PL38A 6 T N5 PL26B 6 C N5 PL38B 6 C R1 PL27A 6 T R1 PL39A 6 T GND GND6 6 GND GND6 6 C R2 PL27B 6 C P4 PL28A 6 T PCLKT7_0 GND Dual Function PCLKC7_0 LDQS28 N2 PL34A 7 GND GND7 7 N1 PL34B 7 N3 XRES 6 R2 PL39B 6 C P4 PL40A 6 T P3 PL28B 6 C P3 PL40B 6 C M5 PL29A 6 T M5 PL41A 6 T M6 PL29B 6 C M6 PL41B 6 C T1 PL30A 6 T T1 PL42A 6 T T2 PL30B 6 C T2 PL42B 6 C R4 PL31A 6 T R4 PL43A 6 T GND GND6 6 GND GND6 6 R3 PL31B 6 C R3 PL43B 6 C N6 PL32A 6 T N6 PL44A 6 T 4-63 LDQS31 LDQS40 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number Ball Function P5 PL32B 6 Bank LVDS LFECP/EC33 Dual Function Ball Number Ball Function Bank LVDS P5 PL44B 6 C C P6 PL33A 6 T P6 PL45A 6 T R5 PL33B 6 C R5 PL45B 6 C U1 PL34A 6 T U1 PL46A 6 T U2 PL34B 6 C U2 PL46B 6 C T3 PL35A 6 T T3 PL47A 6 T GND GND6 6 GND GND6 6 T4 PL35B 6 C R6 PL36A 6 T T4 PL47B 6 C R6 PL48A 6 T T5 PL36B 6 T6 PL37A 6 C T5 PL48B 6 C T T6 PL49A 6 T U5 PL37B U3 PL38A 6 C U5 PL49B 6 C 6 T U3 PL50A 6 T LDQS36 U4 PL38B 6 C U4 PL50B 6 C V1 PL39A 6 T V1 PL51A 6 T GND GND6 6 V2 PL39B 6 GND GND6 6 V2 PL51B 6 U7 TCK V4 TDI 6 U7 TCK 6 6 V4 TDI 6 V5 TMS V3 TDO 6 V5 TMS 6 6 V3 TDO 6 U6 VCCJ 6 W1 PL41A 6 T C Dual Function LDQS48 C U6 VCCJ 6 LLM0_PLLT_IN_A W1 PL53A 6 T LLM0_PLLT_IN_A W2 PL41B 6 C LLM0_PLLC_IN_A W2 PL53B 6 C LLM0_PLLC_IN_A V6 PL42A 6 T LLM0_PLLT_FB_A V6 PL54A 6 T LLM0_PLLT_FB_A LLM0_PLLC_FB_A W6 PL54B 6 C LLM0_PLLC_FB_A Y1 PL55A 6 T W6 PL42B 6 C Y1 PL43A 6 T Y2 PL43B 6 C Y2 PL55B 6 C W3 PL44A 6 T W3 PL56A 6 T GND GND6 6 W4 PL44B 6 AA1 PL45A 6 T AB1 PL45B 6 C Y4 PL46A 6 T Y4 PL58A 6 T Y3 PL46B 6 C Y3 PL58B 6 C C LDQS45 GND GND6 6 W4 PL56B 6 C AA1 PL57A 6 T AB1 PL57B 6 C AC1 PL47A 6 T AC1 PL59A 6 T AB2 PL47B 6 C AB2 PL59B 6 C AA2 NC - AA2 PL60A 6 T - - - GND GND6 6 AA3 NC - AA3 PL60B 6 C W5 NC - W5 PL61A 6 T Y5 NC - Y5 PL61B 6 C 4-64 LDQS57 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number Ball Function Y6 NC - Bank LVDS LFECP/EC33 Dual Function Ball Number Ball Function Bank LVDS Y6 PL62A 6 T W7 NC - W7 PL62B 6 C AA4 NC - AA4 PL63A 6 T AB3 NC - AB3 PL63B 6 C AC2 NC - AC2 PL64A 6 T - - - GND GND6 6 AC3 NC - AC3 PL64B 6 AA5 NC - AA5 PL65A 6 T AB5 NC - AB5 PL65B 6 C AD3 NC - AD3 PL66A 6 T AD2 NC - AD2 PL66B 6 C Dual Function C AE1 NC - AE1 PL67A 6 T AD1 NC - AD1 PL67B 6 C LDQS65 AB4 PL48A 6 T VREF1_6 AB4 PL68A 6 T VREF1_6 AC4 PL48B 6 C VREF2_6 AC4 PL68B 6 C VREF2_6 GND GND6 6 GND GND6 6 GND GND5 5 GND GND5 5 AB6 PB2A 5 T AB6 PB2A 5 T AA6 PB2B 5 C AA6 PB2B 5 C AC7 PB3A 5 T AC7 PB3A 5 T Y8 PB3B 5 C Y8 PB3B 5 C AB7 PB4A 5 T AB7 PB4A 5 T AA7 PB4B 5 C AA7 PB4B 5 C AC6 PB5A 5 T AC6 PB5A 5 T AC5 PB5B 5 C AC5 PB5B 5 C AB8 PB6A 5 T AC8 PB6B 5 C AB8 PB6A 5 T AC8 PB6B 5 C BDQS6 AE2 PB7A 5 T AE2 PB7A 5 T AA8 PB7B 5 C AA8 PB7B 5 C AF2 PB8A 5 T AF2 PB8A 5 T Y9 PB8B 5 C Y9 PB8B 5 C AD5 PB9A 5 T AD5 PB9A 5 T GND GND5 5 GND GND5 5 AD4 PB9B 5 C AD4 PB9B 5 C AD8 PB10A 5 T AD8 PB10A 5 T AC9 PB10B 5 C AC9 PB10B 5 C AE3 PB11A 5 T AE3 PB11A 5 T AB9 PB11B 5 C AB9 PB11B 5 C AF3 PB12A 5 T AF3 PB12A 5 T AD9 PB12B 5 C AD9 PB12B 5 C AE4 PB13A 5 T AE4 PB13A 5 T GND GND5 5 GND GND5 5 4-65 BDQS6 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 LFECP/EC33 Ball Number Ball Function AF4 PB13B 5 AE5 PB14A 5 T AE5 PB14A 5 T AA9 PB14B 5 C AA9 PB14B 5 C AF5 PB15A 5 T AF5 PB15A 5 T Y10 PB15B 5 C Y10 PB15B 5 C Bank LVDS Dual Function Ball Number Ball Function Bank LVDS AF4 PB13B 5 C C BDQS14 AD6 PB16A 5 T AD6 PB16A 5 T AC10 PB16B 5 C AC10 PB16B 5 C T T AF6 PB17A 5 GND GND5 5 AF6 PB17A 5 GND GND5 5 AE6 PB17B 5 AF7 PB18A 5 C AE6 PB17B 5 C T AF7 PB18A 5 T AB10 PB18B AE7 PB19A 5 C AB10 PB18B 5 C 5 T AE7 PB19A 5 T AD10 PB19B 5 C AD10 PB19B 5 C AD7 PB20A 5 T AD7 PB20A 5 T AA10 PB20B 5 C AA10 PB20B 5 C AF8 PB21A 5 T AF8 PB21A 5 T GND GND5 5 AF9 PB21B 5 C AD11 PB22A 5 T Y11 PB22B 5 C AE8 PB23A 5 AC11 PB23B 5 BDQS22 GND GND5 5 AF9 PB21B 5 PB22A 5 T Y11 PB22B 5 C T AE8 PB23A 5 T C AC11 PB23B 5 C AF10 PB24A 5 T AF10 PB24A 5 T AB11 PB24B 5 C AB11 PB24B 5 C AE10 PB25A 5 T AE10 PB25A 5 T GND GND5 5 GND GND5 5 AE9 PB25B 5 C AE9 PB25B 5 C AA11 PB26A 5 T AA11 PB26A 5 T Y12 PB26B 5 C Y12 PB26B 5 C AE11 PB27A 5 T AE11 PB27A 5 T AF11 PB27B 5 C AF11 PB27B 5 C AF12 PB28A 5 T AF12 PB28A 5 T AE12 PB28B 5 C AE12 PB28B 5 C AD12 PB29A 5 T AD12 PB29A 5 T GND GND5 5 C AC12 PB29B 5 GND GND5 5 AC12 PB29B 5 AA12 PB30A 5 T AA12 PB30A 5 T AB12 PB30B 5 C AB12 PB30B 5 C AE13 PB31A 5 T AE13 PB31A 5 T AF13 PB31B 5 C AF13 PB31B 5 C AD13 PB32A 5 T AD13 PB32A 5 T VREF2_5 4-66 BDQS14 C AD11 BDQS30 Dual Function BDQS22 C BDQS30 VREF2_5 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number Ball Function AC13 PB32B 5 AF14 PB33A 5 GND GND5 5 AE14 PB33B 5 C AA13 PB34A 4 T AB13 PB34B 4 AD14 PB35A LFECP/EC33 Dual Function Ball Number Ball Function Bank LVDS Dual Function C VREF1_5 AC13 PB32B 5 C VREF1_5 T PCLKT5_0 AF14 PB33A 5 T PCLKT5_0 GND GND5 5 PCLKC5_0 AE14 PB33B 5 C PCLKC5_0 WRITEN AA13 PB34A 4 T WRITEN C CS1N AB13 PB34B 4 C CS1N 4 T VREF1_4 AD14 PB35A 4 T VREF1_4 Bank LVDS AA14 PB35B 4 C CSN AA14 PB35B 4 C CSN AC14 PB36A 4 T VREF2_4 AC14 PB36A 4 T VREF2_4 AB14 PB36B 4 C D0/SPID7 AB14 PB36B 4 C D0/SPID7 AF15 PB37A 4 T D2/SPID5 AF15 PB37A 4 T D2/SPID5 GND GND4 4 C D1/SPID6 AE15 PB37B 4 C D1/SPID6 GND GND4 4 AE15 PB37B 4 AD15 PB38A 4 T BDQS38 AD15 PB38A 4 T BDQS38 AC15 PB38B 4 C D3/SPID4 AC15 PB38B 4 C D3/SPID4 AF16 PB39A 4 T Y14 PB39B 4 C AE16 PB40A 4 T AB15 PB40B 4 C AF17 PB41A 4 T GND GND4 4 AE17 PB41B 4 C Y15 PB42A 4 T AF16 PB39A 4 T Y14 PB39B 4 C AE16 PB40A 4 T AB15 PB40B 4 C AF17 PB41A 4 T GND GND4 4 D4/SPID3 D5/SPID2 D6/SPID1 AE17 PB41B 4 C Y15 PB42A 4 T AA15 PB42B 4 C AA15 PB42B 4 C AD17 PB43A 4 T AD17 PB43A 4 T Y16 PB43B 4 C Y16 PB43B 4 C AD18 PB44A 4 T AD18 PB44A 4 T AC16 PB44B 4 C AC16 PB44B 4 C AE18 PB45A 4 T AE18 PB45A 4 T GND GND4 4 C AF18 PB45B 4 GND GND4 4 AF18 PB45B 4 AD16 PB46A 4 T AB16 PB46B 4 C BDQS46 D5/SPID2 D6/SPID1 C AD16 PB46A 4 T AB16 PB46B 4 C AF19 PB47A 4 T AF19 PB47A 4 T AA16 PB47B 4 C AA16 PB47B 4 C AA17 PB48A 4 T AA17 PB48A 4 T Y17 PB48B 4 C Y17 PB48B 4 C AF21 PB49A 4 T AF21 PB49A 4 T GND GND4 4 GND GND4 4 AF20 PB49B 4 C AF20 PB49B 4 C AE21 PB50A 4 T AE21 PB50A 4 T AC17 PB50B 4 C AC17 PB50B 4 C 4-67 D4/SPID3 BDQS46 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number Ball Function AF22 PB51A 4 AB17 PB51B AE22 PB52A AA18 AE19 LFECP/EC33 Ball Number Ball Function Bank LVDS T AF22 PB51A 4 T 4 C AB17 PB51B 4 C 4 T AE22 PB52A 4 T PB52B 4 C AA18 PB52B 4 C PB53A 4 T AE19 PB53A 4 T GND GND4 4 C AE20 PB53B 4 Bank LVDS GND GND4 4 AE20 PB53B 4 AA19 PB54A 4 T Y18 PB54B 4 C Dual Function BDQS54 C AA19 PB54A 4 T Y18 PB54B 4 C AF23 PB55A 4 T AF23 PB55A 4 T AA20 PB55B 4 C AA20 PB55B 4 C AC18 PB56A 4 T AC18 PB56A 4 T AB18 PB56B 4 C AB18 PB56B 4 C AF24 PB57A 4 T AF24 PB57A 4 T - - - GND GND4 4 AE23 PB57B 4 AE23 PB57B 4 C AD19 NC - AD19 PB58A 4 T AD20 NC - AD20 PB58B 4 C AC19 NC - AC19 PB59A 4 T C Dual Function AB19 NC - AB19 PB59B 4 C AD21 NC - AD21 PB60A 4 T AC20 NC - AC20 PB60B 4 C AF25 NC - AF25 PB61A 4 T - - - GND GND4 4 AE25 NC - AE25 PB61B 4 AB21 NC - AB21 PB62A 4 T AB20 NC - AB20 PB62B 4 C AE24 NC - AE24 PB63A 4 T AD23 NC - AD23 PB63B 4 C AD22 NC - AD22 PB64A 4 T AC21 NC - AC21 PB64B 4 C BDQS54 C BDQS62 AC22 NC - AC22 PB65A 4 T AB22 NC - AB22 PB65B 4 C GND GND4 4 GND GND4 4 GND GND3 3 GND GND3 3 AC23 PR48B 3 C VREF2_3 AC23 PR68B 3 C VREF2_3 AC24 PR48A 3 T VREF1_3 AC24 PR68A 3 T VREF1_3 AD24 NC - AD24 PR67B 3 C AD25 NC - AD25 PR67A 3 T AE26 NC - AE26 PR66B 3 C AD26 NC - AD26 PR66A 3 T Y20 NC - Y20 PR65B 3 C 4-68 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number Ball Function Y19 NC AA23 - LFECP/EC33 Ball Number Ball Function Bank LVDS Dual Function - Y19 PR65A 3 T RDQS65 NC - AA23 PR64B 3 C - - GND GND3 3 AA22 NC - AA22 PR64A 3 T AB23 NC - AB23 PR63B 3 C AB24 NC - AB24 PR63A 3 T Y21 NC - Y21 PR62B 3 C AA21 NC - AA21 PR62A 3 T Y23 NC - Y23 PR61B 3 C Bank LVDS Dual Function Y22 NC - Y22 PR61A 3 T AA24 NC - AA24 PR60B 3 C - - - GND GND3 3 Y24 NC - Y24 PR60A 3 T AC25 PR47B 3 C AC25 PR59B 3 C AC26 PR47A 3 T AC26 PR59A 3 T AB25 PR46B 3 C AB25 PR58B 3 C AA25 PR46A 3 T AA25 PR58A 3 T AB26 PR45B 3 C AB26 PR57B 3 C AA26 PR45A 3 T RDQS45 AA26 PR57A 3 T RDQS57 C RLM0_PLLC_IN_A W23 PR56B 3 C RLM0_PLLC_IN_A GND GND3 3 W23 PR44B 3 GND GND3 3 W24 PR44A 3 T RLM0_PLLT_IN_A W24 PR56A 3 T RLM0_PLLT_IN_A W22 PR43B 3 C RLM0_PLLC_FB_A W22 PR55B 3 C RLM0_PLLC_FB_A W21 PR43A 3 T RLM0_PLLT_FB_A W21 PR55A 3 T RLM0_PLLT_FB_A Y25 PR42B 3 C DI/CSSPIN Y25 PR54B 3 C DI/CSSPIN Y26 PR42A 3 T DOUT/CSON Y26 PR54A 3 T DOUT/CSON W25 PR41B 3 C BUSY/SISPI W25 PR53B 3 C BUSY/SISPI W26 PR41A 3 T D7/SPID0 W26 PR53A 3 T D7/SPID0 V24 CFG2 3 V24 CFG2 3 V21 CFG1 3 V21 CFG1 3 V23 CFG0 3 V23 CFG0 3 V22 PROGRAMN 3 V22 PROGRAMN 3 V20 CCLK 3 V20 CCLK 3 V25 INITN 3 V25 INITN 3 U20 DONE 3 U20 DONE 3 V26 PR51B 3 GND GND3 3 V26 PR39B 3 GND GND3 3 C U26 PR39A 3 T U26 PR51A 3 T U24 PR38B 3 C U24 PR50B 3 C U25 PR38A 3 T U25 PR50A 3 T U23 PR37B 3 C U23 PR49B 3 C U22 PR37A 3 T U22 PR49A 3 T 4-69 C Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number Ball Function U21 PR36B 3 T21 PR36A 3 T T25 PR35B 3 C Bank LVDS LFECP/EC33 Dual Function Ball Number Ball Function Bank LVDS U21 PR48B 3 C C RDQS36 T21 PR48A 3 T T25 PR47B 3 C GND GND3 3 GND GND3 3 T26 PR35A 3 T T26 PR47A 3 T T22 PR34B 3 C T22 PR46B 3 C T23 PR34A 3 T T23 PR46A 3 T T24 PR33B 3 C T24 PR45B 3 C R23 PR33A 3 T R23 PR45A 3 T R25 PR32B 3 C R25 PR44B 3 C R24 PR32A 3 T R24 PR44A 3 T C C R26 PR31B 3 GND GND3 3 R26 PR43B 3 GND GND3 3 P26 PR31A 3 T P26 PR43A 3 T R21 PR30B 3 C R21 PR42B 3 C R22 PR30A 3 T R22 PR42A 3 T P25 PR29B 3 C P25 PR41B 3 C P24 PR29A 3 T P24 PR41A 3 T P23 PR28B 3 C P23 PR40B 3 C P22 PR28A 3 T N26 PR27B 3 C GND GND3 3 M26 PR27A 3 T N21 PR26B 3 C N21 P21 PR26A 3 T P21 N23 PR25B 3 C N23 N22 PR25A 3 T N22 N25 PR24B 3 C N24 PR24A 3 T C L26 PR22B 2 GND GND2 2 RDQS28 PCLKC2_0 PCLKT2_0 P22 PR40A 3 T PR39B 3 C GND GND3 3 M26 PR39A 3 T PR38B 3 C PR38A 3 T PR37B 3 C PR37A 3 T N25 PR36B 3 C N24 PR36A 3 T C PCLKC2_0 PCLKT2_0 L26 PR34B 2 GND GND2 2 K26 PR34A 2 T M22 PR33B 2 C K26 PR22A 2 T PR21B 2 C M23 PR21A 2 T M23 PR33A 2 T M25 PR20B 2 C M25 PR32B 2 C M24 PR20A 2 T M24 PR32A 2 T M21 PR19B 2 C M21 PR31B 2 C L21 PR19A 2 T L22 PR18B 2 C L21 PR31A 2 T L22 PR30B 2 C GND GND2 2 GND GND2 2 L23 PR18A 2 T L23 PR30A 2 T L25 PR17B 2 C L25 PR29B 2 C 4-70 RDQS48 N26 M22 RDQS19 Dual Function RDQS40 RDQS31 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number Ball Function L24 PR17A 2 K25 PR16B J25 PR16A LFECP/EC33 Ball Number Ball Function Bank LVDS T L24 PR29A 2 T 2 C K25 PR28B 2 C 2 T J25 PR28A 2 T Bank LVDS Dual Function J26 PR15B 2 C J26 PR27B 2 C H26 PR15A 2 T H26 PR27A 2 T C H25 PR26B 2 C GND GND2 2 H25 PR14B 2 GND GND2 2 J24 PR14A 2 T J24 PR26A 2 T K21 PR13B 2 C K21 PR25B 2 C K22 PR13A 2 T K22 PR25A 2 T K20 PR12B 2 C K20 PR24B 2 C J20 PR12A 2 T J20 PR24A 2 T K23 PR11B 2 C K23 PR23B 2 C K24 PR11A 2 T K24 PR23A 2 T J21 NC - J21 PR22B 2 C - - - GND GND2 2 J22 NC - J22 PR22A 2 T J23 NC - J23 PR21B 2 C H22 NC - H22 PR21A 2 T Dual Function RDQS23 G26 NC - G26 PR20B 2 C F26 NC - F26 PR20A 2 T E26 NC - E26 PR19B 2 C E25 NC - E25 PR19A 2 T F25 PR9B 2 F25 PR17B 2 C RUM0_PLLC_FB_A GND GND2 2 GND GND2 2 C RUM0_PLLC_FB_A G25 PR9A 2 T RUM0_PLLT_FB_A G25 PR17A 2 T RUM0_PLLT_FB_A H23 PR8B 2 C RUM0_PLLC_IN_A H23 PR16B 2 C RUM0_PLLC_IN_A H24 PR8A 2 T RUM0_PLLT_IN_A H24 PR16A 2 T RUM0_PLLT_IN_A H21 PR7B 2 C H21 PR15B 2 C G21 PR7A 2 T G21 PR15A 2 T D26 PR6B 2 C D26 PR14B 2 C D25 PR6A 2 T D25 PR14A 2 T F21 PR5B 2 C F21 PR13B 2 C RDQS6 - - - GND GND2 2 G22 PR5A 2 T G22 PR13A 2 T G24 PR4B 2 C G24 PR12B 2 C G23 PR4A 2 T G23 PR12A 2 T C26 PR3B 2 C C26 PR11B 2 C C25 PR3A 2 T C25 PR11A 2 T F24 NC - F24 PR9B 2 C - - - GND GND2 2 F23 NC - F23 PR9A 2 4-71 T RDQS14 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number Ball Function E24 NC D24 E22 LFECP/EC33 Ball Number Ball Function Bank LVDS - E24 PR8B 2 C NC - D24 PR8A 2 T NC - E22 PR7B 2 C F22 NC - F22 PR7A 2 T E21 NC - E21 PR6B 2 C D22 PR6A 2 T RDQS6 E23 PR2B 2 C VREF1_2 T VREF2_2 Bank LVDS Dual Function D22 NC - E23 PR2B 2 C VREF1_2 T VREF2_2 D23 PR2A 2 D23 PR2A 2 GND GND2 2 GND GND2 2 GND GND1 1 GND GND1 1 G20 NC - G20 PT65B 1 C F20 NC - F20 PT65A 1 T D21 NC - D21 PT64B 1 C C21 NC - C21 PT64A 1 T C23 NC - C23 PT63B 1 C C22 NC - C22 PT63A 1 T B23 NC - B23 PT62B 1 C C24 NC - C24 PT62A 1 T D20 NC - D20 PT61B 1 C - - - GND GND1 1 E19 NC - E19 PT61A 1 T B25 NC - B25 PT60B 1 C B24 NC - B24 PT60A 1 T B26 NC - B26 PT59B 1 C A25 NC - A25 PT59A 1 T C20 NC - C20 PT58B 1 C C19 NC - C19 PT58A 1 T A24 PT57B 1 A24 PT57B 1 C - - - GND GND1 1 A23 PT57A 1 T A23 PT57A 1 T E18 PT56B 1 C E18 PT56B 1 C D19 PT56A 1 T D19 PT56A 1 T F19 PT55B 1 C F19 PT55B 1 C C B22 PT55A 1 T B22 PT55A 1 T G19 PT54B 1 C G19 PT54B 1 C B21 PT54A 1 T D18 PT53B 1 C GND GND1 1 C18 PT53A 1 T TDQS54 B21 PT54A 1 T D18 PT53B 1 C GND GND1 1 C18 PT53A 1 T F18 PT52B 1 C F18 PT52B 1 C A22 PT52A 1 T A22 PT52A 1 T G18 PT51B 1 C G18 PT51B 1 C 4-72 Dual Function TDQS62 TDQS54 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number Ball Function A21 PT51A 1 E17 PT50B B17 PT50A LFECP/EC33 Ball Number Ball Function Bank LVDS T A21 PT51A 1 T 1 C E17 PT50B 1 C 1 T B17 PT50A 1 T C C Bank LVDS C17 PT49B 1 GND GND1 1 D17 PT49A 1 F17 PT48B 1 Dual Function C17 PT49B 1 GND GND1 1 T D17 PT49A 1 T C F17 PT48B 1 C E20 PT48A 1 T E20 PT48A 1 T G17 PT47B 1 C G17 PT47B 1 C B20 PT47A 1 T B20 PT47A 1 T E16 PT46B 1 C E16 PT46B 1 C A20 PT46A 1 T A19 PT45B 1 C TDQS46 A20 PT46A 1 T A19 PT45B 1 C GND GND1 1 GND GND1 1 B19 PT45A 1 T B19 PT45A 1 T D16 PT44B 1 C D16 PT44B 1 C C16 PT44A 1 T C16 PT44A 1 T F16 PT43B 1 C F16 PT43B 1 C A18 PT43A 1 T A18 PT43A 1 T G16 PT42B 1 C G16 PT42B 1 C B18 PT42A 1 T B18 PT42A 1 T C C A17 PT41B 1 GND GND1 1 A17 PT41B 1 GND GND1 1 A16 PT41A 1 T A16 PT41A 1 T D15 PT40B 1 C D15 PT40B 1 C B16 PT40A 1 T B16 PT40A 1 T E15 PT39B 1 C E15 PT39B 1 C C15 PT39A 1 T C15 PT39A 1 T F15 PT38B 1 C F15 PT38B 1 C G15 PT38A 1 T B15 PT37B 1 C GND GND1 1 A15 PT37A 1 T TDQS38 G15 PT38A 1 T B15 PT37B 1 C GND GND1 1 A15 PT37A 1 T Dual Function TDQS46 TDQS38 E14 PT36B 1 C E14 PT36B 1 C G14 PT36A 1 T G14 PT36A 1 T D14 PT35B 1 C VREF2_1 D14 PT35B 1 C VREF2_1 E13 PT35A 1 T VREF1_1 E13 PT35A 1 T VREF1_1 F14 PT34B 1 C F14 PT34B 1 C C14 PT34A 1 T C14 PT34A 1 T C C PCLKC0_0 T PCLKT0_0 B14 PT33B 0 GND GND0 0 A14 PT33A 0 T PCLKC0_0 PCLKT0_0 4-73 B14 PT33B 0 GND GND0 0 A14 PT33A 0 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number Ball Function D13 PT32B 0 C13 PT32A A13 PT31B B13 PT31A F13 PT30B LFECP/EC33 Dual Function Ball Number Ball Function Bank LVDS Dual Function C VREF1_0 D13 PT32B 0 C VREF1_0 0 T VREF2_0 C13 PT32A 0 T VREF2_0 0 C A13 PT31B 0 C 0 T B13 PT31A 0 T 0 C F13 PT30B 0 C Bank LVDS F12 PT30A 0 T A12 PT29B 0 C TDQS30 F12 PT30A 0 T A12 PT29B 0 C GND GND0 0 GND GND0 0 B12 PT29A 0 T B12 PT29A 0 T A11 PT28B 0 C A11 PT28B 0 C B11 PT28A 0 T B11 PT28A 0 T D12 PT27B 0 C D12 PT27B 0 C C12 PT27A 0 T C12 PT27A 0 T B10 PT26B 0 C B10 PT26B 0 C A10 PT26A 0 T A10 PT26A 0 T C C G12 PT25B 0 GND GND0 0 G12 PT25B 0 GND GND0 0 A9 PT25A 0 T A9 PT25A 0 T E12 PT24B 0 C E12 PT24B 0 C B9 PT24A 0 T B9 PT24A 0 T F11 PT23B 0 C F11 PT23B 0 C A8 PT23A 0 T A8 PT23A 0 T D11 PT22B 0 C D11 PT22B 0 C C11 PT22A 0 T B8 PT21B 0 C TDQS22 C11 PT22A 0 T B8 PT21B 0 C GND GND0 0 GND GND0 0 B7 PT21A 0 T B7 PT21A 0 T E11 PT20B 0 C E11 PT20B 0 C A7 PT20A 0 T A7 PT20A 0 T G11 PT19B 0 C G11 PT19B 0 C C7 PT19A 0 T C7 PT19A 0 T G10 PT18B 0 C G10 PT18B 0 C C6 PT18A 0 T C6 PT18A 0 T C C C10 PT17B 0 GND GND0 0 D10 PT17A 0 F10 PT16B 0 C10 PT17B 0 GND GND0 0 T D10 PT17A 0 T C F10 PT16B 0 C A6 PT16A 0 T A6 PT16A 0 T E10 PT15B 0 C E10 PT15B 0 C C9 PT15A 0 T C9 PT15A 0 T G9 PT14B 0 C G9 PT14B 0 C D9 PT14A 0 T D9 PT14A 0 T TDQS14 4-74 TDQS30 TDQS22 TDQS14 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number Ball Function A5 PT13B Bank LVDS 0 LFECP/EC33 Dual Function Ball Number Ball Function Bank LVDS A5 PT13B 0 C C GND GND0 0 A4 PT13A 0 T GND GND0 0 A4 PT13A 0 T F9 PT12B 0 C F9 PT12B 0 C B6 PT12A 0 T B6 PT12A 0 T E9 PT11B 0 C E9 PT11B 0 C C8 PT11A 0 T C8 PT11A 0 T G8 PT10B 0 C G8 PT10B 0 C B5 PT10A 0 T B5 PT10A 0 T C C A3 PT9B 0 GND GND0 0 A3 PT9B 0 GND GND0 0 A2 PT9A 0 F8 PT8B 0 T A2 PT9A 0 T C F8 PT8B 0 C B4 PT8A 0 T B4 PT8A 0 T E8 PT7B 0 C E8 PT7B 0 C B3 PT7A 0 T B3 PT7A 0 T D8 PT6B 0 C D8 PT6B 0 C G7 PT6A 0 T G7 PT6A 0 T C4 PT5B 0 C TDQS6 C4 PT5B 0 C C5 PT5A 0 T C5 PT5A 0 T E7 PT4B 0 C E7 PT4B 0 C D4 PT4A 0 T D4 PT4A 0 T F7 PT3B 0 C F7 PT3B 0 C D6 PT3A 0 T D6 PT3A 0 T D7 PT2B 0 C D7 PT2B 0 C T T E6 PT2A 0 E6 PT2A 0 GND GND0 0 GND GND0 0 K10 GND - K10 GND - K11 GND - K11 GND - K12 GND - K12 GND - K13 GND - K13 GND - K14 GND - K14 GND - K15 GND - K15 GND - K16 GND - K16 GND - L10 GND - L10 GND - L11 GND - L11 GND - L12 GND - L12 GND - L13 GND - L13 GND - L14 GND - L14 GND - L15 GND - L15 GND - L16 GND - L16 GND - L17 GND - L17 GND - 4-75 Dual Function TDQS6 Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number Ball Function M10 GND M11 M12 LFECP/EC33 Ball Number Ball Function Bank - M10 GND - GND - M11 GND - GND - M12 GND - M13 GND - M13 GND - M14 GND - M14 GND - M15 GND - M15 GND - M16 GND - M16 GND - Bank LVDS Dual Function M17 GND - M17 GND - N10 GND - N10 GND - N11 GND - N11 GND - N12 GND - N12 GND - N13 GND - N13 GND - N14 GND - N14 GND - N15 GND - N15 GND - N16 GND - N16 GND - N17 GND - N17 GND - P10 GND - P10 GND - P11 GND - P11 GND - P12 GND - P12 GND - P13 GND - P13 GND - P14 GND - P14 GND - P15 GND - P15 GND - P16 GND - P16 GND - P17 GND - P17 GND - R10 GND - R10 GND - R11 GND - R11 GND - R12 GND - R12 GND - R13 GND - R13 GND - R14 GND - R14 GND - R15 GND - R15 GND - R16 GND - R16 GND - R17 GND - R17 GND - T10 GND - T10 GND - T11 GND - T11 GND - T12 GND - T12 GND - T13 GND - T13 GND - T14 GND - T14 GND - T15 GND - T15 GND - T16 GND - T16 GND - T17 GND - T17 GND - U10 GND - U10 GND - U11 GND - U11 GND - 4-76 LVDS Dual Function Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number Ball Function U12 GND U13 U14 LFECP/EC33 Ball Number Ball Function Bank - U12 GND - GND - U13 GND - GND - U14 GND - U15 GND - U15 GND - U16 GND - U16 GND - U17 GND - U17 GND - H10 VCC - H10 VCC - H11 VCC - H11 VCC - H16 VCC - H16 VCC - H17 VCC - H17 VCC - H18 VCC - H18 VCC - Bank LVDS Dual Function H19 VCC - H19 VCC - H8 VCC - H8 VCC - H9 VCC - H9 VCC - J18 VCC - J18 VCC - J9 VCC - J9 VCC - K8 VCC - K8 VCC - L19 VCC - L19 VCC - M19 VCC - M19 VCC - N7 VCC - N7 VCC - R20 VCC - R20 VCC - R7 VCC - R7 VCC - T19 VCC - T19 VCC - V18 VCC - V18 VCC - V8 VCC - V8 VCC - V9 VCC - V9 VCC - W10 VCC - W10 VCC - W11 VCC - W11 VCC - W16 VCC - W16 VCC - W17 VCC - W17 VCC - W18 VCC - W18 VCC - W19 VCC - W19 VCC - W8 VCC - W8 VCC - W9 VCC - W9 VCC - H12 VCCIO0 0 H12 VCCIO0 0 H13 VCCIO0 0 H13 VCCIO0 0 J10 VCCIO0 0 J10 VCCIO0 0 J11 VCCIO0 0 J11 VCCIO0 0 J12 VCCIO0 0 J12 VCCIO0 0 J13 VCCIO0 0 J13 VCCIO0 0 H14 VCCIO1 1 H14 VCCIO1 1 H15 VCCIO1 1 H15 VCCIO1 1 4-77 LVDS Dual Function Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number Ball Function J14 VCCIO1 J15 J16 LFECP/EC33 Ball Number Ball Function Bank 1 J14 VCCIO1 1 VCCIO1 1 J15 VCCIO1 1 VCCIO1 1 J16 VCCIO1 1 Bank LVDS Dual Function J17 VCCIO1 1 J17 VCCIO1 1 K17 VCCIO2 2 K17 VCCIO2 2 K18 VCCIO2 2 K18 VCCIO2 2 L18 VCCIO2 2 L18 VCCIO2 2 M18 VCCIO2 2 M18 VCCIO2 2 N18 VCCIO2 2 N18 VCCIO2 2 N19 VCCIO2 2 N19 VCCIO2 2 P18 VCCIO3 3 P18 VCCIO3 3 P19 VCCIO3 3 P19 VCCIO3 3 R18 VCCIO3 3 R18 VCCIO3 3 R19 VCCIO3 3 R19 VCCIO3 3 T18 VCCIO3 3 T18 VCCIO3 3 U18 VCCIO3 3 U18 VCCIO3 3 V14 VCCIO4 4 V14 VCCIO4 4 V15 VCCIO4 4 V15 VCCIO4 4 V16 VCCIO4 4 V16 VCCIO4 4 V17 VCCIO4 4 V17 VCCIO4 4 W14 VCCIO4 4 W14 VCCIO4 4 W15 VCCIO4 4 W15 VCCIO4 4 V10 VCCIO5 5 V10 VCCIO5 5 V11 VCCIO5 5 V11 VCCIO5 5 V12 VCCIO5 5 V12 VCCIO5 5 V13 VCCIO5 5 V13 VCCIO5 5 W12 VCCIO5 5 W12 VCCIO5 5 W13 VCCIO5 5 W13 VCCIO5 5 P8 VCCIO6 6 P8 VCCIO6 6 P9 VCCIO6 6 P9 VCCIO6 6 R8 VCCIO6 6 R8 VCCIO6 6 R9 VCCIO6 6 R9 VCCIO6 6 T9 VCCIO6 6 T9 VCCIO6 6 U9 VCCIO6 6 U9 VCCIO6 6 K9 VCCIO7 7 K9 VCCIO7 7 L9 VCCIO7 7 L9 VCCIO7 7 M8 VCCIO7 7 M8 VCCIO7 7 M9 VCCIO7 7 M9 VCCIO7 7 N8 VCCIO7 7 N8 VCCIO7 7 N9 VCCIO7 7 N9 VCCIO7 7 G13 VCCAUX - G13 VCCAUX - H20 VCCAUX - H20 VCCAUX - 4-78 LVDS Dual Function Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.) LFEC20/LFECP20 Ball Number Ball Function H7 VCCAUX LFECP/EC33 Ball Number Ball Function Bank - H7 VCCAUX - Bank LVDS Dual Function J19 VCCAUX - J19 VCCAUX - J8 VCCAUX - J8 VCCAUX - K7 VCCAUX - K7 VCCAUX - L20 VCCAUX - L20 VCCAUX - M20 VCCAUX - M20 VCCAUX - M7 VCCAUX - M7 VCCAUX - N20 VCCAUX - N20 VCCAUX - P20 VCCAUX - P20 VCCAUX - P7 VCCAUX - P7 VCCAUX - T20 VCCAUX - T20 VCCAUX - T7 VCCAUX - T7 VCCAUX - T8 VCCAUX - T8 VCCAUX - V19 VCCAUX - V19 VCCAUX - V7 VCCAUX - V7 VCCAUX - W20 VCCAUX - W20 VCCAUX - Y13 VCCAUX - Y13 VCCAUX - Y7 VCCAUX - Y7 VCCAUX - K19 VCC1 - K19 VCCPLL - L8 VCC1 - L8 VCCPLL - U19 VCC1 - U19 VCCPLL - U8 VCC1 - U8 VCCPLL - 1. Tied to VCCPLL. 4-79 LVDS Dual Function Pinout Information LatticeECP/EC Family Data Sheet Lattice Semiconductor Thermal Management Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets. Designers must complete a thermal analysis of their specific design to ensure that the device and package do not exceed the junction temperature limits. Refer to the Thermal Management document to find the device/package specific thermal values. For Further Information For further information regarding Thermal Management, refer to the following located on the Lattice website at www.latticesemi.com. • Thermal Management document • Technical Note TN1052 - Power Estimation and Management for LatticeECP/EC and LatticeXP Devices • Power Calculator tool included with Lattice’s ispLEVER design tool, or as a standalone download from www.latticesemi.com/software 4-80 LatticeECP/EC Family Data Sheet Ordering Information November 2005 Data Sheet Part Number Description LFXXX XX X – X XXXX X Device Family Lattice EC (FPGA) Lattice ECP (EC FPGA + DSP Blocks) Grade C = Commercial I = Industrial Logic Capacity 1* = 1.5K LUTs 3* = 3K LUTs 6 = 6K LUTs 10 = 10K LUTs 15 = 15K LUTs 20 = 20K LUTs 33 = 33K LUTs Package T100 = 100-pin TQFP* T144 = 144-pin TQFP Q208 = 208-pin PQFP F256 = 256-ball fpBGA F484 = 484-ball fpBGA F672 = 672-ball fpBGA TN100 = 100-pin Lead-free TQFP* TN144 = 144-pin Lead-free TQFP QN208 = 208-pin Lead-free PQFP FN256 = 256-ball Lead-free fpBGA FN484 = 484-ball Lead-free fpBGA FN672 = 672-ball Lead-free fpBGA Supply Voltage E = 1.2V Speed 3 = Slowest 4 5 = Fastest *Not available in the LatticeECP Family. Ordering Information Note: LatticeECP/EC devices are dual marked. For example, the commercial speed grade LFEC20E-4F484C is also marked with industrial grade -3I (LFEC20E-3F484I). The commercial grade is one speed grade faster than the associated dual mark industrial grade. The slowest commercial speed grade does not have industrial markings. The markings appear as follows: EC LFEC20E4F484C-3I Datecode © 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 5-1 Order Info_02.3 Ordering Information LatticeECP/EC Family Data Sheet Lattice Semiconductor Conventional Packaging LatticeEC Commercial Part Number I/Os Grade Package Pins Temp. LUTs LFEC1E-3Q208C 112 -3 PQFP 208 COM 1.5K LFEC1E-4Q208C 112 -4 PQFP 208 COM 1.5K LFEC1E-5Q208C 112 -5 PQFP 208 COM 1.5K LFEC1E-3T144C 97 -3 TQFP 144 COM 1.5K LFEC1E-4T144C 97 -4 TQFP 144 COM 1.5K LFEC1E-5T144C 97 -5 TQFP 144 COM 1.5K LFEC1E-3T100C 67 -3 TQFP 100 COM 1.5K LFEC1E-4T100C 67 -4 TQFP 100 COM 1.5K LFEC1E-5T100C 67 -5 TQFP 100 COM 1.5K I/Os Grade Package Pins Temp. LUTs LFEC3E-3F256C Part Number 160 -3 fpBGA 256 COM 3.1K LFEC3E-4F256C 160 -4 fpBGA 256 COM 3.1K LFEC3E-5F256C 160 -5 fpBGA 256 COM 3.1K LFEC3E-3Q208C 145 -3 PQFP 208 COM 3.1K LFEC3E-4Q208C 145 -4 PQFP 208 COM 3.1K LFEC3E-5Q208C 145 -5 PQFP 208 COM 3.1K LFEC3E-3T144C 97 -3 TQFP 144 COM 3.1K LFEC3E-4T144C 97 -4 TQFP 144 COM 3.1K LFEC3E-5T144C 97 -5 TQFP 144 COM 3.1K LFEC3E-3T100C 67 -3 TQFP 100 COM 3.1K LFEC3E-4T100C 67 -4 TQFP 100 COM 3.1K LFEC3E-5T100C 67 -5 TQFP 100 COM 3.1K I/Os Grade Package Pins Temp. LUTs LFEC6E-3F484C Part Number 224 -3 fpBGA 484 COM 6.1K LFEC6E-4F484C 224 -4 fpBGA 484 COM 6.1K LFEC6E-5F484C 224 -5 fpBGA 484 COM 6.1K LFEC6E-3F256C 195 -3 fpBGA 256 COM 6.1K LFEC6E-4F256C 195 -4 fpBGA 256 COM 6.1K LFEC6E-5F256C 195 -5 fpBGA 256 COM 6.1K LFEC6E-3Q208C 147 -3 PQFP 208 COM 6.1K LFEC6E-4Q208C 147 -4 PQFP 208 COM 6.1K LFEC6E-5Q208C 147 -5 PQFP 208 COM 6.1K LFEC6E-3T144C 97 -3 TQFP 144 COM 6.1K LFEC6E-4T144C 97 -4 TQFP 144 COM 6.1K LFEC6E-5T144C 97 -5 TQFP 144 COM 6.1K I/Os Grade Package Pins Temp. LUTs LFEC10E-3F484C Part Number 288 -3 fpBGA 484 COM 10.2K LFEC10E-4F484C 288 -4 fpBGA 484 COM 10.2K LFEC10E-5F484C 288 -5 fpBGA 484 COM 10.2K LFEC10E-3F256C 195 -3 fpBGA 256 COM 10.2K 5-2 Ordering Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LatticeEC Commercial (Continued) Part Number LFEC10E-4F256C I/Os Grade Package Pins Temp. LUTs 195 -4 fpBGA 256 COM 10.2K LFEC10E-5F256C 195 -5 fpBGA 256 COM 10.2K LFEC10E-3Q208C 147 -3 PQFP 208 COM 10.2K LFEC10E-4Q208C 147 -4 PQFP 208 COM 10.2K LFEC10E-5Q208C 147 -5 PQFP 208 COM 10.2K I/Os Grade Package Pins Temp. LUTs LFEC15E-3F484C 352 -3 fpBGA 484 COM 15.3K LFEC15E-4F484C 352 -4 fpBGA 484 COM 15.3K LFEC15E-5F484C 352 -5 fpBGA 484 COM 15.3K LFEC15E-3F256C 195 -3 fpBGA 256 COM 15.3K LFEC15E-4F256C 195 -4 fpBGA 256 COM 15.3K LFEC15E-5F256C 195 -5 fpBGA 256 COM 15.3K I/Os Grade Package Pins Temp. LUTs LFEC20E-3F672C 400 -3 fpBGA 672 COM 19.7K LFEC20E-4F672C 400 -4 fpBGA 672 COM 19.7K LFEC20E-5F672C 400 -5 fpBGA 672 COM 19.7K LFEC20E-3F484C 360 -3 fpBGA 484 COM 19.7K LFEC20E-4F484C 360 -4 fpBGA 484 COM 19.7K LFEC20E-5F484C 360 -5 fpBGA 484 COM 19.7K I/Os Grade Package Pins Temp. LUTs LFEC33E-3F672C 496 -3 fpBGA 672 COM 32.8K LFEC33E-4F672C 496 -4 fpBGA 672 COM 32.8K LFEC33E-5F672C 496 -5 fpBGA 672 COM 32.8K LFEC33E-3F484C 360 -3 fpBGA 484 COM 32.8K LFEC33E-4F484C 360 -4 fpBGA 484 COM 32.8K LFEC33E-5F484C 360 -5 fpBGA 484 COM 32.8K Part Number Part Number Part Number 5-3 Ordering Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LatticeECP Commercial Part Number I/Os Grade Package Pins Temp. LUTs LFECP6E-3F484C 224 -3 fpBGA 484 COM 6.1K LFECP6E-4F484C 224 -4 fpBGA 484 COM 6.1K LFECP6E-5F484C 224 -5 fpBGA 484 COM 6.1K LFECP6E-3F256C 195 -3 fpBGA 256 COM 6.1K LFECP6E-4F256C 195 -4 fpBGA 256 COM 6.1K LFECP6E-5F256C 195 -5 fpBGA 256 COM 6.1K LFECP6E-3Q208C 147 -3 PQFP 208 COM 6.1K LFECP6E-4Q208C 147 -4 PQFP 208 COM 6.1K LFECP6E-5Q208C 147 -5 PQFP 208 COM 6.1K LFECP6E-3T144C 97 -3 TQFP 144 COM 6.1K LFECP6E-4T144C 97 -4 TQFP 144 COM 6.1K LFECP6E-5T144C 97 -5 TQFP 144 COM 6.1K Part Number I/Os Grade Package Pins Temp. LUTs LFECP10E-3F484C 288 -3 fpBGA 484 COM 10.2K LFECP10E-4F484C 288 -4 fpBGA 484 COM 10.2K LFECP10E-5F484C 288 -5 fpBGA 484 COM 10.2K LFECP10E-3F256C 195 -3 fpBGA 256 COM 10.2K LFECP10E-4F256C 195 -4 fpBGA 256 COM 10.2K LFECP10E-5F256C 195 -5 fpBGA 256 COM 10.2K LFECP10E-3Q208C 147 -3 PQFP 208 COM 10.2K LFECP10E-4Q208C 147 -4 PQFP 208 COM 10.2K LFECP10E-5Q208C 147 -5 PQFP 208 COM 10.2K Part Number I/Os Grade Package Pins Temp. LUTs LFECP15E-3F484C 352 -3 fpBGA 484 COM 15.3K LFECP15E-4F484C 352 -4 fpBGA 484 COM 15.3K LFECP15E-5F484C 352 -5 fpBGA 484 COM 15.3K LFECP15E-3F256C 195 -3 fpBGA 256 COM 15.3K LFECP15E-4F256C 195 -4 fpBGA 256 COM 15.3K LFECP15E-5F256C 195 -5 fpBGA 256 COM 15.3K Part Number I/Os Grade Package Pins Temp. LUTs LFECP20E-3F672C 400 -3 fpBGA 672 COM 19.7K LFECP20E-4F672C 400 -4 fpBGA 672 COM 19.7K LFECP20E-5F672C 400 -5 fpBGA 672 COM 19.7K LFECP20E-3F484C 360 -3 fpBGA 484 COM 19.7K LFECP20E-4F484C 360 -4 fpBGA 484 COM 19.7K LFECP20E-5F484C 360 -5 fpBGA 484 COM 19.7K Part Number I/Os Grade Package Pins Temp. LUTs LFECP33E-3F672C 496 -3 fpBGA 672 COM 32.8K LFECP33E-4F672C 496 -4 fpBGA 672 COM 32.8K LFECP33E-5F672C 496 -5 fpBGA 672 COM 32.8K 5-4 Ordering Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LatticeECP Commercial (Continued) Part Number I/Os Grade Package Pins Temp. LUTs LFECP33E-3F484C 360 -3 fpBGA 484 COM 32.8K LFECP33E-4F484C 360 -4 fpBGA 484 COM 32.8K LFECP33E-5F484C 360 -5 fpBGA 484 COM 32.8K LatticeEC Industrial I/Os Grade Package Pins Temp. LUTs LFEC1E-3Q208I Part Number 112 -3 PQFP 208 IND 1.5K LFEC1E-4Q208I 112 -4 PQFP 208 IND 1.5K LFEC1E-3T144I 97 -3 TQFP 144 IND 1.5K LFEC1E-4T144I 97 -4 TQFP 144 IND 1.5K LFEC1E-3T100I 67 -3 TQFP 100 IND 1.5K LFEC1E-4T100I 67 -4 TQFP 100 IND 1.5K I/Os Grade Package Pins Temp. LUTs 160 -3 fpBGA 256 IND 3.1K LFEC3E-4F256I 160 -4 fpBGA 256 IND 3.1K LFEC3E-3Q208I 145 -3 PQFP 208 IND 3.1K LFEC3E-4Q208I 145 -4 PQFP 208 IND 3.1K LFEC3E-3T144I 97 -3 TQFP 144 IND 3.1K LFEC3E-4T144I 97 -4 TQFP 144 IND 3.1K LFEC3E-3T100I 67 -3 TQFP 100 IND 3.1K LFEC3E-4T100I 67 -4 TQFP 100 IND 3.1K Part Number LFEC3E-3F256I I/Os Grade Package Pins Temp. LUTs LFEC6E-3F484I Part Number 224 -3 fpBGA 484 IND 6.1K LFEC6E-4F484I 224 -4 fpBGA 484 IND 6.1K LFEC6E-3F256I 195 -3 fpBGA 256 IND 6.1K LFEC6E-4F256I 195 -4 fpBGA 256 IND 6.1K LFEC6E-3Q208I 147 -3 PQFP 208 IND 6.1K LFEC6E-4Q208I 147 -4 PQFP 208 IND 6.1K LFEC6E-3T144I 97 -3 TQFP 144 IND 6.1K LFEC6E-4T144I 97 -4 TQFP 144 IND 6.1K I/Os Grade Package Pins Temp. LUTs LFEC10E-3F484I Part Number 288 -3 fpBGA 484 IND 10.2K LFEC10E-4F484I 288 -4 fpBGA 484 IND 10.2K LFEC10E-3F256I 195 -3 fpBGA 256 IND 10.2K LFEC10E-4F256I 195 -4 fpBGA 256 IND 10.2K LFEC10E-3 P208I 147 -3 PQFP 208 IND 10.2K LFEC10E-4 P208I 147 -4 PQFP 208 IND 10.2K 5-5 Ordering Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LatticeEC Industrial (Continued) I/Os Grade Package Pins Temp. LUTs LFEC15E-3F484I Part Number 352 -3 fpBGA 484 IND 15.3K LFEC15E-4F484I 352 -4 fpBGA 484 IND 15.3K LFEC15E-3F256I 195 -3 fpBGA 256 IND 15.3K LFEC15E-4F256I 195 -4 fpBGA 256 IND 15.3K I/Os Grade Package Pins Temp. LUTs LFEC20E-3F672I Part Number 400 -3 fpBGA 672 IND 19.7K LFEC20E-4F672I 400 -4 fpBGA 672 IND 19.7K LFEC20E-3F484I 360 -3 fpBGA 484 IND 19.7K LFEC20E-4F484I 360 -4 fpBGA 484 IND 19.7K I/Os Grade Package Pins Temp. LUTs LFEC33E-3F672I Part Number 496 -3 fpBGA 672 IND 32.8 LFEC33E-4F672I 496 -4 fpBGA 672 IND 32.8 LFEC33E-3F484I 360 -3 fpBGA 484 IND 32.8 LFEC33E-4F484I 360 -4 fpBGA 484 IND 32.8 LatticeECP Industrial Part Number I/Os Grade Package Pins Temp. LUTs LFECP6E-3F484I 224 -3 fpBGA 484 IND 6.1K LFECP6E-4F484I 224 -4 fpBGA 484 IND 6.1K LFECP6E-3F256I 195 -3 fpBGA 256 IND 6.1K LFECP6E-4F256I 195 -4 fpBGA 256 IND 6.1K LFECP6E-3Q208I 147 -3 PQFP 208 IND 6.1K LFECP6E-4Q208I 147 -4 PQFP 208 IND 6.1K LFECP6E-3T144I 97 -3 TQFP 144 IND 6.1K LFECP6E-4T144I 97 -4 TQFP 144 IND 6.1K I/Os Grade Package Pins Temp. LUTs LFECP10E-3F484I 288 -3 fpBGA 484 IND 10.2K LFECP10E-4F484I 288 -4 fpBGA 484 IND 10.2K LFECP10E-3F256I 195 -3 fpBGA 256 IND 10.2K LFECP10E-4F256I 195 -4 fpBGA 256 IND 10.2K LFECP10E-3Q208I 147 -3 PQFP 208 IND 10.2K LFECP10E-4Q208I 147 -4 PQFP 208 IND 10.2K I/Os Grade Package Pins Temp. LUTs LFECP15E-3F484I 352 -3 fpBGA 484 IND 15.3K LFECP15E-4F484I 352 -4 fpBGA 484 IND 15.3K LFECP15E-3F256I 195 -3 fpBGA 256 IND 15.3K LFECP15E-4F256I 195 -4 fpBGA 256 IND 15.3K Part Number Part Number 5-6 Ordering Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LatticeECP Industrial (Continued) I/Os Grade Package Pins Temp. LUTs LFECP20E-3F672I Part Number 400 -3 fpBGA 672 IND 19.7K LFECP20E-4F672I 400 -4 fpBGA 672 IND 19.7K LFECP20E-3F484I 360 -3 fpBGA 484 IND 19.7K LFECP20E-4F484I 360 -4 fpBGA 484 IND 19.7K I/Os Grade Package Pins Temp. LUTs LFECP33E-3F672I 496 -3 fpBGA 672 IND 32.8K LFECP33E-4F672I 496 -4 fpBGA 672 IND 32.8K LFECP33E-3F484I 360 -3 fpBGA 484 IND 32.8K LFECP33E-4F484I 360 -4 fpBGA 484 IND 32.8K Part Number 5-7 Ordering Information LatticeECP/EC Family Data Sheet Lattice Semiconductor Lead-Free Packaging LatticeEC Commercial Part Number I/Os Grade Package Pins/Balls Temp. LUTs LFEC1E-3QN208C 112 -3 Lead-Free PQFP 208 COM 1.5K LFEC1E-4QN208C 112 -4 Lead-Free PQFP 208 COM 1.5K LFEC1E-5QN208C 112 -5 Lead-Free PQFP 208 COM 1.5K LFEC1E-3TN144C 97 -3 Lead-Free TQFP 144 COM 1.5K LFEC1E-4TN144C 97 -4 Lead-Free TQFP 144 COM 1.5K LFEC1E-5TN144C 97 -5 Lead-Free TQFP 144 COM 1.5K LFEC1E-3TN100C 67 -3 Lead-Free TQFP 100 COM 1.5K LFEC1E-4TN100C 67 -4 Lead-Free TQFP 100 COM 1.5K LFEC1E-5TN100C 67 -5 Lead-Free TQFP 100 COM 1.5K I/Os Grade Package Pins/Balls Temp. LUTs LFEC3E-3FN256C Part Number 160 -3 Lead-Free fpBGA 256 COM 3.1K LFEC3E-4FN256C 160 -4 Lead-Free fpBGA 256 COM 3.1K LFEC3E-5FN256C 160 -5 Lead-Free fpBGA 256 COM 3.1K LFEC3E-3QN208C 145 -3 Lead-Free PQFP 208 COM 3.1K LFEC3E-4QN208C 145 -4 Lead-Free PQFP 208 COM 3.1K LFEC3E-5QN208C 145 -5 Lead-Free PQFP 208 COM 3.1K LFEC3E-3TN144C 97 -3 Lead-Free TQFP 144 COM 3.1K LFEC3E-4TN144C 97 -4 Lead-Free TQFP 144 COM 3.1K LFEC3E-5TN144C 97 -5 Lead-Free TQFP 144 COM 3.1K LFEC3E-3TN100C 67 -3 Lead-Free TQFP 100 COM 3.1K LFEC3E-4TN100C 67 -4 Lead-Free TQFP 100 COM 3.1K LFEC3E-5TN100C 67 -5 Lead-Free TQFP 100 COM 3.1K I/Os Grade Package Pins/Balls Temp. LUTs LFEC6E-3FN484C Part Number 224 -3 Lead-Free fpBGA 484 COM 6.1K LFEC6E-4FN484C 224 -4 Lead-Free fpBGA 484 COM 6.1K LFEC6E-5FN484C 224 -5 Lead-Free fpBGA 484 COM 6.1K LFEC6E-3FN256C 195 -3 Lead-Free fpBGA 256 COM 6.1K LFEC6E-4FN256C 195 -4 Lead-Free fpBGA 256 COM 6.1K LFEC6E-5FN256C 195 -5 Lead-Free fpBGA 256 COM 6.1K LFEC6E-3QN208C 147 -3 Lead-Free PQFP 208 COM 6.1K LFEC6E-4QN208C 147 -4 Lead-Free PQFP 208 COM 6.1K LFEC6E-5QN208C 147 -5 Lead-Free PQFP 208 COM 6.1K LFEC6E-3TN144C 97 -3 Lead-Free TQFP 144 COM 6.1K LFEC6E-4TN144C 97 -4 Lead-Free TQFP 144 COM 6.1K LFEC6E-5TN144C 97 -5 Lead-Free TQFP 144 COM 6.1K I/Os Grade Package Pins/Balls Temp. LUTs LFEC10E-3FN484C Part Number 288 -3 Lead-Free fpBGA 484 COM 10.2K LFEC10E-4FN484C 288 -4 Lead-Free fpBGA 484 COM 10.2K LFEC10E-5FN484C 288 -5 Lead-Free fpBGA 484 COM 10.2K LFEC10E-3FN256C 195 -3 Lead-Free fpBGA 256 COM 10.2K 5-8 Ordering Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LatticeEC Commercial (Continued) I/Os Grade Package Pins/Balls Temp. LUTs LFEC10E-4FN256C Part Number 195 -4 Lead-Free fpBGA 256 COM 10.2K LFEC10E-5FN256C 195 -5 Lead-Free fpBGA 256 COM 10.2K LFEC10E-3QN208C 147 -3 Lead-Free PQFP 208 COM 10.2K LFEC10E-4QN208C 147 -4 Lead-Free PQFP 208 COM 10.2K LFEC10E-5QN208C 147 -5 Lead-Free PQFP 208 COM 10.2K Part Number I/Os Grade Package Pins/Balls Temp. LUTs LFEC15E-3FN484C 352 -3 Lead-Free fpBGA 484 COM 15.3K LFEC15E-4FN484C 352 -4 Lead-Free fpBGA 484 COM 15.3K LFEC15E-5FN484C 352 -5 Lead-Free fpBGA 484 COM 15.3K LFEC15E-3FN256C 195 -3 Lead-Free fpBGA 256 COM 15.3K LFEC15E-4FN256C 195 -4 Lead-Free fpBGA 256 COM 15.3K LFEC15E-5FN256C 195 -5 Lead-Free fpBGA 256 COM 15.3K I/Os Grade Package Pins/Balls Temp. LUTs LFEC20E-3FN672C 400 -3 Lead-Free fpBGA 672 COM 19.7K LFEC20E-4FN672C 400 -4 Lead-Free fpBGA 672 COM 19.7K LFEC20E-5FN672C 400 -5 Lead-Free fpBGA 672 COM 19.7K LFEC20E-3FN484C 400 -3 Lead-Free fpBGA 484 COM 19.7K LFEC20E-4FN484C 400 -4 Lead-Free fpBGA 484 COM 19.7K LFEC20E-5FN484C 400 -5 Lead-Free fpBGA 484 COM 19.7K I/Os Grade Package Pins/Balls Temp. LUTs LFEC33E-3FN672C 496 -3 Lead-Free fpBGA 672 COM 32.8K LFEC33E-4FN672C 496 -4 Lead-Free fpBGA 672 COM 32.8K LFEC33E-5FN672C 496 -5 Lead-Free fpBGA 672 COM 32.8K LFEC33E-3FN484C 360 -3 Lead-Free fpBGA 484 COM 32.8K LFEC33E-4FN484C 360 -4 Lead-Free fpBGA 484 COM 32.8K LFEC33E-5FN484C 360 -5 Lead-Free fpBGA 484 COM 32.8K Part Number Part Number 5-9 Ordering Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LatticeECP Commercial Part Number I/Os Grade Package Pins/Balls Temp. LUTs LFECP6E-3FN484C 224 -3 Lead-Free fpBGA 484 COM 6.1K LFECP6E-4FN484C 224 -4 Lead-Free fpBGA 484 COM 6.1K LFECP6E-5FN484C 224 -5 Lead-Free fpBGA 484 COM 6.1K LFECP6E-3FN256C 195 -3 Lead-Free fpBGA 256 COM 6.1K LFECP6E-4FN256C 195 -4 Lead-Free fpBGA 256 COM 6.1K LFECP6E-5FN256C 195 -5 Lead-Free fpBGA 256 COM 6.1K LFECP6E-3QN208C 147 -3 Lead-Free PQFP 208 COM 6.1K LFECP6E-4QN208C 147 -4 Lead-Free PQFP 208 COM 6.1K LFECP6E-5QN208C 147 -5 Lead-Free PQFP 208 COM 6.1K LFECP6E-3TN144C 97 -3 Lead-Free TQFP 144 COM 6.1K LFECP6E-4TN144C 97 -4 Lead-Free TQFP 144 COM 6.1K LFECP6E-5TN144C 97 -5 Lead-Free TQFP 144 COM 6.1K Part Number I/Os Grade Package Pins/Balls Temp. LUTs LFECP10E-3FN484C 288 -3 Lead-Free fpBGA 484 COM 10.2K LFECP10E-4FN484C 288 -4 Lead-Free fpBGA 484 COM 10.2K LFECP10E-5FN484C 288 -5 Lead-Free fpBGA 484 COM 10.2K LFECP10E-3FN256C 195 -3 Lead-Free fpBGA 256 COM 10.2K LFECP10E-4FN256C 195 -4 Lead-Free fpBGA 256 COM 10.2K LFECP10E-5FN256C 195 -5 Lead-Free fpBGA 256 COM 10.2K LFECP10E-3QN208C 147 -3 Lead-Free PQFP 208 COM 10.2K LFECP10E-4QN208C 147 -4 Lead-Free PQFP 208 COM 10.2K LFECP10E-5QN208C 147 -5 Lead-Free PQFP 208 COM 10.2K Part Number I/Os Grade Package Pins/Balls Temp. LUTs LFECP15E-3FN484C 352 -3 Lead-Free fpBGA 484 COM 15.3K LFECP15E-4FN484C 352 -4 Lead-Free fpBGA 484 COM 15.3K LFECP15E-5FN484C 352 -5 Lead-Free fpBGA 484 COM 15.3K LFECP15E-3FN256C 195 -3 Lead-Free fpBGA 256 COM 15.3K LFECP15E-4FN256C 195 -4 Lead-Free fpBGA 256 COM 15.3K LFECP15E-5FN256C 195 -5 Lead-Free fpBGA 256 COM 15.3K Part Number I/Os Grade Package Pins/Balls Temp. LUTs LFECP20E-3FN672C 400 -3 Lead-Free fpBGA 672 COM 19.7K LFECP20E-4FN672C 400 -4 Lead-Free fpBGA 672 COM 19.7K LFECP20E-5FN672C 400 -5 Lead-Free fpBGA 672 COM 19.7K LFECP20E-3FN484C 400 -3 Lead-Free fpBGA 484 COM 19.7K LFECP20E-4FN484C 400 -4 Lead-Free fpBGA 484 COM 19.7K LFECP20E-5FN484C 400 -5 Lead-Free fpBGA 484 COM 19.7K Part Number I/Os Grade Package Pins/Balls Temp. LUTs LFECP33E-3FN672C 496 -3 Lead-Free fpBGA 672 COM 32.8K LFECP33E-4FN672C 496 -4 Lead-Free fpBGA 672 COM 32.8K LFECP33E-5FN672C 496 -5 Lead-Free fpBGA 672 COM 32.8K 5-10 Ordering Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LatticeECP Commercial (Continued) Part Number I/Os Grade Package Pins/Balls Temp. LUTs LFECP33E-3FN484C 360 -3 Lead-Free fpBGA 484 COM 32.8K LFECP33E-4FN484C 360 -4 Lead-Free fpBGA 484 COM 32.8K LFECP33E-5FN484C 360 -5 Lead-Free fpBGA 484 COM 32.8K LatticeEC Industrial Part Number I/Os Grade Package Pins/Balls Temp. LUTs LFEC1E-3QN208I 112 -3 Lead-Free PQFP 208 IND 1.5K LFEC1E-4QN208I 112 -4 Lead-Free PQFP 208 IND 1.5K LFEC1E-3TN144I 97 -3 Lead-Free TQFP 144 IND 1.5K LFEC1E-4TN144I 97 -4 Lead-Free TQFP 144 IND 1.5K LFEC1E-3TN100I 67 -3 Lead-Free TQFP 100 IND 1.5K LFEC1E-4TN100I 67 -4 Lead-Free TQFP 100 IND 1.5K Part Number I/Os Grade Package Pins/Balls Temp. LUTs LFEC3E-3FN256I 160 -3 Lead-Free fpBGA 256 IND 3.1K LFEC3E-4FN256I 160 -4 Lead-Free fpBGA 256 IND 3.1K LFEC3E-3QN208I 145 -3 Lead-Free PQFP 208 IND 3.1K LFEC3E-4QN208I 145 -4 Lead-Free PQFP 208 IND 3.1K LFEC3E-3TN144I 97 -3 Lead-Free TQFP 144 IND 3.1K LFEC3E-4TN144I 97 -4 Lead-Free TQFP 144 IND 3.1K LFEC3E-3TN100I 67 -3 Lead-Free TQFP 100 IND 3.1K LFEC3E-4TN100I 67 -4 Lead-Free TQFP 100 IND 3.1K Part Number I/Os Grade Package Pins/Balls Temp. LUTs LFEC6E-3FN484I 224 -3 Lead-Free fpBGA 484 IND 6.1K LFEC6E-4FN484I 224 -4 Lead-Free fpBGA 484 IND 6.1K LFEC6E-3FN256I 195 -3 Lead-Free fpBGA 256 IND 6.1K LFEC6E-4FN256I 195 -4 Lead-Free fpBGA 256 IND 6.1K LFEC6E-3QN208I 147 -3 Lead-Free PQFP 208 IND 6.1K LFEC6E-4QN208I 147 -4 Lead-Free PQFP 208 IND 6.1K LFEC6E-3TN144I 97 -3 Lead-Free TQFP 144 IND 6.1K LFEC6E-4TN144I 97 -4 Lead-Free TQFP 144 IND 6.1K I/Os Grade Package Pins/Balls Temp. LUTs LFEC10E-3FN484I 288 -3 Lead-Free fpBGA 484 IND 10.2K LFEC10E-4FN484I 288 -4 Lead-Free fpBGA 484 IND 10.2K LFEC10E-3FN256I 195 -3 Lead-Free fpBGA 256 IND 10.2K LFEC10E-4FN256I 195 -4 Lead-Free fpBGA 256 IND 10.2K LFEC10E-3QN208I 147 -3 Lead-Free PQFP 208 IND 10.2K LFEC10E-4QN208I 147 -4 Lead-Free PQFP 208 IND 10.2K Part Number 5-11 Ordering Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LatticeEC Industrial (Continued) Part Number I/Os Grade Package Pins/Balls Temp. LUTs LFEC15E-3FN484I 352 -3 Lead-Free fpBGA 484 IND 15.3K LFEC15E-4FN484I 352 -4 Lead-Free fpBGA 484 IND 15.3K LFEC15E-3FN256I 195 -3 Lead-Free fpBGA 256 IND 15.3K LFEC15E-4FN256I 195 -4 Lead-Free fpBGA 256 IND 15.3K I/Os Grade Package Pins/Balls Temp. LUTs LFEC20E-3FN672I 400 -3 Lead-Free fpBGA 672 IND 19.7K LFEC20E-4FN672I 400 -4 Lead-Free fpBGA 672 IND 19.7K LFEC20E-3FN484I 400 -3 Lead-Free fpBGA 484 IND 19.7K LFEC20E-4FN484I 400 -4 Lead-Free fpBGA 484 IND 19.7K I/Os Grade Package Pins/Balls Temp. LUTs LFEC33E-3FN672I 496 -3 Lead-Free fpBGA 672 IND 32.8K LFEC33E-4FN672I 496 -4 Lead-Free fpBGA 672 IND 32.8K LFEC33E-3FN484I 360 -3 Lead-Free fpBGA 484 IND 32.8K LFEC33E-4FN484I 360 -4 Lead-Free fpBGA 484 IND 32.8K Part Number Part Number LatticeECP Industrial Part Number I/Os Grade Package Pins/Balls Temp. LUTs LFECP6E-3FN484I 224 -3 Lead-Free fpBGA 484 IND 6.1K LFECP6E-4FN484I 224 -4 Lead-Free fpBGA 484 IND 6.1K LFECP6E-3FN256I 195 -3 Lead-Free fpBGA 256 IND 6.1K LFECP6E-4FN256I 195 -4 Lead-Free fpBGA 256 IND 6.1K LFECP6E-3QN208I 147 -3 Lead-Free PQFP 208 IND 6.1K LFECP6E-4QN208I 147 -4 Lead-Free PQFP 208 IND 6.1K LFECP6E-3TN144I 97 -3 Lead-Free TQFP 144 IND 6.1K LFECP6E-4TN144I 97 -4 Lead-Free TQFP 144 IND 6.1K I/Os Grade Package Pins/Balls Temp. LUTs LFECP10E-3FN484I 288 -3 Lead-Free fpBGA 484 IND 10.2K LFECP10E-4FN484I 288 -4 Lead-Free fpBGA 484 IND 10.2K LFECP10E-3FN256I 195 -3 Lead-Free fpBGA 256 IND 10.2K LFECP10E-4FN256I 195 -4 Lead-Free fpBGA 256 IND 10.2K LFECP10E-3QN208I 147 -3 Lead-Free PQFP 208 IND 10.2K LFECP10E-4QN208I 147 -4 Lead-Free PQFP 208 IND 10.2K I/Os Grade Package Pins/Balls Temp. LUTs LFECP15E-3FN484I 352 -3 Lead-Free fpBGA 484 IND 15.3K LFECP15E-4FN484I 352 -4 Lead-Free fpBGA 484 IND 15.3K LFECP15E-3FN256I 195 -3 Lead-Free fpBGA 256 IND 15.3K LFECP15E-4FN256I 195 -4 Lead-Free fpBGA 256 IND 15.3K Part Number Part Number 5-12 Ordering Information LatticeECP/EC Family Data Sheet Lattice Semiconductor LatticeECP Industrial (Continued) I/Os Grade Package Pins/Balls Temp. LUTs LFECP20E-3FN672I Part Number 400 -3 Lead-Free fpBGA 672 IND 19.7K LFECP20E-4FN672I 400 -4 Lead-Free fpBGA 672 IND 19.7K LFECP20E-3FN484I 400 -3 Lead-Free fpBGA 484 IND 19.7K LFECP20E-4FN484I 400 -4 Lead-Free fpBGA 484 IND 19.7K I/Os Grade Package Pins/Balls Temp. LUTs LFECP33E-3FN672I Part Number 496 -3 Lead-Free fpBGA 672 IND 32.8K LFECP33E-4FN672I 496 -4 Lead-Free fpBGA 672 IND 32.8K LFECP33E-3FN484I 360 -3 Lead-Free fpBGA 484 IND 32.8K LFECP33E-4FN484I 360 -4 Lead-Free fpBGA 484 IND 32.8K 5-13 LatticeECP/EC Family Data Sheet Supplemental Information November 2007 Data Sheet For Further Information A variety of technical notes for the LatticeECP/EC family are available on the Lattice web site at www.latticesemi.com. • • • • • • • LatticeECP/EC sysIO Usage Guide (TN1056) LatticeECP/EC sysCLOCK PLL Design and Usage Guide (TN1049) Memory Usage Guide for LatticeECP/EC Devices (TN1051) LatticeECP/EC DDR Usage Guide (TN1050) Power Estimation and Management for LatticeECP/EC and LatticeXP Devices (TN1052) LatticeECP-DSP sysDSP Usage Guide (TN1057) LatticeECP/EC sysCONFIG Usage Guide (TN1053) • IEEE 1149.1 Boundary Scan Testability in Lattice Devices For further information about interface standards refer to the following web sites: • JEDEC Standards (LVTTL, LVCMOS, SSTL, HSTL): www.jedec.org • PCI: ww.pcisig.com © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 6-1 Further Info_01.3 LatticeECP/EC Family Data Sheet Revision History February 2008 Data Sheet DS1000 Revision History Date Version Section June 2004 01.0 — August 2004 01.1 Change Summary Initial release. Introduction Added new device LFECP/LFEC33 in Table 1-1. Architecture Added New device LFECP/LFEC33 in Tables 2-9, 2-10 and 2-11. DC & Switching Characteristics Added New device LFECP/LFEC33 on Supply current (Standby) tables. Ordering Information Added 33K Logic Capacity Device in Part Number Description section. Added New device LFECP/LFEC33 on Initialization Supply current tables. Added EC33, ECP33 device: Industrial and Commercial to Part Number table. Corrected I/O counts in the part number tables for 100/144 TQFP and 208 PQFP packages to match Table 1-1 on page 1. November 2004 01.3 Introduction Changed DDR333 (166MHz) to DDR400 (200MHz) Added “RSDS” offering to the Features list: Flexible I/O Buffer Architecture Added information about Secondary Clock Sources Added information about DCS Added a section on “Recommended Power-up Sequence” Updated Figure 2-24 “DQS Routing” Added DSP Block performance numbers to Table 2-11 Added another row for RSDS in Table 2-13 and Table 2-14 DC & Switching Characteristics Updated new timing numbers Added numbers to derating table Added DC conditions to RSDS table Changed LVDS Max. VCCIO to 2.625 Added a row for RSDS in “Operating Condition” table Updated standby and initialization current table Added figure 3-12: sysConfig SPI port sequence Added DDR Timing Table and DDR Timings Figure 3-6 Pinout Information Added LFECP/EC6 to Pin Information Added LFECP/EC6 to Power Supply and NC Connections Added LFECP/EC6 144 TQFP Logic Signal Connections Added LFECP/EC6 208 PQFP Logic Signal Connections Added LFECP/EC6 256 fpBGA Logic Signal Connections Added LFECP/EC6 484 fpBGA Logic Signal Connections Ordering Information Added 33K Logic Capacity Device in Part Number Description section. Added Part Number table for Commercial EC33. Added Part Number table for Commercial ECP33. Added Part Number table for Industrial EC33. Added Part Number table for Industrial ECP33. © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 7-1 Revision History LatticeECP/EC Family Data Sheet Lattice Semiconductor Date Version December 2004 01.4 Section Architecture Pinout Information Change Summary Updated Hot Socketing Recommended Power Up Sequence section. Added LFEC1, LFEC3, LFECP/EC10, LFECP/EC15 to Pin Information Added LFEC1, LFEC3, LFECP/EC10, LFECP/EC15 to Power Supply and NC Connections Added LFEC1 and LFEC3 100 TQFP Pinout Added LFEC1 and LFEC3 144 TQFP Pinout Added LFEC1, LFEC3 and LFECP/EC10 208 PQFP Pinout Added LFEC3, LFECP/EC10 and LFECP/EC15 256 fpBGA Pinout Added LFECP/EC10 and LFECP/EC15 484 fpBGA Pinout Ordering Information Added Lead-Free Package Designators Added Lead-Free Ordering Part Numbers Supplemental Information April 2005 01.5 Architecture Updated list of technical notes. EBR memory support section has been updated with clarification. Updated sysIO buffer pair section. DC & Switching Characteristics Hot Socketing Specification has been updated. DC Electrical Characteristics table (IIL, IIH) has been updated. Supply Current (Standby) table has been updated. Initialization Supply Current table has been updated. External Switching Characteristics section has been updated. Removed tRSTW spec. from PLL Parameter table. tRST specifications have been updated. sysCONFIG Port Timing Specifications (tBSCL, tIODISS, tPRGMRJ) have been updated. Pinout Information Added LFECP/EC33 Pinout Information Pin Information Summary table has been updated. Power Supply and NC Connection table has been updated. 484-fpBGA logic connection has been updated (Ball # J6, J17, P6 and P17 for ECP/EC33 are now called VCCPLL). 672-fpBGA logic connection has been updated (Ball # K19, L8, U19, U8 for ECP/EC33 are now called VCCPLL). May 2005 01.6 Introduction ECP/EC33 EBR SRAM Bits and Blocks have been updated to 498K and 54 respectively. Architecture Table 2-10 has been updated (ECP/EC33 EBR SRAM Bits and Blocks have been updated to 498K and 54 respectively.) Recommended Power Up Sequence section has been removed. DC & Switching Characteristics Supply Current (Standby) table has been updated. Initialization Supply Current table has been updated. Vos test condition has been updated to (VOP+VOM)/2. Register-to-Register performance table has been updated (rev. G 0.27). External switching characteristics have been updated (rev. G 0.27). Internal timing parameters have been updated (rev. G 0.27). Timing adders have been updated (rev. G 0.27). sysCONFIG port timing specifications have been updated. Pinout Information Pin Information Summary table has been updated. Power Supply and NC Connection table has been updated. Ordering Information OPN list has been updated. 7-2 Revision History LatticeECP/EC Family Data Sheet Lattice Semiconductor Date Version September 2005 02.0 Section Architecture DC & Switching Characteristics Change Summary sysIO section has been updated. Recommended Operating Conditions has been updated with VCCPLL. DC Electrical Characteristics table has been updated Removed 5V Tolerant Input Buffer section. Register-to-Register performance table has been updated (rev. G 0.28). LatticeECP/EC External Switching Characteristics table has been updated (rev. G 0.28). LatticeECP/EC Internal Switching Characteristics table has been updated (rev. G 0.28). LatticeECP/EC Family Timing Adders have been updated (rev. G 0.28). sysCLOCK PLL timing table has been updated (rev. G 0.28) LatticeECP/EC sysCONFIG Port Timing specification table has been updated (rev. G 0.28). Master Clock table has been updated (rev. G 0.28). JTAG Port Timing specification table has been updated (rev. G 0.28). Pinout Information November 2005 02.1 DC & Switching Characteristics Signal Description table has been updated with VCCPLL. Pin-to-Pin Performance table has been updated (G 0.30) - 4:1MUX, 8:1MUX, 16:1MUX, 32:1MUX Register-to-Register Performance (G 0.30) - No timing number changes. External Switching Characteristics (G 0.30) - No timing number changes. Internal Switching Characteristics (G 0.30) -tSUP_DSP, tHP_DSP, tSUO_DSP, tHO_DSP, tCOI_DSP, tCOD_DSP numbers have been updated. Family Timing Adders (G 0.30) - No timing number changes. sysCLOCK PLL Timing (G 0.30) - No timing number changes. sysCONFIG Port Timing Specifications (G 0.30) - No timing number changes. Master Clock (G 0.30) - No timing number changes. JTAG Port Timing Specification (G 0.30) - No timing number changes. Ordering Information Added 208-PQFP lead-free part numbers. Added footnote 3. to VCCAUX in the Recommended Operating Conditions table. March 2006 02.2 DC & Switching Characteristics January 2007 02.3 Architecture EBR Asynchronous Reset section added. February 2007 02.4 Architecture Updated EBR Asynchronous Reset section. Updated Maximum Number of Elements in a Block table - MAC value for x9 changed to 2. May 2007 02.5 Architecture November 2007 02.6 DC & Switching Characteristics Updated text in Ripple Mode section. Added JTAG Port Waveforms diagram. Updated tRST timing information in the sysCLOCK PLL Timing table. Pinout Information Supplemental Information February 2008 02.7 DC & Switching Characteristics Added Thermal Management text section. Updated title list. Read/Write Mode (Normal) and Read/Write Mode with Input and Output Registers waveforms in the EBR Memory Timing Diagrams section have been updated. 7-3