ispXPGA Family ® Includes High, Performance Low-Cost “E-Series” July 2008 ■ Non-volatile, Infinitely Reconfigurable • Microprocessor configuration interface • Program E2CMOS while operating from SRAM • Instant-on - Powers up in microseconds via on-chip E2CMOS® based memory • No external configuration memory • Excellent design security, no bit stream to intercept • Reconfigure SRAM based logic in milliseconds ■ Eight sysCLOCK™ Phase Locked Loops (PLLs) for Clock Management • • • • • ■ High Logic Density for System-level Integration • • • • Data Sheet DS1026 139K to 1.25M system gates 160 to 496 I/O 1.8V, 2.5V, and 3.3V VCC operation Up to 414Kb sysMEM™ embedded memory True PLL technology 10MHz to 320MHz operation Clock multiplication and division Phase adjustment Shift clocks in 250ps steps ■ sysIO™ for High System Performance • High speed memory support through SSTL and HSTL • Advanced buses supported through PCI, GTL+, LVDS, BLVDS, and LVPECL • Standard logic supported through LVTTL, LVCMOS 3.3, 2.5 and 1.8 • 5V tolerant I/O for LVCMOS 3.3 and LVTTL interfaces • Programmable drive strength for series termination • Programmable bus maintenance ■ High Performance Programmable Function Unit (PFU) • Four LUT-4 per PFU supports wide and narrow functions • Dual flip-flops per LUT-4 for extensive pipelining • Dedicated logic for adders, multipliers, multiplexers, and counters ■ Flexible Memory Resources • Multiple sysMEM Embedded RAM Blocks – Single port, Dual port, and FIFO operation • 64-bit distributed memory in each PFU – Single port, Double port, FIFO, and Shift Register operation ■ Two Options Available • High-performance sysHSI (standard part number) • Low-cost, no sysHSI (“E-Series”) ■ sysHSI™ Capability for Ultra Fast Serial Communications ■ Flexible Programming, Reconfiguration, and Testing • Up to 800Mbps performance • Up to 20 channels per device • Built in Clock Data Recovery (CDR) and Serialization and De-serialization (SERDES) • Supports IEEE 1532 and 1149.1 Table 1. ispXPGA Family Selection Guide System Gates ispXPGA 125/E ispXPGA 200/E ispXPGA 500/E ispXPGA 1200/E 139K 210K 476K 1.25M PFUs 484 676 1764 3844 LUT-4s 1936 2704 7056 15376 Logic FFs 3.8K 5.4K 14.1K 30.7K sysMEM Memory 92K 111K 184K 414K Distributed Memory 30K 43K 112K 246K 20 24 40 90 EBR 1 sysHSI Channels User I/O Packaging 4 8 12 20 160/176 160/208 336 496 256 fpBGA 516 fpBGA2 256 fpBGA 516 fpBGA2 516 fpBGA2 900 fpBGA 680 fpSBGA2 900 fpBGA 1. “E-Series” does not support sysHSI. 2. FH516 package was converted to F516 via PCN# 09A-08. © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 DS1026_14.1 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Family Overview The ispXPGA family of devices provides the ideal vehicle for the creation of high-performance logic designs that are both non-volatile and infinitely re-programmable. Other FPGA solutions force a compromise, being either reprogrammable or non-volatile. This family couples this capability with a mainstream architecture containing the features required for today’s system-level design. The ispXPGA family is available in two options. The standard device supports sysHSI capability for ultra fast serial communications while the lower-cost “E-Series” supports the same high-performance FPGA fabric without the sysHSI Block. Electrically Erasable CMOS (E2CMOS) memory cells provide the ispXPGA family with non-volatile capability. These allow logic to be functional microseconds after power is applied, allowing easy interfacing in many applications. This capability also means that expensive external configuration memories are not required and that designs can be secured from unauthorized read back. Internal SRAM cells allow the device to be infinitely reconfigured if desired. Both the SRAM and E2CMOS cells can be programmed and verified through the IEEE 1532 industry standard. Additionally, the SRAM cells can be configured and read-back through the sysCONFIG™ peripheral port. The family spans the density and I/O range required for the majority of today’s logic designs, 139K to 1.25M system gates and 160 to 496 I/O. The devices are available for operation from 1.8V, 2.5V, and 3.3V power supplies, providing easy integration into the overall system. System-level design needs are met through the incorporation of sysMEM dual-port memory blocks, sysIO advanced I/O support, and sysCLOCK Phase Locked Loops (PLLs). High-speed serial communications are supported through multiple sysHSI blocks, which provide clock data recovery (CDR) and serialization/de-serialization (SERDES). The ispLEVER™ design tool from Lattice allows easy implementation of designs using the ispXPGA product. Synthesis library support is available for major logic synthesis tools. The ispLEVER tool takes the output from these common synthesis packages and place and routes the design in the ispXPGA product. The tool supports floor planning and the management of other constraints within the device. The tool also provides outputs to common timing analysis tools for timing analysis. To increase designer productivity, Lattice provides a variety of pre-designed modules referred to as IP cores for the ispXPGA product. These IP cores allow designers to concentrate on the unique portions of their design while using pre-designed blocks to implement standard functions such as bus interfaces, standard communication interfaces, and memory controllers. Through the use of advanced technology and innovative architecture the ispXPGA FPGA devices provide designers with excellent speed performance. Although design dependent, many typical designs can run at over 150MHz. Certain designs can run at over 300MHz. Table 2 details the performance of several building blocks commonly used by logic designers. Table 2. ispXPGA Speed Performance for Typical Building Blocks Function Performance 8:1 Asynch MUX 150 MHz 1:32 Asynch Demultiplexer 125 MHz 8 x 8 2-LL Pipelined Multiplier 225 MHz 32-bit Up/Down Counter 290 MHz 32-bit Shift Register 360 MHz 2 Lattice Semiconductor ispXPGA Family Data Sheet Architecture Overview The ispXPGA architecture is a symmetrical architecture consisting of an array of Programmable Function Units (PFUs) enclosed by Input Output Groups (PICs) with columns of sysMEM Embedded Block RAMs (EBRs) distributed throughout the array. Figure 1 illustrates the ispXPGA architecture. Each PIC has two corresponding sysIO blocks, each of which includes one input and output buffer. On two sides of the device, between the PICs and the sysIO blocks, there are sysHSI High-Speed Interface blocks. The symmetrical architecture allows designers to easily implement their designs, since any logic function can be placed in any section of the device. The PFUs contain the basic building blocks to create logic, memory, arithmetic, and register functions. They are optimized for speed and flexibility allowing complex designs to be implemented quickly and efficiently. The PICs interface the PFUs and EBRs to the external pins of the device. They allow the signals to be registered quickly to minimize setup times for high-speed designs. They also allow connections directly to the different logic elements for fast access to combinatorial functions. The sysMEM EBRs are large, fast memory elements that can be configured as RAM, ROM, FIFO, and other storage types. They are designed to facilitate both single and dual-port memory for high-speed applications. These three components of the architecture are interconnected via a high-speed, flexible routing array. The routing array consists of Variable Length Interconnect (VLI) lines between the PICs, PFUs, and EBRs. There is additional routing available to the PFU for feedback and direct routing of signals to adjacent PFUs or PICs. The sysIO blocks consist of configurable input and output buffers connected directly to the PICs. These buffers can be configured to interface with 16 different I/O standards. This allows the ispXPGA to interface with other devices without the need for external transceivers. The sysHSI blocks provide the necessary components to allow the ispXPGA device to transfer data at up to 800Mbps using the LVDS standard. These components include serializing, de-serializing, and clock data recovery (CDR) logic. The sysCLOCK blocks provide clock multiplication/division, clock distribution, delay compensation, and increased performance through the use of PLL circuitry that manipulates the global clocks. There is one sysCLOCK block for each global clock tree in the device. 3 Lattice Semiconductor ispXPGA Family Data Sheet Figure 1. ispXPGA Block Diagram PFU PIC sysMEM Block sysCLOCK PLL sysHSI Block sysIO Buffer Programmable Function Unit The Programmable Function Unit (PFU) is the basic building block of the ispXPGA architecture. The PFUs are arranged in rows and columns in the device with PFU (1,1) referring to (row 1, column 1). Each PFU consists of four Configurable Logic Elements (CLEs), four Configurable Sequential Elements (CSEs), and a Wide Logic Generator (WLG). By utilizing these components, the PFU can implement a variety of functions. Table 3 lists some of the function capabilities of the PFU. There are 57 inputs to each PFU and nine outputs. The PFU uses 20 inputs for logic, and 37 inputs drive the control logic from which six control signals are derived for the PFU. Table 3. Function Capability of ispXPGA PFU Function Capability Look-up table LUT-4, LUT-5, LUT-6 Wide logic functions Up to 20 input logic functions Multiplexing 2:1, 4:1, 8:1 Arithmetic logic Dedicated carry chain and booth multiplication logic Single-port RAM 16X1, 16X2, 16X4, 32X1, 32X2, 64X1 Double-port RAM 16X1, 16X2, 32X1 Shift register 8-bit shift registers (up to 32-bit shift capability) 4 Lattice Semiconductor ispXPGA Family Data Sheet Figure 2. ispXPGA PFU COUT(r,c) OE OE PFUCLK0 PFUCLK1 CEB0 CEB1 SR WLGW0 S3 SYNC/ASYNC CLE0 WIN2 CCG WIN3 D S R IN WIN2 WIN3 CLK/LE CE WLGW1 D S R SEL0 XIN3 LUT-4 CCG SEL0 IN XIN2 XIN3 SEL1 SEL1 4C YIN0 YIN2 LUT-4 COUT LUT-4 SUM S1 WLGY0 SYNC/ASYNC CLE2 IN YIN2 YIN3 WLGY1 4D CLE3 ZIN2 LUT-4 WLGZ0 CCG ZIN3 IN ZIN2 ZIN3 SEL3 SEL3 CIN(r,c) from COUT(r-1,c) 5 CLK/LE CLK/LE CE CE DD SS RR S0 SYNC/ASYNC ZIN1 Y0 QQ Y1 Q CLK/LE CE SEL2 COUT LUT-4 SUM DD SS RR D S R SEL2 ZIN0 X1 Q CLK/LE CE CCG YIN3 D S R X0 QQ CLK/LE CLK/LE CE CE WLGX1 SYNC/ASYNC YIN1 DD SS RR S2 Wide Logic Generator CLE1 XIN2 WLGX0 4B COUT LUT-4 SUM SYNC/ASYNC XIN1 W1 Q CLK/LE CE SEL0 XIN0 W0 Q CSE1 LUT-4 COUT LUT-4 SUM CSE2 WIN1 CSE0 COUT 4A WIN0 WLGZ1 CLK/LE CLK/LE CE CE D S R Z0 QQ Q CLK/LE CE CSE3 Control Logic Z1 Lattice Semiconductor ispXPGA Family Data Sheet Configurable Logic Element The CLE is made up of a four-input Look-up Table (LUT-4), a Carry Chain Generator (CCG), and a two-input AND gate. The LUT-4 creates various combinatorial and memory elements, the CCG creates a single one-bit full adder, and the two-input AND gate can expand the CCG to incorporate Booth Multiplier capability by feeding the output of the AND gate to one of the inputs of the CCG. Of the five inputs that feed each CLE, two are dedicated inputs into each LUT-4 and the remaining three take on varying functionality. The third and fourth inputs can be used as either inputs to the LUT-4 or as a Feed-Thru to the CSE via the WLG. The fifth input can be a data port when the LUT is configured as Distributed Memory, a select line for multiplexer operation, or a Feed-Thru directly to the CSE via the WLG (Figure 2). Look-Up Table – Combinatorial Mode In combinatorial mode, the LUT-4 can implement any logic function up to four inputs. By using the carry chain and the WLG, each LUT-4 can be combined to form the enhanced functions listed in Table 3. Look-Up Table – Distributed Memory Mode In the distributed memory mode, the LUT functions as a memory element. The inputs to the LUT function as Address and Data. Each PFU is capable of implementing up to 64 SRAM bits. Both single and double port RAM can be performed in the PFU (Table 3). Furthermore, the distributed memory can be configured as either synchronous or asynchronous memory. Figure 3 illustrates the LUT while in distributed memory mode. When using any LUT in the PFU in memory mode, the Set/Reset signal will be used for Write Enable (WE(SR)) and the CLK0 signal will be used as the clock for synchronous read and write. Figure 3. LUT in Distributed Memory Mode PFUCLK0 CEB0 WE (SR) ADDR[0] (IN0) ADDR[1] (IN1) ADDR[2] (IN2) LUT-4 DOUT (4A) ADDR[3] (IN3) DIN (SEL) Look-Up Table – Shift Register Mode In the shift register mode, the LUT functions as a 1-bit to 8-bit shift register. This means that each PFU can implement up to four 8-bit shift registers or any cascaded combination. Figure 4 illustrates the LUT when configured in shift register mode. 6 Lattice Semiconductor ispXPGA Family Data Sheet Figure 4. LUT in Shift Register Mode PFUCLK0 CEB0 SEL (SHIFTIN) LUT-4 SHIFTOUT (4A) Carry Chain Generator The Carry Chain Generator is useful for implementing high-speed arithmetic functions. The CCG consists of a twoinput XOR gate whose carryout can be cascaded with the input of the adjacent CCG. As shown in Figure 5, the carryin signal feeds CLE3 of the PFU and is propagated through CLE2 and CLE1 before reaching CLE0. The sum output of the CCG can be fed to the CSE through the WLG. The carryout must propagate to CLE0 for use outside the PFU. The carryout from the PFU can feed the W0 input of CSE0. The CCG also helps to effectively implement wider functions by using its logic elements to expand the capabilities of the LUT-4. Figure 5. Carry Chain Generator COUT(r,c) COUT to CSE0 CLE0 SUM3 CLE1 SUM2 CLE2 SUM1 CLE3 SUM0 A B COUT SUM CIN CIN from Routing COUT(r+1,c) Wide Logic Generator The WLG contains the logic necessary to implement wide gate functions. This is made up of a set of multiplexers that are located between the CLE and the CSE. The WLG helps in enhancing the wide gating capability of the PFU. The outputs of each CLE can be cascaded in the WLG to build wide gating functions. Wide multiplexing functions are also possible with a similar use of the WLG. Figure 6 illustrates the WLG. 7 Lattice Semiconductor ispXPGA Family Data Sheet Figure 6. ispXPGA Wide Logic Generator COUT WIN2 WIN3 4A S3 SEL0 WLGW0 WLGW1 4B XIN2 XIN3 WLGX0 S2 SEL1 WLGX1 SEL3 4C SEL2 4D YIN2 YIN3 S1 WLGY0 WLGY1 ZIN2 ZIN3 WLGZ0 S0 WLGZ1 Configurable Sequential Element There are two registers in each CSE for a total of eight registers in each PFU. This high register count assists in implementing efficient pipelined applications with no utilization penalty. Each register can be configured as a latch or D type flip-flop with either synchronous or asynchronous set or reset. Figure 2 shows the signals that feed the register’s D inputs. Feed-through signals in the architecture ensure that registers are efficiently utilized even if the accompanying LUT is occupied. Control Logic The control signals available to the registers in a PFU are Clock, Clock Enable, and Set/Reset. Figure 7 shows the various options available to generate the clock signal. As can be seen, the clock signal is the output of a 12:1 MUX with true and compliment versions available from the 12:1 MUX. Each CSE can chose whether it uses the true or complement form of the clock. Figure 8 shows the Set/Reset selection for each PFU in the ispXPGA. A common 8 Lattice Semiconductor ispXPGA Family Data Sheet Set/Reset signal controls all the registers for each PFU. This common Set/Reset signal is composed of the logical OR term of the Global Set/Reset signal (GSR) and the selected signal from routing. The polarity of this signal is not controllable inside the PFU. The polarity of the Global Set/Reset signal (GSR) is programmable. Figure 9 shows the Clock Enable and Output Enable selection for each PFU. Figure 7. Clock Selection per PFU CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 PFUCLK0 PFUCLK1 From routing 4 Figure 8. Set/Reset Selection per PFU 8 From routing Set/Reset GSR Figure 9. Clock Enable and Output Enable Selection per PFU 8 CEB0 From routing 8 CEB1 From routing OE Programmable Input/Output Cell The Programmable Input/Output Cell (PIC) is an essential part of the symmetrical architecture of the ispXPGA Family. The PICs interface the PFUs and EBRs to the sysIO and sysHSI blocks of the device. Each PIC contains two Programmable Input/Outputs (PIOs) with a total of 21 inputs and 10 outputs. There are 18 inputs from routing, two inputs from the sysIO buffers, and the Global Set/Reset signal. Four outputs of the PIC connect to routing and two outputs are available as Output Enables for the tri-statable Long Lines. The remaining four outputs feed the sysIO buffers directly (one output enable and one output to each). Each PIC associated with a sysHSI block has four additional inputs and six additional outputs to support the sysHSI blocks. The four additional inputs come from the sysHSI block associated with the PIC. The four of the six additional outputs come from the PIC outputs and feed the sysHSI block, while the remaining two outputs feed routing. Figure 10 shows the block diagram of the PIC with the sysHSI block inputs and outputs. 9 Lattice Semiconductor ispXPGA Family Data Sheet Figure 10. ispXPGA PIC GSR sysIO 9 2 From routing PIO0 To routing 2 From sysHSI block 2 To sysHSI block Only for PICs associated with sysHSI blocks To routing Only for PICs associated with sysHSI blocks PIC 2 To routing From sysHSI block 2 To sysHSI block 9 2 To routing PIO1 From routing sysIO OE1 OE0 Programmable Input/Output The PIO is the building block of a PIC. The PIO has a total of 11 inputs and five outputs. Nine of the 11 inputs are generated from routing. The inputs from routing are the PIO Input (IN), Feed-Thru (FT), Clock (CLK), Input Clock Enable (ICE), Input Set/Reset (ISR), Output Clock Enable (OCEN), Output Set/Reset (OSR), PIO Output Enable (OEN), and PIO Input Enable (IEN). The remaining inputs are the sysIO input buffer signal and the Global Set/ Reset signal. Three of the five outputs (OUT0, OUT1, and OE) feed routing. The last two outputs feed the sysIO buffer directly as the output and output enable of the sysIO output buffer. PIOs associated with sysHSI blocks contain two additional inputs and outputs to support the sysHSI block. The two inputs come from the sysHSI block associated with the PIO, and the two outputs feed the sysHSI block. One of the inputs routes directly through the PIO to routing, while the other is multiplexed with the Feed-Thru, register bypass, and Q output of the register to form the OUT1 output of the PIO. The outputs to the sysHSI block are the same signals as the outputs which feed the sysIO buffers (sysIO Output and sysIO Output Enable). Each PIO has an input register, an output register, and an output enable register as shown in Figure 11. The input register path of the PIO has a ‘delay’ option, which slows the data-flow. A two-input OR function of the Global Set/ Reset (GSR) and Set/Reset (ISR or OSR) signals creates the set/reset term for the respective registers. Each PIO has two pairs of set/reset and clock enable signals. One is exclusive to the input register, whereas the other is common for both the output and output enable registers. The clock (CLK) is common to all registers in a PIO, and the polarity of the clock is controllable. The input, output, and the output enable registers can be configured as a latch or D-type flip-flop. Each PIO is capable of generating an output enable signal, which in turn becomes a PIC output. 10 Lattice Semiconductor ispXPGA Family Data Sheet Figure 11. ispXPGA PIO Only for PIOs associated with sysHSI Blocks From sysHSI block From sysHSI block To Routing Feed-through (FT) From sysIO Input Clock (CLK) Input Clock Enable (ICEN) OUT0 Delay D Q OUT1 CLK/LE CE S R Input Set/Reset (ISR) Global Set/Reset(GSR) To sysIO Output PIO Input (IN) D Q To sysHSI block CLK/LE Output Clock Enable (OCEN) CE S R Output Set/Reset (OSR) PIO Output Enable(OEN) Only for PIOs Associated with sysHSI Blocks To sysHSI block D Q To sysIO Output Enable CLK/LE CE PIO Input Enable (IEN) S R OE VLI Routing Resources The ispXPGA architecture contains a Variable-Length-Interconnect (VLI) routing technology connecting the PFUs, PICs, and EBRs in the device. There are four types of routing resources, Global Lines, Long Lines, General Interconnect, and Local Lines forming the global routing structure. This allows a signal to be routed to any element in the device with the optimal delay. The Global Lines consist of global clock lines and a global set/reset line. These lines are routed to all elements in the device. They are specifically designed for high speed, predictable timing regardless of fan-out. The global clock lines can also be used as dedicated inputs. The Long Lines consist of Horizontal and Vertical Long Lines (HLL and VLL). The VLL and HLL are tri-statable lines spanning the entire device. These lines allow fast routing for high fan-out nets and general-purpose functions. The General Interconnect consists of Double and Deca Lines. The Double Lines connect up to three elements (two plus the driving element), while the Deca Lines connect up to eleven elements (ten plus the driving element). The Local Lines are extremely fast routing paths consisting of Feedback and Direct Connect Lines. The Feedback Lines are internal routing paths from the PFU outputs to the PFU inputs. The Direct Connect Lines connect all adjacent elements. The Common Interface Block (CIB) provides the link between the logic element (PFU, PIC, or EBR) and the VLI Routing resources. The CIB is a switch matrix that can be programmed to connect virtually any routing resource to any input or output of the logic element. 11 Lattice Semiconductor ispXPGA Family Data Sheet Memory The ispXPGA architecture provides a large amount of resources for memory intensive applications. Embedded Block RAMs (EBRs) are available to complement the Distributed Memory that is configured in the PFUs (see LookUp Table -Distributed Memory Mode in the PFU section above). Each memory element can be configured as RAM or ROM. Additionally, the internal logic of the device can be used to configure the memory elements as FIFO and other storage types. These EBRs are referred to as sysMEM blocks. Refer to Table 1 for memory resources per device. sysMEM Blocks The sysMEM blocks are organized in columns distributed throughout the device. Each EBR contains 4.6K bits of dual-port RAM with dedicated control, address, and data lines for each port. Each column of sysMEM blocks has dedicated address and control lines that can be used by each block separately or cascaded to form larger memory elements. The memory cells are symmetrical and contain two sets of identical control signals. Each port has a read/write clock, clock enable, write enable, and output enable. Figure 12 illustrates the sysMEM block. The ispXPGA memory block can operate as single-port or dual-port RAM. Supported configurations are: • • • • 512 x 9 bits single-port 256 x 18 bits single-port 512 x 9 bits dual-port 256 x18 bits dual-port (8 bits data / 1 bit parity) (16 bits data / 2 bits parity) (8 bits data / 1 bit parity) (16 bits data / 2 bits parity) The data widths of “9” and “18” are ideal for applications where parity is necessary. This allows 9 data bits, 8 data bits plus a parity bit, 18 data bits, or 16 data bits plus two parity bits. The logic for generating and checking the parity must be customized separately. Figure 12. sysMEM Block Diagram ADDRA ADDRB DATAA DATAB CLKA CEA CLKB sysMEM Block CEB WEA WEB OEA OEB Read and Write Operations The ispXPGA EBR has fully synchronous read and write operations as well as an asynchronous read operation. These operations allow several different types of memory to be implemented in the device. Synchronous Read: The Clock Enable (CE) and Write Enable (WE) signals control the synchronous read operation. When the CE signal is low, the clock is enabled. When the WE signal is low the read operation begins. Once the address (ADDR) is present, a rising clock edge (or falling edge depending on polarity) causes the stored data to be available on the DATA port. Figure 13 illustrates the synchronous read timing. 12 Lattice Semiconductor ispXPGA Family Data Sheet Figure 13. EBR Synchronous Read Timing Diagram tEBCPW CLK CE tEBCES tEBCEH WE tEBWES tEBWEH OE DATA tEBOEDIS Invalid Data tEBCO tEBWEDIS Valid Data tEBADDS ADDR tEBOEEN tEBWEEN Valid Data tEBADDH Synchronous Write: The WE signal controls the synchronous write operation. When the WE signal is high, the write operation begins. Once the address and data are present and the Output Enable (OE) is active, a rising clock edge (or falling edge depending on polarity) causes the data to be stored into the EBR. Figure 14 illustrates the synchronous write timing. Figure 14. EBR Synchronous Write Timing Diagram CLK tEBPW tEBWES WE tEBWEH tEBDATAH DATA tEBDATAS tEBADDH ADDR WRITE tEBADDS WRITE Asynchronous Read: The WE signal controls the asynchronous read operation. When the WE signal is low, the read operation begins. Shortly after the address is present, the stored data is available on the DATA port. Figure 15 illustrates the asynchronous read timing. For more information about the EBR, refer to Lattice technical note number TN1028 ispXPGA Memory Usage Guidelines, available at www.latticesemi.com. Figure 15. EBR Asynchronous Read Timing Diagram WE OE tEBOEDIS Invalid Data DATA0 DATA ADDR ADDR0 tEBOEEN tEBWEEN tEBWEDIS DATA1 tEBARAD_H DATA1 ADDR1 tEBARADO 13 ADDR2 Lattice Semiconductor ispXPGA Family Data Sheet sysCLOCK PLL Description The sysCLOCK PLL circuitry consists of Phase-Lock Loops (PLLs) and the various dividers, reset, and feedback signals associated with the PLLs. This feature gives the user the ability to synthesize clock frequencies and generate multiple clock signals for routing within the device. Furthermore, it can generate clock signals that are aligned either at the board level or the device level. The ispXPGA devices provide up to eight PLLs. Each PLL receives its input clock from its associated global clock pin, and its output is routed to the associated global clock net. For example, PLL0 receives its clock input from the GCLK0 global clock pin and provides output to the CLK0 global clock net. The PLL also has the ability to output a secondary clock that is a division of the primary clock output. When using the secondary clock, the secondary clock will be routed to the neighboring global clock net. For example, PLL0 will drive its primary clock output on the CLK0 global clock net and its secondary clock output will drive the CLK1 global clock net. Additionally, each PLL has a set of PLL_RST, PLL_FBK, and PLL_LOCK signals. The PLL_RST signal can be generated through routing or a dedicated dual-function I/O pin. The PLL_FBK signal can be generated through a dedicated dual-function I/O pin or internally from the Global Clock net associated with the PLL. The PLL_LOCK signal feeds routing directly from the sysCLOCK PLL circuit. Figure 17 illustrates how the PLL_RST and PLL_FBK signals are generated. Each PLL has four dividers associated with it, M, N, V, and K. The M divider is used to divide the clock signal, while the N divider is used to multiply the clock signal. The V divider allows the VCO frequency to operate at higher frequencies than the clock output, thereby increasing the frequency range. The K divider is only used when a secondary clock output is needed. This divider divides the primary clock output and feeds to the adjacent global clock net. Different combinations of these dividers allow the user to synthesize clock frequencies. Figure 16 shows the ispXPGA PLL block diagram. The PLL also has a delay feature that allows the output clock to be advanced or delayed to improve set-up and clock-to-out times for better performance. This operates by inserting delay on the input or feedback lines of the PLL. For more information on the PLL, please refer to Lattice technical note number TN1003, sysCLOCK PLL Usage and Design Guidelines, available at www.latticesemi.com. Figure 16. ispXPGA PLL Block Diagram PLL_LOCK CLK_OUT GCLK_IN Input Clock (M) Divider ÷ 1 to 32 Programmable +Delay -------------------- Post-scalar (V) Divider ÷ 1, 2, 4, 8, 16, 32 PLL (n) Programmable -Delay Clock Net PLL_RST Clock (K) Divider ÷ 2, 4, 8, 16, 32 To Adjacent_PLL From Adjacent_PLL Feedback Divider (N) X 1 to 32 PLL_FBK 14 Lattice Semiconductor ispXPGA Family Data Sheet Figure 17. ispXPGA PLL_RST and PLL_FBK Generation I/O/PLL_RST To PLL From Routing I/O/PLL_FBK To PLL From Clock Net Clock Routing The Global Clock Lines (GCLK) have two sources, their dedicated pins and the sysCLOCK circuit. Figure 18 illustrates the generation of the Global Clock Lines. Figure 18. Global Clock Line Generation From Routing GCLK0 GCLK7 CLK_OUT0 PLL0 CLK0 CLK_OUT7 CLK7 SEC_OUT0 PLL7 SEC_OUT7 From Routing GCLK1 GCLK6 CLK_OUT1 PLL1 CLK1 CLK_OUT6 CLK6 SEC_OUT1 PLL6 SEC_OUT6 From Routing GCLK2 GCLK5 CLK_OUT2 PLL2 CLK2 CLK_OUT5 CLK5 SEC_OUT2 PLL5 SEC_OUT5 From Routing GCLK3 GCLK4 CLK_OUT3 PLL3 CLK3 CLK_OUT4 CLK4 SEC_OUT3 PLL4 SEC_OUT4 sysIO Capability All the ispXPGA devices have eight sysIO banks, where each bank is capable of supporting multiple I/O standards. Each sysIO bank has its own I/O supply voltage (VCCO) and reference voltage (VREF) resources allowing each bank complete independence from the others. Each I/O is individually configurable based on the bank’s VCCO and VREF settings. In addition, each I/O has configurable drive strength, weak pull-up, weak pull-down, or a bus-keeper latch. Table 4 lists the number of I/Os supported per bank in each of the ispXPGA devices. In addition, 5V tolerant inputs are specified within an I/O bank that is connected to VCCO of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI interfaces. Table 5 lists the sysIO standards with the typical values for VCCO, VREF and VTT. The TOE, JTAG TAP pins, PROGRAM, CFG0 and DONE pins of the ispXPGA device are the only pins that do not have the sysIO capabilities. The TOE and CFG0 pins operate off the VCC of the device, supporting only the LVCMOS standard corresponding to the device supply voltage. The TAP pins have a separate supply voltage (VCCJ), which determines the LVCMOS standard corresponding to that supply voltage. There are three classes of I/O interface standards that are implemented in the ispXPGA devices. The first is the unterminated, single-ended interface. It includes the 3.3V LVTTL standard along with the 1.8V, 2.5V, and 3.3V LVCMOS interface standards. Additionally, PCI and AGP-1X are subsets of this type of interface. 15 Lattice Semiconductor ispXPGA Family Data Sheet The second type of interface implemented is the terminated, single-ended interface standard. This group of interfaces includes different versions of SSTL and HSTL interfaces along with CTT, and GTL+. Usage of these particular I/O interfaces requires an additional VREF signal. At the system level a termination voltage, VTT, is also required. Typically an output will be terminated to VTT at the receiving end of the transmission line it is driving. The third type of interface standards are the differential standards LVDS, BLVDS, and LVPECL. The differential standards require two I/O pins to create the differential pair. The logic level is determined by the difference in the two signals. Table 6 lists how these interface standards are implemented in the ispXPGA devices. For more information on sysIO capability, refer to Lattice technical note number TN1000, sysIO Usage Guidelines for Lattice Devices available at www.latticesemi.com. Figure 19. sysIO Banks per Device VCCO6 I/O 0 I/O N I/O 0 Bank 6 VREF0 GND I/O N VCCO5 Bank 5 Bank 0 VCCO0 VREF6 GND VCCO7 VREF7 GND I/O N Bank 7 I/O 0 VREF5 GND I/O N I/O 0 I/O 0 I/O N VREF1 GND I/O N VCCO4 Bank 4 Bank 1 VCCO1 Bank 2 VREF4 GND I/O 0 Bank 3 I/O N I/O 0 I/O N I/O 0 VCCO3 VREF3 GND VCCO2 VREF2 GND Table 4. Number of I/Os per Bank Device Max. Number of I/Os per Bank (N) XPGA 1200 62 XPGA 500 42 XPGA 200 26 XPGA 125 22 16 Lattice Semiconductor ispXPGA Family Data Sheet Table 5. ispXPGA Supported I/O Standards sysIO Standard VCCO VREF VTT LVTTL 3.3V N/A N/A LVCMOS-3.3 3.3V N/A N/A LVCMOS-2.5 2.5V N/A N/A LVCMOS-1.8 1.8V N/A N/A PCI 3.3V N/A N/A AGP-1X 3.3V N/A N/A SSTL3, Class I, II 3.3V 1.5V 1.5V SSTL2, Class I, II 2.5V 1.25V 1.25V HSTL, Class I 1.5V 0.75V 0.75V HSTL, Class III 1.5V 0.9V 1.5V GTL+ N/A 1.0V 1.5V LVPECL 3.3V N/A N/A LVDS 2.5V N/A N/A BLVDS 2.5V N/A N/A 1 1. VCCO must be 2.5V for high speed serial operations (sysHSI block). Table 6. Differential Interface Standard Support1 sysIO Buffer Not Using sysHSI Block LVDS BLVDS LVPECL sysIO Buffer Using sysHSI Block Driver Supported with external resistor network Supported Receiver Supported with standard termination Supported with standard termination Driver Supported with external resistor network Not supported Receiver Supported (may need termination) Supported (may need termination) Driver Supported with external resistor network Not supported Receiver Supported with termination Supported with termination 1. For more information, refer to Lattice technical note TN1000, sysIO Usage Guidelines, available at www.latticesemi.com. 17 Lattice Semiconductor ispXPGA Family Data Sheet High Speed Serial Interface Block (sysHSI Block)1 The High Speed Serial Interface (sysHSI) allows high speed serial data transfer over a pair of LVDS I/O. The ispXPGA devices have multiple sysHSI blocks. Each sysHSI block has two SERDES blocks which contain two main sub-blocks, Transmitter (with a serializer) and Receiver (with a deserializer) including Clock/Data Recovery Circuit (CDR). Each SERDES can be used as a full duplex channel. The two SERDES in sysHSI blocks share a common clock and must operate at the same nominal frequency. Figure 20 shows the sysHSI block. Device features support two data coding modes: 10B/12B and 8B/10B (for use with other encoding schemes, see Lattice’s sysHSI technical notes). The encoding and decoding of the 10B/12B standard are performed within the sysHSI block. For the 8B/10B standard, the symbol boundaries are aligned internally but the encoding and decoding are performed outside the sysHSI block. Each SERDES block receives a single high speed serial data input stream (with embedded clock) from an input, and provide a low speed 10-bit wide data stream and a recovered clock to the device. For transmitting, SERDES converts a 10-bit wide low-speed data stream to a single high-speed data stream with embedded clock for output. Additionally, multiple sysHSI blocks can be grouped together to form a source synchronous interface of 1-10 channels. For more information on the SERDES/CDR, refer to Lattice technical note number TN1020, sysHSI Usage Guidelines. Figure 20. sysHSI Block Diagram SOUT SERDES(HSI#A) Serializer SIN 10 TXD 10 RXD RECCLK From PICs To PICs To PICs Deserializer and Clock/Data Recovery SYDT sysIO Shared Source Synchronous Pins Drive Multiple sysHSI blocks CDRRST CAL SS_CLKOUT CSLOCK CSPLL REFCLK SS_CLKIN CDRRST SYDT To PICs From PICs From PICs To PICs From Global Clock Tree From PICs To PICs Deserializer and Clock/Data Recovery SIN RECCLK 10 SOUT Serializer SERDES(HSI#B) 1. “E-Series” does not support sysHSI. 18 10 RXD TXD To PICs To PICs From PICs Lattice Semiconductor ispXPGA Family Data Sheet Configuration and Programming The ispXPGA family of devices takes a unique approach to FPGA configuration memory. It contains two types of memory, Static RAM and non-volatile E2CMOS cells. The static RAM is used to control the functionality of the device during normal operation and the E2CMOS memory cells are used to load the SRAM. The E2CMOS memory module can be thought of as the hard drive for the ispXPGA configuration and the SRAM as the working configuration memory. There is a one-to-one relationship between SRAM memory and the E2CMOS cells. The SRAM can be configured either from the E2CMOS memory or from an external source, as shown in Figure 21. Figure 21 shows the different ports and modes that are used in the configuration and programming of the ispXPGA devices. There are two possible ports that can be used for configuration of the SRAM memory: the ISP port which supports the IEEE 1149.1 Test Access Port (TAP) Std., accommodates bit-wide configuration. The sysCONFIG port allows byte-wide configuration of the SRAM configuration memory. When programming the E2CMOS memory, only the 1149.1 TAP can be used. Configuration and programming done through the 1149.1 Test Access Port (TAP) supports both the IEEE Std. 1149.1 Boundary Scan TAP specification and the IEEE Std. 1532 In-System Configuration specification. To configure or program the device using the 1149.1 TAP the device must be in the ISP mode. To configure the SRAM memory using the sysCONFIG Port, the device must be in the sysCONFIG mode. Upon power-up, the device’s SRAM memory can be configured either from the E2CMOS memory or from an external source through the sysCONFIG mode. Additionally, the SRAM can be re-configured from the E2CMOS memory by executing a “REFRESH.” See Lattice technical note number TN1026, ispXP Configuration Usage Guide, for more in depth information on the different programming modes, timing and wake-up, available at www.latticesemi.com. Figure 21. ispXP Block Diagram sysCONFIG Peripheral Port ISP 1149.1 TAP Port Port ISP BACKGND 1532 sysCONFIG Mode Configuration in milliseconds Programming in seconds Power-up E2CMOS Memory Space Refresh SRAM Memory Space Download in microseconds Memory Space Supports IEEE 1149.1 Boundary Scan Testability All ispXPGA devices have boundary scan cells and supports the IEEE 1149.1 standard. This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic notes. Internal boundary scan registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be linked into a board-level serial scan path for more board level testing. Security Scheme A programmable security scheme is provided on the ispXPGA devices as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, the security scheme prevents read-back of the programmed 19 Lattice Semiconductor ispXPGA Family Data Sheet pattern by a device programmer, securing proprietary designs from competitors. The entire device must be erased in order to erase the security scheme. Density Shifting The ispXPGA family has been designed to ensure that different density devices in the same package have the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration from lower density parts to higher density parts. In many cases, it is possible to shift a lower utilization design targeted for a high-density device to a lower density device. However, the exact details of the final resource utilization will impact the likely success in each case. Temperature Sensing Diode The built-in temperature-sensing diodes allow junction temperature to be measured during device operation. A pair of pins (DXp and DXn) are dedicated for monitoring device junction temperature. The measurement is done by forcing 10 µA and 100 µA current in the forward direction, and then measuring the resulting voltage. The voltage decreases with increasing temperature at approximately 1.64 mV/°C. A typical device with a 85°C junction temperature will measure approximately 593 mV. The temperature-sensing diode works for the entire operating range as shown in Figure 22 - Sensing Diode Voltage-Temperature Relationship. Refer to Lattice’s Thermal Management document for thermal coefficients. Also refer to Lattice technical note number TN1043, Power Estimation in ispXPGA Devices. Figure 22. Sensing Diode Voltage-Temperature Relationship 0.85 0.80 100 uA 10 uA 0.75 Voltage 0.70 0.65 0.60 0.55 0.50 -50 -25 0 25 50 75 Junction Temperature (°C) 20 100 125 Lattice Semiconductor ispXPGA Family Data Sheet Absolute Maximum Ratings1, 2, 3 1.8V 2.5V/3.3V Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . .-0.5 to 5.5V PLL Supply Voltage (VCCP) . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . .-0.5 to 5.5V Output Supply Voltage (VCCO) . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V IEEE 1149.1 TAP Supply Voltage (VCCJ) . . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V Input Voltage Applied4, 5 . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V . . . . . . . . . .-0.5 to 5.5V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C. . . . . . . . . -65 to 150°C Junction Temperature (TJ) with Power Applied . . -55 to 150°C. . . . . . . . . -55 to 150°C 1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied (while programming, following the programming specifications). 2. Compliance with the Lattice Thermal Management document is required. 3. All voltages referenced to GND. 4. Overshoot and undershoot of -2V to (VIH (MAX) + 2) volts not to exceed 6V is permitted for a duration of <20ns. 5. A maximum of 64 I/Os per device with VIN > 3.6V is allowed. Recommended Operating Conditions Symbol VCC Min Max Units Supply Voltage for 1.8V device1 Parameter 1.65 1.95 V Supply Voltage for 2.5V device 2.3 2.7 V Supply Voltage for 3.3V device 3.0 3.6 V Supply Voltage for PLL and sysHSI blocks, 1.8V devices 1.65 1.95 V Supply Voltage for PLL and sysHSI blocks, 2.5V devices 2.3 2.7 V 1 VCCP VCCJ Supply Voltage for PLL and sysHSI blocks, 3.3V devices 3.0 3.6 V Supply Voltage for IEEE 1149.1 Test Access Port for LVCMOS 1.8V 1.65 1.95 V Supply Voltage for IEEE 1149.1 Test Access Port for LVCMOS 2.5V 2.3 2.7 V Supply Voltage for IEEE 1149.1 Test Access Port for LVCMOS 3.3V 3.0 3.6 V TJ (COM) Junction Temperature Commercial Operation TJ (IND) Junction Temperature Industrial Operation 0 85 C -40 105 C Min Max Units 1,000 — Cycles 1. sysHSI specification is valid for VCC and VCCP = 1.7V to 1.9V. E2CMOS Erase Reprogram Specifications Parameter Erase/Reprogram Cycle1 1. Valid over commercial temperature range. Hot Socketing Characteristics1, 2, 3, 4 Symbol IDK Parameter Condition Input or Tristated I/O Leakage Current 0 ≤ VIN ≤ 3.0V Min Typ Max Units — +/-50 +/-800 μA 1. Insensitive to sequence of VCC and VCCO when VCCO ≤ 1.0V. For VCCO > 1.0V, VCC min must be present. However, assumes monotonic rise/fall rates for VCC and VCCO, provided (VIN - VCCO) ≤ 3.6V. 2. LVTTL, LVCMOS only. 3. 0 < VCC ≤ VCC (MAX), 0 < VCCO ≤ VCCO (MAX). 4. IDK is additive to IPU, IPD or IBH. Device defaults to pull-up until non-volatile cells are active. 21 Lattice Semiconductor ispXPGA Family Data Sheet DC Electrical Characteristics Over Recommended Operating Conditions Symbol Parameter Min Typ Max Units 0 ≤ VIN < (VCCO - 0.2V) Condition — — 10 μA IIL, IIH1 Input or I/O Low Leakage (VCCO - 0.2V) ≤ VIN ≤ 3.6V — — 300 μA IIH2 Input High Leakage Current 3.6V < VIN ≤ 5.5V and 3.0V ≤ VCCO ≤ 3.6V — — 3 mA IPU I/O Active Pull-up Current 0 ≤ VIN ≤ 0.7 VCCO -30 — -150 μA IPD I/O Active Pull-down Current VIL (MAX) ≤ VIN ≤ VIH (MAX) 30 — 150 μA IBHLS Bus Hold Low Sustaining Current VIN = VIL (MAX) 30 — — μA IBHHS Bus Hold High Sustaining Current VIN = 0.7 VCCO -30 — — μA IBHLO Bus Hold Low Overdrive Current — — 150 μA IBHHO Bus Hold High Overdrive Current 0 ≤ VIN ≤ VIH (MAX) VBHT Bus Hold Trip Points C1 I/O Capacitance3 C2 Clock Capacitance3 C3 Global Input Capacitance3 0 ≤ VIN ≤ VIH (MAX) — — -150 μA VCCO * 0.35 — VCCO * 0.65 V VCCO = 3.3V, 2.5V, 1.8V — VCC = 1.8V, VIO = 0 to VIH (MAX) — VCCO = 3.3V, 2.5V, 1.8V — VCC = 1.8V, VIO = 0 to VIH (MAX) — VCCO = 3.3V, 2.5V, 1.8V — VCC = 1.8V, VIO = 0 to VIH (MAX) — 8 8 6 — — — — — — pf pf pf 1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Bus maintenance circuits are disabled. 2. 5V tolerant inputs and I/Os should be placed in banks where 3.0V ≤ VCCO ≤ 3.6V. The JTAG and sysCONFIG ports are not included for the 5V tolerant interface. 3. TA = 25°C, f = 1.0MHz. 22 Lattice Semiconductor ispXPGA Family Data Sheet Supply Current Over Recommended Operating Conditions Symbol Parameter Device LFX125 LFX200 ICC1, 2 Standby Core Operating Power Supply Current LFX500 LFX1200 ICCO3 ICCP4 ICCJ5 Standby Output Power Supply Current Standby PLL Operating Supply Current Standby IEEE 1149.1 TAP Power Supply Current Condition Min. Typ. Max. Units VCC = 3.3V — 60 — mA VCC = 2.5V — 60 — mA VCC = 1.8V — 40 — mA VCC = 3.3V — 70 — mA VCC = 2.5V — 70 — mA VCC = 1.8V — 50 — mA VCC = 3.3V — 120 — mA VCC = 2.5V — 120 — mA VCC = 1.8V — 100 — mA VCC = 3.3V — 220 — mA VCC = 2.5V — 220 — mA VCC = 1.8V — 200 — mA VCCO = 3.3V — 2.0 — mA VCCO = 2.5V — 2.0 — mA VCCO = 1.8V — 2.0 — mA VCCO = 1.5V — 2.0 — mA VCCP = 3.3V — 17.0 — mA VCCP = 2.5V — 17.0 — mA VCCP = 1.8V — 15.0 — mA VCCJ = 3.3V — 2.0 — mA VCCJ = 2.5V — 1.5 — mA VCCJ = 1.8V — 1.0 — mA 1. TA = 25˚C, frequency = 1.0 MHz, device configured with 16-bit counters. 2. ICC varies with specific device configuration and operating frequency. For more accurate power calculation, see Lattice technical note number TN1043, Power Estimation in ispXPGA Devices. 3. TA = 25˚C, per bank, no DC load, frequency = 0 MHz. 4. TA = 25˚C, per PLL, frequency = 10 MHz. 5. TA = 25˚C 23 Lattice Semiconductor ispXPGA Family Data Sheet sysIO Recommended Operating Conditions VCCO (V)1 Standard VREF (V) Min. Typ. Max. Min. Typ. Max. LVCMOS 3.3 3.0 3.3 3.6 - - - LVCMOS 2.5 2.3 2.5 2.7 - - - LVCMOS 1.8 1.65 1.8 1.95 - - - LVTTL 3.0 3.3 3.6 - - - 2 PCI 3.3 3.0 3.3 3.6 - - - AGP-1X 3.15 3.3 3.45 - - - SSTL 2 2.3 2.5 2.7 1.15 1.25 1.35 SSTL 3 3.0 3.3 3.6 1.3 1.5 1.7 CTT 3.3 3.0 3.3 3.6 1.35 1.5 1.65 CTT 2.5 2.3 2.5 2.7 1.35 1.5 1.65 HSTL Class I 1.4 1.5 1.6 0.68 0.75 0.9 HSTL Class III 1.4 1.5 1.6 - 0.9 - GTL+ - - - 0.882 1.0 1.122 LVDS 2.3 2.5 2.7 - - - LVPECL 3.0 3.3 3.6 - - - BLVDS 2.3 2.5 2.7 - - - 1. Inputs independent of VCCO. 2. Design tool default setting. 24 Lattice Semiconductor ispXPGA Family Data Sheet sysIO DC Electrical Characteristics Over Recommended Operating Conditions VIL Standard LVCMOS 3.3 LVCMOS 2.5 LVCMOS 1.81 Min. (V) -0.3 -0.3 -0.3 LVTTL -0.3 PCI 3.3 -0.3 AGP-1X -0.3 SSTL 3 Class I SSTL 3 Class II VIH Max. (V) 0.8 Min. (V) 2.0 0.7 1.7 0.683 1.073 0.35VCC 0.65VCC Max. (V) 5.5 3.6 3.6 VOL Max. (V) VOH Min. (V) IOL (mA) IOH (mA) 20, 16, 12, -20, -16,-12, 8, 5.33, 4 -8, -5.33, -4 0.4 VCCO - 0.4 0.2 VCCO - 0.2 0.1 -0.1 0.4 VCCO - 0.4 16, 12, 8, 5.33, 4 -16, -12, -8, -5.33, -4 0.2 VCCO - 0.2 0.1 -0.1 0.4 VCCO - 0.4 12, 81, 5.33, 4 -12, -81, -5.33, -4 0.1 -0.1 0.2 VCCO - 0.2 0.4 VCCO - 0.4 4 -4 0.2 VCCO - 0.2 0.1 -0.1 5.5 0.1 VCCO 0.9 VCCO 1.5 -0.5 3.6 0.1 VCCO 0.9 VCCO 1.5 -0.5 0.8 2.0 5.5 1.083 1.53 0.3VCCO 0.5 VCCO 1.083 1.53 0.3 VCCO 0.5 VCCO -0.3 VREF - 0.2 VREF + 0.2 3.6 0.7 VCCO - 1.1 8 -8 -0.3 VREF - 0.2 VREF + 0.2 3.6 0.5 VCCO - 0.9 16 -16 SSTL 2 Class I -0.3 VREF - 0.18 VREF + 0.18 3.6 0.54 VCCO - 0.62 7.6 -7.6 SSTL 2 Class II -0.3 VREF - 0.18 VREF + 0.18 3.6 0.35 VCCO - 0.43 15.2 -15.2 CTT 3.3 -0.3 VREF - 0.2 VREF + 0.2 3.6 VREF - 0.4 VREF + 0.4 8 -8 CTT 2.5 -0.3 VREF - 0.2 VREF + 0.2 3.6 VREF - 0.4 VREF + 0.4 8 -8 HSTL Class I -0.3 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCO - 0.4 8 -8 HSTL Class III -0.3 VREF - 0.1 VREF + 0.1 3.6 0.4 VCCO - 0.4 24 -8 GTL+ -0.3 VREF - 0.2 VREF + 0.2 3.6 0.6 N/A 36 N/A 1. Design tool default setting. 2. The average DC current drawn by I/Os between adjacent bank GND connections, or between the last GND in an I/O bank and the end of the I/O bank, as shown in the logic signals connection table, shall not exceed n*8mA. Where n is the number of I/Os between bank GND connections or between the last GND in a bank and the end of a bank 3. Applicable for ispXPGA B devices. 25 Lattice Semiconductor ispXPGA Family Data Sheet sysIO Differential Standards DC Electrical Characteristics1 Parameter Description Test Conditions Min. Typ. Max. 0V — 2.4V +/-100mV — — — — +/-10uA 2 LVDS VINP, VINM Input voltage VTHD Differential input threshold 0.2V ≤ VCM ≤ 1.8V IIN Input current Power on VOH Output High Voltage for VOP or VOM RT = 100 Ohm — 1.38V 1.60V VOL Output Low Voltage for VOP or VOM RT = 100 Ohm 0.9V 1.03V — VOD Output Voltage Differential |VOP - VOM|, RT = 100 ohm 250mV 350mV 450mV ΔVOD Change in VOD between high and low — — 50mV 1.125V 1.25V 1.375V — — 50mV — — 24mA 0V — 2.4V +/-100mV — — — — +/-10uA VOS Output Voltage Offset ΔVOS Change in VOS between H and L IOSD Output short circuit current |VOP + VOM|/2, RT = 100 ohm VOD = 0V Driver outputs shorted BLVDS1 VINP, VINM Input voltage VTHD Differential input threshold 0.2V ≤ VCM ≤ 1.8V IIN Input current Power on VOH Output High Voltage for VOP or VOM RT = 27Ω — 1.4V 1.80V VOL Output Low Voltage for VOP or VOM RT = 27Ω 0.95V 1.1V — |VOP - VOM|, RT = 27Ω 240mV 300mV 460mV VOD Output Voltage Differential ΔVOD Change in VOD Between H and L VOS Output Voltage Offset ΔVOS Change in VOS Between H and L IOSD Output Short Circuit Current 27mV |VOP + VOM| /2, RT = 27Ω 1.1V 1.3V 1.5V 27mV VOD = 0. Driver Outputs Shorted. 36mA 65mA 1. Refer to Lattice technical note TN1000, sysIO Usage Guidelines for Lattice Devices. 2. VOP and VOM are the two outputs of the LVDS/BLVDS output buffer. LVPECL1 DC Parameter Parameter Description Min. Max. Min. 3.0 VCCO Max. Min. 3.3 Max. 3.6 Units V VIH Input Voltage High 1.49 2.72 1.49 2.72 1.49 2.72 V VIL Input Voltage Low 0.86 2.125 0.86 2.125 0.86 2.125 V VOH Output Voltage High 1.8 2.11 1.92 2.28 2.13 2.41 V VOL Output Voltage Low 0.96 1.27 1.06 1.43 1.3 1.57 V VDIFF2 Differential Input threshold 0.3 — 0.3 — 0.3 — V 1. These values are valid at the output of the source termination pack as shown above with 100-ohm differential load only (see Figure 23). The VOH levels are 200mV below the standard LVPECL levels and are compatible with devices tolerant of the lower common mode ranges. 2. Valid for 0.2 ≤ VCM ≤ 1.8V. 26 Lattice Semiconductor ispXPGA Family Data Sheet Figure 23. LVPECL Driver with Three Resistor Pack ispXPLD Emulated LVPECL Buffer 1/4 of Bourns P/N CAT 16-PC4F12 A Zo to LVPECL differential receiver RD RT=100 Rs Rs Zo ispXPGA 125B/C & ispXPGA 125EB/EC External Switching Characteristics Over Recommended Operating Conditions -51 Parameter Description Conditions PIO Output Register -4 -3 Min. Max. Min. Max. Min. Max. Units — 5.3 — 5.7 — 6.6 ns tCO Global Clock Input to Output tS Global Clock Input Setup PIO Input Register without input delay -1.9 — -1.8 — -1.5 — ns tH Global Clock Input Hold PIO Input Register without input delay 2.7 — 2.9 — 3.3 — ns tSINDLY Global Clock Input Setup PIO Input Register with input delay 3.1 — 3.3 — 3.8 — ns tHINDLY Global Clock Input Hold PIO Input Register with input delay 0.0 — 0.0 — 0.0 — tCOPLL Global Clock Input to Output PIO Output Register using PLL without delay — 3.6 — 3.9 — 4.5 ns tSPLL Global Clock Input Setup PIO Input Register without input delay using PLL without delay 0 — 0.1 — 0.3 — ns tHPLL Global Clock Input Hold PIO Input Register without input delay using PLL without delay 0.9 — 1.0 — 1.2 — ns tSINDLYPLL Global Clock Input Setup PIO Input Register with input delay using PLL without delay 5.1 — 5.5 — 6.3 — ns tHINDLYPLL Global Clock Input Hold PIO Input Register with input delay using PLL without delay -3.0 — -2.8 — -2.4 — ns 1. Only available for ispXPGA 125B and ispXPGA 125EB (2.5V/3.3V) devices. 27 Timing v.0.3 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA 125B/C & ispXPGA 125EB/EC PFU Timing Parameters Over Recommended Operating Conditions -51 Parameter Description -4 -3 Min. Max. Min. Max. Min. Max. Units Functional Delays LUTs tLUT4 4-Input LUT Delay — 0.41 — 0.44 — 0.51 ns tLUT5 5-Input LUT Delay — 0.73 — 0.79 — 0.91 ns tLUT6 6-Input LUT Delay — 0.86 — 0.93 — 1.07 ns — -0.62 — -0.53 — ns Shift Register (LUT) tLSR_S Shift Register Setup Time -0.64 tLSR_H Shift Register Hold Time 0.61 — 0.63 — 0.72 — ns tLSR_CO Shift Register Clock to Output Delay — 0.70 — 0.75 — 0.86 ns — 0.08 — 0.09 — 0.10 ns Arithmetic Functions tLCTHRUR 2 MC (Macro Cell) Carry In to MC Carry Out Delay (Ripple) MC Carry In to MC Carry Out Delay (Look Ahead) — 0.05 — 0.05 — 0.06 ns tLSTHRU MC Sum In to MC Sum Out Delay — 0.42 — 0.45 — 0.52 ns tLSINCOUT MC Sum In to MC Carry Out Delay — 0.29 — 0.31 — 0.36 ns tLCINSOUTR MC Carry In to MC Sum Out Delay (Ripple) — 0.36 — 0.39 — 0.45 ns tLCINSOUTL MC Carry In to MC Sum Out Delay (Look Ahead) — 0.26 — 0.28 — 0.32 ns PFU Feed-Thru Delay — 0.15 — 0.16 — 0.18 ns tLCTHRUL Feed-thru tLFT Distributed RAM tLRAM_CO Clock to RAM Output — 1.24 — 1.33 — 1.53 ns tLRAMAD_S Address Setup Time -0.41 — -0.40 — -0.34 — ns tLRAMD_S Data Setup Time 0.21 — 0.22 — 0.25 — ns tLRAMWE_S Write Enable Setup Time 0.45 — 0.46 — 0.53 — ns tLRAMAD_H Address Hold Time 0.58 — 0.60 — 0.69 — ns tLRAMD_H Data Hold Time 0.11 — 0.11 — 0.13 — ns tLRAMWE_H Write Enable Hold Time 0.12 — 0.12 — 0.14 — ns tLRAMCPW Clock Pulse Width (High or Low) 2.91 — 3.00 — 3.45 — ns tLRAMADO Address to Output Delay — 0.86 — 0.93 — 1.07 ns — 0.58 — 0.62 — 0.71 ns Register/Latch Delays Registers tL_CO Register Clock to Output Delay tL_S Register Setup Time (Data before Clock) 0.14 — 0.14 — 0.16 — ns tL_H Register Hold Time (Data after Clock) -0.12 — -0.12 — -0.10 — ns tLCE_S Register Clock Enable Setup Time -0.11 — -0.11 — -0.09 — ns tLCE_H Register Clock Enable Hold Time 0.11 — 0.11 — 0.13 — ns — 0.09 — 0.10 — 0.12 ns Latches tL_GO Latch Gate to Output Delay tLL_S Latch Setup Time 0.14 — 0.14 — 0.16 — ns tLL_H Latch Hold Time -0.12 — -0.12 — -0.10 — ns tLLPD Latch Propagation Delay (Transparent Mode) — 0.09 — 0.10 — 0.12 ns 28 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA 125B/C & ispXPGA 125EB/EC PFU Timing Parameters (Cont.) Over Recommended Operating Conditions -51 Parameter Description -4 -3 Min. Max. Min. Max. Min. Max. Units — 1.09 — 1.17 — 1.35 ns Reset/Set tLASSRO Asynchronous Set/Reset to Output tLASSRPW Asynchronous Set/Reset Pulse Width 4.19 — 4.50 — 5.18 — ns tLASSRR Asynchronous Set/Reset Recovery — 0.51 — 0.55 — 0.63 ns tLSSR_S Synchronous Set/Reset Setup Time -0.03 — -0.03 — -0.03 — ns tLSSR_H Synchronous Set/Reset Hold Time 0.03 — 0.03 — 0.03 — ns 1. Only available for ispXPGA 125B and ispXPGA 125EB (2.5V/3.3V) devices. 2. tLCTHRUL quoted bit by bit. Timing v.0.3 ispXPGA 125B/C & ispXPGA 125EB/EC PIC Timing Parameters -51 Parameter Description -4 -3 Min. Max. Min. Max. Min. Max. Units — 0.89 — 0.96 — 1.10 ns Register/Latch Delays tIO_CO Register Clock to Output Delay tIO_S Register Setup Time (Data before Clock) 0.05 — 0.05 — 0.06 — ns tIO_H Register Hold Time (Data after Clock) 0.06 — 0.06 — 0.07 — ns tIOCE_S Register Clock Enable Setup Time -0.03 — -0.03 — -0.03 — ns tIOCE_H Register Clock Enable Hold Time 0.13 0.13 — 0.15 — ns tIO_GO Latch Gate to Output Delay — 0.68 — 0.73 — 0.84 ns tIOL_S Latch Setup Time 0.05 — 0.05 — 0.06 — ns tIOL_H Latch Hold Time 0.06 — 0.06 — 0.07 — ns tIOLPD Latch Propagation Delay (Transparent Mode) — 0.09 — 0.10 — 0.12 ns tIOASRO Asynchronous Set/Reset to Output tIOASRPW Asynchronous Set/Reset Pulse Width tIOASRR Asynchronous Set/Reset Recovery Time — 1.00 — 1.08 — 1.24 ns 4.19 — 4.50 — 5.18 — ns — 0.23 — 0.25 — 0.29 ns Input/Output Delays tIOBUF Output Buffer Delay — 0.97 — 1.04 — 1.20 ns tIOIN Input Buffer Delay — 0.57 — 0.61 — 0.70 ns tIOEN Output Enable Delay — 0.53 — 0.57 — 0.66 ns tIODIS Output Disable Delay — -0.14 — -0.13 — -0.11 ns tIOFT Feed-thru Delay — 0.19 — 0.20 — 0.23 ns 1. Only available for ispXPGA 125B and ispXPGA 125EB (2.5V/3.3V) devices. 29 Timing v.0.3 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA 125B/C & ispXPGA 125EB/EC EBR Timing Parameters -51 Parameter Description -4 Min. Max. -3 Min. Max. Min. Max. Units Synchronous Write tEBSWAD_S Address Setup Delay 0.59 — 0.61 — 0.70 — ns tEBSWAD_H Address Hold Delay -0.40 — -0.39 — -0.33 — ns tEBSWCPW Clock Pulse Width 3.16 — 3.40 — 3.91 — ns tEBSWWE_S Write Enable Setup Time -0.12 — -0.12 — -0.10 — ns tEBSWWE_H Write Enable Hold Time 0.16 — 0.16 — 0.18 — ns tEBSWD_S Data Setup Time 0.27 — 0.28 — 0.32 — ns tEBSWD_H Data Hold Time -0.27 — -0.26 — -0.22 — ns Synchronous Read tEBSR_CO Clock to Data Delay — 2.04 — 2.19 — 2.52 ns tEBSRAD_S Address Setup Delay 0.10 — 0.10 — 0.12 — ns tEBSRAD_H Address Hold Delay -0.07 — -0.07 — -0.06 — ns tEBSRCPW Clock Pulse Width 3.16 — 3.40 — 3.91 — ns tEBSRCE_S Clock Enable Setup Time -1.76 — -1.71 — -1.45 — ns tEBSRCE_H Clock Enable Hold Time 1.64 — 1.69 — 1.94 — ns tEBSRWE_S Write Enable Setup Time -0.18 — -0.17 — -0.14 — ns tEBSRWE_H Write Enable Hold Time 0.12 — 0.12 — 0.14 — ns tEBSRWEEN Write Enable to Data Enable Time — 1.02 — 1.05 — 1.21 ns tEBSRWEDIS Write Enable to Data Disable Time — 0.99 — 1.02 — 1.17 ns tEBSREN Output Enable to Data Enable Time — 1.02 — 1.05 — 1.21 ns tEBSRDIS Output Enable to Data Disable Time — 0.83 — 0.86 — 0.99 ns Asynchronous Read tEBARADO Address to New Valid Data Delay — 2.39 — 2.46 — 2.83 ns tEBARAD_H Address to Previous Valid Data Delay — 2.10 — 2.17 — 2.50 ns tEBARWEEN Write Enable to Data Enable Time — 1.01 — 1.04 — 1.20 ns tEBARWEDIS Write Enable to Data Disable Time — 0.98 — 1.01 — 1.16 ns tEBAREN Output Enable to Data Enable Time — 1.02 — 1.05 — 1.21 ns tEBARDIS Output Enable to Data Disable Time — 0.83 — 0.86 — 0.99 ns 1. Only available for ispXPGA 125B and ispXPGA 125EB (2.5V/3.3V) devices. 30 Timing v.0.3 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA 125B/C & ispXPGA 125EB/EC Timing Adders Parameter Description Base Parameter -51 -4 -3 Min. Max. Min. Max. Min. Max. Units Optional Adders Input Delay — — 4.28 — 4.6 — 5.29 ns LVTTL_in Using 3.3V TTL tIOIN — 0.5 — 0.5 — 0.5 ns LVCMOS_18_in Using 1.8V CMOS tIOIN — 0.0 — 0.0 — 0.0 ns LVCMOS_25_in Using 2.5V CMOS tIOIN — 0.3 — 0.3 — 0.3 ns tIOINDLY tIOI Input Adjusters LVCMOS_33_in Using 3.3V CMOS tIOIN — 0.5 — 0.5 — 0.5 ns AGP_1X_in Using AGP 1x tIOIN — 1.0 — 1.0 — 1.0 ns CTT25_in Using CTT 2.5V tIOIN — 1.0 — 1.0 — 1.0 ns CTT33_in Using CTT 3.3V tIOIN — 1.0 — 1.0 — 1.0 ns GTL+_in Using GTL+ tIOIN — 0.5 — 0.5 — 0.5 ns HSTL_I_in Using HSTL 2.5V, Class I tIOIN — 0.5 — 0.5 — 0.5 ns HSTL_III_in Using HSTL 2.5V, Class III tIOIN — 0.5 — 0.5 — 0.5 ns LVDS_in Using Low Voltage Differential Signaling (LVDS) tIOIN — 0.8 — 0.8 — 0.8 ns BLVDS_in Using Bus Low Voltage tIOIN Differential Signaling (BLVDS) — 0.8 — 0.8 — 0.8 ns LVPECL_in Using Low Voltage PECL tIOIN — 0.8 — 0.8 — 0.8 ns PCI_in Using PCI tIOIN — 1.0 — 1.0 — 1.0 ns SSTL2_I_in Using SSTL 2.5V, Class I tIOIN — 0.8 — 0.8 — 0.8 ns SSTL2_II_in Using SSTL 2.5V, Class II tIOIN — 0.5 — 0.5 — 0.5 ns SSTL3_I_in Using SSTL 3.3V, Class I tIOIN — 0.8 — 0.8 — 0.8 ns SSTL3_II_in Using SSTL 3.3V, Class II tIOIN — 0.8 — 0.8 — 0.8 ns tIOO Output Adjusters Slow Slew Using Slow Slew (LVTTL and tIOBUF, tIOEN LVCMOS Outputs only) — 0.7 — 0.7 — 0.7 ns LVTTL_out Using 3.3V TTL Drive tIOBUF, tIOEN, tIODIS — 1.0 — 1.0 — 1.0 ns LVCMOS_18_4mA_out Using 1.8V CMOS Standard, 4mA Drive tIOBUF, tIOEN, tIODIS — 0.8 — 0.8 — 0.8 ns LVCMOS_18_5.33mA_out Using 1.8V CMOS Standard, 5.33mA Drive tIOBUF, tIOEN, tIODIS — 0.6 — 0.6 — 0.6 ns LVCMOS_18_8mA_out Using 1.8V CMOS Standard, 8mA Drive tIOBUF, tIOEN, tIODIS — 0.0 — 0.0 — 0.0 ns LVCMOS_18_12mA_out Using 1.8V CMOS Standard, 12mA Drive tIOBUF, tIOEN, tIODIS — 0.2 — 0.2 — 0.2 ns LVCMOS_25_4mA_out Using 2.5V CMOS Standard, 4mA Drive tIOBUF, tIOEN, tIODIS — 0.7 — 0.7 — 0.7 ns LVCMOS_25_5.33mA_out Using 2.5V CMOS Standard, 5.33 mA Drive tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns LVCMOS_25_8mA_out Using 2.5V CMOS Standard, 8mA Drive tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns LVCMOS_25_12mA_out Using 2.5V CMOS Standard, 12mA Drive tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns LVCMOS_25_16mA_out Using 2.5V CMOS Standard, 16mA Drive tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns 31 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA 125B/C & ispXPGA 125EB/EC Timing Adders (Cont.) Parameter Description Base Parameter Using 3.3V CMOS Standard, 4mA Drive -51 -4 -3 Min. Max. Min. Max. Min. tIOBUF, tIOEN, tIODIS — 1.0 — 1.0 — 1.0 ns LVCMOS_33_5.33mA_out Using 3.3V CMOS Standard, 5.33mA Drive tIOBUF, tIOEN, tIODIS — 1.0 — 1.0 — 1.0 ns LVCMOS_33_8mA_out Using 3.3V CMOS Standard, 8mA Drive tIOBUF, tIOEN, tIODIS — 0.7 — 0.7 — 0.7 ns LVCMOS_33_12mA_out Using 3.3V CMOS Standard, 12mA Drive tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns LVCMOS_33_16mA_out Using 3.3V CMOS Standard, 16mA Drive tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns LVCMOS_33_24mA_out Using 3.3V CMOS Standard, 24mA Drive tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns AGP_1X_out Using AGP 1x Standard tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns CTT25_out Using CTT 2.5V tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns CTT33_out Using CTT 3.3V tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns GTL+_out Using GTL+ tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns HSTL_I_out Using HSTL 2.5V, Class I tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns HSTL_III_out Using HSTL 2.5V, Class III tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns LVDS_out Using Low Voltage Differential Signaling (LVDS) tIOBUF, tIOEN, tIODIS — 1.0 — 1.0 — 1.0 ns BLVDS_out Using Bus Low Voltage Differ- tIOBUF, tIOEN, tIODIS ential Signaling (BLVDS) — 1.0 — 1.0 — 1.0 ns LVPECL_out Using Low Voltage PECL tIOBUF, tIOEN, tIODIS — 1.0 — 1.0 — 1.0 ns PCI_out Using PCI Standard tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns SSTL2_I_out Using SSTL 2.5V, Class I tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns SSTL2_II_out Using SSTL 2.5V, Class II tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns SSTL3_I_out Using SSTL 3.3V, Class I tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns SSTL3_II_out Using SSTL 3.3V, Class II tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns LVCMOS_33_4mA_out 1. Only available for ispXPGA 125B and ispXPGA 125EB (2.5V/3.3V) devices. 32 Max. Units Timing v.0.3 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA 200B/C & ispXPGA 200EB/EC External Switching Characteristics Over Recommended Operating Conditions -51 Parameter Description Conditions -4 -3 Min. Max. Min. Max. Min. Max. Units — 5.5 — 5.9 — 6.8 ns tCO Global Clock Input to Out- PIO Output Register put tS Global Clock Input Setup PIO Input Register without input delay -2.0 — -2.0 — -1.7 — ns tH Global Clock Input Hold PIO Input Register without input delay 3.7 — 3.8 — 4.4 — ns ns tSINDLY Global Clock Input Setup PIO Input Register with input delay 3.8 — 3.8 — 4.4 — tHINDLY Global Clock Input Hold PIO Input Register with input delay 0.0 — 0.0 — 0.0 — tCOPLL Global Clock Input to Output PIO Output Register using PLL without delay — 3.3 — 3.6 — 4.2 ns tSPLL Global Clock Input Setup PIO Input Register without input delay using PLL without delay -0.2 — -0.2 — 0.1 — ns tHPLL Global Clock Input Hold PIO Input Register without input delay using PLL without delay 1.5 — 1.5 — 1.8 — ns tSINDLYPLL Global Clock Input Setup PIO Input Register with input delay using PLL without delay 6.3 — 6.3 — 7.3 — ns tHINDLYPLL Global Clock Input Hold PIO Input Register with input delay using PLL without delay -2.7 — -2.6 — -2.2 — ns 1. Only available for ispXPGA 200B and ispXPGA 200EB (2.5V/3.3V) devices. 33 Timing v.0.2 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA 200B/C & ispXPGA 200EB/EC PFU Timing Parameters Over Recommended Operating Conditions -51 Parameter Description -4 -3 Min. Max. Min. Max. Min. Max. Units Functional Delays LUTs tLUT4 4-Input LUT Delay — 0.41 — 0.44 — 0.51 ns tLUT5 5-Input LUT Delay — 0.73 — 0.79 — 0.91 ns tLUT6 6-Input LUT Delay — 0.86 — 0.93 — 1.07 ns — -0.62 — -0.53 — ns Shift Register (LUT) tLSR_S Shift Register Setup Time -0.64 tLSR_H Shift Register Hold Time 0.61 — 0.63 — 0.72 — ns tLSR_CO Shift Register Clock to Output Delay — 0.70 — 0.75 — 0.86 ns — 0.08 — 0.09 — 0.10 ns Arithmetic Functions tLCTHRUR 2 MC (Macro Cell) Carry In to MC Carry Out Delay (Ripple) MC Carry In to MC Carry Out Delay (Look Ahead) — 0.05 — 0.05 — 0.06 ns tLSTHRU MC Sum In to MC Sum Out Delay — 0.42 — 0.45 — 0.52 ns tLSINCOUT MC Sum In to MC Carry Out Delay — 0.29 — 0.31 — 0.36 ns tLCINSOUTR MC Carry In to MC Sum Out Delay (Ripple) — 0.36 — 0.39 — 0.45 ns tLCINSOUTL MC Carry In to MC Sum Out Delay (Look Ahead) — 0.26 — 0.28 — 0.32 ns PFU Feed-Thru Delay — 0.15 — 0.16 — 0.18 ns tLCTHRUL Feed-thru tLFT Distributed RAM tLRAM_CO Clock to RAM Output — 1.24 — 1.33 — 1.53 ns tLRAMAD_S Address Setup Time -0.41 — -0.40 — -0.34 — ns tLRAMD_S Data Setup Time 0.21 — 0.22 — 0.25 — ns tLRAMWE_S Write Enable Setup Time 0.45 — 0.46 — 0.53 — ns tLRAMAD_H Address Hold Time 0.58 — 0.60 — 0.69 — ns tLRAMD_H Data Hold Time 0.11 — 0.11 — 0.13 — ns tLRAMWE_H Write Enable Hold Time 0.12 — 0.12 — 0.14 — ns tLRAMCPW Clock Pulse Width (High or Low) 2.91 — 3.00 — 3.45 — ns tLRAMADO Address to Output Delay — 0.86 — 0.93 — 1.07 ns — 0.58 — 0.62 — 0.71 ns Register/Latch Delays Registers tL_CO Register Clock to Output Delay tL_S Register Setup Time (Data before Clock) 0.14 — 0.14 — 0.16 — ns tL_H Register Hold Time (Data after Clock) -0.12 — -0.12 — -0.10 — ns tLCE_S Register Clock Enable Setup Time -0.11 — -0.11 — -0.09 — ns tLCE_H Register Clock Enable Hold Time 0.11 — 0.11 — 0.13 — ns — 0.09 — 0.10 — 0.12 ns Latches tL_GO Latch Gate to Output Delay tLL_S Latch Setup Time 0.14 — 0.14 — 0.16 — ns tLL_H Latch Hold Time -0.12 — -0.12 — -0.10 — ns tLLPD Latch Propagation Delay (Transparent Mode) — 0.09 — 0.10 — 0.12 ns 34 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA 200B/C & ispXPGA 200EB/EC PFU Timing Parameters (Cont.) Over Recommended Operating Conditions -51 Parameter Description -4 -3 Min. Max. Min. Max. Min. Max. Units — 1.09 — 1.17 — 1.35 ns Reset/Set tLASSRO Asynchronous Set/Reset to Output tLASSRPW Asynchronous Set/Reset Pulse Width 4.19 — 4.50 — 5.18 — ns tLASSRR Asynchronous Set/Reset Recovery — 0.51 — 0.55 — 0.63 ns tLSSR_S Synchronous Set/Reset Setup Time -0.03 — -0.03 — -0.03 — ns tLSSR_H Synchronous Set/Reset Hold Time 0.03 — 0.03 — 0.03 — ns 1. Only available for ispXPGA 200B and ispXPGA 200EB (2.5V/3.3V) devices. 2. tLCTHRUL quoted bit by bit. Timing v.0.3 ispXPGA 200B/C & ispXPGA 200EB/EC PIC Timing Parameters -51 Parameter Description -4 -3 Min. Max. Min. Max. Min. Max. Units — 0.93 — 1.00 — 1.15 ns Register/Latch Delays tIO_CO Register Clock to Output Delay tIO_S Register Setup Time (Data before Clock) 0.05 — 0.05 — 0.06 — ns tIO_H Register Hold Time (Data after Clock) 0.06 — 0.06 — 0.07 — ns tIOCE_S Register Clock Enable Setup Time -0.03 — -0.03 — -0.03 — ns tIOCE_H Register Clock Enable Hold Time 0.13 0.13 — 0.15 — ns tIO_GO Latch Gate to Output Delay — 0.72 — 0.77 — 0.89 ns tIOL_S Latch Setup Time 0.05 — 0.05 — 0.06 — ns tIOL_H Latch Hold Time 0.06 — 0.06 — 0.07 — ns tIOLPD Latch Propagation Delay (Transparent Mode) — 0.09 — 0.10 — 0.12 ns tIOASRO Asynchronous Set/Reset to Output tIOASRPW Asynchronous Set/Reset Pulse Width tIOASRR Asynchronous Set/Reset Recovery Time — 1.04 — 1.12 — 1.29 ns 4.19 — 4.50 — 5.18 — ns — 0.23 — 0.25 — 0.29 ns Input/Output Delays tIOBUF Output Buffer Delay — 0.97 — 1.04 — 1.20 ns tIOIN Input Buffer Delay — 0.60 — 0.64 — 0.74 ns tIOEN Output Enable Delay — 0.53 — 0.57 — 0.66 ns tIODIS Output Disable Delay — -0.13 — -0.12 — -0.10 ns tIOFT Feed-thru Delay — 0.19 — 0.20 — 0.23 ns 1. Only available for ispXPGA 200B and ispXPGA 200EB (2.5V/3.3V) devices. 35 Timing v.0.3 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA 200B/C & ispXPGA 200EB/EC EBR Timing Parameters -51 Parameter Description -4 Min. Max. -3 Min. Max. Min. Max. Units Synchronous Write tEBSWAD_S Address Setup Delay 0.59 — 0.61 — 0.70 — ns tEBSWAD_H Address Hold Delay -0.40 — -0.39 — -0.33 — ns tEBSWCPW Clock Pulse Width 3.16 — 3.40 — 3.91 — ns tEBSWWE_S Write Enable Setup Time -0.12 — -0.12 — -0.10 — ns tEBSWWE_H Write Enable Hold Time 0.16 — 0.16 — 0.18 — ns tEBSWD_S Data Setup Time 0.27 — 0.28 — 0.32 — ns tEBSWD_H Data Hold Time -0.27 — -0.26 — -0.22 — ns Synchronous Read tEBSR_CO Clock to Data Delay — 2.04 — 2.19 — 2.52 ns tEBSRAD_S Address Setup Delay 0.10 — 0.10 — 0.12 — ns tEBSRAD_H Address Hold Delay -0.07 — -0.07 — -0.06 — ns tEBSRCPW Clock Pulse Width 3.16 — 3.40 — 3.91 — ns tEBSRCE_S Clock Enable Setup Time -1.76 — -1.71 — -1.45 — ns tEBSRCE_H Clock Enable Hold Time 1.64 — 1.69 — 1.94 — ns tEBSRWE_S Write Enable Setup Time -0.18 — -0.17 — -0.14 — ns tEBSRWE_H Write Enable Hold Time 0.12 — 0.12 — 0.14 — ns tEBSRWEEN Write Enable to Data Enable Time — 1.02 — 1.05 — 1.21 ns tEBSRWEDIS Write Enable to Data Disable Time — 0.99 — 1.02 — 1.17 ns tEBSREN Output Enable to Data Enable Time — 1.02 — 1.05 — 1.21 ns tEBSRDIS Output Enable to Data Disable Time — 0.83 — 0.86 — 0.99 ns Asynchronous Read tEBARADO Address to New Valid Data Delay — 2.39 — 2.46 — 2.83 ns tEBARAD_H Address to Previous Valid Data Delay — 2.10 — 2.17 — 2.50 ns tEBARWEEN Write Enable to Data Enable Time — 1.01 — 1.04 — 1.20 ns tEBARWEDIS Write Enable to Data Disable Time — 0.98 — 1.01 — 1.16 ns tEBAREN Output Enable to Data Enable Time — 1.02 — 1.05 — 1.21 ns tEBARDIS Output Enable to Data Disable Time — 0.83 — 0.86 — 0.99 ns 1. Only available for ispXPGA 200B and ispXPGA 200EB (2.5V/3.3V) devices. 36 Timing v.0.3 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA 200B/C & ispXPGA 200EB/EC Timing Adders Parameter Description Base Parameter -51 -4 -3 Min. Max. Min. Max. Min. Max. Units Optional Adders Input Delay — — 4.84 — 5.2 — 5.98 ns LVTTL_in Using 3.3V TTL tIOIN — 0.5 — 0.5 — 0.5 ns LVCMOS_18_in Using 1.8V CMOS tIOIN — 0.0 — 0.0 — 0.0 ns LVCMOS_25_in Using 2.5V CMOS tIOIN — 0.3 — 0.3 — 0.3 ns tIOINDLY tIOI Input Adjusters LVCMOS_33_in Using 3.3V CMOS tIOIN — 0.5 — 0.5 — 0.5 ns AGP_1X_in Using AGP 1x tIOIN — 1.0 — 1.0 — 1.0 ns CTT25_in Using CTT 2.5V tIOIN — 1.0 — 1.0 — 1.0 ns CTT33_in Using CTT 3.3V tIOIN — 1.0 — 1.0 — 1.0 ns GTL+_in Using GTL+ tIOIN — 0.5 — 0.5 — 0.5 ns HSTL_I_in Using HSTL 2.5V, Class I tIOIN — 0.5 — 0.5 — 0.5 ns HSTL_III_in Using HSTL 2.5V, Class III tIOIN — 0.5 — 0.5 — 0.5 ns LVDS_in Using Low Voltage Differential Signaling (LVDS) tIOIN — 0.8 — 0.8 — 0.8 ns BLVDS_in Using Bus Low Voltage tIOIN Differential Signaling (BLVDS) — 0.8 — 0.8 — 0.8 ns LVPECL_in Using Low Voltage PECL tIOIN — 0.8 — 0.8 — 0.8 ns PCI_in Using PCI tIOIN — 1.0 — 1.0 — 1.0 ns SSTL2_I_in Using SSTL 2.5V, Class I tIOIN — 0.8 — 0.8 — 0.8 ns SSTL2_II_in Using SSTL 2.5V, Class II tIOIN — 0.5 — 0.5 — 0.5 ns SSTL3_I_in Using SSTL 3.3V, Class I tIOIN — 0.8 — 0.8 — 0.8 ns SSTL3_II_in Using SSTL 3.3V, Class II tIOIN — 0.8 — 0.8 — 0.8 ns tIOO Output Adjusters Slow Slew Using Slow Slew (LVTTL and tIOBUF, tIOEN LVCMOS Outputs only) — 0.7 — 0.7 — 0.7 ns LVTTL_out Using 3.3V TTL Drive tIOBUF, tIOEN, tIODIS — 1.0 — 1.0 — 1.0 ns LVCMOS_18_4mA_out Using 1.8V CMOS Standard, 4mA Drive tIOBUF, tIOEN, tIODIS — 0.8 — 0.8 — 0.8 ns LVCMOS_18_5.33mA_out Using 1.8V CMOS Standard, 5.33mA Drive tIOBUF, tIOEN, tIODIS — 0.6 — 0.6 — 0.6 ns LVCMOS_18_8mA_out Using 1.8V CMOS Standard, 8mA Drive tIOBUF, tIOEN, tIODIS — 0.0 — 0.0 — 0.0 ns LVCMOS_18_12mA_out Using 1.8V CMOS Standard, 12mA Drive tIOBUF, tIOEN, tIODIS — 0.2 — 0.2 — 0.2 ns LVCMOS_25_4mA_out Using 2.5V CMOS Standard, 4mA Drive tIOBUF, tIOEN, tIODIS — 0.7 — 0.7 — 0.7 ns LVCMOS_25_5.33mA_out Using 2.5V CMOS Standard, 5.33 mA Drive tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns LVCMOS_25_8mA_out Using 2.5V CMOS Standard, 8mA Drive tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns LVCMOS_25_12mA_out Using 2.5V CMOS Standard, 12mA Drive tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns LVCMOS_25_16mA_out Using 2.5V CMOS Standard, 16mA Drive tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns 37 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA 200B/C & ispXPGA 200EB/EC Timing Adders (Cont.) Parameter Description Base Parameter Using 3.3V CMOS Standard, 4mA Drive -51 -4 -3 Min. Max. Min. Max. Min. tIOBUF, tIOEN, tIODIS — 1.0 — 1.0 — 1.0 ns LVCMOS_33_5.33mA_out Using 3.3V CMOS Standard, 5.33mA Drive tIOBUF, tIOEN, tIODIS — 1.0 — 1.0 — 1.0 ns LVCMOS_33_8mA_out Using 3.3V CMOS Standard, 8mA Drive tIOBUF, tIOEN, tIODIS — 0.7 — 0.7 — 0.7 ns LVCMOS_33_12mA_out Using 3.3V CMOS Standard, 12mA Drive tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns LVCMOS_33_16mA_out Using 3.3V CMOS Standard, 16mA Drive tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns LVCMOS_33_24mA_out Using 3.3V CMOS Standard, 24mA Drive tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns AGP_1X_out Using AGP 1x Standard tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns CTT25_out Using CTT 2.5V tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns CTT33_out Using CTT 3.3V tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns GTL+_out Using GTL+ tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns HSTL_I_out Using HSTL 2.5V, Class I tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns HSTL_III_out Using HSTL 2.5V, Class III tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns LVDS_out Using Low Voltage Differential Signaling (LVDS) tIOBUF, tIOEN, tIODIS — 1.0 — 1.0 — 1.0 ns BLVDS_out Using Bus Low Voltage Differ- tIOBUF, tIOEN, tIODIS ential Signaling (BLVDS) — 1.0 — 1.0 — 1.0 ns LVPECL_out Using Low Voltage PECL tIOBUF, tIOEN, tIODIS — 1.0 — 1.0 — 1.0 ns PCI_out Using PCI Standard tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns SSTL2_I_out Using SSTL 2.5V, Class I tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns SSTL2_II_out Using SSTL 2.5V, Class II tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns SSTL3_I_out Using SSTL 3.3V, Class I tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns SSTL3_II_out Using SSTL 3.3V, Class II tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns LVCMOS_33_4mA_out 1. Only available for ispXPGA 200B and ispXPGA 200EB (2.5V/3.3V) devices. 38 Max. Units Timing v.0.3 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA 500B/C & ispXPGA 500EB/EC External Switching Characteristics Over Recommended Operating Conditions -51 Parameter Description Conditions -4 -3 Min. Max. Min. Max. Min. Max. Units — 6.4 — 6.9 — 7.9 ns tCO Global Clock Input to Out- PIO Output Register put tS Global Clock Input Setup PIO Input Register without input delay -2.9 — -2.7 — -2.3 — ns tH Global Clock Input Hold PIO Input Register without input delay 3.6 — 3.9 — 4.5 — ns ns tSINDLY Global Clock Input Setup PIO Input Register with input delay 3.3 — 3.6 — 4.1 — tHINDLY Global Clock Input Hold PIO Input Register with input delay 0.0 — 0.0 — 0.0 — tCOPLL Global Clock Input to Output PIO Output Register using PLL without delay — 3.2 — 3.4 — 3.9 ns tSPLL Global Clock Input Setup PIO Input Register without input delay using PLL without delay 0.1 — 0.2 — 0.3 — ns tHPLL Global Clock Input Hold PIO Input Register without input delay using PLL without delay 0.8 — 0.9 — 1.0 — ns tSINDLYPLL Global Clock Input Setup PIO Input Register with input delay using PLL without delay 6.7 — 7.2 — 8.3 — ns tHINDLYPLL Global Clock Input Hold PIO Input Register with input delay using PLL without delay -4.3 — -4.0 — -3.4 — ns 1. Only available for ispXPGA 500B and ispXPGA 500EB (2.5V/3.3V) devices. 39 Timing v.0.3 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA 500B/C & ispXPGA 500EB/EC PFU Timing Parameters Over Recommended Operating Conditions -51 Parameter Description -4 -3 Min. Max. Min. Max. Min. Max. Units Functional Delays LUTs tLUT4 4-Input LUT Delay — 0.41 — 0.44 — 0.51 ns tLUT5 5-Input LUT Delay — 0.73 — 0.79 — 0.91 ns tLUT6 6-Input LUT Delay — 0.86 — 0.93 — 1.07 ns — -0.62 — -0.53 — ns Shift Register (LUT) tLSR_S Shift Register Setup Time -0.64 tLSR_H Shift Register Hold Time 0.61 — 0.63 — 0.72 — ns tLSR_CO Shift Register Clock to Output Delay — 0.70 — 0.75 — 0.86 ns — 0.08 — 0.09 — 0.10 ns Arithmetic Functions tLCTHRUR 2 MC (Macro Cell) Carry In to MC Carry Out Delay (Ripple) MC Carry In to MC Carry Out Delay (Look Ahead) — 0.05 — 0.05 — 0.06 ns tLSTHRU MC Sum In to MC Sum Out Delay — 0.42 — 0.45 — 0.52 ns tLSINCOUT MC Sum In to MC Carry Out Delay — 0.29 — 0.31 — 0.36 ns tLCINSOUTR MC Carry In to MC Sum Out Delay (Ripple) — 0.36 — 0.39 — 0.45 ns tLCINSOUTL MC Carry In to MC Sum Out Delay (Look Ahead) — 0.26 — 0.28 — 0.32 ns PFU Feed-Thru Delay — 0.15 — 0.16 — 0.18 ns tLCTHRUL Feed-thru tLFT Distributed RAM tLRAM_CO Clock to RAM Output — 1.24 — 1.33 — 1.53 ns tLRAMAD_S Address Setup Time -0.41 — -0.40 — -0.34 — ns tLRAMD_S Data Setup Time 0.21 — 0.22 — 0.25 — ns tLRAMWE_S Write Enable Setup Time 0.45 — 0.46 — 0.53 — ns tLRAMAD_H Address Hold Time 0.58 — 0.60 — 0.69 — ns tLRAMD_H Data Hold Time 0.11 — 0.11 — 0.13 — ns tLRAMWE_H Write Enable Hold Time 0.12 — 0.12 — 0.14 — ns tLRAMCPW Clock Pulse Width (High or Low) 2.91 — 3.00 — 3.45 — ns tLRAMADO Address to Output Delay — 0.86 — 0.93 — 1.07 ns — 0.58 — 0.62 — 0.71 ns Register/Latch Delays Registers tL_CO Register Clock to Output Delay tL_S Register Setup Time (Data before Clock) 0.14 — 0.14 — 0.16 — ns tL_H Register Hold Time (Data after Clock) -0.12 — -0.12 — -0.10 — ns tLCE_S Register Clock Enable Setup Time -0.11 — -0.11 — -0.09 — ns tLCE_H Register Clock Enable Hold Time 0.11 — 0.11 — 0.13 — ns — 0.09 — 0.10 — 0.12 ns Latches tL_GO Latch Gate to Output Delay tLL_S Latch Setup Time 0.14 — 0.14 — 0.16 — ns tLL_H Latch Hold Time -0.12 — -0.12 — -0.10 — ns tLLPD Latch Propagation Delay (Transparent Mode) — 0.09 — 0.10 — 0.12 ns 40 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA 500B/C & ispXPGA 500EB/EC PFU Timing Parameters (Cont.) Over Recommended Operating Conditions -51 Parameter Description -4 -3 Min. Max. Min. Max. Min. Max. Units — 1.09 — 1.17 — 1.35 ns Reset/Set tLASSRO Asynchronous Set/Reset to Output tLASSRPW Asynchronous Set/Reset Pulse Width 4.19 — 4.50 — 5.18 — ns tLASSRR Asynchronous Set/Reset Recovery — 0.51 — 0.55 — 0.63 ns tLSSR_S Synchronous Set/Reset Setup Time -0.03 — -0.03 — -0.03 — ns tLSSR_H Synchronous Set/Reset Hold Time 0.03 — 0.03 — 0.03 — ns 1. Only available for ispXPGA 500B and ispXPGA 500EB (2.5V/3.3V) devices. 2. tLCTHRUL quoted bit by bit. Timing v.0.3 ispXPGA 500B/C & ispXPGA 500EB/EC PIC Timing Parameters -51 Parameter Description -4 Min. Max. — 0.05 -3 Min. Max. Min. Max. Units 1.00 — — 0.05 1.07 — 1.23 ns — 0.06 — ns Register/Latch Delays tIO_CO Register Clock to Output Delay tIO_S Register Setup Time (Data before Clock) tIO_H Register Hold Time (Data after Clock) 0.06 — 0.06 — 0.07 — ns tIOCE_S Register Clock Enable Setup Time -0.03 — -0.03 — -0.03 — ns tIOCE_H Register Clock Enable Hold Time 0.13 0.13 — 0.15 — ns tIO_GO Latch Gate to Output Delay — 0.84 — 0.97 ns tIOL_S Latch Setup Time 0.05 — 0.05 — 0.06 — ns tIOL_H Latch Hold Time 0.06 — 0.06 — 0.07 — ns tIOLPD Latch Propagation Delay (Transparent Mode) — 0.09 — 0.10 — 0.12 ns tIOASRO Asynchronous Set/Reset to Output — 1.11 — 1.19 — 1.37 ns tIOASRPW Asynchronous Set/Reset Pulse Width 4.19 — 4.50 — 5.18 — ns tIOASRR Asynchronous Set/Reset Recovery Time — 0.23 — 0.25 — 0.29 ns — 0.98 — 1.05 — 1.21 ns — 0.78 Input/Output Delays tIOBUF Output Buffer Delay tIOIN Input Buffer Delay — 0.65 — 0.70 — 0.81 ns tIOEN Output Enable Delay — 0.52 — 0.56 — 0.64 ns tIODIS Output Disable Delay — -0.12 — -0.11 — -0.09 ns tIOFT Feed-thru Delay — 0.19 — 0.20 — 0.23 ns 1. Only available for ispXPGA 500B and ispXPGA 500EB (2.5V/3.3V) devices. 41 Timing v.0.3 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA 500B/C & ispXPGA 500EB/EC EBR Timing Parameters -51 Parameter Description -4 Min. Max. -3 Min. Max. Min. Max. Units Synchronous Write tEBSWAD_S Address Setup Delay 0.59 — 0.61 — 0.70 — ns tEBSWAD_H Address Hold Delay -0.40 — -0.39 — -0.33 — ns tEBSWCPW Clock Pulse Width 3.16 — 3.40 — 3.91 — ns tEBSWWE_S Write Enable Setup Time -0.12 — -0.12 — -0.10 — ns tEBSWWE_H Write Enable Hold Time 0.16 — 0.16 — 0.18 — ns tEBSWD_S Data Setup Time 0.27 — 0.28 — 0.32 — ns tEBSWD_H Data Hold Time -0.27 — -0.26 — -0.22 — ns Synchronous Read tEBSR_CO Clock to Data Delay — 2.04 — 2.19 — 2.52 ns tEBSRAD_S Address Setup Delay 0.10 — 0.10 — 0.12 — ns tEBSRAD_H Address Hold Delay -0.07 — -0.07 — -0.06 — ns tEBSRCPW Clock Pulse Width 3.16 — 3.40 — 3.91 — ns tEBSRCE_S Clock Enable Setup Time -1.76 — -1.71 — -1.45 — ns tEBSRCE_H Clock Enable Hold Time 1.64 — 1.69 — 1.94 — ns tEBSRWE_S Write Enable Setup Time -0.18 — -0.17 — -0.14 — ns tEBSRWE_H Write Enable Hold Time 0.12 — 0.12 — 0.14 — ns tEBSRWEEN Write Enable to Data Enable Time — 1.02 — 1.05 — 1.21 ns tEBSRWEDIS Write Enable to Data Disable Time — 0.99 — 1.02 — 1.17 ns tEBSREN Output Enable to Data Enable Time — 1.02 — 1.05 — 1.21 ns tEBSRDIS Output Enable to Data Disable Time — 0.83 — 0.86 — 0.99 ns Asynchronous Read tEBARADO Address to New Valid Data Delay — 2.39 — 2.46 — 2.83 ns tEBARAD_H Address to Previous Valid Data Delay — 2.10 — 2.17 — 2.50 ns tEBARWEEN Write Enable to Data Enable Time — 1.01 — 1.04 — 1.20 ns tEBARWEDIS Write Enable to Data Disable Time — 0.98 — 1.01 — 1.16 ns tEBAREN Output Enable to Data Enable Time — 1.02 — 1.05 — 1.21 ns tEBARDIS Output Enable to Data Disable Time — 0.83 — 0.86 — 0.99 ns 1. Only available for ispXPGA 500B and ispXPGA 500EB (2.5V/3.3V) devices. 42 Timing v.0.3 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA 500B/C & ispXPGA 500EB/EC Timing Adders Parameter Description Base Parameter -51 -4 -3 Min. Max. Min. Max. Min. Max. Units Optional Adders Input Delay — — 5.21 — 5.60 — 6.44 ns LVTTL_in Using 3.3V TTL tIOIN — 0.5 — 0.5 — 0.5 ns LVCMOS_18_in Using 1.8V CMOS tIOIN — 0.0 — 0.0 — 0.0 ns LVCMOS_25_in Using 2.5V CMOS tIOIN — 0.3 — 0.3 — 0.3 ns tIOINDLY tIOI Input Adjusters LVCMOS_33_in Using 3.3V CMOS tIOIN — 0.5 — 0.5 — 0.5 ns AGP_1X_in Using AGP 1x tIOIN — 1.0 — 1.0 — 1.0 ns CTT25_in Using CTT 2.5V tIOIN — 1.0 — 1.0 — 1.0 ns CTT33_in Using CTT 3.3V tIOIN — 1.0 — 1.0 — 1.0 ns GTL+_in Using GTL+ tIOIN — 0.5 — 0.5 — 0.5 ns HSTL_I_in Using HSTL 2.5V, Class I tIOIN — 0.5 — 0.5 — 0.5 ns HSTL_III_in Using HSTL 2.5V, Class III tIOIN — 0.5 — 0.5 — 0.5 ns LVDS_in Using Low Voltage Differential Signaling (LVDS) tIOIN — 0.8 — 0.8 — 0.8 ns BLVDS_in Using Bus Low Voltage tIOIN Differential Signaling (BLVDS) — 0.8 — 0.8 — 0.8 ns LVPECL_in Using Low Voltage PECL tIOIN — 0.8 — 0.8 — 0.8 ns PCI_in Using PCI tIOIN — 1.0 — 1.0 — 1.0 ns SSTL2_I_in Using SSTL 2.5V, Class I tIOIN — 0.8 — 0.8 — 0.8 ns SSTL2_II_in Using SSTL 2.5V, Class II tIOIN — 0.5 — 0.5 — 0.5 ns SSTL3_I_in Using SSTL 3.3V, Class I tIOIN — 0.8 — 0.8 — 0.8 ns SSTL3_II_in Using SSTL 3.3V, Class II tIOIN — 0.8 — 0.8 — 0.8 ns tIOO Output Adjusters Slow Slew Using Slow Slew (LVTTL and tIOBUF, tIOEN LVCMOS Outputs only) — 0.7 — 0.7 — 0.7 ns LVTTL_out Using 3.3V TTL Drive tIOBUF, tIOEN, tIODIS — 1.0 — 1.0 — 1.0 ns LVCMOS_18_4mA_out Using 1.8V CMOS Standard, 4mA Drive tIOBUF, tIOEN, tIODIS — 0.8 — 0.8 — 0.8 ns LVCMOS_18_5.33mA_out Using 1.8V CMOS Standard, 5.33mA Drive tIOBUF, tIOEN, tIODIS — 0.6 — 0.6 — 0.6 ns LVCMOS_18_8mA_out Using 1.8V CMOS Standard, 8mA Drive tIOBUF, tIOEN, tIODIS — 0.0 — 0.0 — 0.0 ns LVCMOS_18_12mA_out Using 1.8V CMOS Standard, 12mA Drive tIOBUF, tIOEN, tIODIS — 0.2 — 0.2 — 0.2 ns LVCMOS_25_4mA_out Using 2.5V CMOS Standard, 4mA Drive tIOBUF, tIOEN, tIODIS — 0.7 — 0.7 — 0.7 ns LVCMOS_25_5.33mA_out Using 2.5V CMOS Standard, 5.33 mA Drive tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns LVCMOS_25_8mA_out Using 2.5V CMOS Standard, 8mA Drive tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns LVCMOS_25_12mA_out Using 2.5V CMOS Standard, 12mA Drive tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns LVCMOS_25_16mA_out Using 2.5V CMOS Standard, 16mA Drive tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns 43 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA 500B/C & ispXPGA 500EB/EC Timing Adders (Cont.) Parameter Description Base Parameter Using 3.3V CMOS Standard, 4mA Drive -51 -4 -3 Min. Max. Min. Max. Min. tIOBUF, tIOEN, tIODIS — 1.0 — 1.0 — 1.0 ns LVCMOS_33_5.33mA_out Using 3.3V CMOS Standard, 5.33mA Drive tIOBUF, tIOEN, tIODIS — 1.0 — 1.0 — 1.0 ns LVCMOS_33_8mA_out Using 3.3V CMOS Standard, 8mA Drive tIOBUF, tIOEN, tIODIS — 0.7 — 0.7 — 0.7 ns LVCMOS_33_12mA_out Using 3.3V CMOS Standard, 12mA Drive tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns LVCMOS_33_16mA_out Using 3.3V CMOS Standard, 16mA Drive tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns LVCMOS_33_24mA_out Using 3.3V CMOS Standard, 24mA Drive tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns AGP_1X_out Using AGP 1x Standard tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns CTT25_out Using CTT 2.5V tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns CTT33_out Using CTT 3.3V tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns GTL+_out Using GTL+ tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns HSTL_I_out Using HSTL 2.5V, Class I tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns HSTL_III_out Using HSTL 2.5V, Class III tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns LVDS_out Using Low Voltage Differential Signaling (LVDS) tIOBUF, tIOEN, tIODIS — 1.0 — 1.0 — 1.0 ns BLVDS_out Using Bus Low Voltage Differ- tIOBUF, tIOEN, tIODIS ential Signaling (BLVDS) — 1.0 — 1.0 — 1.0 ns LVPECL_out Using Low Voltage PECL tIOBUF, tIOEN, tIODIS — 1.0 — 1.0 — 1.0 ns PCI_out Using PCI Standard tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns SSTL2_I_out Using SSTL 2.5V, Class I tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns SSTL2_II_out Using SSTL 2.5V, Class II tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns SSTL3_I_out Using SSTL 3.3V, Class I tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns SSTL3_II_out Using SSTL 3.3V, Class II tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns LVCMOS_33_4mA_out 1. Only available for ispXPGA 500B and ispXPGA 500EB (2.5V/3.3V) devices. 44 Max. Units Timing v.0.3 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA 1200B/C & ispXPGA 1200EB/EC External Switching Characteristics Over Recommended Operating Conditions -51 Parameter Description Conditions -4 -3 Min. Max. Min. Max. Min. Max. Units — 6.6 — 7.1 — 8.2 ns tCO Global Clock Input to Out- PIO Output Register put tS Global Clock Input Setup PIO Input Register without input delay -2.7 — -2.7 — -2.3 — ns tH Global Clock Input Hold PIO Input Register without input delay 4.5 — 4.6 — 5.3 — ns tSINDLY Global Clock Input Setup PIO Input Register with input delay 3.8 — 3.8 — 4.4 — ns tHINDLY Global Clock Input Hold PIO Input Register with input delay 0.0 — 0.0 — 0.0 — tCOPLL Global Clock Input to Output PIO Output Register using PLL without delay — 3.1 — 3.3 — 3.8 ns tSPLL Global Clock Input Setup PIO Input Register without input delay using PLL without delay 0.5 — 0.5 — 0.6 — ns tHPLL Global Clock Input Hold PIO Input Register without input delay using PLL without delay 0.8 — 0.8 — 1.0 — ns tSINDLYPLL Global Clock Input Setup PIO Input Register with input delay using PLL without delay 7.6 — 7.6 — 8.8 — ns tHINDLYPLL Global Clock Input Hold PIO Input Register with input delay using PLL without delay -4.1 — -4.0 — -3.4 — ns 1. Only available for ispXPGA 1200B and ispXPGA 1200EB (2.5V/3.3V) devices. 45 Timing v.0.2 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA 1200B/C & ispXPGA 1200EB/EC PFU Timing Parameters Over Recommended Operating Conditions -51 Parameter Description -4 -3 Min. Max. Min. Max. Min. Max. Units Functional Delays LUTs tLUT4 4-Input LUT Delay — 0.41 — 0.44 — 0.51 ns tLUT5 5-Input LUT Delay — 0.73 — 0.79 — 0.91 ns tLUT6 6-Input LUT Delay — 0.86 — 0.93 — 1.07 ns — -0.62 — -0.53 — ns Shift Register (LUT) tLSR_S Shift Register Setup Time -0.64 tLSR_H Shift Register Hold Time 0.61 — 0.63 — 0.72 — ns tLSR_CO Shift Register Clock to Output Delay — 0.70 — 0.75 — 0.86 ns — 0.08 — 0.09 — 0.10 ns Arithmetic Functions tLCTHRUR 2 MC (Macro Cell) Carry In to MC Carry Out Delay (Ripple) MC Carry In to MC Carry Out Delay (Look Ahead) — 0.05 — 0.05 — 0.06 ns tLSTHRU MC Sum In to MC Sum Out Delay — 0.42 — 0.45 — 0.52 ns tLSINCOUT MC Sum In to MC Carry Out Delay — 0.29 — 0.31 — 0.36 ns tLCINSOUTR MC Carry In to MC Sum Out Delay (Ripple) — 0.36 — 0.39 — 0.45 ns tLCINSOUTL MC Carry In to MC Sum Out Delay (Look Ahead) — 0.26 — 0.28 — 0.32 ns PFU Feed-Thru Delay — 0.15 — 0.16 — 0.18 ns tLCTHRUL Feed-thru tLFT Distributed RAM tLRAM_CO Clock to RAM Output — 1.24 — 1.33 — 1.53 ns tLRAMAD_S Address Setup Time -0.41 — -0.40 — -0.34 — ns tLRAMD_S Data Setup Time 0.21 — 0.22 — 0.25 — ns tLRAMWE_S Write Enable Setup Time 0.45 — 0.46 — 0.53 — ns tLRAMAD_H Address Hold Time 0.58 — 0.60 — 0.69 — ns tLRAMD_H Data Hold Time 0.11 — 0.11 — 0.13 — ns tLRAMWE_H Write Enable Hold Time 0.12 — 0.12 — 0.14 — ns tLRAMCPW Clock Pulse Width (High or Low) 2.91 — 3.00 — 3.45 — ns tLRAMADO Address to Output Delay — 0.86 — 0.93 — 1.07 ns — 0.58 — 0.62 — 0.71 ns Register/Latch Delays Registers tL_CO Register Clock to Output Delay tL_S Register Setup Time (Data before Clock) 0.14 — 0.14 — 0.16 — ns tL_H Register Hold Time (Data after Clock) -0.12 — -0.12 — -0.10 — ns tLCE_S Register Clock Enable Setup Time -0.11 — -0.11 — -0.09 — ns tLCE_H Register Clock Enable Hold Time 0.11 — 0.11 — 0.13 — ns — 0.09 — 0.10 — 0.12 ns Latches tL_GO Latch Gate to Output Delay tLL_S Latch Setup Time 0.14 — 0.14 — 0.16 — ns tLL_H Latch Hold Time -0.12 — -0.12 — -0.10 — ns tLLPD Latch Propagation Delay (Transparent Mode) — 0.09 — 0.10 — 0.12 ns 46 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA 1200B/C & ispXPGA 1200EB/EC PFU Timing Parameters (Cont.) Over Recommended Operating Conditions -51 Parameter Description -4 -3 Min. Max. Min. Max. Min. Max. Units — 1.09 — 1.17 — 1.35 ns Reset/Set tLASSRO Asynchronous Set/Reset to Output tLASSRPW Asynchronous Set/Reset Pulse Width 4.19 — 4.50 — 5.18 — ns tLASSRR Asynchronous Set/Reset Recovery — 0.51 — 0.55 — 0.63 ns tLSSR_S Synchronous Set/Reset Setup Time -0.03 — -0.03 — -0.03 — ns tLSSR_H Synchronous Set/Reset Hold Time 0.03 — 0.03 — 0.03 — ns 1. Only available for ispXPGA 1200B and ispXPGA 1200EB (2.5V/3.3V) devices. 2. tLCTHRUL quoted bit by bit. Timing v.2.1 ispXPGA 1200B/C & ispXPGA 1200EB/EC PIC Timing Parameters -51 Parameter Description -4 -3 Min. Max. Min. Max. Min. Max. Units — 1.01 — 1.09 — 1.25 ns Register/Latch Delays tIO_CO Register Clock to Output Delay tIO_S Register Setup Time (Data before Clock) 0.05 — 0.05 — 0.06 — ns tIO_H Register Hold Time (Data after Clock) 0.06 — 0.06 — 0.07 — ns tIOCE_S Register Clock Enable Setup Time -0.03 — -0.03 — -0.03 — ns tIOCE_H Register Clock Enable Hold Time 0.13 0.13 — 0.15 — ns tIO_GO Latch Gate to Output Delay — 0.85 — 0.91 — 1.05 ns tIOL_S Latch Setup Time 0.05 — 0.05 — 0.06 — ns tIOL_H Latch Hold Time 0.06 — 0.06 — 0.07 — ns tIOLPD Latch Propagation Delay (Transparent Mode) — 0.09 — 0.10 — 0.12 ns tIOASRO Asynchronous Set/Reset to Output tIOASRPW Asynchronous Set/Reset Pulse Width tIOASRR Asynchronous Set/Reset Recovery Time — 1.17 — 1.26 — 1.45 ns 4.19 — 4.50 — 5.18 — ns — 0.23 — 0.25 — 0.29 ns Input/Output Delays tIOBUF Output Buffer Delay — 0.99 — 1.06 — 1.22 ns tIOIN Input Buffer Delay — 0.71 — 0.76 — 0.87 ns tIOEN Output Enable Delay — 0.52 — 0.56 — 0.64 ns tIODIS Output Disable Delay — -0.11 — -0.10 — -0.09 ns tIOFT Feed-thru Delay — 0.19 — 0.20 — 0.23 ns 1. Only available for ispXPGA 1200B and ispXPGA 1200EB (2.5V/3.3V) devices. 47 Timing v.2.1 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA 1200B/C & ispXPGA 1200EB/EC EBR Timing Parameters -51 Parameter Description -4 Min. Max. -3 Min. Max. Min. Max. Units Synchronous Write tEBSWAD_S Address Setup Delay 0.59 — 0.61 — 0.70 — ns tEBSWAD_H Address Hold Delay -0.40 — -0.39 — -0.33 — ns tEBSWCPW Clock Pulse Width 3.16 — 3.40 — 3.91 — ns tEBSWWE_S Write Enable Setup Time -0.12 — -0.12 — -0.10 — ns tEBSWWE_H Write Enable Hold Time 0.16 — 0.16 — 0.18 — ns tEBSWD_S Data Setup Time 0.27 — 0.28 — 0.32 — ns tEBSWD_H Data Hold Time -0.27 — -0.26 — -0.22 — ns Synchronous Read tEBSR_CO Clock to Data Delay — 2.04 — 2.19 — 2.52 ns tEBSRAD_S Address Setup Delay 0.10 — 0.10 — 0.12 — ns tEBSRAD_H Address Hold Delay -0.07 — -0.07 — -0.06 — ns tEBSRCPW Clock Pulse Width 3.16 — 3.40 — 3.91 — ns tEBSRCE_S Clock Enable Setup Time -1.76 — -1.71 — -1.45 — ns tEBSRCE_H Clock Enable Hold Time 1.64 — 1.69 — 1.94 — ns tEBSRWE_S Write Enable Setup Time -0.18 — -0.17 — -0.14 — ns tEBSRWE_H Write Enable Hold Time 0.12 — 0.12 — 0.14 — ns tEBSRWEEN Write Enable to Data Enable Time — 1.02 — 1.05 — 1.21 ns tEBSRWEDIS Write Enable to Data Disable Time — 0.99 — 1.02 — 1.17 ns tEBSREN Output Enable to Data Enable Time — 1.02 — 1.05 — 1.21 ns tEBSRDIS Output Enable to Data Disable Time — 0.83 — 0.86 — 0.99 ns Asynchronous Read tEBARADO Address to New Valid Data Delay — 2.39 — 2.46 — 2.83 ns tEBARAD_H Address to Previous Valid Data Delay — 2.10 — 2.17 — 2.50 ns tEBARWEEN Write Enable to Data Enable Time — 1.01 — 1.04 — 1.20 ns tEBARWEDIS Write Enable to Data Disable Time — 0.98 — 1.01 — 1.16 ns tEBAREN Output Enable to Data Enable Time — 1.02 — 1.05 — 1.21 ns tEBARDIS Output Enable to Data Disable Time — 0.83 — 0.86 — 0.99 ns 1. Only available for ispXPGA 1200B and ispXPGA 1200EB (2.5V/3.3V) devices. 48 Timing v.2.1 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA 1200B/C & ispXPGA 1200EB/EC Timing Adders Parameter Description Base Parameter -51 -4 -3 Min. Max. Min. Max. Min. Max. Units Optional Adders Input Delay — — 5.58 — 6.0 — 6.90 ns LVTTL_in Using 3.3V TTL tIOIN — 0.5 — 0.5 — 0.5 ns LVCMOS_18_in Using 1.8V CMOS tIOIN — 0.0 — 0.0 — 0.0 ns LVCMOS_25_in Using 2.5V CMOS tIOIN — 0.3 — 0.3 — 0.3 ns tIOINDLY tIOI Input Adjusters LVCMOS_33_in Using 3.3V CMOS tIOIN — 0.5 — 0.5 — 0.5 ns AGP_1X_in Using AGP 1x tIOIN — 1.0 — 1.0 — 1.0 ns CTT25_in Using CTT 2.5V tIOIN — 1.0 — 1.0 — 1.0 ns CTT33_in Using CTT 3.3V tIOIN — 1.0 — 1.0 — 1.0 ns GTL+_in Using GTL+ tIOIN — 0.5 — 0.5 — 0.5 ns HSTL_I_in Using HSTL 2.5V, Class I tIOIN — 0.5 — 0.5 — 0.5 ns HSTL_III_in Using HSTL 2.5V, Class III tIOIN — 0.5 — 0.5 — 0.5 ns LVDS_in Using Low Voltage Differential Signaling (LVDS) tIOIN — 0.8 — 0.8 — 0.8 ns BLVDS_in Using Bus Low Voltage tIOIN Differential Signaling (BLVDS) — 0.8 — 0.8 — 0.8 ns LVPECL_in Using Low Voltage PECL tIOIN — 0.8 — 0.8 — 0.8 ns PCI_in Using PCI tIOIN — 1.0 — 1.0 — 1.0 ns SSTL2_I_in Using SSTL 2.5V, Class I tIOIN — 0.8 — 0.8 — 0.8 ns SSTL2_II_in Using SSTL 2.5V, Class II tIOIN — 0.5 — 0.5 — 0.5 ns SSTL3_I_in Using SSTL 3.3V, Class I tIOIN — 0.8 — 0.8 — 0.8 ns SSTL3_II_in Using SSTL 3.3V, Class II tIOIN — 0.8 — 0.8 — 0.8 ns tIOO Output Adjusters Slow Slew Using Slow Slew (LVTTL and tIOBUF, tIOEN LVCMOS Outputs only) — 0.7 — 0.7 — 0.7 ns LVTTL_out Using 3.3V TTL Drive tIOBUF, tIOEN, tIODIS — 1.0 — 1.0 — 1.0 ns LVCMOS_18_4mA_out Using 1.8V CMOS Standard, 4mA Drive tIOBUF, tIOEN, tIODIS — 0.8 — 0.8 — 0.8 ns LVCMOS_18_5.33mA_out Using 1.8V CMOS Standard, 5.33mA Drive tIOBUF, tIOEN, tIODIS — 0.6 — 0.6 — 0.6 ns LVCMOS_18_8mA_out Using 1.8V CMOS Standard, 8mA Drive tIOBUF, tIOEN, tIODIS — 0.0 — 0.0 — 0.0 ns LVCMOS_18_12mA_out Using 1.8V CMOS Standard, 12mA Drive tIOBUF, tIOEN, tIODIS — 0.2 — 0.2 — 0.2 ns LVCMOS_25_4mA_out Using 2.5V CMOS Standard, 4mA Drive tIOBUF, tIOEN, tIODIS — 0.7 — 0.7 — 0.7 ns LVCMOS_25_5.33mA_out Using 2.5V CMOS Standard, 5.33 mA Drive tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns LVCMOS_25_8mA_out Using 2.5V CMOS Standard, 8mA Drive tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns LVCMOS_25_12mA_out Using 2.5V CMOS Standard, 12mA Drive tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns LVCMOS_25_16mA_out Using 2.5V CMOS Standard, 16mA Drive tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns 49 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA 1200B/C & ispXPGA 1200EB/EC Timing Adders (Cont.) Parameter Description Base Parameter Using 3.3V CMOS Standard, 4mA Drive -51 -4 -3 Min. Max. Min. Max. Min. tIOBUF, tIOEN, tIODIS — 1.0 — 1.0 — 1.0 ns LVCMOS_33_5.33mA_out Using 3.3V CMOS Standard, 5.33mA Drive tIOBUF, tIOEN, tIODIS — 1.0 — 1.0 — 1.0 ns LVCMOS_33_8mA_out Using 3.3V CMOS Standard, 8mA Drive tIOBUF, tIOEN, tIODIS — 0.7 — 0.7 — 0.7 ns LVCMOS_33_12mA_out Using 3.3V CMOS Standard, 12mA Drive tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns LVCMOS_33_16mA_out Using 3.3V CMOS Standard, 16mA Drive tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns LVCMOS_33_24mA_out Using 3.3V CMOS Standard, 24mA Drive tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns AGP_1X_out Using AGP 1x Standard tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns CTT25_out Using CTT 2.5V tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns CTT33_out Using CTT 3.3V tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns GTL+_out Using GTL+ tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns HSTL_I_out Using HSTL 2.5V, Class I tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns HSTL_III_out Using HSTL 2.5V, Class III tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns LVDS_out Using Low Voltage Differential Signaling (LVDS) tIOBUF, tIOEN, tIODIS — 1.0 — 1.0 — 1.0 ns BLVDS_out Using Bus Low Voltage Differ- tIOBUF, tIOEN, tIODIS ential Signaling (BLVDS) — 1.0 — 1.0 — 1.0 ns LVPECL_out Using Low Voltage PECL tIOBUF, tIOEN, tIODIS — 1.0 — 1.0 — 1.0 ns PCI_out Using PCI Standard tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns SSTL2_I_out Using SSTL 2.5V, Class I tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns SSTL2_II_out Using SSTL 2.5V, Class II tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns SSTL3_I_out Using SSTL 3.3V, Class I tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns SSTL3_II_out Using SSTL 3.3V, Class II tIOBUF, tIOEN, tIODIS — 0.5 — 0.5 — 0.5 ns LVCMOS_33_4mA_out 1. Only available for ispXPGA 1200B and ispXPGA 1200EB (2.5V/3.3V) devices. 50 Max. Units Timing v.2.1 Lattice Semiconductor ispXPGA Family Data Sheet sysHSI Block Timing Figure 24 provides a graphical representation of the SERDES receiver input requirements. It provides guidance on a number of input parameters, including signal amplitude and rise time limits, noise and jitter limits, and P and N input skew tolerance. Figure 24. Receive Data Eye Diagram Template (Differential) Bit Time V THD 200 mV Differential +/- 100 mV Single Ended jt TH eo SIN jtTH jtTH : Optimum Threshold Crossing Jitter The data pattern eye opening at the receive end of a link is considered the ultimate measure of received signal quality. Almost all detrimental characteristics of a transmit signal and the interconnection link design result in eye closure. This combined with the eye-opening limitations of the line receiver can provide a good indication of a link’s ability to transfer error-free data. Signal jitter is of special interest to system designers. It is often the primary limiting characteristic of long digital links and of systems with high noise level environments. An interesting characteristic of the clock and data recovery (CDR) portion of the ispXPGA SERDES receiver is its ability to filter incoming signal jitter that is below the clock recovery PLL bandwidth. For signals with high levels of low frequency jitter, the receiver can detect incoming data error free, with eye openings significantly less than that shown in Figure 24. 51 Lattice Semiconductor ispXPGA Family Data Sheet sysHSI Block AC Specifications Operating Frequency Ranges Symbol Description Mode SS:CAL fCLK Reference Clock 10B12B Frequency 8B10B SS:CAL fSIN2 Serial Input 10B12B 8B10B fOUT2 Serial Out LVDS -51 Test Condition with eoSIN with eoSIN with eoSIN CL = 5 pF, RL = 100Ω fCLK with no jitter Device -4 -3 Min. Max. Min. Max. Min. LFX125B/C 50 200 50 200 50 Max. Units 200 LFX200B/C 50 188 50 188 50 188 LFX500B/C 50 188 50 188 50 188 LFX1200B/C 50 175 50 175 50 175 LFX125B/C 33 67 33 67 33 67 LFX200B/C 33 63 33 63 33 63 LFX500B/C 33 63 33 63 33 63 LFX1200B/C 33 58 33 58 33 58 LFX125B/C 40 80 40 80 40 80 LFX200B/C 40 75 40 75 40 75 LFX500B/C 40 75 40 75 40 75 LFX1200B/C 40 70 40 70 40 70 LFX125B/C 400 800 400 800 400 800 LFX200B/C 400 750 400 750 400 750 LFX500B/C 400 750 400 750 400 750 LFX1200B/C 400 700 400 700 400 700 LFX125B/C 400 800 400 800 400 800 LFX200B/C 400 750 400 750 400 750 LFX500B/C 400 750 400 750 400 750 LFX1200B/C 400 700 400 700 400 700 LFX125B/C 400 800 400 800 400 800 LFX200B/C 400 750 400 750 400 750 LFX500B/C 400 750 400 750 400 750 LFX1200B/C 400 700 400 700 400 700 LFX125B/C 400 800 400 800 400 800 LFX200B/C 400 750 400 750 400 750 LFX500B/C 400 750 400 750 400 750 LFX1200B/C 400 700 400 700 400 700 MHz MHz MHz Mbps Mbps Mbps Mbps 1. Only available for ispXPGA 125B, 200B, 500B and 1200B (2.5V/3.3V) devices. 2. fSIN and fSOUT speeds are supported at VCC and VCCP at 1.7V to 1.9V for ispXPGA 1.8V devices. LOCKIN Time Symbol tSCLOCK tCDRLOCK Description CSPLL Lock Time CDRPLL Lock-in Time Mode Condition Min Max Unit All After input is stabilized 25 μS SS With SS mode sync pattern 1024 tRCP1 10B12B With 10B12B sync pattern 1024 tRCP 8B10B With 8B10B idle pattern 960 tRCP tSYNC SyncPat Length SS 1200 tRCP tCAL CAL Duration SS 1100 tRCP tSUSYNC SyncPat Set-up Time to CAL SS 50 tRCP tHDSYNC SyncPat Hold Time from CAL SS 50 tRCP 1. REFCLK clock period. 52 Lattice Semiconductor ispXPGA Family Data Sheet REFCLK and SS_CLKIN Timing Symbol Description Mode Condition tDREFCLK Frequency Deviation Between TX REFCLK and CDRX REFCLK on One Link 8B10B/ 10B12B tJPPREFCLK REFCLK, SS_CLKIN Peak-to-Peak Period Jitter All tPWREFCLK REFCLK, SS_CLKIN Pulse Width, (80% to 80% or 20% to 20%). All tRFREFCLK REFCLK, SS_CLKIN Rise/Fall Time (20% to 80% or 80% to 20%) All Min Max Unit -100 100 ppm 0.01 UIPP Random Jitter 40-100MHz 2 100-200MHz 1 ns 2 ns Serializer Timing2 Symbol Description Mode Max Unit fCLK with no jitter 0.25 UIPP 8B10B 800 Mbps w/K28.7- 130 ps SOUT Peak-to-Peak Deterministic Jitter 8B10B 800 Mbps w/K28.5+ 160 ps tRFSOUT SOUT Output Data Rise/Fall Time (20%, 80%) LVDS 700 ps tCOSOUT REFCLK to SOUT Delay 2Bt1 +10 ns tSKTX Skew of SOUT with Respect to SS_CLKOUT SS tCKOSOUT SS_CLKOUT to bit0 of SOUT SS tJPP8B10B All Min SOUT Peak-to-Peak Random Jitter tJPPSOUT SOUT Peak-to-Peak Output Data Jitter Condition SS/8B10B 2Bt1 + 2 10B12B 1 1Bt + 2 1 1Bt +10 ns 300 ps 2Bt1 - tSKTX 2Bt1 + tSKTX tHSITXDDATAS TXD Data Setup Time All Note 3 tHSITXDDATAH TXD Data Hold Time All Note 3 1.5 ns ns 1.0 ns 1. Bt: Bit Time Period. High Speed Serial Bit Time. 2. The SIN and SOUT jitter specifications listed above are under the condition that the clock tree that drives the REFCLK to sysHSI Block is in sysCLOCK PLL BYPASS mode. 3. Internal timing for reference only. Deserializer Timing Symbol Description fDSIN SIN Frequency Deviation from REFCLK eoSIN SIN Eye Opening Tolerance Mode Conditions 8B10B/ 10B12B All Notes 1, 2 Min Max Units -100 100 ppm 0.45 UIPP -12 Bit Error Rate All tHSIOUTVALIDPRE RXD, SYDT Valid Time Before RECCLK Falling Edge All Note 3 tRCP/2 - 0.7 ns tHSIOUTVALIDPOST RXD, SYDT Valid Time After RECCLK Falling Edge All Note 3 tRCP/2 - 0.7 ns tDSIN Bit 0 of SIN Delay to RXD Valid at RECCLK Falling edge All 1. Eye opening based on jitter frequency of 100KHz. 2. Lower frequency operation assumes maximum eye closure of 800ps. 3. Internal timing for reference only. 53 10 Bits ber 1.5 tRCP + 4.5Bt + 3 1.5 tRCP + 4.5Bt + 15 ns Lattice Semiconductor ispXPGA Family Data Sheet Lock-in Timing CDRX_SS LOCK-IN (DE-SKEW) TIMING SIN CAL MIN. 1200 SYNCPAT DATA (SERIAL) MIN. 1100 LS CYCLE tHDSYNC tSUSYNC SYDT RXD(0:7) SYNCPAT TRAINING SEQUENCE DATA (PARALLEL) SS MODE DATA TRANSFER CDR_10B12B LOCK-IN TIMING SIN 1024 SYNCPAT DATA (SERIAL) SYDT RXD(0:9) SYNCPAT DATA (PARALLEL) CDR_8B10B LOCK-IN TIMING SIN 240 Idle Pattern(960 TRCP) DATA (SERIAL) SYDT RXD(0:9) Idle Pattern DATA (PARALLEL) SYDT Timing SYDT TIMING FOR CDRX_10B12B RECCLK SYDT RXD(0:9) Data0 Data1 Data2 Data3 Data4 SYNC PATTERN Parallel Data SYDT TIMING FOR CDRX_8B10B RECCLK SYDT RXD(0:9) K28.5 D21.4 D21.5 D21.5 K28.5 D21.4 D21.5 D21.5 IDLE PATTERN IDLE PATTERN 54 D0 D1 D2 Data Lattice Semiconductor ispXPGA Family Data Sheet Serializer Timing 8B/10B SERIALIZER DELAY TIMING SYMBOL N TXD SYMBOL N+1 tCOSOUT REFCLK SOUT b4 b5 b6 b7 b8 b9 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b0 b1 b2 SYMBOL N SYMBOL N-1 SYMBOL N+1 10B/12B SERIALIZER DELAY TIMING SYMBOL N TXD SYMBOL N+1 t COSOUT REFCLK b4 b5 b6 b7 b8 b9 "0" "1" b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 "0" "1" SOUT SYMBOL N SYMBOL N-1 SS Mode SERIALIZER DELAY TIMING SYMBOL N TXD SYMBOL N+1 t COSOUT REFCLK SS_CLKOUT t CKOSOUT SOUT b4 b5 b6 b7 t SKTX b0 b1 b2 b3 SYMBOL N SYMBOL N-1 INTERNAL TIMING FOR sysHSI BLOCK RECCLK tHSIOUTVALIDPRE t HSIOUTVALIDPOST SYDT, RXD 55 b4 b5 b6 b7 b0 SYMBOL N+1 Lattice Semiconductor ispXPGA Family Data Sheet Deserializer Timing 8B/10B DESERIALIZER DELAY TIMING SYMBOL N+1 SYMBOL N SIN SYMBOL N+2 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b0 b1 b2 b3 b4 b5 TDSIN RECCLK SYMBOL N SYMBOL N-1 RXD 10B/12B DESERIALIZER DELAY TIMING SYMBOL N SIN SYMBOL N+2 SYMBOL N+1 "1" b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 "0" "1" b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 "0" "1" b0 b1 b2 b3 b4 TTDSIN RECCLK RXD SYMBOL N-1 SYMBOL N-2 SYMBOL N CDRX_SS DESERIALIZER DELAY TIMING SYMBOL N SIN b0 b1 b2 b3 b4 SYMBOL N+2 SYMBOL N+1 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 TDSIN RECCLK RXD SYMBOL N-2 SYMBOL N-1 INTERNAL TIMING FOR sysHSI BLOCK TPWREFCLK REFCLK t HSITXDDATAS t HSITXDDATAH TXD 56 SYMBOL N b0 b1 b2 b3 b4 Lattice Semiconductor ispXPGA Family Data Sheet sysCLOCK PLL Timing Over Recommended Operating Conditions Symbol Parameter Conditions Min Max Units tPWH Input clock, high time 80% to 80% 1.2 — ns tPWL Input clock, low time 20% to 20% 1.2 — ns tR, tF Input Clock, rise and fall time 20% to 80% — 3.0 ns tINSTB Input clock stability, cycle to cycle (peak) — +/- 250 ps fMDIVIN M Divider input, frequency range 10 320 MHz fMDIVOUT M Divider output, frequency range 10 320 MHz fNDIVIN N Divider input, frequency range 10 320 MHz fNDIVOUT N Divider output, frequency range 10 320 MHz fVDIVIN V Divider input, frequency range 100 400 MHz fVDIVOUT V Divider output, frequency range 10 320 MHz tOUTDUTY output clock, duty cycle Output clock, cycle to cycle jitter (peak) tJIT(CC) tJIT(PER) 2 Output clock, period jitter (peak) 40 60 % Clean reference1 10MHz ≤ fMDIVOUT ≤ 40MHz or 100MHz ≤ f VDIVIN ≤ 160MHz — +/- 600 ps Clean reference1 40MHz ≤ fMDIVOUT ≤ 320MHz and 160MHz ≤ fVDIVIN ≤ 400MHz — +/- 150 ps Clean reference1 10MHz ≤ fMDIVOUT ≤ 40MHz or 100MHz ≤ fVDIVIN ≤ 160MHz — +/- 600 ps Clean reference1 40MHz ≤ fMDIVOUT ≤ 320MHz and 160MHz ≤ fVDIVIN ≤ 400MHz — +/- 150 ps — 3.0 ns — 1.5 ns — 25 us tCLK_OUT_DELAY Input clock to CLK_OUT delay Internal feedback tPHASE Input clock to external feedback delta External feedback tLOCK Time to acquire phase lock after input stable tPLL_DELAY Delay increment (Lead/Lag) tRANGE Total output delay range (lead/lag) tPLL_RSTW Minimum reset pulse width 1.8 — ns tCLK_IN3 Global clock input delay — 1.0 ns — 1.5 ns Typical = +/- 250ps tPLL_SEC_DELAY Secondary PLL output delay +/- 120 +/- 550 ps +/- 0.84 +/- 3.85 ns 1. This condition assures that the output phase jitter will remain within specifications. Jitter spec is based on optimized M, N and V settings determined by the ispLEVER software. 2. Accumulated jitter measured over 10,000 waveform samples 3. Internal timing for reference only. 57 Lattice Semiconductor ispXPGA Family Data Sheet ispXP sysCONFIG Port Timing Specifications Symbol Timing Parameter Min. Typ. Max. Units 10 — — ns sysCONFIG Write Cycle Timing tSUCS Input setup time of CS to CCLK rise tHCS Hold time of CS to CCLK Rise 0 — — ns tSUWD Input setup time of write data to CCLK rise 12 — — ns tHWD Hold time of write data to CCLK rise 0 — — ns tPRGM Low time to reset device SRAM 5 — 50 ns tWINIT INIT pulse width — — 5 ms tIODISS User I/O disable — — 30 ns tIOENSS User I/O enable — — 30 ns tWH Write clock High pulse width 12 — — ns tWL Write clock Low pulse width 12 — — ns fMAXW Write fMAX — — 33 MHz 0 — — ns sysCONFIG Read Cycle Timing tHREAD Hold time of READ to CCLK rise tSUREAD Input setup time of READ High to CCLK rise 30 — — ns tRH READ clock high pulse width 12 — — ns tRL READ clock low pulse width 15 — — ns fMAXR Read fMAX — — 33 MHz tCORD Clock to out for read data — — 25 ns Boundary Scan Timing Parameter Description Min. Max. Units tBTCP TCK [BSCAN] Clock Pulse Width 40 — ns tBTCPH TCK [BSCAN] Clock Pulse Width High 20 — ns tBTCPL TCK [BSCAN] Clock Pulse Width Low 20 — ns tBTS TCK [BSCAN] Setup Time 8 — ns tBTH TCK [BSCAN] Hold Time 10 — ns tBTRF TCK [BSCAN] Rise/Fall Time 50 — mV/ns tBTCO TAP Controller Falling Edge of Clock to Valid Output — 18 ns tBTCODIS TAP Controller Falling Edge of Clock to Valid Disable — 18 ns tBTCOEN TAP Controller Falling Edge of Clock to Valid Enable — 18 ns tBTCRS BSCAN Test Capture Register Setup Time 8 — ns tBTCRH BSCAN Test Capture Register Hold Time 25 — ns tBUTCO BSCAN Test Update Register, Falling Edge of Clock to Valid Output — 45 ns tBTUODIS BSCAN Test Update Register, Falling Edge of Clock to Valid Disable — 20 ns tBTUPOEN BSCAN Test Update Register, Falling Edge of Clock to Valid Enable — 20 ns 58 Lattice Semiconductor ispXPGA Family Data Sheet Switching Test Conditions Figure 25 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 7. Figure 25. Output Test Load, LVTTL and LVCMOS Standards VCCO R1 Test Point Device Output R2 CL* *CL includes test fixture and probe capacitance. Table 7. Text Fixture Required Components Test Condition LVCMOS I/O, (L -> H, H -> L) R1 106 R2 106 CL 35pF Timing Reference VCCO LVCMOS 3.3 = VCCO/2 LVCMOS 3.3 = 3.0V LVCMOS 2.5 = VCCO/2 LVCMOS 2.5 = 2.3V LVCMOS 1.8 = VCCO/2 LVCMOS 1.8 = 1.65V Default LVCMOS 1.8 I/O (Z -> H) ∞ 106 35pF 0.9V 1.65V Default LVCMOS 1.8 I/O (Z -> L) 106 ∞ 35pF 0.9V 1.65V Default LVCMOS 1.8 I/O (H -> Z) ∞ 106 5pF VOH - 0.3 1.65V Default LVCMOS 1.8 I/O (L -> Z) 106 ∞ 5pF VOL + 0.3 1.65V Note: Output test conditions for all other interfaces are determined by the respective standards. 59 Lattice Semiconductor ispXPGA Family Data Sheet Signal Descriptions1 Signal Name Signal Type Description General Purpose BKy_IOx1,2 Input/Output GCLKn/In 7 Input GSR Input NC — General purpose I/O number x in I/O Bank y Global clock/input8 Global Set/Reset No Connect GND GND Ground VCC VCC Core logic power supply VCCJ VCC IEEE 1149.1 TAP power supply VCCOy2 VCC I/O Bank y power supply Input I/O Bank y reference voltage VREFy 2 DXN, DXP Output Temperature Sensing Diodes, provide a differential voltage, which corresponds to the temperature of the device. Test and Program/Configuration TMS Input Test Mode Select TCK Input Test Clock TDI Input Test Data In TDO Output TOE Input Test Output Enable tri-states all I/O pins when driven low CFG0 Input Selects the SRAM memory configuration type (Peripheral or E2CMOS Refresh) PROGRAMb Input Initiates download from E2CMOS or the peripheral port to SRAM memory (active low) Test Data Out DONE Bi-directional Indicates when configuration is complete INITb Bi-directional Indicates the device is ready for programming (active low) READ Input Selects the READ operation when in sysCONFIG mode CCLK Input sysCONFIG Configuration Clock CSb Input sysCONFIG Chip Select (active low) DATA[0:7] Bi-directional sysCONFIG Peripheral Port Data I/O sysCLOCK PLL3 PLL_FBKz Input Optional external feedback PLL_RSTz Input Optional external M divider reset CLK_OUTz Internal Signal Clock output (routable to any I/O) PLL_LOCKz Internal Signal Lock output (routable to any I/O) GNDP0 GND Left side PLL Ground GNDP1 GND Right side PLL Ground VCCP0 VCC Left side PLL power supply VCCP1 VCC Right side PLL power supply Input P-side of differential serial data input 4, 5 sysHSI Block HSImA_SINP, HSImB_SINP HSImA_SINN, HSImB_SINN HSImA_SOUTP, HSImB_SOUTP HSImA_SOUTN, HSImB_SOUTN Input N-side of differential serial data input Output P-side of differential serial data output Output N-side of differential serial data output HSImA_SYDT, HSImB_SYDT Internal Signal Symbol alignment detect HSImA_RECCLK, HSImB_RECCLK Internal Signal Recovered clock 60 Lattice Semiconductor ispXPGA Family Data Sheet Signal Descriptions1 (Cont.) Signal Name Signal Type HSImA_CDRRST, HSImB_CDRRST HSIm_CSLOCK, HSIm_CSLOCK Input Description CDR Reset Internal Signal Indicates when the CSPLL circuit is locked sysHSI Block (Source Synchronous Mode)6 SS_CLKIN0P, SS_CLKIN1P Input P-side of differential clock input SS_CLKIN0N, SS_CLKIN1N Input N-side of differential clock input SS_CLKOUT0P, SS_CLKOUT1P Output P-side of differential clock output SS_CLKOUT0N, SS_CLKOUT1N Output N-side of differential clock output CAL0, CAL1 1. 2. 3. 4. 5. 6. 7. 8. Input Initiates source synchronous calibration sequence x is a variable for the I/O number. y is a variable for the I/O Bank. z is a variable for the PLL number. m is a variable for the sysHSI block number. A and B refer to the sysHSI block channels. 0 and 1 refer to Source Synchronous group 0 and 1 n is a variable for the GCLK and Input number See Logic Signal Connections Table for differential pairing. 61 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Power Supply and NC Connections1 256-Ball fpBGA3 Signal 516-Ball fpBGA3 VCC C3, C14, D4, D13, E5, E12, F6, F11, A9, A22, D4, D27, J1, J30, L11, L12, L15, L16, L19, L20, M11, M20, R11, L6, L11, M5, M12, N4, N13, P3, P14 R20, T11, T20, W11, W20, Y11, Y12, Y15, Y16, Y19, Y20, AB1, AB30, AG4, AG27, AK9, AK22 VCCO0 F5, G5 F4, J4, M4, N11, P4, P11 VCCO1 K5, L5 U4, U11, V11, W4, AB4, AE4 VCCO2 M6, M7 Y13, Y14, AG6, AG9, AG12, AG14 VCCO3 M10, M11 Y17, Y18, AG17, AG19, AG22, AG25 VCCO4 K12, L12 U20, U27, V20, W27, AB27, AE27 VCCO5 G12, F12 F27, J27, M27, N20, P20, P27 VCCO6 E10, E11 D17, D19, D22, D25, L17, L18 VCCO7 E6, E7 D6, D9, D12, D14, L13, L14 VCCP H3, J15 R4, T30 VCCJ A2 C4 GND A1, A16, B2, B15, F7, F8, F9, F10, G6, G7, G8, G9, G10, G11, H6, H7, H8, H9, H10, H11, J6, J7, J8, J9, J10, J11, K6, K7, K8, K9, K10, K11, L7, L8, L9, L10, R2, R15, T1, T16 A1, A30, B2, B29, C3, C28, M12, M13, M14, M15, M16, M17, M18, M19, N12, N13, N14, N15, N16, N17, N18, N19, P12, P13, P14, P15, P16, P17, P18, P19, R12, R13, R14, R15, R16, R17, R18, R19, T12, T13, T14, T15, T16, T17, T18, T19, U12, U13, U14, U15, U16, U17, U18, U19, V12, V13, V14, V15, V16, V17, V18, V19, W12, W13, W14, W15, W16, W17, W18, W19, AH3, AH28, AJ2, AJ29, AK1, AK30 GNDP H15, J4 R29, T4 NC2 — LFX125: A10, A13, A16, A17, A24, A25, A26, A4, A5, A6, A7, AA1, AA2, AA28, AA29, AA3, AB28, AC1, AC28, AD1, AD27, AD4, AE28, AE29, AE3, AE30, AF27, AF28, AF29, AF3, AF4, AG1, AG10, AG11, AG15, AG2, AG20, AG23, AG24, AG29, AG3, AG8, AH1, AH15, AH19, AH2, AH20, AH23, AH24, AH30, AH7, AH8, AH9, AJ1, AJ12, AJ14, AJ15, AJ19, AJ20, AJ21, AJ23, AJ24, AJ25, AJ27, AJ30, AJ6, AJ7, AJ8, AK11, AK14, AK15, AK20, AK21, AK23, AK24, AK25, AK27, AK5, AK6, AK7, B10, B13, B16, B17, B18, B23, B24, B25, B5, B6, B7, C11, C13, C14, C16, C17, C22, C23, C24, C25, C6, C7, C8, D11, D16, D23, D24, D28, D29, D3, D7, D8, E30, E4, F1, F29, F30, G1, G2, G27, G28, G29, G30, H1, H2, H27, H28, H29, H30, J2, J28, J29, J3, K1, K2, K27, K28, K3, K4, L1, L2, L27, L3, L4, M1, M2, M29, M3, M30, V27, V28, V3, V4, W1, W30, Y1, Y27, Y28, Y3, Y30 LFX200: A26, A25, A24, A17, A10, A7, A6, A5, A4, B25, B24, B23, B17, B10, B7, B6, B5, C25, C24, C23, C22, C16, C11, C8, C7, C6, D24, D23, D16, D11, D8, D7, E30, F30, F29, F1, G30, G29, G28, G27, G2, G1, H30, H29, H28, H27, H2, H1, J29, J28, J3, J2, K28, K27, K4, K3, K2, K1, L27, L4, L3, L2, L1, M3, V28, V27, V4, V3, W30, W1, Y30, Y28, Y27, Y3, Y1, AA29, AA28, AA3, AA2, AA1, AD27, AD4, AE28, AE3, AF29, AF28, AF27, AF3, AG29, AG24, AG23, AG20, AG11, AG10, AG8, AG2, AG1, AH30, AH24, AH23, AH20, AH9, AH8, AH7, AH2, AH1, AJ30, AJ27, AJ25, AJ24, AJ23, AJ21, AJ15, AJ12, AJ8, AJ7, AJ6, AJ1, AK27, AK25, AK24, AK23, AK21, AK15, AK11, AK7, AK6, AK5 1. All grounds must be electrically connected at the board level. 2. NC pins should not be connected to any active signals, VCC or GND. 3. Balls for GND, VCC and VCCOx are connected within the substrate to their respective common signals. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally. 62 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Power Supply and NC Connections1 (Continued) 680-Ball fpBGA3 Signal 900-Ball fpBGA3 VCC AE35, AE5, AL5, AR15, AR25, AR31, AR35, AR5, L11, L20, M12, M13, M14, M17, M18, M19, N12, N19, P12, P19, AT36, AT4, AU3, AU37, C3, C37, D36, D4, E15, E25, U12, U19, V12, V19, W12, W13, W14, W17, W18, W19, Y11, Y20 E35, E5, E9, J35, R35, R5 VCCO0 E11, E12, E13, E17, E18, E7 K3, L10, M11, N11, N5, P11, R11, R12 VCCO1 E22, E23, E27, E29, E31, E33 AA3, T11, T12, U11, V11, V5, W11, Y10 VCCO2 G35, L35, M35, N35, U35, V35 AA11, AF13, AH10, W15, Y12, Y13, Y14, Y15 VCCO3 AB35, AC35, AG35, AJ35, AL35, AN35 AA20, AF18, AH21, W16, Y16, Y17, Y18, Y19 VCCO4 AR22, AR23, AR27, AR28, AR29, AR33 AA28, T19, T20, U20, V20, V26, W20, Y21 VCCO5 AR11, AR13, AR17, AR18, AR7, AR9 K28, L21, M20, N20, N26, P20, R19, R20 VCCO6 AB5, AC5, AG5, AH5, AJ5, AN5 C21, E18, K20, L16, L17, L18, L19, M16 VCCO7 G5, J5, L5, N5, U5, V5 C10, E13, K11, L12, L13, L14, L15, M15 VCCP E20, AW22 R5, T26 VCCJ D3 B3 GND A1, A2, A20, A38, A39, AE3, AE37, AK3, AK37, AR36, AR4, AT20, AT35, AT5, AU10, AU14, AU20, AU26, AU30, AV1, AV2, AV20, AV38, AV39, AW1, AW2, AW20, AW38, AW39, B1, B2, B20, B38, B39, C10, C14, C20, C26, C30, D20, D35, D5, E36, E4, K3, K37, P37, R3, Y1, Y2, Y3, Y36, Y37, Y38, Y39, Y4 A1, A2, A29, A30, AB28, AB3, AG27, AG4, AH22, AH28, AH3, AH9, AJ1, AJ2, AJ29, AJ30, AK1, AK2, AK29, AK30, B1, B2, B29, B30, C22, C28, C3, C9, D27, D4, J28, J3, N13, N14, N15, N16, N17, N18, P13, P14, P15, P16, P17, P18, R13, R14, R15, R16, R17, R18, T13, T14, T15, T16, T17, T18, U13, U14, U15, U16, U17, U18, V13, V14, V15, V16, V17, V18 GNDP AR20, A21 R28, T3 63 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Power Supply and NC Connections1 (Continued) Signal NC 2 680-Ball fpBGA3 A3, B29, AW3, AV3, AW11, AV11, AV29, AW29, AW37, B3, AV37, C39, C38, AU39, AU38, AJ39, AJ38, N38, N39, C2, C1, AU1, AU2, AJ2, AJ1, N2, N1, B11, A11, A37, B37, A29 900-Ball fpBGA3 LFX500: A8, A9, A10, A11, A19, A20, A21, A22, B8, B9, B10, B11, B19, B20, B21, B22, C1, C2, C11, C12, C19, C20, C23, D3, D10, D11, D12, D19, D20, D21, D22, D23, E3, E5, E6, E10, E11, E12, E21, E22, E25, E26, E28, E29, E30, F1, F2, F6, F9, F10, F11, F12, F21, F22, F25, F26, F29, F30, G1, G2, G3, G4, G7, G8, G9, G10, G11, G12, G14, G15, G16, G17, G19, G20, G21, G22, G23, G24, G25, G26, G27, G28, G29, G30, H1, H2, H3, H4, H5, H6, H7, H8, H9, H10, H11, H12, H13, H14, H15, H16, H17, H18, H19, H20, H21, H22, H23, H24, H27, H28, H29, H30, J1, J2, J4, J5, J6, J7, J8, J9, J10, J11, J12, J13, J14, J15, J16, J17, J18, J19, J20, J21, J22, J23, J24, J25, J26, J27, K6, K7, K8, K9, K10, K12, K13, K14, K15, K16, K17, K18, K19, K21, K22, K23, K24, K25, L7, L8, L9, L22, L23, L24, M7, M8, M9, M10, M21, M22, M23, M24, N8, N9, N10, N21, N22, N23, P7, P8, P9, P10, P21, P22, P23, P24, R8, R9, R10, R21, R22, R23, R24, R25, T6, T7, T8, T9, T10, T21, T22, T23, T24, T25, U7, U8, U9, U10, U21, U22, U23, U24, V8, V9, V10, V21, V22, V23, W7, W8, W9, W10, W21, W22, W23, W24, W25, W26, Y3, Y4, Y5, Y6, Y7, Y8, Y9, Y22, Y23, Y24, Y25, Y26, Y27, Y28, AA4, AA5, AA6, AA7, AA8, AA9, AA10, AA12, AA13, AA14, AA15, AA16, AA17, AA18, AA19, AA21, AA22, AA23, AA24, AA25, AA26, AA27, AB1, AB2, AB4, AB5, AB6, AB7, AB8, AB9, AB10, AB11, AB12, AB13, AB14, AB15, AB16, AB17, AB18, AB19, AB20, AB21, AB22, AB23, AB24, AB25, AB26, AB27, AC1, AC2, AC3, AC4, AC5, AC6, AC7, AC8, AC9, AC10, AC11, AC12, AC13, AC14, AC15, AC16, AC17’ AC18’ AC19, AC20, AC21, AC22, AC23, AC24, AC27, AC28, AC29, AC30, AD1, AD2, AD7, AD8, AD9, AD10, AD11, AD12, AD14, AD15, AD16, AD17, AD19, AD20, AD21, AD22, AD23, AD24, AD29, AD30, AE6, AE9, AE10, AE11, AE12, AE19, AE20, AE21, AE22, AE25, AE29, AE30, AF5, AF6, AF10, AF11, AF12, AF19, AF20, AF21, AF22, AF25, AF26, AG10, AG11, AG12, AG19, AG20, AG21, AG22, AH11, AH12, AH19, AH20, AJ8, AJ9, AJ10, AJ11, AJ20, AJ21, AJ22, AK8, AK9, AK10, AK11, AK20, AK21, AK22 LFX1200: AA22, AA23, AA24, AA25, AB23, AC24, T21, T22, T23, T24, T25, U21, U22, U23, U24, V21, V22, V23, W21, W22, W23, W24, Y22, Y23, Y24, AA16, AA17, AA18, AA19, AA21, AB16, AB17, AB18, AB19, AB20, AB21, AB22, AC16, AC17, AC18, AC19, AC20, AC21, AC22, AC23, AD16, AD17, AD19, AD20, AD22, AD23, AD24, AE22, AE25, AF25, AF26, AA10, AA12, AA13, AA14, AA15, AB10, AB11, AB12, AB13, AB14, AB15, AB9, AC10, AC11, AC12, AC13, AC14, AC15, AC8, AC9, AD11, AD12, AD14, AD15, AD7, AD8, AD9, AE6, AE9, AF5, AF6, H24, J23, K22, K23, K24, K25, L22, L23, L24, M21, M22, M23, M24, N21, N22, N23, P21, P22, P23, P24, R21, R22, R23, R24, R25, AA6, AA7, AA8, AA9, AB8, AC7, T10, T6, T7, T8, T9, U10, U7, U8, U9, V10, V8, V9, W10, W7, W8, W9, Y7, Y8, Y9, H5, H6, H7, J8, K6, K7, K8, K9, L7, L8, L9, M10, M7, M8, M9, N10, N8, N9, P10, P7, P8, P9, R10, R8, R9, E25, E26, F22, F25, G16, G17, G19, G20, G22, G23, G24, H16, H17, H18, H19, H20, H21, H22, H23, J16, J17, J18, J19, J20, J21, J22, K16, K17, K18, K19, K21, E5, E6, F6, F9, G11, G12, G14, G15, G7, G8, G9, H10, H11, H12, H13, H14, H15, H8, H9, J10, J11, J12, J13, J14, J15, J9, K10, K12, K13, K14, K15 1. All grounds must be electrically connected at the board level. 2. NC pins should not be connected to any active signals, VCC or GND. 3. Balls for GND, VCC and VCCOx are connected within the substrate to their respective common signals. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally. 64 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 256-Ball fpBGA LFX200 256-fpBGA Ball LFX125 Signal Name Second Function LVDS Pair/ sysHSI Reserved2 Signal Name Second Function LVDS Pair/ sysHSI Reserved2 C2 BK0_IO2 HSI0A_SOUTP 1P/HSI0 BK0_IO0 HSI0A_SOUTP 0P - GND (Bank 0) - - - - - D2 BK0_IO3 HSI0A_SOUTN 1N/HSI0 BK0_IO1 HSI0A_SOUTN 0N B1 BK0_IO6 HSI0A_SINP 3P/HSI0 BK0_IO4 HSI0A_SINP 2P/HSI0 - - - - GND (Bank 0) - - C1 BK0_IO7 HSI0A_SINN 3N/HSI0 BK0_IO5 HSI0A_SINN 2N/HSI0 D3 BK0_IO8 - 4P/HSI0 BK0_IO6 - 3P/HSI0 E3 BK0_IO9 VREF0 4N/HSI0 BK0_IO7 VREF0 3N/HSI0 D1 BK0_IO10 HSI0B_SOUTP 5P/HSI0 BK0_IO8 HSI0B_SOUTP 4P/HSI0 - GND (Bank 0) - - - - - E1 BK0_IO11 HSI0B_SOUTN 5N/HSI0 BK0_IO9 HSI0B_SOUTN 4N/HSI0 E2 BK0_IO12 - 6P/HSI0 BK0_IO10 - 5P/HSI0 F2 BK0_IO13 - 6N/HSI0 BK0_IO11 - 5N/HSI0 F1 BK0_IO14 HSI0B_SINP 7P/HSI0 BK0_IO12 HSI0B_SINP 6P/HSI0 - - - - GND (Bank 0) - - G1 BK0_IO15 HSI0B_SINN 7N/HSI0 BK0_IO13 HSI0B_SINN 6N/HSI0 F3 BK0_IO18 PLL_FBK0 9P BK0_IO14 PLL_FBK0 7P/HSI0 - GND (Bank 0) - - - - - G2 BK0_IO19 PLL_RST1 9N BK0_IO15 PLL_RST1 7N/HSI0 E4 BK0_IO20 - 10P BK0_IO16 - 8P/HSI0 F4 BK0_IO21 PLL_FBK1 10N BK0_IO17 PLL_FBK1 8N/HSI0 H1 BK0_IO22 PLL_RST0 11P BK0_IO18 PLL_RST0 9P - - - - GND (Bank 0) - - J1 BK0_IO23 - 11N BK0_IO19 - 9N H2 BK0_IO24 CLK_OUT0 12P BK0_IO20 CLK_OUT0 10P G3 BK0_IO25 CLK_OUT1 12N BK0_IO21 CLK_OUT1 10N - GND (Bank 0) - - - - - G4 GCLK0 - LVDS Pair0P GCLK0 - LVDS Pair0P H4 GCLK1 - LVDS Pair0N GCLK1 - LVDS Pair0N H3 VCCP0 - - VCCP0 - - J4 GNDP0 - - GNDP0 - - J2 GCLK2 - LVDS Pair1P GCLK2 - LVDS Pair1P J3 GCLK3 - LVDS Pair1N GCLK3 - LVDS Pair1N - GND (Bank 1) - - - - - H5 BK1_IO0 CLK_OUT2 13P BK1_IO0 CLK_OUT2 11P J5 BK1_IO1 CLK_OUT3 13N BK1_IO1 CLK_OUT3 11N K1 BK1_IO2 SS_CLKOUT0P 14P BK1_IO2 SS_CLKOUT0P 12P - - - - GND (Bank 1) - - L1 BK1_IO3 SS_CLKOUT0N 14N BK1_IO3 SS_CLKOUT0N 12N K4 BK1_IO4 PLL_FBK2 15P BK1_IO4 PLL_FBK2 13P L4 BK1_IO5 PLL_FBK3 15N BK1_IO5 PLL_FBK3 13N K3 BK1_IO6 SS_CLKIN0P 16P BK1_IO6 SS_CLKIN0P 14P 65 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 256-Ball fpBGA (Cont.) LFX200 LFX125 256-fpBGA Ball Signal Name Second Function LVDS Pair/ sysHSI Reserved2 Signal Name Second Function LVDS Pair/ sysHSI Reserved2 - GND (Bank 1) - - - - - L3 BK1_IO7 SS_CLKIN0N 16N BK1_IO7 SS_CLKIN0N 14N K2 BK1_IO8 - 17P BK1_IO8 - 15P - - - - GND (Bank 1) - - L2 BK1_IO9 - 17N BK1_IO9 - 15N M1 BK1_IO10 HSI1A_SOUTP 18P/HSI1 BK1_IO10 - 16P N1 BK1_IO11 HSI1A_SOUTN 18N/HSI1 BK1_IO11 - 16N M3 BK1_IO12 PLL_RST2 19P/HSI1 BK1_IO12 PLL_RST2 17P M4 BK1_IO13 PLL_RST3 19N/HSI1 BK1_IO13 PLL_RST3 17N - GND (Bank 1) - - - - - M2 BK1_IO161 VREF1 - BK1_IO141 VREF1 - P1 BK1_IO18 HSI1B_SOUTP 22P/HSI1 BK1_IO16 - 19P - - - - GND (Bank 1) - - R1 BK1_IO19 HSI1B_SOUTN 22N/HSI1 BK1_IO17 - 19N N3 BK1_IO201 - - BK1_IO181 - - N2 BK1_IO22 HSI1B_SINP 24P/HSI1 BK1_IO20 - 21P - GND (Bank 1) - - - - - P2 BK1_IO23 HSI1B_SINN 24N/HSI1 BK1_IO21 - 21N P4 TCK - - TCK - - T2 TMS - - TMS - - T3 TOE - - TOE - - R3 BK2_IO0 - 26P BK2_IO0 - 22P R4 BK2_IO1 - 26N BK2_IO1 - 22N N5 BK2_IO2 - 27P BK2_IO2 - 23P - GND (Bank 2) - - - - - P5 BK2_IO3 - 27N BK2_IO3 - 23N - - - - GND (Bank 2) - - T4 BK2_IO6 - 29P BK2_IO6 - 25P T5 BK2_IO7 - 29N BK2_IO7 - 25N N6 BK2_IO8 - 30P BK2_IO8 - 26P P6 BK2_IO9 VREF2 30N BK2_IO9 VREF2 26N R5 BK2_IO10 - 31P BK2_IO10 - 27P - GND (Bank 2) - - - - - R6 BK2_IO11 - 31N BK2_IO11 - 27N N7 BK2_IO12 - 32P BK2_IO12 - 28P - - - - GND (Bank 2) - - P7 BK2_IO13 - 32N BK2_IO13 - 28N T6 BK2_IO14 - 33P BK2_IO14 - 29P T7 BK2_IO15 - 33N BK2_IO15 - 29N M8 BK2_IO16 - 34P BK2_IO16 - 30P M9 BK2_IO17 - 34N BK2_IO17 - 30N R7 BK2_IO18 - 35P BK2_IO18 - 31P 66 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 256-Ball fpBGA (Cont.) LFX200 LFX125 256-fpBGA Ball Signal Name Second Function LVDS Pair/ sysHSI Reserved2 Signal Name Second Function LVDS Pair/ sysHSI Reserved2 - GND (Bank 2) - - GND (Bank 2) - - R8 BK2_IO19 - 35N BK2_IO19 - 31N N8 BK2_IO20 - 36P BK2_IO20 - 32P P8 BK2_IO21 - 36N BK2_IO21 - 32N - GND (Bank 2) - - - - - - GND (Bank 3) - - - - - T8 BK3_IO0 - 39P BK3_IO0 - 33P T9 BK3_IO1 - 39N BK3_IO1 - 33N R9 BK3_IO2 - 40P BK3_IO2 - 34P - - - - GND (Bank 3) - - R10 BK3_IO3 - 40N BK3_IO3 - 34N P9 BK3_IO4 - 41P BK3_IO4 - 35P N9 BK3_IO5 - 41N BK3_IO5 - 35N 36P T10 BK3_IO6 - 42P BK3_IO6 - - GND (Bank 3) - - - - - T11 BK3_IO7 - 42N BK3_IO7 - 36N P10 BK3_IO8 - 43P BK3_IO8 - 37P - - - - GND (Bank 3) - - N10 BK3_IO9 - 43N BK3_IO9 - 37N R11 BK3_IO14 - 46P BK3_IO10 - 38P - GND (Bank 3) - - - - - R12 BK3_IO15 - 46N BK3_IO11 - 38N P11 BK3_IO16 VREF3 47P BK3_IO12 VREF3 39P N11 BK3_IO17 - 47N BK3_IO13 - 39N T12 BK3_IO18 - 48P BK3_IO14 - 40P T13 BK3_IO19 - 48N BK3_IO15 - 40N R13 BK3_IO20 - 49P BK3_IO16 - 41P - - - - GND (Bank 3) - - R14 BK3_IO21 - 49N BK3_IO17 - 41N P12 BK3_IO22 - 50P BK3_IO18 - 42P - GND (Bank 3) - - - - - N12 BK3_IO23 - 50N BK3_IO19 - 42N T14 GSR - - GSR - - T15 DXP - - DXP - - P13 DXN - - DXN - - P15 BK4_IO0 - 52P/HSI2 BK4_IO0 - 44P N14 BK4_IO1 - 52N/HSI2 BK4_IO1 - 44N R16 BK4_IO2 HSI2A_SINP 53P/HSI2 BK4_IO2 - 45P - GND (Bank 4) - - - - - P16 BK4_IO3 HSI2A_SINN 53N/HSI2 BK4_IO3 - 45N N15 BK4_IO4 - 54P/HSI2 BK4_IO4 - 46P - - - - GND (Bank 4) - - 67 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 256-Ball fpBGA (Cont.) LFX200 LFX125 256-fpBGA Ball Signal Name Second Function LVDS Pair/ sysHSI Reserved2 Signal Name Second Function LVDS Pair/ sysHSI Reserved2 M15 BK4_IO5 - 54N/HSI2 BK4_IO5 - 46N M14 BK4_IO8 - 56P/HSI2 BK4_IO6 - 47P M13 BK4_IO9 VREF4 56N/HSI2 BK4_IO7 VREF4 47N - GND (Bank 4) - - - - - L13 BK4_IO12 PLL_RST4 58P/HSI2 BK4_IO8 PLL_RST4 48P L14 BK4_IO13 PLL_RST5 58N/HSI2 BK4_IO9 PLL_RST5 48N N16 BK4_IO14 HSI2B_SOUTP 59P/HSI2 BK4_IO10 - 49P M16 BK4_IO15 HSI2B_SOUTN 59N/HSI2 BK4_IO11 - 49N - - - - GND (Bank 4) - - L15 BK4_IO18 SS_CLKIN1P 61P BK4_IO14 SS_CLKIN1P 51P - GND (Bank 4) - - - - - K15 BK4_IO19 SS_CLKIN1N 61N BK4_IO15 SS_CLKIN1N 51N K14 BK4_IO20 PLL_FBK4 62P BK4_IO16 PLL_FBK4 52P K13 BK4_IO21 PLL_FBK5 62N BK4_IO17 PLL_FBK5 52N L16 BK4_IO22 SS_CLKOUT1P 63P BK4_IO18 SS_CLKOUT1P 53P - - - - GND (Bank 4) - - K16 BK4_IO23 SS_CLKOUT1N 63N BK4_IO19 SS_CLKOUT1N 53N J13 BK4_IO24 CLK_OUT4 64P BK4_IO20 CLK_OUT4 54P J12 BK4_IO25 CLK_OUT5 64N BK4_IO21 CLK_OUT5 54N - GND (Bank 4) - - - - - J14 GCLK4 - LVDS Pair2P GCLK4 - LVDS Pair2P H14 GCLK5 - LVDS Pair2N GCLK5 - LVDS Pair2N J15 VCCP1 - - VCCP1 - - H15 GNDP1 - - GNDP1 - - J16 GCLK6 - LVDS Pair3P GCLK6 - LVDS Pair3P H16 GCLK7 - LVDS Pair3N GCLK7 - LVDS Pair3N - GND (Bank 5) - - - - - H12 BK5_IO0 CLK_OUT6 65P BK5_IO0 CLK_OUT6 55P H13 BK5_IO1 CLK_OUT7 65N BK5_IO1 CLK_OUT7 55N G14 BK5_IO2 - 66P BK5_IO2 - 56P - - - - GND (Bank 5) - - G15 BK5_IO3 PLL_RST7 66N BK5_IO3 PLL_RST7 56N G13 BK5_IO6 PLL_RST6 68P BK5_IO6 PLL_RST6 58P/HSI1 - GND (Bank 5) - - - - - F13 BK5_IO7 PLL_FBK7 68N BK5_IO7 PLL_FBK7 58N/HSI1 G16 BK5_IO10 HSI3A_SINP 70P BK5_IO8 HSI1A_SINP 59P/HSI1 - - - - GND (Bank 5) - - F16 BK5_IO11 HSI3A_SINN 70N/HSI3 BK5_IO9 HSI1A-SINN 59N/HSI1 F14 BK5_IO12 - 71P/HSI3 BK5_IO10 - 60P/HSI1 F15 BK5_IO13 - 71N/HSI3 BK5_IO11 - 60N/HSI1 E16 BK5_IO14 HSI3A_SOUTP 72P/HSI3 BK5_IO12 HSI1A_SOUTP 61P/HSI1 - GND (Bank 5) - - - - - 68 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 256-Ball fpBGA (Cont.) LFX200 LFX125 256-fpBGA Ball Signal Name Second Function LVDS Pair/ sysHSI Reserved2 Signal Name Second Function LVDS Pair/ sysHSI Reserved2 D16 BK5_IO15 HSI3A_SOUTN 72N/HSI3 BK5_IO13 HSI1A_SOUTN 61N/HSI1 E13 BK5_IO16 VREF5 73P/HSI3 BK5_IO14 VREF5 62P/HSI1 E14 BK5_IO17 - 73N/HSI3 BK5_IO15 - 62N/HSI1 E15 BK5_IO18 HSI3B_SINP 74P/HSI3 BK5_IO16 HSI1B_SINP 63P/HSI1 - - - - GND (Bank 5) - - D15 BK5_IO19 HSI3B_SINN 74N/HSI3 BK5_IO17 HSI1B_SINN 63N/HSI1 C16 BK5_IO22 HSI3B_SOUTP 76P/HSI3 BK5_IO20 HSI1B_SOUTP 65P/HSI1 - GND (Bank 5) - - - - - B16 BK5_IO23 HSI3B_SOUTN 76N/HSI3 BK5_IO21 HSI1B_SOUTN 65N/HSI1 D14 BK5_IO24 - 77P/HSI3 BK5_IO18 - 64P/HSI1 C15 BK5_IO25 - 77N/HSI3 BK5_IO19 - 64N/HSI1 C13 CFG0 - - CFG0 - - A15 DONE - - DONE - - A14 PROGRAMb - - PROGRAMb - - D12 BK6_IO0 INITb 78P BK6_IO0 INITb 66P C12 BK6_IO1 CCLK 78N BK6_IO1 CCLK 66N B14 BK6_IO2 - 79P BK6_IO2 - 67P - GND (Bank 6) - - - - - B13 BK6_IO3 - 79N BK6_IO3 - 67N A13 BK6_IO4 CSb 80P BK6_IO4 CSb 68P - - - - GND (Bank 6) - - A12 BK6_IO5 Read 80N BK6_IO5 READ 68N D11 BK6_IO6 DATA7 81P BK6_IO6 DATA7 69P C11 BK6_IO7 DATA6 81N BK6_IO7 DATA6 69N B12 BK6_IO8 - 82P BK6_IO8 - 70P B11 BK6_IO9 VREF6 82N BK6_IO9 VREF6 70N D10 BK6_IO10 DATA5 83P BK6_IO10 DATA5 71P - GND (Bank 6) - - - - - C10 BK6_IO11 DATA4 83N BK6_IO11 DATA4 71N - - - - GND (Bank 6) - - A11 BK6_IO14 DATA3 85P BK6_IO14 DATA3 73P A10 BK6_IO15 DATA2 85N BK6_IO15 DATA2 73N D9 BK6_IO16 - 86P BK6_IO16 - 74P C9 BK6_IO17 - 86N BK6_IO17 - 74N B10 BK6_IO18 DATA1 87P BK6_IO18 DATA1 75P - GND (Bank 6) - - GND (Bank 6) - - B9 BK6_IO19 DATA0 87N BK6_IO19 DATA0 75N E9 BK6_IO20 - 88P BK6_IO20 - 76P E8 BK6_IO21 - 88N BK6_IO21 - 76N - GND (Bank 6) - - - - - - GND (Bank 7) - - - - - D8 BK7_IO0 - 91P BK7_IO0 - 77P 69 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 256-Ball fpBGA (Cont.) LFX200 LFX125 256-fpBGA Ball Signal Name Second Function LVDS Pair/ sysHSI Reserved2 Signal Name Second Function LVDS Pair/ sysHSI Reserved2 C8 BK7_IO1 - 91N BK7_IO1 - 77N B8 BK7_IO2 - 92P BK7_IO2 - 78P B7 BK7_IO3 - 92N BK7_IO3 - 78N A9 BK7_IO6 - 94P BK7_IO4 - 79P - GND (Bank 7) - - - - - A8 BK7_IO7 - 94N BK7_IO5 - 79N C7 BK7_IO10 - 96P BK7_IO6 - 80P D7 BK7_IO11 - 96N BK7_IO7 - 80N D6 BK7_IO12 - 97P BK7_IO8 - 81P - - - - GND (Bank 7) - - C6 BK7_IO13 - 97N BK7_IO9 - 81N B6 BK7_IO14 - 98P BK7_IO10 - 82P - GND (Bank 7) - - - - - B5 BK7_IO15 - 98N BK7_IO11 - 82N A7 BK7_IO16 VREF7 99P BK7_IO12 VREF7 83P A6 BK7_IO17 - 99N BK7_IO13 - 83N D5 BK7_IO18 - 100P BK7_IO14 - 84P C5 BK7_IO19 - 100N BK7_IO15 - 84N A5 BK7_IO20 - 101P BK7_IO16 - 85P - - - - GND (Bank 7) - - A4 BK7_IO21 - 101N BK7_IO17 - 85N B4 BK7_IO22 - 102P BK7_IO18 - 86P - GND (Bank 7) - - - - - B3 BK7_IO23 - 102N BK7_IO19 - 86N A3 TDO - - TDO - - A2 VCCJ - - VCCJ - - C4 TDI - - TDI - - 1. Not available for differential pairs. 2. If a sysHSI Block is used, the indicated sysHSI reserved pins are unavailable for general purpose I/O use. 70 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 516-Ball fpBGA LFX500 516-Ball BGA Ball Signal Name Second Function LFX200 LVDS Pair/ sysHSI Reserved1 Signal Name Second Function LFX125 LVDS Pair/ sysHSI Reserved1 Signal Name Second Function LVDS Pair/ sysHSI Reserved1 - E4 BK0_IO0 - 0P BK0_IO0 - 0P/HSI0 NC - D3 BK0_IO1 - 0N BK0_IO1 - 0N/HSI0 NC - - E3 BK0_IO2 HSI0A_SOUTP 1P/HSI0 BK0_IO2 HSI0A_SOUTP 1P/HSI0 BK0_IO0 HSI0A_SOUTP 0P - GND (Bank 0) - - GND (Bank 0) - - - - - F3 BK0_IO3 HSI0A_SOUTN 1N/HSI0 BK0_IO3 HSI0A_SOUTN 1N/HSI0 BK0_IO1 HSI0A_SOUTN 0N C2 BK0_IO4 - 2P/HSI0 BK0_IO4 - 2P/HSI0 BK0_IO2 - 1P/HSI0 B1 BK0_IO5 - 2N/HSI0 BK0_IO5 - 2N/HSI0 BK0_IO3 - 1N/HSI0 G4 BK0_IO6 HSI0A_SINP 3P/HSI0 BK0_IO6 HSI0A_SINP 3P/HSI0 BK0_IO4 HSI0A_SINP 2P/HSI0 - - - - - - - GND (Bank 0) - - G3 BK0_IO7 HSI0A_SINN 3N/HSI0 BK0_IO7 HSI0A_SINN 3N/HSI0 BK0_IO5 HSI0A_SINN 2N/HSI0 C1 BK0_IO8 - 4P/HSI0 BK0_IO8 - 4P/HSI0 BK0_IO6 - 3P/HSI0 D2 BK0_IO9 VREF0 4N/HSI0 BK0_IO9 VREF0 4N/HSI0 BK0_IO7 VREF0 3N/HSI0 H4 BK0_IO10 HSI0B_SOUTP 5P/HSI0 BK0_IO10 HSI0B_SOUTP 5P/HSI0 BK0_IO8 HSI0B_SOUTP 4P/HSI0 - GND (Bank 0) - - GND (Bank 0) - - - - - H3 BK0_IO11 HSI0B_SOUTN 5N/HSI0 BK0_IO11 HSI0B_SOUTN 5N/HSI0 BK0_IO9 HSI0B_SOUTN 4N/HSI0 D1 BK0_IO12 - 6P/HSI0 BK0_IO12 6P/HSI0 BK0_IO10 - 5P/HSI0 E1 BK0_IO13 - 6N/HSI0 BK0_IO13 - 6N/HSI0 BK0_IO11 - 5N/HSI0 E2 BK0_IO14 HSI0B_SINP 7P/HSI0 BK0_IO14 HSI0B_SINP 7P/HSI0 BK0_IO12 HSI0B_SINP 6P/HSI0 - - - - - - - GND (Bank 0) - - F2 BK0_IO15 HSI0B_SINN 7N/HSI0 BK0_IO15 HSI0B_SINN 7N/HSI0 BK0_IO13 HSI0B_SINN 6N/HSI0 G2 BK0_IO16 - 8P/HSI0 NC - - NC - - F1 BK0_IO17 - 8N/HSI0 NC - - NC - - J3 BK0_IO18 HSI1A_SOUTP 9P NC - - NC - - - GND (Bank 0) - - - - - - - - K3 BK0_IO19 HSI1A_SOUTN 9N NC - - NC - - K4 BK0_IO20 - 10P NC - - NC - - L4 BK0_IO21 - 10N NC - - NC - - H2 BK0_IO22 HSI1A_SINP 11P NC - - NC - - J2 BK0_IO23 HSI1A_SINN 11N NC - - NC - - G1 BK0_IO24 - 12P NC - - NC - - H1 BK0_IO25 - 12N NC - - NC - - L3 BK0_IO26 HSI1B_SOUTP 13P NC - - NC - - - GND (Bank 0) - - - - - - - - M3 BK0_IO27 HSI1B_SOUTN 13N NC - - NC - - K2 BK0_IO28 - 14P NC - - NC - - L2 BK0_IO29 - 14N NC - - NC - - K1 BK0_IO30 HSI1B_SINP 15P NC - - NC - - L1 BK0_IO31 HSI1B_SINN 15N NC - - NC - - M2 BK0_IO32 - 16P BK0_IO16 - 8P NC - - M1 BK0_IO33 - 16N BK0_IO17 - 8N NC - - N3 BK0_IO34 PLL_FBK0 17P BK0_IO18 PLL_FBK0 9P BK0_IO14 PLL_FBK0 7P/HSI0 - GND (Bank 0) - - GND (Bank 0) - - - - - N4 BK0_IO35 PLL_RST1 17N BK0_IO19 PLL_RST1 9N BK0_IO15 PLL_RST1 7N/HSI0 N2 BK0_IO36 - 18P BK0_IO20 - 10P BK0_IO16 - 8P/HSI0 N1 BK0_IO37 PLL_FBK1 18N BK0_IO21 PLL_FBK1 10N BK0_IO17 PLL_FBK1 8N/HSI0 P1 BK0_IO38 PLL_RST0 19P BK0_IO22 PLL_RST0 11P BK0_IO18 PLL_RST0 9P - - - - - - - GND (Bank 0) - - R1 BK0_IO39 - 19N BK0_IO23 - 11N BK0_IO19 - 9N P3 BK0_IO40 CLK_OUT0 20P BK0_IO24 CLK_OUT0 12P BK0_IO20 CLK_OUT0 10P - GND (Bank 0) - - - - - - - - P2 BK0_IO41 CLK_OUT1 20N BK0_IO25 CLK_OUT1 12N BK0_IO21 CLK_OUT1 10N 71 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.) LFX500 LFX200 LVDS Pair/ sysHSI Reserved1 516-Ball BGA Ball Signal Name Second Function - - - - R2 GCLK0 - LVDS Pair0P LFX125 Signal Name Second Function LVDS Pair/ sysHSI Reserved1 Signal Name Second Function LVDS Pair/ sysHSI Reserved1 GND (Bank 0) - - - - - GCLK0 - LVDS Pair0P GCLK0 - LVDS Pair0P R3 GCLK1 - LVDS Pair0N GCLK1 - LVDS Pair0N GCLK1 - LVDS Pair0N R4 VCCP0 - - VCCP0 - - VCCP0 - - T4 GNDP0 - - GNDP0 - - GNDP0 - - T3 GCLK2 - LVDS Pair1P GCLK2 - LVDS Pair1P GCLK2 - LVDS Pair1P T2 GCLK3 - LVDS Pair1N GCLK3 - LVDS Pair1N GCLK3 - LVDS Pair1N - - - - GND (Bank 1) - - - - - T1 BK1_IO0 CLK_OUT2 21P BK1_IO0 CLK_OUT2 13P BK1_IO0 CLK_OUT2 11P - GND (Bank 1) - - - - - - - - U1 BK1_IO1 CLK_OUT3 21N BK1_IO1 CLK_OUT3 13N BK1_IO1 CLK_OUT3 11N U2 BK1_IO2 SS_CLKOUT0P 22P BK1_IO2 SS_CLKOUT0P 14P BK1_IO2 SS_CLKOUT0P 12P - - - - - - - GND (Bank 1) - - U3 BK1_IO3 SS_CLKOUT0N 22N BK1_IO3 SS_CLKOUT0 N 14N BK1_IO3 SS_CLKOUT0 N 12N V1 BK1_IO4 PLL_FBK2 23P BK1_IO4 PLL_FBK2 15P BK1_IO4 PLL_FBK2 13P V2 BK1_IO5 PLL_FBK3 23N BK1_IO5 PLL_FBK3 15N BK1_IO5 PLL_FBK3 13N V3 BK1_IO6 - 24P NC - - NC - - - GND (Bank 1) - - - - - - - - V4 BK1_IO7 - 24N NC - - NC - - W1 BK1_IO8 - 25P NC - - NC - - Y1 BK1_IO9 - 25N NC - - NC - - W2 BK1_IO10 SS_CLKINOP 26P BK1_IO6 SS_CLKIN0P 16P BK1_IO6 SS_CLKIN0P 14P - - - - GND (Bank 1) - - - - - W3 BK1_IO11 SS_CLKINON 26N BK1_IO7 SS_CLKIN0N 16N BK1_IO7 SS_CLKIN0N 14N Y2 BK1_IO12 - 27P BK1_IO8 - 17P BK1_IO8 - 15P - - - - - - - GND (Bank 1) - - Y4 BK1_IO13 - 27N BK1_IO9 - 17N BK1_IO9 - 15N Y3 BK1_IO14 - 28P NC - - NC - - - GND (Bank 1) - - - - - - - - AA1 BK1_IO15 - 28N NC - - NC - - AA2 BK1_IO16 - 29P NC - - NC - - AA3 BK1_IO17 - 29N NC - - NC - - AB2 BK1_IO18 HSI2A_SOUTP 30P BK1_IO10 HSI1A_SOUTP 18P/HSI1 BK1_IO10 - 16P AC2 BK1_IO19 HSI2A_SOUTN 30N BK1_IO11 HSI1A_SOUTN 18N/HSI1 BK1_IO11 - 16N AB3 BK1_IO20 PLL_RST2 31P BK1_IO12 PLL_RST2 19P/HSI1 BK1_IO12 PLL_RST2 17P AA4 BK1_IO21 PLL_RST3 31N BK1_IO13 PLL_RST3 19N/HSI1 BK1_IO13 PLL_RST3 17N AC1 BK1_IO22 HSI2A_SINP 32P BK1_IO14 HSI1A_SINP 20P/HSI1 NC - - - GND (Bank 1) - - GND (Bank 1) - - - - - AD1 BK1_IO23 HSI2A_SINN 32N BK1_IO15 HSI1A_SINN 20N/HSI1 NC - - AE1 BK1_IO24 VREF1 33P/HSI2 BK1_IO16 VREF1 21P/HSI1 BK1_IO14 VREF1 18P AF1 BK1_IO25 - 33N/HSI2 BK1_IO17 - 21N/HSI1 BK1_IO15 - 18N AC3 BK1_IO26 HSI2B_SOUTP 34P/HSI2 BK1_IO18 HSI1B_SOUTP 22P/HSI1 BK1_IO16 - 19P - - - - - - - GND (Bank 1) - - AC4 BK1_IO27 HSI2B_SOUTN 34N/HSI2 BK1_IO19 HSI1B_SOUTN 22N/HSI1 BK1_IO17 - 19N AD2 BK1_IO28 - 35P/HSI2 BK1_IO20 - 23P/HSI1 BK1_IO18 - 20P AD3 BK1_IO29 - 35N/HSI2 BK1_IO21 - 23N/HSI1 BK1_IO19 - 20N AE2 BK1_IO30 HSI2B_SINP 36P/HSI2 BK1_IO22 HSI1B_SINP 24P/HSI1 BK1_IO20 - 21P - GND (Bank 1) - - GND (Bank 1) - - - - - AF2 BK1_IO31 HSI2B_SINN 36N/HSI2 BK1_IO23 HSI1B_SINN 24N/HSI1 BK1_IO21 - 21N AD4 BK1_IO32 - 37P/HSI2 NC - - NC - - 72 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.) LFX500 LFX200 LVDS Pair/ sysHSI Reserved1 LFX125 LVDS Pair/ sysHSI Reserved1 Signal Name Second Function LVDS Pair/ sysHSI Reserved1 NC - - NC - - - NC - - - - NC - - NC - - NC - - 40P/HSI2 NC - - NC - - - - - - - - - - 516-Ball BGA Ball Signal Name Second Function Signal Name Second Function AE3 BK1_IO33 - 37N/HSI2 NC - - AG1 BK1_IO34 - 38P/HSI2 NC - - AH1 BK1_IO35 - 38N/HSI2 NC - AG2 BK1_IO36 - 39P/HSI2 NC AF3 BK1_IO37 - 39N/HSI2 AJ1 BK1_IO38 - - GND (Bank 1) AH2 BK1_IO39 - 40N/HSI2 NC - - NC - - AG3 BK1_IO40 - 41P BK1_IO24 - 25P/HSI1 NC - - AF4 BK1_IO41 - 41N BK1_IO25 - 25N/HSI1 NC - - AK2 TCK - - TCK - - TCK - - AJ3 TMS - - TMS - - TMS - AG5 TOE - - TOE - - TOE - - AH4 BK2_IO0 - 42P BK2_IO0 - 26P BK2_IO0 - 22P AK3 BK2_IO1 - 42N BK2_IO1 - 26N BK2_IO1 - 22N AJ4 BK2_IO2 - 43P BK2_IO2 - 27P BK2_IO2 - 23P - GND (Bank 2) - - GND (Bank 2) - - - - - AH5 BK2_IO3 - 43N BK2_IO3 - 27N BK2_IO3 - 23N AK4 BK2_IO4 - 44P BK2_IO4 - 28P BK2_IO4 - 24P - - - - - - - GND (Bank 2) - - AJ5 BK2_IO5 - 44N BK2_IO5 - 28N BK2_IO5 - 24N AG7 BK2_IO6 - 45P BK2_IO6 - 29P BK2_IO6 - 25P AH6 BK2_IO7 - 45N BK2_IO7 - 29N BK2_IO7 - 25N AK5 BK2_IO8 - 46P NC - - NC - - AJ6 BK2_IO9 - 46N NC - - NC - - AG8 BK2_IO10 - 47P NC - - NC - - - GND (Bank 2) - - - - - - - - AH7 BK2_IO11 - 47N NC - - NC - - AK6 BK2_IO12 - 48P NC - - NC - - AJ7 BK2_IO13 - 48N NC - - NC - - AH8 BK2_IO14 - 49P NC - - NC - - AG10 BK2_IO15 - 49N NC - - NC - - AK7 BK2_IO16 - 50P NC - - NC - - AJ8 BK2_IO17 - 50N NC - - NC - - AH9 BK2_IO18 - 51P NC - - NC - - - GND (Bank 2) - - - - - - - AG11 BK2_IO19 - 51N NC - - NC - - AK8 BK2_IO20 - 52P BK2_IO8 - 30P BK2_IO8 - 26P AJ9 BK2_IO21 VREF2 52N BK2_IO9 VREF2 30N BK2_IO9 VREF2 26N AH10 BK2_IO22 - 53P BK2_IO10 - 31P BK2_IO10 - 27P - - - - GND (Bank 2) - - - - - AH11 BK2_IO23 - 53N BK2_IO11 - 31N BK2_IO11 - 27N 32P BK2_IO12 - 28P - 32N BK2_IO13 - 28N 29P AJ10 BK2_IO24 - 54P BK2_IO12 AK10 BK2_IO25 - 54N BK2_IO13 AH12 BK2_IO26 - 55P BK2_IO14 - 33P BK2_IO14 - - GND (Bank 2) - - - - - - - - AJ11 BK2_IO27 - 55N BK2_IO15 - 33N BK2_IO15 - 29N AK11 BK2_IO28 - 56P NC - - NC - - AJ12 BK2_IO29 - 56N NC - - NC - - AG13 BK2_IO30 - 57P BK2_IO16 - 34P BK2_IO16 - 30P AH13 BK2_IO31 - 57N BK2_IO17 - 34N BK2_IO17 - 30N 73 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.) LFX500 LFX200 LVDS Pair/ sysHSI Reserved1 LFX125 Signal Name Second Function LVDS Pair/ sysHSI Reserved1 BK2_IO18 - 35P - GND (Bank 2) - - - 58N BK2_IO19 - 35N BK2_IO19 516-Ball BGA Ball Signal Name Second Function AJ13 BK2_IO32 - 58P - - - AK12 BK2_IO33 Second Function LVDS Pair/ sysHSI Reserved1 BK2_IO18 - 31P GND (Bank 2) - - - 31N 32P Signal Name AK13 BK2_IO34 - 59P BK2_IO20 - 36P BK2_IO20 - - GND (Bank 2) - - - - - - - - AH14 BK2_IO35 - 59N BK2_IO21 - 36N BK2_IO21 - 32N AJ14 BK2_IO36 - 60P BK2_IO22 - 37P NC - - AK14 BK2_IO37 - 60N BK2_IO23 - 37N NC - - AG15 BK2_IO38 - 61P BK2_IO24 - 38P NC - - AH15 BK2_IO39 - 61N BK2_IO25 - 38N NC - - AJ15 BK2_IO40 - 62P NC - - NC - - AK15 BK2_IO41 - 62N NC - - NC - - - GND (Bank 2) - - GND (Bank 2) - - - - - - GND (Bank 3) - - GND (Bank 3) - - - - - AK16 BK3_IO0 - 63P BK3_IO0 - 39P BK3_IO0 - 33P 33N AJ16 BK3_IO1 - 63N BK3_IO1 - 39N BK3_IO1 - AH16 BK3_IO2 - 64P BK3_IO2 - 40P BK3_IO2 - 34P AG16 BK3_IO3 - 64N BK3_IO3 - 40N BK3_IO3 - 34N AK17 BK3_IO4 - 65P BK3_IO4 - 41P BK3_IO4 - 35P AJ17 BK3_IO5 - 65N BK3_IO5 - 41N BK3_IO5 - 35N 36P AH17 BK3_IO6 - 66P BK3_IO6 - 42P BK3_IO6 - - GND (Bank 3) - - GND (Bank 3) - - - - - AJ18 BK3_IO7 - 66N BK3_IO7 - 42N BK3_IO7 - 36N AH18 BK3_IO8 - 67P BK3_IO8 - 43P BK3_IO8 - 37P - - - - - - - GND (Bank 3) - - AG18 BK3_IO9 - 67N BK3_IO9 - 43N BK3_IO9 - 37N AK18 BK3_IO10 - 68P BK3_IO10 - 44P BK3_IO10 - 38P AK19 BK3_IO11 - 68N BK3_IO11 - 44N BK3_IO11 - 38N - AJ19 BK3_IO12 - 69P BK3_IO12 AH19 BK3_IO13 - 69N BK3_IO13 45P NC - - 45N NC - - AK20 BK3_IO14 - 70P BK3_IO14 - 46P NC - - - GND (Bank 3) - - GND (Bank 3) - - - - - AJ20 BK3_IO15 - 70N BK3_IO15 - 46N NC - - AH20 BK3_IO16 - 71P NC - - NC - - AG20 BK3_IO17 - 71N NC - - NC - - AK21 BK3_IO18 - 72P NC - - NC - - AJ21 BK3_IO19 - 72N NC - - NC - - AH21 BK3_IO20 VREF3 73P BK3_IO16 VREF3 47P BK3_IO12 VREF3 39P AG21 BK3_IO21 - 73N BK3_IO17 - 47N BK3_IO13 - 39N AJ22 BK3_IO22 - 74P BK3_IO18 - 48P BK3_IO14 - 40P - GND (Bank 3) - - - - - - - - AH22 BK3_IO23 - 74N BK3_IO19 - 48N BK3_IO15 - 40N AK23 BK3_IO24 - 75P NC - - NC - - AJ23 BK3_IO25 - 75N NC - - NC - - AH23 BK3_IO26 - 76P NC - - NC - - AK24 BK3_IO27 - 76N NC - - NC - - AJ24 BK3_IO28 - 77P NC - - NC - - AG23 BK3_IO29 - 77N NC - - NC - - NC AH24 BK3_IO30 - 78P - GND (Bank 3) - - AK25 BK3_IO31 - 78N NC 74 - - NC - - - - - - - - - NC - - Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.) LFX500 LFX200 LVDS Pair/ sysHSI Reserved1 LFX125 LVDS Pair/ sysHSI Reserved1 Signal Name Second Function LVDS Pair/ sysHSI Reserved1 NC - - NC - - 49P BK3_IO16 - 41P 516-Ball BGA Ball Signal Name Second Function Signal Name Second Function AJ25 BK3_IO32 - 79P NC - - AG24 BK3_IO33 - 79N NC - - AK26 BK3_IO34 - 80P BK3_IO20 - - - - - - - - GND (Bank 3) - - AH25 BK3_IO35 - 80N BK3_IO21 - 49N BK3_IO17 - 41N AJ26 BK3_IO36 - 81P BK3_IO22 - 50P BK3_IO18 - 42P - - - - GND (Bank 3) - - - - - AH26 BK3_IO37 - 81N BK3_IO23 - 50N BK3_IO19 - 42N AK27 BK3_IO38 - 82P NC - - NC - - - GND (Bank 3) - - - - - - - - AJ27 BK3_IO39 - 82N NC - - NC - - AG26 BK3_IO40 - 83P BK3_IO24 - 51P BK3_IO20 - 43P AH27 BK3_IO41 - 83N BK3_IO25 - 51N BK3_IO21 - 43N AK28 GSR - - GSR - - GSR - - AJ28 DXP - - DXP - - DXP - - AK29 DXN - - DXN - - DXN - - AH29 BK4_IO0 - 84P BK4_IO0 - 52P/HSI2 BK4_IO0 - 44P AG28 BK4_IO1 - 84N BK4_IO1 - 52N/HSI2 BK4_IO1 - 44N AF27 BK4_IO2 - 85P/HSI3 NC - - NC - - - GND (Bank 4) - - - - - - - - AF28 BK4_IO3 - 85N/HSI3 NC - - NC - - AJ30 BK4_IO4 - 86P/HSI3 NC - - NC - - AH30 BK4_IO5 - 86N/HSI3 NC - - NC - - AG29 BK4_IO6 - 87P/HSI3 NC - - NC - - AF29 BK4_IO7 - 87N/HSI3 NC - - NC - - AE28 BK4_IO8 - 88P/HSI3 NC - - NC - - AD27 BK4_IO9 - 88N/HSI3 NC - - NC - - AG30 BK4_IO10 HSI3A_SINP 89P/HSI3 BK4_IO2 HSI2A_SINP 53P/HSI2 BK4_IO2 - 45P - GND (Bank 4) - - GND (Bank 4) - - - - - AF30 BK4_IO11 HSI3A_SINN 89N/HSI3 BK4_IO3 HSI2A_SINN 53N/HSI2 BK4_IO3 - 45N AD28 BK4_IO12 - 90P/HSI3 BK4_IO4 - 54P/HSI2 BK4_IO4 - 46P - - - - - - - GND (Bank 4) - - AC27 BK4_IO13 - 90N/HSI3 BK4_IO5 - 54N/HSI2 BK4_IO5 - 46N AE29 BK4_IO14 HSI3A_SOUTP 91P/HSI3 BK4_IO6 HSI2A_SOUTP 55P/HSI2 NC - - AE30 BK4_IO15 HSI3A_SOUTN 91N/HSI3 BK4_IO7 HSI2A_SOUTN 55N/HSI2 NC - - AD29 BK4_IO16 - 92P/HSI3 BK4_IO8 - 56P/HSI2 BK4_IO6 - 47P AD30 BK4_IO17 VREF4 92N/HSI3 BK4_IO9 VREF4 56N/HSI2 BK4_IO7 VREF4 47N AC28 BK4_IO18 HSI3B_SINP 93P BK4_IO10 HSI2B_SINP 57P/HSI2 NC - - - GND (Bank 4) - - GND (Bank 4) - - - - - AB28 BK4_IO19 HSI3B_SINN 93N BK4_IO11 HSI2B_SINN 57N/HSI2 NC - - AA27 BK4_IO20 PLL_RST4 94P BK4_IO12 PLL_RST4 58P/HSI2 BK4_IO8 PLL_RST4 48P 48N AB29 BK4_IO21 PLL_RST5 94N BK4_IO13 PLL_RST5 58N/HSI2 BK4_IO9 PLL_RST5 AC29 BK4_IO22 HSI3B_SOUTP 95P BK4_IO14 HSI2B_SOUTP 59P/HSI2 BK4_IO10 - 49P AC30 BK4_IO23 HSI3B_SOUTN 95N BK4_IO15 HSI2B_SOUTN 59N/HSI2 BK4_IO11 - 49N AA28 BK4_IO24 - 96P NC - - NC - - Y27 BK4_IO25 - 96N NC - - NC - - Y28 BK4_IO26 - 97P NC - - NC - - - GND (Bank 4) - - - - - - - - AA29 BK4_IO27 - 97N NC - - NC - - Y29 BK4_IO28 - 98P BK4_IO16 - 60P BK4_IO12 - 50P - - - - - - - GND (Bank 4) - - 75 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.) LFX500 LFX200 LVDS Pair/ sysHSI Reserved1 LFX125 LVDS Pair/ sysHSI Reserved1 Second Function LVDS Pair/ sysHSI Reserved1 Signal Name BK4_IO13 - 50N BK4_IO14 SS_CLKIN1P 51P - - - - 61N BK4_IO15 SS_CLKIN1N 51N 516-Ball BGA Ball Signal Name Second Function Signal Name Second Function AA30 BK4_IO29 - 98N BK4_IO17 - 60N W28 BK4_IO30 SS_CLKIN1P 99P BK4_IO18 SS_CLKIN1P 61P - - - - GND (Bank 4) - W29 BK4_IO31 SS_CLKIN1N 99N BK4_IO19 SS_CLKIN1N Y30 BK4_IO32 - 100P NC - - NC - - W30 BK4_IO33 - 100N NC - - NC - - V27 BK4_IO34 - 101P NC - - NC - - - GND (Bank 4) - - - - - - - - V28 BK4_IO35 - 101N NC - - NC - - V29 BK4_IO36 PLL_FBK4 102P BK4_IO20 PLL_FBK4 62P BK4_IO16 PLL_FBK4 52P 52N V30 BK4_IO37 PLL_FBK5 102N BK4_IO21 PLL_FBK5 62N BK4_IO17 PLL_FBK5 U30 BK4_IO38 SS_CLKOUT1P 103P BK4_IO22 SS_CLKOUT1P 63P BK4_IO18 SS_CLKOUT1P 53P U29 BK4_IO39 SS_CLKOUT1N 103N BK4_IO23 SS_CLKOUT1N 63N BK4_IO19 SS_CLKOUT1N 53N U28 BK4_IO40 CLK_OUT4 104P BK4_IO24 CLK_OUT4 64P BK4_IO20 CLK_OUT4 54P - GND (Bank 4) - - - - - - - - T27 BK4_IO41 CLK_OUT5 104N BK4_IO25 CLK_OUT5 64N BK4_IO21 CLK_OUT5 54N - - - - GND (Bank 4) - - - - - T28 GCLK4 - LVDS Pair2P GCLK4 - LVDS Pair2P GCLK4 - LVDS Pair2P T29 GCLK5 - LVDS Pair2N GCLK5 - LVDS Pair2N GCLK5 - LVDS Pair2N T30 VCCP1 - - VCCP1 - - VCCP1 - - R29 GNDP1 - - GNDP1 - - GNDP1 - - R28 GCLK6 - LVDS Pair3P GCLK6 - LVDS Pair3P GCLK6 - LVDS Pair3P R27 GCLK7 - LVDS Pair3N GCLK7 - LVDS Pair3N GCLK7 - LVDS Pair3N - - - - GND (Bank 5) - - - - - R30 BK5_IO0 CLK_OUT6 105P BK5_IO0 CLK_OUT6 65P BK5_IO0 CLK_OUT6 55P - GND (Bank 5) - - - - - - - - P30 BK5_IO1 CLK_OUT7 105N BK5_IO1 CLK_OUT7 65N BK5_IO1 CLK_OUT7 55N P29 BK5_IO2 - 106P BK5_IO2 - 66P BK5_IO2 - 56P - - - - - - - GND (Bank 5) - - P28 BK5_IO3 PLL_RST7 106N BK5_IO3 PLL_RST7 66N BK5_IO3 PLL_RST7 56N N30 BK5_IO4 PLL_FBK6 107P BK5_IO4 PLL_FBK6 67P BK5_IO4 PLL_FBK6 57P/HSI1 N29 BK5_IO5 - 107N BK5_IO5 - 67N BK5_IO5 - 57N/HSI1 N28 BK5_IO6 PLL-RST6 108P BK5_IO6 PLL_RST6 68P BK5_IO6 PLL_RST6 58P//HSI1 - GND (Bank 5) - - GND (Bank 5) - - - - - N27 BK5_IO7 PLL_FBK7 108N BK5_IO7 PLL_FBK7 68N BK5_IO7 PLL_FBK7 58N/HSI1 M30 BK5_IO8 - 109P/HSI4 BK5_IO8 - 69P NC - - M29 BK5_IO9 - 109N/HSI4 BK5_IO9 - 69N NC - - L30 BK5_IO10 HSI4A_SINP 110P/HSI4 BK5_IO10 HSI3A_SINP 70P/HSI3 BK5_IO8 HSI1A_SINP 59P/HSI1 - - - - - - - GND (Bank 5) - - L29 BK5_IO11 HSI4A_SINN 110N/HSI4 BK5_IO11 HSI3A_SINN 70N/HSI3 BK5_IO9 HSI1A_SINN 59N/HSI1 M28 BK5_IO12 - 111P/HSI4 BK5_IO12 - L28 BK5_IO13 - 111N/HSI4 BK5_IO13 K30 BK5_IO14 HSI4A_SOUTP 112P/HSI4 BK5_IO14 - GND (Bank 5) - - GND (Bank 5) K29 BK5_IO15 HSI4A_SOUTN 112N/HSI4 BK5_IO15 71P/HSI3 BK5_IO10 - 60P/HSI1 71N/HSI3 BK5_IO11 - 60N/HSI1 HSI3A_SOUTP 72P/HSI3 BK5_IO12 HSI1A_SOUTP 61P/HSI1 - - - - - HSI3A_SOUTN 72N/HSI3 BK5_IO13 HSI1A_SOUTN 61N/HSI1 L27 BK5_IO16 - 113P/HSI4 NC - - NC - - K28 BK5_IO17 - 113N/HSI4 NC - - NC - - H30 BK5_IO18 HSI4B_SINP 114P/HSI4 NC - - NC - - G30 BK5_IO19 HSI4B_SINN 114N/HSI4 NC - - NC - - J28 BK5_IO20 - 115P/HSI4 NC - - NC - - K27 BK5_IO21 - 115N/HSI4 NC - - NC - - 76 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.) LFX500 LFX200 LVDS Pair/ sysHSI Reserved1 LFX125 LVDS Pair/ sysHSI Reserved1 Signal Name Second Function LVDS Pair/ sysHSI Reserved1 516-Ball BGA Ball Signal Name Second Function Signal Name Second Function J29 BK5_IO22 HSI4B_SOUTP 116P/HSI4 NC - - NC - - - GND (Bank 5) - - - - - - - - H29 BK5_IO23 HSI4B_SOUTN 116N/HSI4 NC - - NC - - F30 BK5_IO24 - 117P/HSI5 NC - - NC - - G29 BK5_IO25 - 117N/HSI5 NC - - NC - - H28 BK5_IO26 HSI5A_SINP 118P/HSI5 NC - - NC - - H27 BK5_IO27 HSI5A_SINN 118N/HSI5 NC - - NC - - E30 BK5_IO28 - 119P/HSI5 NC - - NC - - F29 BK5_IO29 - 119N/HSI5 NC - - NC - - G28 BK5_IO30 HSI5A_SOUTP 120P/HSI5 NC - - NC - - - GND (Bank 5) - - - - - - - G27 BK5_IO31 HSI5A_SOUTN 120N/HSI5 NC - - NC - - E29 BK5_IO32 VREF5 121P/HSI5 BK5_IO16 VREF5 73P/HSI3 BK5_IO14 VREF5 62P/HSI1 F28 BK5_IO33 - 121N/HSI5 BK5_IO17 - 73N/HSI3 BK5_IO15 - 62N/HSI1 D30 BK5_IO34 HSI5B_SINP 122P/HSI5 BK5_IO18 HSI3B_SINP 74P/HSI3 BK5_IO16 HSI1B_SINP 63P/HSI1 - - - - - - - GND (Bank 5) - - C30 BK5_IO35 HSI5B_SINN 122N/HSI5 BK5_IO19 HSI3B_SINN 74N/HSI3 BK5_IO17 HSI1B_SINN 63N/HSI1 D29 BK5_IO36 - 123P/HSI5 BK5_IO20 75P/HSI3 NC - - D28 BK5_IO37 - 123N/HSI5 BK5_IO21 75N/HSI3 NC - - E28 BK5_IO38 HSI5B_SOUTP 124P/HSI5 BK5_IO22 76P/HSI3 BK5_IO20 HSI1B_SOUTP 65P/HSI1 - GND (Bank 5) - - GND (Bank 5) - - - - - E27 BK5_IO39 HSI5B_SOUTN 124N/HSI5 BK5_IO23 HSI3B_SOUTN 76N/HSI3 BK5_IO21 HSI1B_SOUTN 65N/HSI1 HSI3B_SOUTP C29 BK5_IO40 - 125P BK5_IO24 - 77P/HSI3 BK5_IO18 - 64P/HSI1 B30 BK5_IO41 - 125N BK5_IO25 - 77N/HSI3 BK5_IO19 - 64N/HSI1 A29 CFG0 - - CFG0 - - CFG0 - - B28 DONE - - DONE - - DONE - - A28 PROGRAMb - - PROGRAMb - - PROGRAMb - - D26 BK6_IO0 INITb 126P BK6_IO0 INITb 78P BK6_IO0 INITb 66P C27 BK6_IO1 CCLK 126N BK6_IO1 CCLK 78N BK6_IO1 CCLK 66N B27 BK6_IO2 - 127P BK6_IO2 - 79P BK6_IO2 - 67P - GND (Bank 6) - - GND (Bank 6) - - - - - A27 BK6_IO3 - 127N BK6_IO3 - 79N BK6_IO3 - 67N C26 BK6_IO4 CSb 128P BK6_IO4 CSb 80P BK6_IO4 CSb 68P - - - - - - - GND (Bank 6) - - B26 BK6_IO5 Read 128N BK6_IO5 Read 80N BK6_IO5 Read 68N A26 BK6_IO6 - 129P NC - - NC - - C25 BK6_IO7 - 129N NC - - NC - - D24 BK6_IO8 - 130P NC - - NC - - B25 BK6_IO9 - 130N NC - - NC - - A25 BK6_IO10 - 131P NC - - NC - - - GND (Bank 6) - - - - - - - - C24 BK6_IO11 - 131N NC - - NC - - D23 BK6_IO12 - 132P NC - - NC - - B24 BK6_IO13 - 132N NC - - NC - - C23 BK6_IO14 - 133P NC - - NC - - A24 BK6_IO15 - 133N NC - - NC - - C22 BK6_IO16 - 134P NC - - NC - - B23 BK6_IO17 - 134N NC - - NC - - B22 BK6_IO18 DATA7 135P BK6_IO6 DATA7 81P BK6_IO6 DATA7 69P - GND (Bank 6) - - - - - - - - A23 BK6_IO19 DATA6 135N BK6_IO7 DATA6 81N BK6_IO7 DATA6 69N 77 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.) LFX500 LFX200 LVDS Pair/ sysHSI Reserved1 LFX125 LVDS Pair/ sysHSI Reserved1 Signal Name Second Function LVDS Pair/ sysHSI Reserved1 516-Ball BGA Ball Signal Name Second Function Signal Name Second Function D21 BK6_IO20 - 136P BK6_IO8 - 82P BK6_IO8 - 70P C21 BK6_IO21 VREF6 136N BK6_IO9 VREF6 82N BK6_IO9 VREF6 70N B21 BK6_IO22 DATA5 137P BK6_IO10 DATA5 83P BK6_IO10 DATA5 71P - - - - GND (Bank 6) - - - - - A21 BK6_IO23 DATA4 137N BK6_IO11 DATA4 83N BK6_IO11 DATA4 71N D20 BK6_IO24 - 138P BK6_IO12 - 84P BK6_IO12 - 72P - - - - - - - GND (Bank 6) - - C20 BK6_IO25 - 138N BK6_IO13 - 84N BK6_IO13 - 72N B20 BK6_IO26 DATA3 139P BK6_IO14 DATA3 85P BK6_IO14 DATA3 73P - GND (Bank 6) - - - - - - - - A20 BK6_IO27 DATA2 139N BK6_IO15 DATA2 85N BK6_IO15 DATA2 73N C19 BK6_IO28 - 140P BK6_IO16 86P BK6_IO16 - 74P B19 BK6_IO29 - 140N BK6_IO17 86N BK6_IO17 - 74N A19 BK6_IO30 DATA1 141P BK6_IO18 DATA1 87P BK6_IO18 DATA1 75P - - - - GND (Bank 6) - - GND (Bank 6) - - A18 BK6_IO31 DATA0 141N BK6_IO19 DATA0 87N BK6_IO19 DATA0 75N D18 BK6_IO32 - 142P BK6_IO20 88P BK6_IO20 - 76P C18 BK6_IO33 - 142N BK6_IO21 88N BK6_IO21 - 76N 89P NC - - - - - - B18 BK6_IO34 - 143P BK6_IO22 - GND (Bank 6) - - - - C17 BK6_IO35 - 143N BK6_IO23 89N NC - - B17 BK6_IO36 - 144P NC - - NC - - A17 BK6_IO37 - 144N NC - - NC - D16 BK6_IO38 - 145P NC - - NC - - C16 BK6_IO39 - 145N NC - - NC - - B16 BK6_IO40 - 146P BK6_IO24 - 90P NC - - A16 BK6_IO41 - 146N BK6_IO25 - 90N NC - - - GND (Bank 6) - - GND (Bank 6) - - - - - - GND (Bank 7) - - GND (Bank 7) - - - - - A15 BK7_IO0 - 147P BK7_IO0 - 91P BK7_IO0 - 77P B15 BK7_IO1 - 147N BK7_IO1 - 91N BK7_IO1 - 77N C15 BK7_IO2 - 148P BK7_IO2 - 92P BK7_IO2 - 78P - - - - - - - GND (Bank 7) - - D15 BK7_IO3 - 148N BK7_IO3 - 92N BK7_IO3 - 78N A14 BK7_IO4 - 149P BK7_IO4 - 93P BK7_IO4 - 79P B14 BK7_IO5 - 149N BK7_IO5 - 93N BK7_IO5 - 79N C14 BK7_IO6 - 150P BK7_IO6 - 94P NC - - - GND (Bank 7) - - GND (Bank 7) - - - - - A13 BK7_IO7 - 150N BK7_IO7 - 94N NC - - B13 BK7_IO8 - 151P BK7_IO8 - 95P NC - - C13 BK7_IO9 - 151N BK7_IO9 - 95N NC - - D13 BK7_IO10 - 152P BK7_IO10 - 96P BK7_IO6 - 80P B12 BK7_IO11 - 152N BK7_IO11 - 96N BK7_IO7 - 80N C12 BK7_IO12 - 153P BK7_IO12 - 97P BK7_IO8 - 81P - - - - - - - GND (Bank 7) - - A12 BK7_IO13 - 153N BK7_IO13 97N BK7_IO9 - 81N 82P A11 BK7_IO14 - 154P BK7_IO14 - 98P BK7_IO10 - - GND (Bank 7) - - GND (Bank 7) - - - - - B11 BK7_IO15 - 154N BK7_IO15 - 98N BK7_IO11 - 82N C11 BK7_IO16 - 155P NC - - NC - - D11 BK7_IO17 - 155N NC - - NC - - 78 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.) LFX500 LFX200 LVDS Pair/ sysHSI Reserved1 LFX125 Signal Name Second Function LVDS Pair/ sysHSI Reserved1 NC - - NC - - NC - - NC - - 157P BK7_IO16 VREF7 99P BK7_IO12 VREF7 83P 157N BK7_IO17 - 99N BK7_IO13 - 83N 84P 516-Ball BGA Ball Signal Name Second Function A10 BK7_IO18 - 156P B10 BK7_IO19 - 156N C10 BK7_IO20 VREF7 D10 BK7_IO21 - Signal Name Second Function LVDS Pair/ sysHSI Reserved1 B9 BK7_IO22 - 158P BK7_IO18 - 100P BK7_IO14 - - GND (Bank 7) - - - - - - - - C9 BK7_IO23 - 158N BK7_IO19 - 100N BK7_IO15 - 84N A8 BK7_IO24 - 159P BK7_IO20 - 101P BK7_IO16 - 85P - - - - - - - GND (Bank 7) - - B8 BK7_IO25 - 159N BK7_IO21 - 101N BK7_IO17 - 85N C8 BK7_IO26 - 160P NC - - NC - - D8 BK7_IO27 - 160N NC - - NC - - A7 BK7_IO28 - 161P NC - - NC - - B7 BK7_IO29 - 161N NC - - NC - - C7 BK7_IO30 - 162P NC - - NC - - - GND (Bank 7) - - - - - - - - D7 BK7_IO31 - 162N NC - - NC - - A6 BK7_IO32 - 163P NC - - NC - - B6 BK7_IO33 - 163N NC - - NC - - B5 BK7_IO34 - 164P NC - - NC - - C6 BK7_IO35 - 164N NC - - NC - - A5 BK7_IO36 - 165P NC - - NC - - A4 BK7_IO37 - 165N NC - - NC - 86P B4 BK7_IO38 - 166P BK7_IO22 - 102P BK7_IO18 - - GND (Bank 7) - - GND (Bank 7) - - - - - C5 BK7_IO39 - 166N BK7_IO23 - 102N BK7_IO19 - 86N A3 BK7_IO40 - 167P BK7_IO24 - 103P BK7_IO20 - 87P A2 BK7_IO41 - 167N BK7_IO25 - 103N BK7_IO21 - 87N D5 TDO - - TDO - - TDO - - C4 VCCJ - - VCCJ - - VCCJ - - B3 TDI - - TDI - - TDI - - 1. If a sysHSI Block is used, the indicated sysHSI reserved pins are unavailable for general purpose I/O use. 79 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 680-Ball fpBGA LFX1200 680-Ball fpBGA Signal Name Second Function LVDS Pair/sysHSI Reserved1 C4 BK0_IO0 - 0P B4 BK0_IO1 - 0N E6 BK0_IO2 - 1P - GND (Bank 0) - D6 BK0_IO3 - A4 BK0_IO4 - 2P E8 BK0_IO5 - 2N C5 BK0_IO6 HSI0A_SOUTP 3P C6 BK0_IO7 HSI0A_SOUTN 3N A6 BK0_IO8 - 4P A5 BK0_IO9 - 4N B6 BK0_IO10 HSI0A_SINP 5P/HSI0 - GND (Bank 0) - - B5 BK0_IO11 HSI0A_SINN 5N/HSI0 B7 BK0_IO12 VREF0 6P/HSI0 1N A7 BK0_IO13 - 6N/HSI0 D8 BK0_IO14 HSI0B_SOUTP 7P/HSI0 D7 BK0_IO15 HSI0B_SOUTN 7N/HSI0 D9 BK0_IO16 - 8P/HSI0 E10 BK0_IO17 - 8N/HSI0 C8 BK0_IO18 HSI0B_SINP 9P/HSI0 - GND (Bank 0) - - C7 BK0_IO19 HSI0B_SINN 9N/HSI0 A8 BK0_IO20 - 10P/HSI0 A9 BK0_IO21 - 10N/HSI0 C9 BK0_IO22 HSI1A_SOUTP 11P/HSI0 B8 BK0_IO23 HSI1A_SOUTN 11N/HSI0 B9 BK0_IO24 - 12P/HSI0 B10 BK0_IO25 - 12N/HSI0 D11 BK0_IO26 HSI1A_SINP 13P/HSI1 - GND (Bank 0) - - D10 BK0_IO27 HSI1A_SINN 13N/HSI1 A10 BK0_IO28 - 14P/HSI1 C12 BK0_IO29 - 14N/HSI1 D12 BK0_IO30 HSI1B_SOUTP 15P/HSI1 C11 BK0_IO31 HSI1B_SOUTN 15N/HSI1 A12 BK0_IO32 - 16P/HSI1 A13 BK0_IO33 - 16N/HSI1 B13 BK0_IO34 HSI1B_SINP 17P/HSI1 - GND (Bank 0) - - B12 BK0_IO35 HSI1B_SINN 17N/HSI1 E14 BK0_IO36 - 18P/HSI1 80 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.) LFX1200 Second Function LVDS Pair/sysHSI Reserved1 BK0_IO37 - 18N/HSI1 BK0_IO38 HSI2A_SOUTP 19P/HSI1 D13 BK0_IO39 HSI2A_SOUTN 19N/HSI1 B14 BK0_IO40 - 20P/HSI1 680-Ball fpBGA Signal Name D14 C13 A14 BK0_IO41 - 20N/HSI1 C15 BK0_IO42 HSI2A_SINP 21P/HSI2 - GND (Bank 0) - - D15 BK0_IO43 HSI2A_SINN 21N/HSI2 A15 BK0_IO44 - 22P/HSI2 C16 BK0_IO45 - 22N/HSI2 B15 BK0_IO46 HSI2B_SOUTP 23P/HSI2 B16 BK0_IO47 HSI2B_SOUTN 23N/HSI2 A16 BK0_IO48 - 24P/HSI2 B17 BK0_IO49 - 24N/HSI2 D16 BK0_IO50 HSI2B_SINP 25P/HSI2 - GND (Bank 0) - 25N/HSI2 E16 BK0_IO51 HSI2B_SINN D17 BK0_IO52 - 26P/HSI2 C17 BK0_IO53 - 26N/HSI2 A18 BK0_IO54 PLL_RST0 27P/HSI2 D18 BK0_IO55 PLL_RST1 27N/HSI2 A17 BK0_IO56 - 28P/HSI2 E19 BK0_IO57 - 28N/HSI2 A19 BK0_IO58 PLL_FBK0 29P - GND (Bank 0) - - B19 BK0_IO59 PLL_FBK1 29N C18 BK0_IO60 CLK_OUT0 30P B18 BK0_IO61 CLK_OUT1 30N - GND (Bank 0) - - D19 GCLK0 - LVDS Pair0P C19 GCLK1 - LVDS Pair0N E20 VCCP0 - - A21 GNDP0 - - B21 GCLK2 - LVDS Pair1P C21 GCLK3 - LVDS Pair1N B23 BK1_IO0 CLK_OUT2 31P C23 BK1_IO1 CLK_OUT3 31N B22 BK1_IO2 SS_CLKOUT0P 32P - GND (Bank 1) - - C22 BK1_IO3 SS_CLKOUT0N 32N D21 BK1_IO4 PLL_FBK2 33P E21 BK1_IO5 PLL_FBK3 33N B24 BK1_IO6 SS_CLKIN0P 34P 81 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.) LFX1200 Signal Name Second Function LVDS Pair/sysHSI Reserved1 C24 BK1_IO7 SS_CLKIN0N 34N A22 BK1_IO8 - 35P D22 BK1_IO9 - 35N A23 BK1_IO10 - 36P 680-Ball fpBGA - GND (Bank 1) - - B25 BK1_IO11 - 36N D23 BK1_IO12 PLL_RST2 37P A24 BK1_IO13 PLL_RST3 37N A25 BK1_IO14 - 38P E24 BK1_IO15 - 38N D24 BK1_IO16 - 39P A26 BK1_IO17 - 39N D25 BK1_IO18 - 40P - GND (Bank 1) - - C25 BK1_IO19 - 40N B26 BK1_IO20 - 41P/HSI3 B27 BK1_IO21 - 41N/HSI3 D26 BK1_IO22 - 42P/HSI3 A27 BK1_IO23 - 42N/HSI3 A28 BK1_IO24 - 43P/HSI3 E26 BK1_IO25 - 43N/HSI3 C27 BK1_IO26 HSI3A_SOUTP 44P/HSI3 - GND (Bank 1) - - D27 BK1_IO27 HSI3A_SOUTN 44N/HSI3 B28 BK1_IO28 - 45P/HSI3 A30 BK1_IO29 - 45N/HSI3 C28 BK1_IO30 HSI3A_SINP 46P/HSI3 D28 BK1_IO31 HSI3A_SINN 46N/HSI3 A31 BK1_IO32 - 47P/HSI3 B30 BK1_IO33 - 47N/HSI3 E28 BK1_IO34 HSI3B_SOUTP 48P/HSI3 - GND (Bank 1) - - D29 BK1_IO35 HSI3B_SOUTN 48N/HSI3 C29 BK1_IO36 - 49P/HSI4 B31 BK1_IO37 - 49N/HSI4 D30 BK1_IO38 HSI3B_SINP 50P/HSI4 E30 BK1_IO39 HSI3B_SINN 50N/HSI4 A32 BK1_IO40 - 51P/HSI4 C31 BK1_IO41 - 51N/HSI4 D31 BK1_IO42 HSI4A_SOUTP 52P/HSI4 - GND (Bank 1) - - C32 BK1_IO43 HSI4A_SOUTN 52N/HSI4 B32 BK1_IO44 - 53P/HSI4 82 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.) LFX1200 680-Ball fpBGA Signal Name Second Function LVDS Pair/sysHSI Reserved1 A33 BK1_IO45 - 53N/HSI4 C33 BK1_IO46 HSI4A_SINP 54P/HSI4 B33 BK1_IO47 HSI4A_SINN 54N/HSI4 A34 BK1_IO48 - 55P/HSI4 A35 BK1_IO49 VREF1 55N/HSI4 D32 BK1_IO50 HSI4B_SOUTP 56P/HSI4 - GND (Bank 1) - - D33 BK1_IO51 HSI4B_SOUTN 56N/HSI4 E32 BK1_IO52 - 57P C34 BK1_IO53 - 57N B34 BK1_IO54 HSI4B_SINP 58P B35 BK1_IO55 HSI4B_SINN 58N A36 BK1_IO56 - 59P D34 BK1_IO57 - 59N C35 BK1_IO58 - 60P - GND (Bank 1) - - E34 BK1_IO59 - 60N B36 BK1_IO60 - 61P C36 BK1_IO61 - 61N D39 TCK - - D37 TMS - - D38 TOE - - E37 BK2_IO0 - 62P F35 BK2_IO1 - 62N E39 BK2_IO2 - 63P - GND (Bank 2) - - F39 BK2_IO3 - 63N F36 BK2_IO4 - 64P E38 BK2_IO5 - 64N G38 BK2_IO6 - 65P F37 BK2_IO7 - 65N G36 BK2_IO8 - 66P G39 BK2_IO9 - 66N H35 BK2_IO10 - 67P - GND (Bank 2) - - F38 BK2_IO11 - 67N J37 BK2_IO12 VREF2 68P H36 BK2_IO13 - 68N G37 BK2_IO14 - 69P H37 BK2_IO15 - 69N H39 BK2_IO16 - 70P K35 BK2_IO17 - 70N J36 BK2_IO18 - 71P 83 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.) LFX1200 LVDS Pair/sysHSI Reserved1 680-Ball fpBGA Signal Name Second Function - GND (Bank 2) - - K36 BK2_IO19 - 71N H38 BK2_IO20 - 72P J38 BK2_IO21 - 72N J39 BK2_IO22 - 73P L36 BK2_IO23 - 73N K38 BK2_IO24 - 74P M36 BK2_IO25 - 74N L37 BK2_IO26 - 75P - GND (Bank 2) - - K39 BK2_IO27 - 75N L38 BK2_IO28 - 76P P35 BK2_IO29 - 76N N36 BK2_IO30 - 77P M37 BK2_IO31 - 77N L39 BK2_IO32 - 78P M38 BK2_IO33 - 78N M39 BK2_IO34 - 79P - GND (Bank 2) - - P36 BK2_IO35 - 79N R36 BK2_IO36 - 80P N37 BK2_IO37 - 80N P38 BK2_IO38 - 81P T35 BK2_IO39 - 81N R37 BK2_IO40 - 82P R38 BK2_IO41 - 82N P39 BK2_IO42 - 83P - GND (Bank 2) - - R39 BK2_IO43 - 83N T38 BK2_IO44 - 84P T36 BK2_IO45 - 84N T37 BK2_IO46 - 85P U36 BK2_IO47 - 85N U37 BK2_IO48 - 86P T39 BK2_IO49 - 86N V36 BK2_IO50 - 87P - GND (Bank 2) - - U38 BK2_IO51 - 87N U39 BK2_IO52 - 88P V38 BK2_IO53 - 88N V37 BK2_IO54 - 89P W36 BK2_IO55 - 89N W35 BK2_IO56 - 90P 84 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.) LFX1200 680-Ball fpBGA Signal Name Second Function LVDS Pair/sysHSI Reserved1 V39 BK2_IO57 - 90N W37 BK2_IO58 - 91P - GND (Bank 2) - - W38 BK2_IO59 - 91N W39 BK2_IO60 - 92P AA39 BK2_IO61 - 92N - GND (Bank 2) - - - GND (Bank 3) - - AA38 BK3_IO0 - 93P Y35 BK3_IO1 - 93N AA37 BK3_IO2 - 94P - GND (Bank 3) - - AA35 BK3_IO3 - 94N AB39 BK3_IO4 - 95P AB38 BK3_IO5 - 95N AA36 BK3_IO6 - 96P AB37 BK3_IO7 - 96N AC39 BK3_IO8 - 97P AC38 BK3_IO9 - 97N AB36 BK3_IO10 - 98P - GND (Bank 3) - - AC37 BK3_IO11 - 98N AC36 BK3_IO12 - 99P AD39 BK3_IO13 - 99N AD37 BK3_IO14 - 100P AD36 BK3_IO15 - 100N AD35 BK3_IO16 - 101P AE38 BK3_IO17 - 101N AD38 BK3_IO18 - 102P - GND (Bank 3) - - AE39 BK3_IO19 - 102N AF38 BK3_IO20 - 103P AF37 BK3_IO21 - 103N AF39 BK3_IO22 - 104P AE36 BK3_IO23 - 104N AF36 BK3_IO24 - 105P AG38 BK3_IO25 - 105N AG39 BK3_IO26 - 106P - GND (Bank 3) - - AG37 BK3_IO27 - 106N AH37 BK3_IO28 - 107P AH38 BK3_IO29 - 107N AG36 BK3_IO30 - 108P 85 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.) LFX1200 680-Ball fpBGA Signal Name Second Function LVDS Pair/sysHSI Reserved1 AH39 BK3_IO31 - 108N AK39 BK3_IO32 - 109P AK38 BK3_IO33 - 109N AF35 BK3_IO34 - 110P - GND (Bank 3) - - AJ37 BK3_IO35 - 110N AH36 BK3_IO36 - 111P AM39 BK3_IO37 - 111N AL38 BK3_IO38 - 112P AL39 BK3_IO39 - 112N AJ36 BK3_IO40 - 113P AH35 BK3_IO41 - 113N AL37 BK3_IO42 - 114P - GND (Bank 3) - - AN38 BK3_IO43 - 114N AM38 BK3_IO44 - 115P AK36 BK3_IO45 - 115N AM37 BK3_IO46 - 116P AN37 BK3_IO47 - 116N AN39 BK3_IO48 - 117P AL36 BK3_IO49 VREF3 117N AK35 BK3_IO50 - 118P - GND (Bank 3) - - AP39 BK3_IO51 - 118N AM36 BK3_IO52 - 119P AP38 BK3_IO53 - 119N AR39 BK3_IO54 - 120P AN36 BK3_IO55 - 120N AM35 BK3_IO56 - 121P AR38 BK3_IO57 - 121N AP37 BK3_IO58 - 122P - GND (Bank 3) - - AT39 BK3_IO59 - 122N AR37 BK3_IO60 - 123P AP36 BK3_IO61 - 123N AT38 GSR - - AP35 DXP - - AT37 DXN - - AU36 BK4_IO0 - 124P AV36 BK4_IO1 - 124N AR34 BK4_IO2 - 125P - GND (Bank 4) - - AW36 BK4_IO3 - 125N 86 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.) LFX1200 680-Ball fpBGA Signal Name Second Function LVDS Pair/sysHSI Reserved1 AW35 BK4_IO4 - 126P AV35 BK4_IO5 - 126N AV34 BK4_IO6 HSI5A_SINP 127P AU34 BK4_IO7 HSI5A_SINN 127N AT34 BK4_IO8 - 128P AU35 BK4_IO9 - 128N AT33 BK4_IO10 HSI5A_SOUTP 129P/HSI5 - GND (Bank 4) - - AU33 BK4_IO11 HSI5A_SOUTN 129N/HSI5 AW34 BK4_IO12 VREF4 130P/HSI5 AV33 BK4_IO13 - 130N/HSI5 AR32 BK4_IO14 HSI5B_SINP 131P/HSI5 AT32 BK4_IO15 HSI5B_SINN 131N/HSI5 AU32 BK4_IO16 - 132P/HSI5 AW33 BK4_IO17 - 132N/HSI5 AV32 BK4_IO18 HSI5B_SOUTP 133P/HSI5 - GND (Bank 4) - - AV31 BK4_IO19 HSI5B_SOUTN 133N/HSI5 AU31 BK4_IO20 - 134P/HSI5 AW32 BK4_IO21 - 134N/HSI5 AR30 BK4_IO22 HSI6A_SINP 135P/HSI5 AT31 BK4_IO23 HSI6A_SINN 135N/HSI5 AW31 BK4_IO24 - 136P/HSI5 AV30 BK4_IO25 - 136N/HSI5 AT30 BK4_IO26 HSI6A_SOUTP 137P/HSI6 - GND (Bank 4) - - AT29 BK4_IO27 HSI6A_SOUTN 137N/HSI6 AW30 BK4_IO28 - 138P/HSI6 AU29 BK4_IO29 - 138N/HSI6 AT28 BK4_IO30 HSI6B_SINP 139P/HSI6 AU28 BK4_IO31 HSI6B_SINN 139N/HSI6 AV28 BK4_IO32 - 140P/HSI6 AT27 BK4_IO33 - 140N/HSI6 AU27 BK4_IO34 HSI6B_SOUTP 141P/HSI6 - GND (Bank 4) - - AV27 BK4_IO35 HSI6B_SOUTN 141N/HSI6 AW28 BK4_IO36 - 142P/HSI6 AR26 BK4_IO37 - 142N/HSI6 AW27 BK4_IO38 - 143P/HSI6 AT26 BK4_IO39 - 143N/HSI6 AV26 BK4_IO40 - 144P/HSI6 AR24 BK4_IO41 - 144N/HSI6 AT25 BK4_IO42 - 145P/HSI6 87 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.) LFX1200 680-Ball fpBGA Signal Name Second Function LVDS Pair/sysHSI Reserved1 - GND (Bank 4) - - AW26 BK4_IO43 - 145N AV25 BK4_IO44 - 146P AT24 BK4_IO45 - 146N AU24 BK4_IO46 - 147P AU25 BK4_IO47 - 147N AW25 BK4_IO48 PLL_RST4 148P AW24 BK4_IO49 PLL_RST5 148N AU23 BK4_IO50 - 149P - GND (Bank 4) - - AT23 BK4_IO51 - 149N AV24 BK4_IO52 - 150P AW23 BK4_IO53 - 150N AV23 BK4_IO54 SS_CLKIN1P 151P AU22 BK4_IO55 SS_CLKIN1N 151N AR21 BK4_IO56 PLL_FBK4 152P AT22 BK4_IO57 PLL_FBK5 152N AV22 BK4_IO58 SS_CLKOUT1P 153P - GND (Bank 4) - - AV21 BK4_IO59 SS_CLKOUT1N 153N AT21 BK4_IO60 CLK_OUT4 154P AU21 BK4_IO61 CLK_OUT5 154N - GND (Bank 4) - - AT19 GCLK4 - LVDS Pair2P AU19 GCLK5 - LVDS Pair2N AW22 VCCP1 - - AR20 GNDP1 - - AU18 GCLK6 - LVDS Pair3P AT18 GCLK7 - LVDS Pair3N - GND (Bank 5) - - AV17 BK5_IO0 CLK_OUT6 155P AV18 BK5_IO1 CLK_OUT7 155N AW21 BK5_IO2 PLL_FBK6 156P - GND (Bank 5) - - AV19 BK5_IO3 PLL_FBK7 156N AR19 BK5_IO4 - 157P/HSI7 AW19 BK5_IO5 - 157N/HSI7 AW18 BK5_IO6 PLL_RST6 158P/HSI7 AW17 BK5_IO7 PLL_RST7 158N/HSI7 AT17 BK5_IO8 - 159P/HSI7 AV16 BK5_IO9 - 159N/HSI7 AU17 BK5_IO10 HSI7A_SINP 160P/HSI7 - GND (Bank 5) - - 88 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.) LFX1200 680-Ball fpBGA Signal Name Second Function LVDS Pair/sysHSI Reserved1 AT16 BK5_IO11 HSI7A_SINN 160N/HSI7 AW16 BK5_IO12 - 161P/HSI7 AU16 BK5_IO13 - 161N/HSI7 AV14 BK5_IO14 HSI7A_SOUTP 162P/HSI7 AV15 BK5_IO15 HSI7A_SOUTN 162N/HSI7 AU15 BK5_IO16 - 163P/HSI7 AW15 BK5_IO17 - 163N/HSI7 AT15 BK5_IO18 HSI7B_SINP 164P/HSI7 - GND (Bank 5) - - AR16 BK5_IO19 HSI7B_SINN 164N/HSI7 AW14 BK5_IO20 - 165P/HSI8 AW13 BK5_IO21 - 165N/HSI8 AR14 BK5_IO22 HSI7B_SOUTP 166P/HSI8 AT14 BK5_IO23 HSI7B_SOUTN 166N/HSI8 AT13 BK5_IO24 - 167P/HSI8 AV13 BK5_IO25 - 167N/HSI8 AU12 BK5_IO26 HSI8A_SINP 168P/HSI8 - GND (Bank 5) - - AU13 BK5_IO27 HSI8A_SINN 168N/HSI8 AV12 BK5_IO28 - 169P/HSI8 AT12 BK5_IO29 - 169N/HSI8 AR12 BK5_IO30 HSI8A_SOUTP 170P/HSI8 AT11 BK5_IO31 HSI8A_SOUTN 170N/HSI8 AW12 BK5_IO32 - 171P/HSI8 AU11 BK5_IO33 - 171N/HSI8 AV9 BK5_IO34 HSI8B_SINP 172P/HSI8 - GND (Bank 5) - - AV10 BK5_IO35 HSI8B_SINN 172N/HSI8 AW10 BK5_IO36 - 173P/HSI9 AW9 BK5_IO37 - 173N/HSI9 AT10 BK5_IO38 HSI8B_SOUTP 174P/HSI9 AU9 BK5_IO39 HSI8B_SOUTN 174N/HSI9 AT9 BK5_IO40 - 175P/HSI9 AR10 BK5_IO41 - 175N/HSI9 AU8 BK5_IO42 HSI9A_SINP 176P/HSI9 - GND (Bank 5) - - AV8 BK5_IO43 HSI9A_SINN 176N/HSI9 AW8 BK5_IO44 - 177P/HSI9 AW7 BK5_IO45 - 177N/HSI9 AU7 BK5_IO46 HSI9A_SOUTP 178P/HSI9 AT8 BK5_IO47 HSI9A_SOUTN 178N/HSI9 AV7 BK5_IO48 - 179P/HSI9 AW6 BK5_IO49 VREF5 179N/HSI9 89 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.) LFX1200 Signal Name Second Function LVDS Pair/sysHSI Reserved1 AU6 BK5_IO50 HSI9B_SINP 180P/HSI9 - GND (Bank 5) - - 680-Ball fpBGA AV6 BK5_IO51 HSI9B_SINN 180N/HSI9 AR8 BK5_IO52 - 181P AT7 BK5_IO53 - 181N AU5 BK5_IO54 HSI9B_SOUTP 182P AV5 BK5_IO55 HSI9B_SOUTN 182N AW5 BK5_IO56 - 183P AW4 BK5_IO57 - 183N AT6 BK5_IO58 - 184P - GND (Bank 5) - - AV4 BK5_IO59 - 184N AR6 BK5_IO60 - 185P AU4 BK5_IO61 - 185N AT1 CFG0 - - AT3 DONE - - AT2 PROGRAMb - - AP4 BK6_IO0 INITb 186P AP5 BK6_IO1 CCLK 186N AR3 BK6_IO2 - 187P - GND (Bank 6) - - AR2 BK6_IO3 - 187N AP3 BK6_IO4 CSb 188P AR1 BK6_IO5 Read 188N AP2 BK6_IO6 - 189P AP1 BK6_IO7 - 189N AN4 BK6_IO8 - 190P AM5 BK6_IO9 - 190N AN3 BK6_IO10 - 191P - GND (Bank 6) - - AN2 BK6_IO11 - 191N AM4 BK6_IO12 VREF6 192P AM3 BK6_IO13 - 192N AN1 BK6_IO14 - 193P AM2 BK6_IO15 - 193N AL4 BK6_IO16 - 194P AK5 BK6_IO17 - 194N AM1 BK6_IO18 - 195P - GND (Bank 6) - - AK4 BK6_IO19 - 195N AL3 BK6_IO20 - 196P AL2 BK6_IO21 - 196N AL1 BK6_IO22 - 197P 90 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.) LFX1200 680-Ball fpBGA Signal Name Second Function LVDS Pair/sysHSI Reserved1 AK2 BK6_IO23 - 197N AK1 BK6_IO24 - 198P AJ4 BK6_IO25 - 198N AJ3 BK6_IO26 - 199P - GND (Bank 6) - - AH4 BK6_IO27 - 199N AH3 BK6_IO28 - 200P AH2 BK6_IO29 - 200N AH1 BK6_IO30 - 201P AG4 BK6_IO31 - 201N AF5 BK6_IO32 DATA7 202P AG3 BK6_IO33 DATA6 202N AG2 BK6_IO34 - 203P - GND (Bank 6) - - AF4 BK6_IO35 - 203N AF3 BK6_IO36 DATA5 204P AG1 BK6_IO37 DATA4 204N AE2 BK6_IO38 - 205P AF1 BK6_IO39 - 205N AF2 BK6_IO40 - 206P AE1 BK6_IO41 - 206N AE4 BK6_IO42 - 207P - GND (Bank 6) - - AD4 BK6_IO43 - 207N AD5 BK6_IO44 - 208P AD3 BK6_IO45 - 208N AD2 BK6_IO46 - 209P AD1 BK6_IO47 - 209N AC4 BK6_IO48 - 210P AC3 BK6_IO49 - 210N AC2 BK6_IO50 DATA3 211P - GND (Bank 6) - - AC1 BK6_IO51 DATA2 211N AB3 BK6_IO52 - 212P AB4 BK6_IO53 - 212N AB2 BK6_IO54 DATA1 213P AB1 BK6_IO55 DATA0 213N AA3 BK6_IO56 - 214P AA4 BK6_IO57 - 214N AA5 BK6_IO58 - 215P - GND (Bank 6) - - AA2 BK6_IO59 - 215N AA1 BK6_IO60 - 216P 91 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.) LFX1200 680-Ball fpBGA Signal Name Second Function LVDS Pair/sysHSI Reserved1 Y5 BK6_IO61 - 216N - GND (Bank 6) - - - GND (Bank 7) - - W3 BK7_IO0 - 217P W1 BK7_IO1 - 217N W2 BK7_IO2 - 218P - GND (Bank 7) - - W4 BK7_IO3 - 218N V1 BK7_IO4 - 219P V2 BK7_IO5 - 219N V3 BK7_IO6 - 220P V4 BK7_IO7 - 220N W5 BK7_IO8 - 221P U1 BK7_IO9 - 221N U2 BK7_IO10 - 222P - GND (Bank 7) - - U3 BK7_IO11 - 222N U4 BK7_IO12 - 223P T1 BK7_IO13 - 223N T2 BK7_IO14 - 224P T3 BK7_IO15 - 224N R1 BK7_IO16 - 225P R2 BK7_IO17 - 225N T4 BK7_IO18 - 226P - GND (Bank 7) - - P1 BK7_IO19 - 226N P2 BK7_IO20 - 227P P3 BK7_IO21 - 227N R4 BK7_IO22 - 228P T5 BK7_IO23 - 228N M1 BK7_IO24 - 229P M2 BK7_IO25 - 229N N3 BK7_IO26 - 230P - GND (Bank 7) - - P4 BK7_IO27 - 230N L1 BK7_IO28 - 231P M3 BK7_IO29 - 231N L2 BK7_IO30 - 232P N4 BK7_IO31 - 232N K1 BK7_IO32 - 233P K2 BK7_IO33 - 233N P5 BK7_IO34 - 234P - GND (Bank 7) - - 92 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.) LFX1200 680-Ball fpBGA Signal Name Second Function LVDS Pair/sysHSI Reserved1 L3 BK7_IO35 - 234N J1 BK7_IO36 - 235P J2 BK7_IO37 - 235N M4 BK7_IO38 - 236P H1 BK7_IO39 - 236N J3 BK7_IO40 - 237P L4 BK7_IO41 - 237N M5 BK7_IO42 - 238P - GND (Bank 7) - - H2 BK7_IO43 - 238N K4 BK7_IO44 - 239P G1 BK7_IO45 - 239N H3 BK7_IO46 - 240P J4 BK7_IO47 VREF7 240N K5 BK7_IO48 - 241P G3 BK7_IO49 - 241N H4 BK7_IO50 - 242P - GND (Bank 7) - - F2 BK7_IO51 - 242N G2 BK7_IO52 - 243P H5 BK7_IO53 - 243N F3 BK7_IO54 - 244P F1 BK7_IO55 - 244N G4 BK7_IO56 - 245P E1 BK7_IO57 - 245N F4 BK7_IO58 - 246P - GND (Bank 7) - - E2 BK7_IO59 - 246N F5 BK7_IO60 - 247P E3 BK7_IO61 - 247N D2 TDO - - D3 VCCJ - - D1 TDI - - 1. If a sysHSI Block is used, the indicated sysHSI reserved pins are unavailable for general purpose I/O use. 93 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA LFX1200 900 fpBGA Ball Signal Name Second Function LFX500 LVDS Pair/ sysHSI Reserved1 Signal Name Second Function LVDS Pair/ sysHSI Reserved1 D3 BK0_IO0 - 0P NC - - E3 BK0_IO1 - 0N NC - - C2 BK0_IO2 - 1P NC - - - GND (Bank 0) - - - - - C1 BK0_IO3 - 1N NC - - E4 BK0_IO4 - 2P BK0_IO0 - 0P F5 BK0_IO5 - 2N BK0_IO1 - 0N D2 BK0_IO6 HSI0A_SOUTP 3P BK0_IO2 HSI0A_SOUTP 1P/HSI0 - - - - GND (Bank 0) - - D1 BK0_IO7 HSI0A_SOUTN 3N BK0_IO3 HSI0A_SOUTN 1N/HSI0 F4 BK0_IO8 - 4P BK0_IO4 - 2P/HSI0 F3 BK0_IO9 - 4N BK0_IO5 - 2N/HSI0 E2 BK0_IO10 HSI0A_SINP 5P/HSI0 BK0_IO6 HSI0A_SINP 3P/HSI0 - GND (Bank 0) - - - - - E1 BK0_IO11 HSI0A_SINN 5N/HSI0 BK0_IO7 HSI0A_SINN 3N/HSI0 G6 BK0_IO12 VREF0 6P/HSI0 BK0_IO9 VREF0 4N/HSI0 G5 BK0_IO13 - 6N/HSI0 BK0_IO8 - 4P/HSI0 F1 BK0_IO14 HSI0B_SOUTP 7P/HSI0 NC - - F2 BK0_IO15 HSI0B_SOUTN 7N/HSI0 NC - - G4 BK0_IO16 - 8P/HSI0 NC - - G3 BK0_IO17 - 8N/HSI0 NC - - G2 BK0_IO18 HSI0B_SINP 9P/HSI0 NC - - - GND (Bank 0) - - - - G1 BK0_IO19 HSI0B_SINN 9N/HSI0 NC - - H3 BK0_IO20 - 10P/HSI0 NC - - H4 BK0_IO21 - 10N/HSI0 NC - - H1 BK0_IO22 HSI1A_SOUTP 11P/HSI0 NC - - H2 BK0_IO23 HSI1A_SOUTN 11N/HSI0 NC - - J7 BK0_IO24 - 12P/HSI0 NC - - J6 BK0_IO25 - 12N/HSI0 NC - - J1 BK0_IO26 HSI1A_SINP 13P/HSI1 NC - - - GND (Bank 0) - - - - - J2 BK0_IO27 HSI1A_SINN 13N/HSI1 NC - - J4 BK0_IO28 - 14P/HSI1 NC - - J5 BK0_IO29 - 14N/HSI1 NC - - K1 BK0_IO30 HSI1B_SOUTP 15P/HSI1 BK0_IO10 HSI0B_SOUTP 5P/HSI0 - - - - GND (Bank 0) - - K2 BK0_IO31 HSI1B_SOUTN 15N/HSI1 BK0_IO11 HSI0B_SOUTN 5N/HSI0 K5 BK0_IO32 - 16P/HSI1 BK0_IO12 - 6P/HSI0 K4 BK0_IO33 - 16N/HSI1 BK0_IO13 - 6N/HSI0 L1 BK0_IO34 HSI1B_SINP 17P/HSI1 BK0_IO14 HSI0B_SINP 7P/HSI0 - GND (Bank 0) - - - - - 94 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.) LFX1200 LFX500 900 fpBGA Ball Signal Name Second Function LVDS Pair/ sysHSI Reserved1 Signal Name Second Function LVDS Pair/ sysHSI Reserved1 L2 BK0_IO35 HSI1B_SINN 17N/HSI1 BK0_IO15 HSI0B_SINN 7N/HSI0 L6 BK0_IO36 - 18P/HSI1 BK0_IO16 - 8P/HSI0 L5 BK0_IO37 - 18N/HSI1 BK0_IO17 - 8N/HSI0 M1 BK0_IO38 HSI2A_SOUTP 19P/HSI1 BK0_IO18 HSI1A_SOUTP 9P/HSI1 - - - - GND (Bank 0) - - M2 BK0_IO39 HSI2A_SOUTN 19N/HSI1 BK0_IO19 HSI1A_SOUTN 9N/HSI1 L3 BK0_IO40 - 20P/HSI1 BK0_IO20 - 10P/HSI1 L4 BK0_IO41 - 20N/HSI1 BK0_IO21 - 10N/HSI1 M6 BK0_IO42 HSI2A_SINP 21P/HSI2 BK0_IO22 HSI1A_SINP 11P/HSI1 - GND (Bank 0) - - - - - M5 BK0_IO43 HSI2A_SINN 21N/HSI2 BK0_IO23 HSI1A_SINN 11N/HSI1 M4 BK0_IO44 - 22P/HSI2 BK0_IO24 - 12P/HSI1 M3 BK0_IO45 - 22N/HSI2 BK0_IO25 - 12N/HSI1 N1 BK0_IO46 HSI2B_SOUTP 23P/HSI2 BK0_IO26 HSI1B_SOUTP 13P/HSI1 - - - - GND (Bank 0) - - N2 BK0_IO47 HSI2B_SOUTN 23N/HSI2 BK0_IO27 HSI1B_SOUTN 13N/HSI1 N7 BK0_IO48 - 24P/HSI2 BK0_IO28 - 14P/HSI1 N6 BK0_IO49 - 24N/HSI2 BK0_IO29 - 14N/HSI1 P1 BK0_IO50 HSI2B_SINP 25P/HSI2 BK0_IO30 HSI1B_SINP 15P/HSI1 - GND (Bank 0) - - - - - P2 BK0_IO51 HSI2B_SINN 25N/HSI2 BK0_IO31 HSI1B_SINN 15N/HSI1 N3 BK0_IO52 - 26P/HSI2 BK0_IO32 - 16P/HSI1 N4 BK0_IO53 - 26N/HSI2 BK0_IO33 - 16N/HSI1 P6 BK0_IO54 PLL_RST0 27P/HSI2 BK0_IO38 PLL_RST0 19P P5 BK0_IO55 PLL_RST1 27N/HSI2 BK0_IO35 PLL_RST1 17N P3 BK0_IO56 - 28P/HSI2 BK0_IO36 - 18P P4 BK0_IO57 - 28N/HSI2 BK0_IO39 - 19N R7 BK0_IO58 PLL_FBK0 29P BK0_IO34 PLL_FBK0 17P - GND (Bank 0) - - GND (Bank 0) - - R6 BK0_IO59 PLL_FBK1 29N BK0_IO37 PLL_FBK1 18N R1 BK0_IO60 CLK_OUT0 30P BK0_IO40 CLK_OUT0 20P - - - - GND (Bank 0) - - R2 BK0_IO61 CLK_OUT1 30N BK0_IO41 CLK_OUT1 20N - GND (Bank 0) - - - - - R3 GCLK0 - LVDS Pair0P GCLK0 - LVDS Pair0P R4 GCLK1 - LVDS Pair0N GCLK1 - LVDS Pair0N R5 VCCP0 - - VCCP0 - - T3 GNDP0 - - GNDP0 - - T4 GCLK2 - LVDS Pair1P GCLK2 - LVDS Pair1P T5 GCLK3 - LVDS Pair1N GCLK3 - LVDS Pair1N - GND (Bank 1) - - - - - T2 BK1_IO0 CLK_OUT2 31P BK1_IO0 CLK_OUT2 21P 95 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.) LFX1200 LFX500 900 fpBGA Ball Signal Name Second Function LVDS Pair/ sysHSI Reserved1 Signal Name Second Function LVDS Pair/ sysHSI Reserved1 - - - - GND (Bank 1) - - T1 BK1_IO1 CLK_OUT3 31N BK1_IO1 CLK_OUT3 21N U2 BK1_IO2 SS_CLKOUT0P 32P BK1_IO2 SS_CLKOUT0P 22P - GND (Bank 1) - - - - - U1 BK1_IO3 SS_CLKOUT0N 32N BK1_IO3 SS_CLKOUT0N 22N U3 BK1_IO4 PLL_FBK2 33P BK1_IO4 PLL_FBK2 23P U4 BK1_IO5 PLL_FBK3 33N BK1_IO5 PLL_FBK3 23N V1 BK1_IO6 SS_CLKIN0P 34P BK1_IO10 SS_CLKIN0P 26P V2 BK1_IO7 SS_CLKIN0N 34N BK1_IO11 SS_CLKIN0N 26N U5 BK1_IO8 - 35P BK1_IO12 - 27P U6 BK1_IO9 - 35N BK1_IO13 - 27N V4 BK1_IO10 - 36P BK1_IO6 - 24P - GND (Bank 1) - - GND (Bank 1) - - V3 BK1_IO11 - 36N BK1_IO7 - 24N V6 BK1_IO12 PLL_RST2 37P BK1_IO20 PLL_RST2 31P V7 BK1_IO13 PLL_RST3 37N BK1_IO21 PLL_RST3 31N W1 BK1_IO14 - 38P BK1_IO8 - 25P W2 BK1_IO15 - 38N BK1_IO9 - 25N W3 BK1_IO16 - 39P BK1_IO14 - 28P - - - - GND (Bank 1) - - W4 BK1_IO17 - 39N BK1_IO15 - 28N W5 BK1_IO18 - 40P BK1_IO16 - 29P - GND (Bank 1) - - - - - W6 BK1_IO19 - 40N BK1_IO17 - 29N Y6 BK1_IO20 - 41P/HSI3 NC - - Y5 BK1_IO21 - 41N/HSI3 NC - - Y4 BK1_IO22 - 42P/HSI3 NC - - Y3 BK1_IO23 - 42N/HSI3 NC - - AA5 BK1_IO24 - 43P/HSI3 NC - - AA4 BK1_IO25 - 43N/HSI3 NC - - Y2 BK1_IO26 HSI3A_SOUTP 44P/HSI3 BK1_IO18 HSI2A_SOUTP 30P - GND (Bank 1) - - - - - Y1 BK1_IO27 HSI3A_SOUTN 44N/HSI3 BK1_IO19 HSI2A_SOUTN 30N AB7 BK1_IO28 - 45P/HSI3 NC - - AB6 BK1_IO29 - 45N/HSI3 NC - - AA2 BK1_IO30 HSI3A_SINP 46P/HSI3 BK1_IO22 HSI2A_SINP 32P - - - - GND (Bank 1) - - AA1 BK1_IO31 HSI3A_SINN 46N/HSI3 BK1_IO23 HSI2A_SINN 32N AB5 BK1_IO32 - 47P/HSI3 NC - - AB4 BK1_IO33 - 47N/HSI3 NC - - AB2 BK1_IO34 HSI3B_SOUTP 48P/HSI3 NC - - - GND (Bank 1) - - - - - 96 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.) LFX1200 LFX500 900 fpBGA Ball Signal Name Second Function LVDS Pair/ sysHSI Reserved1 Signal Name Second Function LVDS Pair/ sysHSI Reserved1 AB1 BK1_IO35 HSI3B_SOUTN 48N/HSI3 NC - - AC6 BK1_IO36 - 49P/HSI4 NC - - AC5 BK1_IO37 - 49N/HSI4 NC - - AC2 BK1_IO38 HSI3B_SINP 50P/HSI4 NC - - AC1 BK1_IO39 HSI3B_SINN 50N/HSI4 NC - - AC4 BK1_IO40 - 51P/HSI4 NC - - AC3 BK1_IO41 - 51N/HSI4 NC - - AD2 BK1_IO42 HSI4A_SOUTP 52P/HSI4 NC - - - GND (Bank 1) - - - - - AD1 BK1_IO43 HSI4A_SOUTN 52N/HSI4 NC - - AD3 BK1_IO44 - 53P/HSI4 BK1_IO32 - 37P/HSI3 AD4 BK1_IO45 - 53N/HSI4 BK1_IO33 - 37N AE2 BK1_IO46 HSI4A_SINP 54P/HSI4 BK1_IO34 - 38P AE1 BK1_IO47 HSI4A_SINN 54N/HSI4 BK1_IO35 - 38N AD5 BK1_IO48 - 55P/HSI4 BK1_IO25 - 33N AD6 BK1_IO49 VREF1 55N/HSI4 BK1_IO24 VREF1 33P AF2 BK1_IO50 HSI4B_SOUTP 56P/HSI4 BK1_IO26 HSI2B_SOUTP 34P - GND (Bank 1) - - - - - AF1 BK1_IO51 HSI4B_SOUTN 56N/HSI4 BK1_IO27 HSI2B_SOUTN 34N AE3 BK1_IO52 - 57P BK1_IO28 - 35P AE4 BK1_IO53 - 57N BK1_IO29 - 35N AG1 BK1_IO54 HSI4B_SINP 58P BK1_IO30 HSI2B_SINP 36P - - - - GND (Bank 1) - - AG2 BK1_IO55 HSI4B_SINN 58N BK1_IO31 HSI2B_SINN 36N AE5 BK1_IO56 - 59P BK1_IO36 - 39P AF4 BK1_IO57 - 59N BK1_IO37 - 39N AH1 BK1_IO58 - 60P BK1_IO38 - 40P - GND (Bank 1) - - GND (Bank 1) - - AH2 BK1_IO59 - 60N BK1_IO39 - 40N AF3 BK1_IO60 - 61P BK1_IO40 - 41P AG3 BK1_IO61 - 61N BK1_IO41 - 41N AH4 TCK - - TCK - - AJ3 TMS - - TMS - - AK3 TOE - - TOE - - AG5 BK2_IO0 - 62P BK2_IO0 - 42P AH5 BK2_IO1 - 62N BK2_IO1 - 42N AJ4 BK2_IO2 - 63P BK2_IO2 - 43P - GND (Bank 2) - - GND (Bank 2) - - AK4 BK2_IO3 - 63N BK2_IO3 - 43N AG6 BK2_IO4 - 64P BK2_IO4 - 44P AH6 BK2_IO5 - 64N BK2_IO5 - 44N AJ5 BK2_IO6 - 65P BK2_IO6 - 45P 97 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.) LFX1200 LFX500 900 fpBGA Ball Signal Name Second Function LVDS Pair/ sysHSI Reserved1 Signal Name Second Function LVDS Pair/ sysHSI Reserved1 AK5 BK2_IO7 - 65N BK2_IO7 - 45N AE7 BK2_IO8 - 66P BK2_IO8 - 46P AF7 BK2_IO9 - 66N BK2_IO9 - 46N AG7 BK2_IO10 - 67P BK2_IO10 - 47P - GND (Bank 2) - - GND (Bank 2) - - AH7 BK2_IO11 - 67N BK2_IO11 - 47N AE8 BK2_IO12 VREF2 68P BK2_IO21 VREF2 52N AF8 BK2_IO13 - 68N BK2_IO20 - 52P AJ6 BK2_IO14 - 69P BK2_IO12 - 48P AK6 BK2_IO15 - 69N BK2_IO13 - 48N AG8 BK2_IO16 - 70P BK2_IO14 - 49P AH8 BK2_IO17 - 70N BK2_IO15 - 49N AJ7 BK2_IO18 - 71P BK2_IO16 - 50P - GND (Bank 2) - - - - - AK7 BK2_IO19 - 71N BK2_IO17 - 50N AF9 BK2_IO20 - 72P BK2_IO18 - 51P - - - - GND (Bank 2) - - AG9 BK2_IO21 - 72N BK2_IO19 - 51N AJ8 BK2_IO22 - 73P NC - - AK8 BK2_IO23 - 73N NC - - AD10 BK2_IO24 - 74P NC - - AE10 BK2_IO25 - 74N NC - - AJ9 BK2_IO26 - 75P NC - - - GND (Bank 2) - - - - - AK9 BK2_IO27 - 75N NC - - AF10 BK2_IO28 - 76P NC - - AG10 BK2_IO29 - 76N NC - - AK10 BK2_IO30 - 77P NC - - AJ10 BK2_IO31 - 77N NC - - AE11 BK2_IO32 - 78P NC - - AF11 BK2_IO33 - 78N NC - - AG11 BK2_IO34 - 79P NC - - - GND (Bank 2) - - - - - AH11 BK2_IO35 - 79N NC - - AE12 BK2_IO36 - 80P NC - - AF12 BK2_IO37 - 80N NC - - AJ11 BK2_IO38 - 81P NC - - AK11 BK2_IO39 - 81N NC - - AG12 BK2_IO40 - 82P NC - - AH12 BK2_IO41 - 82N NC - - AK12 BK2_IO42 - 83P BK2_IO22 - 53P - GND (Bank 2) - - - - - 98 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.) LFX1200 LFX500 900 fpBGA Ball Signal Name Second Function LVDS Pair/ sysHSI Reserved1 Signal Name Second Function LVDS Pair/ sysHSI Reserved1 AJ12 BK2_IO43 - 83N BK2_IO23 - 53N AD13 BK2_IO44 - 84P BK2_IO24 - 54P AE13 BK2_IO45 - 84N BK2_IO25 - 54N AK13 BK2_IO46 - 85P BK2_IO26 - 55P - - - - GND (Bank 2) - - AJ13 BK2_IO47 - 85N BK2_IO27 - 55N AG13 BK2_IO48 - 86P BK2_IO28 - 56P AH13 BK2_IO49 - 86N BK2_IO29 - 56N AE14 BK2_IO50 - 87P BK2_IO30 - 57P - GND (Bank 2) - - - - - AF14 BK2_IO51 - 87N BK2_IO31 - 57N AG14 BK2_IO52 - 88P BK2_IO32 - 58P AH14 BK2_IO53 - 88N BK2_IO33 - 58N AJ14 BK2_IO54 - 89P BK2_IO34 - 59P - - - - GND (Bank 2) - - AK14 BK2_IO55 - 89N BK2_IO35 - 59N AE15 BK2_IO56 - 90P BK2_IO36 - 60P AF15 BK2_IO57 - 90N BK2_IO37 - 60N AG15 BK2_IO58 - 91P BK2_IO38 - 61P - GND (Bank 2) - - - - - AH15 BK2_IO59 - 91N BK2_IO39 - 61N AJ15 BK2_IO60 - 92P BK2_IO40 - 62P AK15 BK2_IO61 - 92N BK2_IO41 - 62N - GND (Bank 2) - - GND (Bank 2) - - - GND (Bank 3) - - GND (Bank 3) - - AK16 BK3_IO0 - 93P BK3_IO0 - 63P AJ16 BK3_IO1 - 93N BK3_IO1 - 63N AH16 BK3_IO2 - 94P BK3_IO2 - 64P - GND (Bank 3) - - - - - AG16 BK3_IO3 - 94N BK3_IO3 - 64N AF16 BK3_IO4 - 95P BK3_IO4 - 65P AE16 BK3_IO5 - 95N BK3_IO5 - 65N AK17 BK3_IO6 - 96P BK3_IO6 - 66P - - - - GND (Bank 3) - - AJ17 BK3_IO7 - 96N BK3_IO7 - 66N AH17 BK3_IO8 - 97P BK3_IO8 - 67P AG17 BK3_IO9 - 97N BK3_IO9 - 67N AF17 BK3_IO10 - 98P BK3_IO10 - 68P - GND (Bank 3) - - - - - AE17 BK3_IO11 - 98N BK3_IO11 - 68N AH18 BK3_IO12 - 99P BK3_IO12 - 69P AG18 BK3_IO13 - 99N BK3_IO13 - 69N 99 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.) LFX1200 LFX500 900 fpBGA Ball Signal Name Second Function LVDS Pair/ sysHSI Reserved1 Signal Name Second Function LVDS Pair/ sysHSI Reserved1 AJ18 BK3_IO14 - 100P BK3_IO14 - 70P - - - - GND (Bank 3) - - AK18 BK3_IO15 - 100N BK3_IO15 - 70N AE18 BK3_IO16 - 101P BK3_IO16 - 71P AD18 BK3_IO17 - 101N BK3_IO17 - 71N AJ19 BK3_IO18 - 102P BK3_IO18 - 72P - GND (Bank 3) - - - - - AK19 BK3_IO19 - 102N BK3_IO19 - 72N AH19 BK3_IO20 - 103P NC - - AG19 BK3_IO21 - 103N NC - - AK20 BK3_IO22 - 104P NC - - AJ20 BK3_IO23 - 104N NC - - AF19 BK3_IO24 - 105P NC - - AE19 BK3_IO25 - 105N NC - - AH20 BK3_IO26 - 106P NC - - - GND (Bank 3) - - - - - AG20 BK3_IO27 - 106N NC - - AF20 BK3_IO28 - 107P NC - - AE20 BK3_IO29 - 107N NC - - AJ21 BK3_IO30 - 108P NC - - AK21 BK3_IO31 - 108N NC - - AG21 BK3_IO32 - 109P NC - - AF21 BK3_IO33 - 109N NC - - AK22 BK3_IO34 - 110P NC - - - GND (Bank 3) - - - - - AJ22 BK3_IO35 - 110N NC - - AE21 BK3_IO36 - 111P NC - - AD21 BK3_IO37 - 111N NC - - AG22 BK3_IO38 - 112P NC - - AF22 BK3_IO39 - 112N NC - - AG23 BK3_IO40 - 113P BK3_IO22 - 74P - - - - GND (Bank 3) - - AH23 BK3_IO41 - 113N BK3_IO23 - 74N AJ23 BK3_IO42 - 114P BK3_IO24 - 75P - GND (Bank 3) - - - - - AK23 BK3_IO43 - 114N BK3_IO25 - 75N AF23 BK3_IO44 - 115P BK3_IO26 - 76P AE23 BK3_IO45 - 115N BK3_IO27 - 76N AJ24 BK3_IO46 - 116P BK3_IO28 - 77P AK24 BK3_IO47 - 116N BK3_IO29 - 77N AH24 BK3_IO48 - 117P BK3_IO21 - 73N AG24 BK3_IO49 VREF3 117N BK3_IO20 VREF3 73P 100 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.) LFX1200 LFX500 900 fpBGA Ball Signal Name Second Function LVDS Pair/ sysHSI Reserved1 Signal Name Second Function LVDS Pair/ sysHSI Reserved1 AJ25 BK3_IO50 - 118P BK3_IO30 - 78P - GND (Bank 3) - - GND (Bank 3) - - AK25 BK3_IO51 - 118N BK3_IO31 - 78N AF24 BK3_IO52 - 119P BK3_IO32 - 79P AE24 BK3_IO53 - 119N BK3_IO33 - 79N AK26 BK3_IO54 - 120P BK3_IO34 - 80P AJ26 BK3_IO55 - 120N BK3_IO35 - 80N AH25 BK3_IO56 - 121P BK3_IO36 - 81P AG25 BK3_IO57 - 121N BK3_IO37 - 81N AK27 BK3_IO58 - 122P BK3_IO38 - 82P - GND (Bank 3) - - GND (Bank 3) - - AJ27 BK3_IO59 - 122N BK3_IO39 - 82N AG26 BK3_IO60 - 123P BK3_IO40 - 83P AH26 BK3_IO61 - 123N BK3_IO41 - 83N AK28 GSR - - GSR - - AJ28 DXP - - DXP - - AH27 DXN - - DXN - - AG28 BK4_IO0 - 124P BK4_IO0 - 84P AF27 BK4_IO1 - 124N BK4_IO1 - 84N AF28 BK4_IO2 - 125P BK4_IO2 - 85P/HSI3 - GND (Bank 4) - - GND (Bank 4) - - AE26 BK4_IO3 - 125N BK4_IO3 - 85N/HSI3 AE27 BK4_IO4 - 126P BK4_IO4 - 86P/HSI3 AE28 BK4_IO5 - 126N BK4_IO5 - 86N/HSI3 AH30 BK4_IO6 HSI5A_SINP 127P BK4_IO10 HSI3A_SINP 89P/HSI3 - - - - GND (Bank 4) - - AH29 BK4_IO7 HSI5A_SINN 127N BK4_IO11 HSI3A_SINN 89N/HSI3 AD25 BK4_IO8 - 128P BK4_IO12 - 90P/HSI3 AD26 BK4_IO9 - 128N BK4_IO13 - 90N/HSI3 AG29 BK4_IO10 HSI5A_SOUTP 129P/HSI5 BK4_IO14 HSI3A_SOUTP 91P/HSI3 - GND (Bank 4) - - - - - AG30 BK4_IO11 HSI5A_SOUTN 129N/HSI5 BK4_IO15 HSI3A_SOUTN 91N/HSI3 AD27 BK4_IO12 VREF4 130P/HSI5 BK4_IO17 VREF4 92N/HSI3 AD28 BK4_IO13 - 130N/HSI5 BK4_IO16 - 92P/HSI3 AF29 BK4_IO14 HSI5B_SINP 131P/HSI5 BK4_IO6 - 87P/HSI3 AF30 BK4_IO15 HSI5B_SINN 131N/HSI5 BK4_IO7 - 87N/HSI3 AC25 BK4_IO16 - 132P/HSI5 BK4_IO8 - 88P/HSI3 AC26 BK4_IO17 - 132N/HSI5 BK4_IO9 - 88N/HSI3 AE29 BK4_IO18 HSI5B_SOUTP 133P/HSI5 NC - - - GND (Bank 4) - - - - - AE30 BK4_IO19 HSI5B_SOUTN 133N/HSI5 NC - - AC28 BK4_IO20 - 134P/HSI5 NC - - 101 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.) LFX1200 LFX500 900 fpBGA Ball Signal Name Second Function LVDS Pair/ sysHSI Reserved1 Signal Name Second Function LVDS Pair/ sysHSI Reserved1 AC27 BK4_IO21 - 134N/HSI5 NC - - AD29 BK4_IO22 HSI6A_SINP 135P/HSI5 NC - - AD30 BK4_IO23 HSI6A_SINN 135N/HSI5 NC - - AB24 BK4_IO24 - 136P/HSI5 NC - - AB25 BK4_IO25 - 136N/HSI5 NC - - AC29 BK4_IO26 HSI6A_SOUTP 137P/HSI6 NC - - - GND (Bank 4) - - - - - AC30 BK4_IO27 HSI6A_SOUTN 137N/HSI6 NC - - AB27 BK4_IO28 - 138P/HSI6 NC - - AB26 BK4_IO29 - 138N/HSI6 NC - - AB30 BK4_IO30 HSI6B_SINP 139P/HSI6 BK4_IO18 HSI3B_SINP 93P - - - - GND (Bank 4) - - AB29 BK4_IO31 HSI6B_SINN 139N/HSI6 BK4_IO19 HSI3B_SINN 93N AA26 BK4_IO32 - 140P/HSI6 NC - - AA27 BK4_IO33 - 140N/HSI6 NC - - AA30 BK4_IO34 HSI6B_SOUTP 141P/HSI6 BK4_IO22 HSI3B_SOUTP 95P - GND (Bank 4) - - - - - AA29 BK4_IO35 HSI6B_SOUTN 141N/HSI6 BK4_IO23 HSI3B_SOUTN 95N Y25 BK4_IO36 - 142P/HSI6 NC - - Y26 BK4_IO37 - 142N/HSI6 NC - - Y28 BK4_IO38 - 143P/HSI6 NC - - Y27 BK4_IO39 - 143N/HSI6 NC - - W25 BK4_IO40 - 144P/HSI6 NC - - W26 BK4_IO41 - 144N/HSI6 NC - - W27 BK4_IO42 - 145P BK4_IO24 - 96P - GND (Bank 4) - - - - - W28 BK4_IO43 - 145N BK4_IO25 - 96N V24 BK4_IO44 - 146P BK4_IO26 - 97P - - - - GND (Bank 4) - - V25 BK4_IO45 - 146N BK4_IO27 - 97N Y29 BK4_IO46 - 147P BK4_IO32 - 100P Y30 BK4_IO47 - 147N BK4_IO33 - 100N V27 BK4_IO48 PLL_RST4 148P BK4_IO20 PLL_RST4 94P V28 BK4_IO49 PLL_RST5 148N BK4_IO21 PLL_RST5 94N W29 BK4_IO50 - 149P BK4_IO34 - 101P - GND (Bank 4) - - GND (Bank 4) - - W30 BK4_IO51 - 149N BK4_IO35 - 101N U25 BK4_IO52 - 150P BK4_IO28 - 98P U26 BK4_IO53 - 150N BK4_IO29 - 98N V29 BK4_IO54 SS_CLKIN1P 151P BK4_IO30 SS_CLKIN1P 99P V30 BK4_IO55 SS_CLKIN1N 151N BK4_IO31 SS_CLKIN1N 99N U28 BK4_IO56 PLL_FBK4 152P BK4_IO36 PLL_FBK4 102P 102 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.) LFX1200 LFX500 900 fpBGA Ball Signal Name Second Function LVDS Pair/ sysHSI Reserved1 Signal Name Second Function LVDS Pair/ sysHSI Reserved1 U27 BK4_IO57 PLL_FBK5 152N BK4_IO37 PLL_FBK5 102N U29 BK4_IO58 SS_CLKOUT1P 153P BK4_IO38 SS_CLKOUT1P 103P - GND (Bank 4) -- - - - - U30 BK4_IO59 SS_CLKOUT1N 153N BK4_IO39 SS_CLKOUT1N 103N T30 BK4_IO60 CLK_OUT4 154P BK4_IO40 CLK_OUT4 104P - - - - GND (Bank 4) - - T29 BK4_IO61 CLK_OUT5 154N BK4_IO41 CLK_OUT5 104N - GND (Bank 4) - - - - - T28 GCLK4 - LVDS Pair2P GCLK4 - LVDS Pair2P T27 GCLK5 - LVDS Pair2N GCLK5 - LVDS Pair2N T26 VCCP1 - - VCCP1 - - R28 GNDP1 - - GNDP1 - - R27 GCLK6 - LVDS Pair3P GCLK6 - LVDS Pair3P R26 GCLK7 - LVDS Pair3N GCLK7 - LVDS Pair3N - GND (Bank 5) - - - - - R29 BK5_IO0 CLK_OUT6 155P BK5_IO0 CLK_OUT6 105P - - - - GND (Bank 5) - - R30 BK5_IO1 CLK_OUT7 155N BK5_IO1 CLK_OUT7 105N P30 BK5_IO2 PLL_FBK6 156P BK5_IO4 PLL_FBK6 107P - GND (Bank 5) - - GND (Bank 5) - - P29 BK5_IO3 PLL_FBK7 156N BK5_IO7 PLL_FBK7 108N P27 BK5_IO4 - 157P/HSI7 BK5_IO2 - 106P P28 BK5_IO5 - 157N/HSI7 BK5_IO5 - 107N P26 BK5_IO6 PLL_RST6 158P/HSI7 BK5_IO6 PLL_RST6 108P P25 BK5_IO7 PLL_RST7 158N/HSI7 BK5_IO3 PLL_RST7 106N N27 BK5_IO8 - 159P/HSI7 BK5_IO8 - 109P/HSI4 N28 BK5_IO9 - 159N/HSI7 BK5_IO9 - 109N/HSI4 N29 BK5_IO10 HSI7A_SINP 160P/HSI7 BK5_IO10 HSI4A_SINP 110P/HSI4 - GND (Bank 5) - - - - - N30 BK5_IO11 HSI7A_SINN 160N/HSI7 BK5_IO11 HSI4A_SINN 110N/HSI4 N25 BK5_IO12 - 161P/HSI7 BK5_IO12 - 111P/HSI4 N24 BK5_IO13 - 161N/HSI7 BK5_IO13 - 111N/HSI4 M29 BK5_IO14 HSI7A_SOUTP 162P/HSI7 BK5_IO14 HSI4A_SOUTP 112P/HSI4 - - - - GND (Bank 5) - - M30 BK5_IO15 HSI7A_SOUTN 162N/HSI7 BK5_IO15 HSI4A_SOUTN 112N/HSI4 M28 BK5_IO16 - 163P/HSI7 BK5_IO16 - 113P/HSI4 M27 BK5_IO17 - 163N/HSI7 BK5_IO17 - 113N/HSI4 L30 BK5_IO18 HSI7B_SINP 164P/HSI7 BK5_IO18 HSI4B_SINP 114P/HSI4 - GND (Bank 5) - - - - - L29 BK5_IO19 HSI7B_SINN 164N/HSI7 BK5_IO19 HSI4B_SINN 114N/HSI4 M26 BK5_IO20 - 165P/HSI8 BK5_IO20 - 115P/HSI4 M25 BK5_IO21 - 165N/HSI8 BK5_IO21 - 115N/HSI4 103 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.) LFX1200 LFX500 900 fpBGA Ball Signal Name Second Function LVDS Pair/ sysHSI Reserved1 Signal Name Second Function LVDS Pair/ sysHSI Reserved1 K30 BK5_IO22 HSI7B_SOUTP 166P/HSI8 BK5_IO22 HSI4B_SOUTP 116P/HSI4 - - - - GND (Bank 5) - - K29 BK5_IO23 HSI7B_SOUTN 166N/HSI8 BK5_IO23 HSI4B_SOUTN 116N/HSI4 L28 BK5_IO24 - 167P/HSI8 BK5_IO24 - 117P/HSI5 L27 BK5_IO25 - 167N/HSI8 BK5_IO25 - 117N/HSI5 L26 BK5_IO26 HSI8A_SINP 168P/HSI8 BK5_IO26 HSI5A_SINP 118P/HSI5 - GND (Bank 5) - - - - - L25 BK5_IO27 HSI8A_SINN 168N/HSI8 BK5_IO27 HSI5A_SINN 118N/HSI5 K27 BK5_IO28 - 169P/HSI8 BK5_IO28 - 119P/HSI5 K26 BK5_IO29 - 169N/HSI8 BK5_IO29 - 119N/HSI5 J30 BK5_IO30 HSI8A_SOUTP 170P/HSI8 BK5_IO30 HSI5A_SOUTP 120P/HSI5 - - - - GND (Bank 5) - - J29 BK5_IO31 HSI8A_SOUTN 170N/HSI8 BK5_IO31 HSI5A_SOUTN 120N/HSI5 J26 BK5_IO32 - 171P/HSI8 NC - - J27 BK5_IO33 - 171N/HSI8 NC - - H30 BK5_IO34 HSI8B_SINP 172P/HSI8 NC - - - GND (Bank 5) - - - - - H29 BK5_IO35 HSI8B_SINN 172N/HSI8 NC - - J25 BK5_IO36 - 173P/HSI9 NC - - J24 BK5_IO37 - 173N/HSI9 NC - - G30 BK5_IO38 HSI8B_SOUTP 174P/HSI9 NC - - G29 BK5_IO39 HSI8B_SOUTN 174N/HSI9 NC - - H27 BK5_IO40 - 175P/HSI9 NC - - H28 BK5_IO41 - 175N/HSI9 NC - - F30 BK5_IO42 HSI9A_SINP 176P/HSI9 NC - - - GND (Bank 5) - - - - - F29 BK5_IO43 HSI9A_SINN 176N/HSI9 NC - - G27 BK5_IO44 - 177P/HSI9 NC - - G28 BK5_IO45 - 177N/HSI9 NC - - E30 BK5_IO46 HSI9A_SOUTP 178P/HSI9 NC - - E29 BK5_IO47 HSI9A_SOUTN 178N/HSI9 NC - - H26 BK5_IO48 - 179P/HSI9 BK5_IO33 - 121N/HSI5 H25 BK5_IO49 VREF5 179N/HSI9 BK5_IO32 VREF5 121P/HSI5 D30 BK5_IO50 HSI9B_SINP 180P/HSI9 BK5_IO34 HSI5B_SINP 122P/HSI5 - GND (Bank 5) - - - - - D29 BK5_IO51 HSI9B_SINN 180N/HSI9 BK5_IO35 HSI5B_SINN 122N/HSI5 F28 BK5_IO52 - 181P BK5_IO36 - 123P/HSI5 F27 BK5_IO53 - 181N BK5_IO37 - 123N/HSI5 C30 BK5_IO54 HSI9B_SOUTP 182P BK5_IO38 HSI5B_SOUTP 124P/HSI5 - - - - GND (Bank 5) - - C29 BK5_IO55 HSI9B_SOUTN 182N BK5_IO39 HSI5B_SOUTN 124N/HSI5 G26 BK5_IO56 - 183P NC - - 104 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.) LFX1200 LFX500 900 fpBGA Ball Signal Name Second Function LVDS Pair/ sysHSI Reserved1 Signal Name Second Function LVDS Pair/ sysHSI Reserved1 G25 BK5_IO57 - 183N NC - - F26 BK5_IO58 - 184P NC - - - GND (Bank 5) - - - - - E28 BK5_IO59 - 184N NC - - E27 BK5_IO60 - 185P BK5_IO40 - 125P D28 BK5_IO61 - 185N BK5_IO41 - 125N C27 CFG0 - - CFG0 - - B28 DONE - - DONE - - A28 PROGRAMb - - PROGRAMb - - D26 BK6_IO0 INITb 186P BK6_IO0 INITb 126P C26 BK6_IO1 CCLK 186N BK6_IO1 CCLK 126N B27 BK6_IO2 - 187P BK6_IO2 - 127P - GND (Bank 6) - - GND (Bank 6) - 127N A27 BK6_IO3 - 187N BK6_IO3 - D25 BK6_IO4 CSb 188P BK6_IO4 CSb 128P C25 BK6_IO5 Read 188N BK6_IO5 READ 128N B26 BK6_IO6 - 189P BK6_IO6 - 129P A26 BK6_IO7 - 189N BK6_IO7 - 129N F24 BK6_IO8 - 190P BK6_IO8 - 130P E24 BK6_IO9 - 190N BK6_IO9 - 130N A25 BK6_IO10 - 191P BK6_IO10 - 131P - GND (Bank 6) - - GND (Bank 6) - - B25 BK6_IO11 - 191N BK6_IO11 - 131N D24 BK6_IO12 VREF6 192P BK6_IO21 VREF6 136N C24 BK6_IO13 - 192N BK6_IO20 - 136P A24 BK6_IO14 - 193P BK6_IO12 - 132P B24 BK6_IO15 - 193N BK6_IO13 - 132N F23 BK6_IO16 - 194P BK6_IO14 - 133P E23 BK6_IO17 - 194N BK6_IO15 - 133N A23 BK6_IO18 - 195P BK6_IO16 - 134P - GND (Bank 6) - - - - - B23 BK6_IO19 - 195N BK6_IO17 - 134N C23 BK6_IO20 - 196P NC - - D23 BK6_IO21 - 196N NC - - E22 BK6_IO22 - 197P NC - - D22 BK6_IO23 - 197N NC - - G21 BK6_IO24 - 198P NC - - F21 BK6_IO25 - 198N NC - - B22 BK6_IO26 - 199P NC - - - GND (Bank 6) - - - - - A22 BK6_IO27 - 199N NC - - E21 BK6_IO28 - 200P NC - - 105 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.) LFX1200 LFX500 900 fpBGA Ball Signal Name Second Function LVDS Pair/ sysHSI Reserved1 Signal Name Second Function LVDS Pair/ sysHSI Reserved1 D21 BK6_IO29 - 200N NC - - A21 BK6_IO30 - 201P NC - - B21 BK6_IO31 - 201N NC - - F20 BK6_IO32 DATA7 202P BK6_IO18 DATA7 135P - - - - GND (Bank 6) - - E20 BK6_IO33 DATA6 202N BK6_IO19 DATA6 135N D20 BK6_IO34 - 203P NC - - - GND (Bank 6) - C20 BK6_IO35 - - - - 203N NC - - F19 BK6_IO36 DATA5 204P BK6_IO22 DATA5 137P E19 BK6_IO37 DATA4 204N BK6_IO23 DATA4 137N B20 BK6_IO38 - 205P NC - - A20 BK6_IO39 - 205N NC - - D19 BK6_IO40 - 206P NC - - C19 BK6_IO41 - 206N NC - - A19 BK6_IO42 - 207P NC - - - GND (Bank 6) - - - - - B19 BK6_IO43 - 207N NC - - G18 BK6_IO44 - 208P BK6_IO24 - 138P F18 BK6_IO45 - 208N BK6_IO25 - 138N A18 BK6_IO46 - 209P BK6_IO32 - 142P B18 BK6_IO47 - 209N BK6_IO33 - 142N D18 BK6_IO48 - 210P BK6_IO34 - 143P - - - - GND (Bank 6) - - C18 BK6_IO49 - 210N BK6_IO35 - 143N F17 BK6_IO50 DATA3 211P BK6_IO26 DATA3 139P - GND (Bank 6) - - GND (Bank 6) - - E17 BK6_IO51 DATA2 211N BK6_IO27 DATA2 139N D17 BK6_IO52 - 212P BK6_IO28 - 140P C17 BK6_IO53 - 212N BK6_IO29 - 140N B17 BK6_IO54 DATA1 213P BK6_IO30 DATA1 141P A17 BK6_IO55 DATA0 213N BK6_IO31 DATA0 141N F16 BK6_IO56 - 214P BK6_IO36 - 144P E16 BK6_IO57 - 214N BK6_IO37 - 144N D16 BK6_IO58 - 215P BK6_IO38 - 145P - GND (Bank 6) - - - - - C16 BK6_IO59 - 215N BK6_IO39 - 145N B16 BK6_IO60 - 216P BK6_IO40 - 146P A16 BK6_IO61 - 216N BK6_IO41 - 146N - GND (Bank 6) - - GND (Bank 6) - - - GND (Bank 7) - - GND (Bank 7) - - A15 BK7_IO0 - 217P BK7_IO0 - 147P 106 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.) LFX1200 LFX500 900 fpBGA Ball Signal Name Second Function LVDS Pair/ sysHSI Reserved1 Signal Name Second Function LVDS Pair/ sysHSI Reserved1 B15 BK7_IO1 - 217N BK7_IO1 - 147N BK7_IO2 C15 BK7_IO2 - 218P - GND (Bank 7) - - - 148P - - D15 BK7_IO3 - 218N BK7_IO3 - 148N E15 BK7_IO4 - 219P BK7_IO4 - 149P F15 BK7_IO5 - 219N BK7_IO5 - 149N A14 BK7_IO6 - 220P BK7_IO6 - 150P - - - - GND (Bank 7) - - B14 BK7_IO7 - 220N BK7_IO7 - 150N C14 BK7_IO8 - 221P BK7_IO8 - 151P D14 BK7_IO9 - 221N BK7_IO9 - 151N E14 BK7_IO10 - 222P BK7_IO10 - 152P - GND (Bank 7) - - - - 152N F14 BK7_IO11 - 222N BK7_IO11 - C13 BK7_IO12 - 223P BK7_IO12 - 153P D13 BK7_IO13 - 223N BK7_IO13 - 153N B13 BK7_IO14 - 224P BK7_IO14 - 154P - - - - GND (Bank 7) - - A13 BK7_IO15 - 224N BK7_IO15 - 154N F13 BK7_IO16 - 225P BK7_IO16 - 155P G13 BK7_IO17 - 225N BK7_IO17 - 155N A12 BK7_IO18 - 226P BK7_IO18 - 156P - GND (Bank 7) - - - - - B12 BK7_IO19 - 226N BK7_IO19 - 156N C12 BK7_IO20 - 227P NC - - D12 BK7_IO21 - 227N NC - - A11 BK7_IO22 - 228P NC - - B11 BK7_IO23 - 228N NC - - E12 BK7_IO24 - 229P NC - - F12 BK7_IO25 - 229N NC - - C11 BK7_IO26 - 230P NC - - - GND (Bank 7) - - - - - D11 BK7_IO27 - 230N NC - - E11 BK7_IO28 - 231P NC - - F11 BK7_IO29 - 231N NC - - B10 BK7_IO30 - 232P NC - - A10 BK7_IO31 - 232N NC - - D10 BK7_IO32 - 233P NC - - E10 BK7_IO33 - 233N NC - - A9 BK7_IO34 - 234P NC - - - GND (Bank 7) - - - - - B9 BK7_IO35 - 234N NC - - 107 Lattice Semiconductor ispXPGA Family Data Sheet ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.) LFX1200 LFX500 900 fpBGA Ball Signal Name Second Function LVDS Pair/ sysHSI Reserved1 Signal Name Second Function LVDS Pair/ sysHSI Reserved1 F10 BK7_IO36 - 235P NC - - G10 BK7_IO37 - 235N NC - - A8 BK7_IO38 - 236P NC - - B8 BK7_IO39 - 236N NC - - D9 BK7_IO40 - 237P BK7_IO22 - 158P - - - - GND (Bank 7) - - E9 BK7_IO41 - 237N BK7_IO23 - 158N BK7_IO24 A7 BK7_IO42 - 238P - GND (Bank 7) - - B7 BK7_IO43 - 238N C8 BK7_IO44 - 239P - 159P - - BK7_IO25 - 159N BK7_IO26 - 160P D8 BK7_IO45 - 239N BK7_IO27 - 160N A6 BK7_IO46 - 240P BK7_IO21 - 157N B6 BK7_IO47 VREF7 240N BK7_IO20 VREF7 157P E8 BK7_IO48 - 241P BK7_IO28 - 161P F8 BK7_IO49 - 241N BK7_IO29 - 161N C7 BK7_IO50 - 242P BK7_IO30 - 162P - GND (Bank 7) - - GND (Bank 7) - - D7 BK7_IO51 - 242N BK7_IO31 - 162N E7 BK7_IO52 - 243P BK7_IO32 - 163P F7 BK7_IO53 - 243N BK7_IO33 - 163N A5 BK7_IO54 - 244P BK7_IO34 - 164P B5 BK7_IO55 - 244N BK7_IO35 - 164N C6 BK7_IO56 - 245P BK7_IO36 - 165P D6 BK7_IO57 - 245N BK7_IO37 - 165N D5 BK7_IO58 - 246P BK7_IO38 - 166P - GND (Bank 7) - - GND (Bank 7) - - C5 BK7_IO59 - 246N BK7_IO39 - 166N B4 BK7_IO60 - 247P BK7_IO40 - 167P A4 BK7_IO61 - 247N BK7_IO41 - 167N A3 TDO - - TDO - - B3 VCCJ - - VCCJ - - C4 TDI - - TDI - - 1. If a sysHSI Block is used, the indicated sysHSI reserved pins are unavailable for general purpose I/O use. 108 Lattice Semiconductor ispXPGA Family Data Sheet Part Number Description LFX XXXX X X – XX XXXXX X Device Family LFX Grade C = Commercial I = Industrial Gates 125 = 139K Gates 200 = 210K Gates 500 = 476K Gates 1200 = 1.25M Gates Package F256 = 256-Ball fpBGA FH516 = 516-Ball fpBGA (with Heat Spreader) F516 = 516-Ball fpBGA (without Heat Spreader) FE680 = 680-Ball fpSBGA F900 = 900-Ball fpBGA FN256 = Lead-Free 256-Ball fpBGA FN900 = Lead-Free 900-Ball fpBGA1 sysHSI Support Blank = Supports sysHSI E = No sysHSI Support Power Supply Voltage B = 2.5/3.3V C = 1.8V Speed 5 = Fastest 4 3 = Slowest 1. Select products only. See Ordering Information tables below for specific support. Ordering Information Conventional Packaging Commercial Part Number Gates Voltage Speed Grade Package Balls LFX125B-05F256C 139K 2.5/3.3 -5 fpBGA 256 LFX125B-04F256C 139K 2.5/3.3 -4 fpBGA 256 LFX125B-03F256C 139K 2.5/3.3 -3 fpBGA 256 LFX125C-04F256C 139K 1.8 -4 fpBGA 256 LFX125C-03F256C 139K 1.8 -3 fpBGA 256 LFX125B-05F516C 139K 2.5/3.3 -5 fpBGA 516 LFX125B-04F516C 139K 2.5/3.3 -4 fpBGA 516 LFX125B-03F516C 139K 2.5/3.3 -3 fpBGA 516 LFX125C-04F516C 139K 1.8 -4 fpBGA 516 LFX125C-03F516C 139K 1.8 -3 fpBGA 516 1 LFX125B-05FH516C 139K 2.5/3.3 -5 fpBGA 516 LFX125B-04FH516C1 139K 2.5/3.3 -4 fpBGA 516 1 LFX125B-03FH516C 139K 2.5/3.3 -3 fpBGA 516 LFX125C-04FH516C1 139K 1.8 -4 fpBGA 516 LFX125C-03FH516C1 139K 1.8 -3 fpBGA 516 LFX200B-05F256C 210K 2.5/3.3 -5 fpBGA 256 LFX200B-04F256C 210K 2.5/3.3 -4 fpBGA 256 LFX200B-03F256C 210K 2.5/3.3 -3 fpBGA 256 LFX200C-04F256C 210K 1.8 -4 fpBGA 256 LFX200C-03F256C 210K 1.8 -3 fpBGA 256 109 Lattice Semiconductor ispXPGA Family Data Sheet Commercial (Cont.) Part Number Gates Voltage Speed Grade Package Balls LFX200B-05F516C 210K 2.5/3.3 -5 fpBGA 516 LFX200B-04F516C 210K 2.5/3.3 -4 fpBGA 516 LFX200B-03F516C 210K 2.5/3.3 -3 fpBGA 516 LFX200C-04F516C 210K 1.8 -4 fpBGA 516 LFX200C-03F516C 210K 1.8 -3 fpBGA 516 1 LFX200B-05FH516C 210K 2.5/3.3 -5 fpBGA 516 LFX200B-04FH516C1 210K 2.5/3.3 -4 fpBGA 516 1 LFX200B-03FH516C 210K 2.5/3.3 -3 fpBGA 516 LFX200C-04FH516C1 210K 1.8 -4 fpBGA 516 LFX200C-03FH516C1 210K 1.8 -3 fpBGA 516 LFX500B-05F516C 476K 2.5/3.3 -5 fpBGA 516 LFX500B-04F516C 476K 2.5/3.3 -4 fpBGA 516 LFX500B-03F516C 476K 2.5/3.3 -3 fpBGA 516 LFX500C-04F516C 476K 1.8 -4 fpBGA 516 LFX500C-03F516C 476K 1.8 -3 fpBGA 516 1 LFX500B-05FH516C 476K 2.5/3.3 -5 fpBGA 516 LFX500B-04FH516C1 476K 2.5/3.3 -4 fpBGA 516 LFX500B-03FH516C1 476K 2.5/3.3 -3 fpBGA 516 LFX500C-04FH516C1 476K 1.8 -4 fpBGA 516 LFX500C-03FH516C1 476K 1.8 -3 fpBGA 516 LFX500B-05F900C 476K 2.5/3.3 -5 fpBGA 900 LFX500B-04F900C 476K 2.5/3.3 -4 fpBGA 900 LFX500B-03F900C 476K 2.5/3.3 -3 fpBGA 900 LFX500C-04F900C 476K 1.8 -4 fpBGA 900 LFX500C-03F900C 476K 1.8 -3 fpBGA 900 LFX1200B-05F900C 1.25M 2.5/3.3 -5 fpBGA 900 LFX1200B-04F900C 1.25M 2.5/3.3 -4 fpBGA 900 LFX1200B-03F900C 1.25M 2.5/3.3 -3 fpBGA 900 LFX1200C-04F900C 1.25M 1.8 -4 fpBGA 900 LFX1200C-03F900C 1.25M 1.8 -3 fpBGA 900 LFX1200B-05FE680C 1.25M 2.5/3.3 -5 fpSBGA 680 LFX1200B-04FE680C 1.25M 2.5/3.3 -4 fpSBGA 680 LFX1200B-03FE680C 1.25M 2.5/3.3 -3 fpSBGA 680 LFX1200C-04FE680C 1.25M 1.8 -4 fpSBGA 680 LFX1200C-03FE680C 1.25M 1.8 -3 fpSBGA 680 1. FH516 package was converted to F516 via PCN# 09A-08. 110 Lattice Semiconductor ispXPGA Family Data Sheet “E-Series” Commercial Part Number Gates Voltage Speed Grade Package Balls LFX125EB-05F256C 139K 2.5/3.3 -5 fpBGA 256 LFX125EB-04F256C 139K 2.5/3.3 -4 fpBGA 256 LFX125EB-03F256C 139K 2.5/3.3 -3 fpBGA 256 LFX125EC-04F256C 139K 1.8 -4 fpBGA 256 LFX125EC-03F256C 139K 1.8 -3 fpBGA 256 LFX125EB-05F516C 139K 2.5/3.3 -5 fpBGA 516 LFX125EB-04F516C 139K 2.5/3.3 -4 fpBGA 516 LFX125EB-03F516C 139K 2.5/3.3 -3 fpBGA 516 LFX125EC-04F516C 139K 1.8 -4 fpBGA 516 LFX125EC-03F516C 139K 1.8 -3 fpBGA 516 1 LFX125EB-05FH516C 139K 2.5/3.3 -5 fpBGA 516 LFX125EB-04FH516C1 139K 2.5/3.3 -4 fpBGA 516 1 LFX125EB-03FH516C 139K 2.5/3.3 -3 fpBGA 516 LFX125EC-04FH516C1 139K 1.8 -4 fpBGA 516 LFX125EC-03FH516C1 139K 1.8 -3 fpBGA 516 LFX200EB-05F256C 210K 2.5/3.3 -5 fpBGA 256 LFX200EB-04F256C 210K 2.5/3.3 -4 fpBGA 256 LFX200EB-03F256C 210K 2.5/3.3 -3 fpBGA 256 LFX200EC-04F256C 210K 1.8 -4 fpBGA 256 LFX200EC-03F256C 210K 1.8 -3 fpBGA 256 LFX200EB-05F516C 210K 2.5/3.3 -5 fpBGA 516 LFX200EB-04F516C 210K 2.5/3.3 -4 fpBGA 516 LFX200EB-03F516C 210K 2.5/3.3 -3 fpBGA 516 LFX200EC-04F516C 210K 1.8 -4 fpBGA 516 LFX200EC-03F516C 210K 1.8 -3 fpBGA 516 LFX200EB-05FH516C1 210K 2.5/3.3 -5 fpBGA 516 LFX200EB-04FH516C1 210K 2.5/3.3 -4 fpBGA 516 LFX200EB-03FH516C1 210K 2.5/3.3 -3 fpBGA 516 1 LFX200EC-04FH516C 210K 1.8 -4 fpBGA 516 LFX200EC-03FH516C1 210K 1.8 -3 fpBGA 516 LFX500EB-05F516C 476K 2.5/3.3 -5 fpBGA 516 LFX500EB-04F516C 476K 2.5/3.3 -4 fpBGA 516 LFX500EB-03F516C 476K 2.5/3.3 -3 fpBGA 516 LFX500EC-04F516C 476K 1.8 -4 fpBGA 516 LFX500EC-03F516C 476K 1.8 -3 fpBGA 516 LFX500EB-05FH516C1 476K 2.5/3.3 -5 fpBGA 516 LFX500EB-04FH516C1 476K 2.5/3.3 -4 fpBGA 516 LFX500EB-03FH516C1 476K 2.5/3.3 -3 fpBGA 516 1 LFX500EC-04FH516C 476K 1.8 -4 fpBGA 516 LFX500EC-03FH516C1 476K 1.8 -3 fpBGA 516 LFX500EB-05F900C 476K 2.5/3.3 -5 fpBGA 900 LFX500EB-04F900C 476K 2.5/3.3 -4 fpBGA 900 LFX500EB-03F900C 476K 2.5/3.3 -3 fpBGA 900 LFX500EC-04F900C 476K 1.8 -4 fpBGA 900 111 Lattice Semiconductor ispXPGA Family Data Sheet “E-Series” Commercial (Cont.) Gates Voltage Speed Grade Package Balls LFX500EC-03F900C Part Number 476K 1.8 -3 fpBGA 900 LFX1200EB-05F900C 1.25M 2.5/3.3 -5 fpBGA 900 LFX1200EB-04F900C 1.25M 2.5/3.3 -4 fpBGA 900 LFX1200EB-03F900C 1.25M 2.5/3.3 -3 fpBGA 900 LFX1200EC-04F900C 1.25M 1.8 -4 fpBGA 900 LFX1200EC-03F900C 1.25M 1.8 -3 fpBGA 900 LFX1200EB-05FE680C 1.25M 2.5/3.3 -5 fpSBGA 680 LFX1200EB-04FE680C 1.25M 2.5/3.3 -4 fpSBGA 680 LFX1200EB-03FE680C 1.25M 2.5/3.3 -3 fpSBGA 680 LFX1200EC-04FE680C 1.25M 1.8 -4 fpSBGA 680 LFX1200EC-03FE680C 1.25M 1.8 -3 fpSBGA 680 1. FH516 package was converted to F516 via PCN# 09A-08. “E-Series” Industrial Part Number Gates Voltage Speed Grade Package Balls LFX125EB-04F256I 139K 2.5/3.3 -4 fpBGA 256 LFX125EB-03F256I 139K 2.5/3.3 -3 fpBGA 256 LFX125EC-03F256I 139K 1.8 -3 fpBGA 256 LFX125EB-04F516I 139K 2.5/3.3 -4 fpBGA 516 LFX125EB-03F516I 139K 2.5/3.3 -3 fpBGA 516 LFX125EC-03F516I 139K 1.8 -3 fpBGA 516 LFX125EB-04FH516I1 139K 2.5/3.3 -4 fpBGA 516 LFX125EB-03FH516I1 139K 2.5/3.3 -3 fpBGA 516 1 LFX125EC-03FH516I 139K 1.8 -3 fpBGA 516 LFX200EB-04F256I 210K 2.5/3.3 -4 fpBGA 256 LFX200EB-03F256I 210K 2.5/3.3 -3 fpBGA 256 LFX200EC-03F256I 210K 1.8 -3 fpBGA 256 LFX200EB-04F516I 210K 2.5/3.3 -4 fpBGA 516 LFX200EB-03F516I 210K 2.5/3.3 -3 fpBGA 516 LFX200EC-03F516I 210K 1.8 -3 fpBGA 516 LFX200EB-04FH516I1 210K 2.5/3.3 -4 fpBGA 516 LFX200EB-03FH516I1 210K 2.5/3.3 -3 fpBGA 516 LFX200EC-03FH516I1 210K 1.8 -3 fpBGA 516 LFX500EB-04F516I 476K 2.5/3.3 -4 fpBGA 516 LFX500EB-03F516I 476K 2.5/3.3 -3 fpBGA 516 LFX500EC-03F516I 476K 1.8 -3 fpBGA 516 LFX500EB-04FH516I1 476K 2.5/3.3 -4 fpBGA 516 LFX500EB-03FH516I1 476K 2.5/3.3 -3 fpBGA 516 LFX500EC-03FH516I1 476K 1.8 -3 fpBGA 516 LFX500EB-04F900I 476K 2.5/3.3 -4 fpBGA 900 LFX500EB-03F900I 476K 2.5/3.3 -3 fpBGA 900 LFX500EC-03F900I 476K 1.8 -3 fpBGA 900 LFX1200EB-04F900I 1.25M 2.5/3.3 -4 fpBGA 900 112 Lattice Semiconductor ispXPGA Family Data Sheet “E-Series” Industrial (Cont.) Gates Voltage Speed Grade Package Balls LFX1200EB-03F900I Part Number 1.25M 2.5/3.3 -3 fpBGA 900 LFX1200EC-03F900I 1.25M 1.8 -3 fpBGA 900 LFX1200EB-04FE680I 1.25M 2.5/3.3 -4 fpSBGA 680 LFX1200EB-03FE680I 1.25M 2.5/3.3 -3 fpSBGA 680 LFX1200EC-03FE680I 1.25M 1.8 -3 fpSBGA 680 1. FH516 package was converted to F516 via PCN# 09A-08. Lead-Free Packaging Commercial Part Number Gates Voltage Speed Grade Package Balls LFX125B-05FN256C 139K 2.5/3.3 -5 Lead-Free fpBGA 256 LFX125B-04FN256C 139K 2.5/3.3 -4 Lead-Free fpBGA 256 LFX125B-03FN256C 139K 2.5/3.3 -3 Lead-Free fpBGA 256 LFX125C-04FN256C 139K 1.8 -4 Lead-Free fpBGA 256 LFX125C-03FN256C 139K 1.8 -3 Lead-Free fpBGA 256 LFX200B-05FN256C 210K 2.5/3.3 -5 Lead-Free fpBGA 256 LFX200B-04FN256C 210K 2.5/3.3 -4 Lead-Free fpBGA 256 LFX200B-03FN256C 210K 2.5/3.3 -3 Lead-Free fpBGA 256 LFX200C-04FN256C 210K 1.8 -4 Lead-Free fpBGA 256 LFX200C-03FN256C 210K 1.8 -3 Lead-Free fpBGA 256 LFX500B-05FN900C 476K 2.5/3.3 -5 Lead-Free fpBGA 900 LFX500B-04FN900C 476K 2.5/3.3 -4 Lead-Free fpBGA 900 LFX500B-03FN900C 476K 2.5/3.3 -3 Lead-Free fpBGA 900 LFX500C-04FN900C 476K 1.8 -4 Lead-Free fpBGA 900 LFX500C-03FN900C 476K 1.8 -3 Lead-Free fpBGA 900 “E-Series” Commercial Gates Voltage Speed Grade Package Balls LFX125EB-05FN256C Part Number 139K 2.5/3.3 -5 Lead-Free fpBGA 256 LFX125EB-04FN256C 139K 2.5/3.3 -4 Lead-Free fpBGA 256 LFX125EB-03FN256C 139K 2.5/3.3 -3 Lead-Free fpBGA 256 LFX125EC-04FN256C 139K 1.8 -4 Lead-Free fpBGA 256 LFX125EC-03FN256C 139K 1.8 -3 Lead-Free fpBGA 256 LFX200EB-05FN256C 210K 2.5/3.3 -5 Lead-Free fpBGA 256 LFX200EB-04FN256C 210K 2.5/3.3 -4 Lead-Free fpBGA 256 LFX200EB-03FN256C 210K 2.5/3.3 -3 Lead-Free fpBGA 256 LFX200EC-04FN256C 210K 1.8 -4 Lead-Free fpBGA 256 LFX200EC-03FN256C 210K 1.8 -3 Lead-Free fpBGA 256 LFX500EB-05FN900C 476K 2.5/3.3 -5 Lead-Free fpBGA 900 LFX500EB-04FN900C 476K 2.5/3.3 -4 Lead-Free fpBGA 900 LFX500EB-03FN900C 476K 2.5/3.3 -3 Lead-Free fpBGA 900 LFX500EC-04FN900C 476K 1.8 -4 Lead-Free fpBGA 900 LFX500EC-03FN900C 476K 1.8 -3 Lead-Free fpBGA 900 113 Lattice Semiconductor ispXPGA Family Data Sheet “E-Series” Industrial Part Number Gates Voltage Speed Grade Package Balls LFX125EB-04FN256I 139K 2.5/3.3 -4 Lead-Free fpBGA 256 LFX125EB-03FN256I 139K 2.5/3.3 -3 Lead-Free fpBGA 256 LFX125EC-03FN256I 139K 1.8 -3 Lead-Free fpBGA 256 LFX200EB-04FN256I 210K 2.5/3.3 -4 Lead-Free fpBGA 256 LFX200EB-03FN256I 210K 2.5/3.3 -3 Lead-Free fpBGA 256 LFX200EC-03FN256I 210K 1.8 -3 Lead-Free fpBGA 256 LFX500EB-04FN900I 476K 2.5/3.3 -4 Lead-Free fpBGA 900 LFX500EB-03FN900I 476K 2.5/3.3 -3 Lead-Free fpBGA 900 LFX500EC-03FN900I 476K 1.8 -3 Lead-Free fpBGA 900 For Further Information In addition to this data sheet, the following Lattice technical notes may be helpful when designing with the ispXPGA Family: • • • • • ispXPGA sysMEM Memory Design and Usage Guidelines (TN1028) Lattice sysCLOCK PLL Design and Usage Guidelines (TN1003) sysIO Usage Guidelines for Lattice Devices (TN1000) ispXP Configuration Usage Guidelines (TN1026) sysHSI Usage Guide (TN1020) Revision History Date Version Change Summary — — Previous Lattice releases. September 2003 07 Improved typical Icc data for LFX125B/C and LFX500B/C. Improved external switching characteristics timing numbers for LFX125B/C. Improved PIC timing numbers for LFX125B/C. Improved tIOINDLY timing numbers for LFX125B/C. Improved external switching characteristics timing numbers for LFX500B/C. Improved PIC timing numbers for LFX500B/C. Improved tIOINDLY timing numbers for LFX500B/C. Enhanced CDR functionality description. Logic Signal Connections and Signal Descriptions - removed CDRLOCK, LOSS and EXLOSS descriptions. January 2004 07.1 Added lead-free package designators. June 2004 08.0 Updated CDR specifications and reference notes. Removed Source Synchronous (SS:No CAL) mode references for the sysHSI blocks. Revised Figures 16 and 24 for clarification. Clarification of VCC sysHSI Block for 1.8V devices. Updated IIL and IIH max specification. Updated LVTTL and PCI 3.3 to support 5V tolerance. Updated Global Clock Input Setup time specifications. Clarification of Serial Out LVDS test condition. Clarification of REFCLK, SS_CLKIN peak-to-peak period jitter condition. Added sysHSI Reserved pins and footnote. Removed industrial ordering part numbers. 114 Lattice Semiconductor ispXPGA Family Data Sheet Revision History (Cont.) Date Version July 2004 09.0 Added “E” Series product family. Change Summary August 2004 10.0 Final release. December 2004 10.1 Updated NC Connections table. April 2005 10.2 Clarification of IDK specification. April 2005 11.0 Select lead-free packages release. July 2005 12.0 Added lead-free 516 fpBGA ordering part numbers. April 2007 13.0 Removed lead-free 680 fpSBGA information from Part Number Description and Ordering Part Number tables. Removed lead-free 516 fpBGA for LFX125 from Ordering Part Number tables. November 2007 14.0 Removed lead-free 516 fpBGA information from Part Number Description and Ordering Part Number tables. July 2008 14.1 Added 516 fpBGA package without heat spreader to Part Number Description and Ordering Part Number tables. 115