TI LM3S8530-IBZ50-A2 Stellarisâ® lm3s8530 microcontroller Datasheet

TE X AS I NS TRUM E NTS - P RO DUCTION D ATA
Stellaris® LM3S8530 Microcontroller
D ATA SH E E T
D S -LM 3S 8530 - 7 3 9 3
C opyri ght © 2007-2010 Texas Instruments
Incorporated
Copyright
Copyright © 2007-2010 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments
Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the
property of others.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor
products and disclaimers thereto appears at the end of this data sheet.
Texas Instruments Incorporated
108 Wild Basin, Suite 350
Austin, TX 78746
http://www.ti.com/stellaris
http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm
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Stellaris® LM3S8530 Microcontroller
Table of Contents
Revision History ............................................................................................................................. 18
About This Document .................................................................................................................... 22
Audience ..............................................................................................................................................
About This Manual ................................................................................................................................
Related Documents ...............................................................................................................................
Documentation Conventions ..................................................................................................................
22
22
22
23
1
Architectural Overview .......................................................................................... 25
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
Product Features ..........................................................................................................
Target Applications ........................................................................................................
High-Level Block Diagram .............................................................................................
Functional Overview ......................................................................................................
ARM Cortex™-M3 .........................................................................................................
Motor Control Peripherals ..............................................................................................
Serial Communications Peripherals ................................................................................
System Peripherals .......................................................................................................
Memory Peripherals ......................................................................................................
Additional Features .......................................................................................................
Hardware Details ..........................................................................................................
25
31
32
34
34
34
35
37
37
38
38
2
ARM Cortex-M3 Processor Core ........................................................................... 40
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
Block Diagram .............................................................................................................. 41
Functional Description ................................................................................................... 41
Serial Wire and JTAG Debug ......................................................................................... 41
Embedded Trace Macrocell (ETM) ................................................................................. 42
Trace Port Interface Unit (TPIU) ..................................................................................... 42
ROM Table ................................................................................................................... 42
Memory Protection Unit (MPU) ....................................................................................... 42
Nested Vectored Interrupt Controller (NVIC) .................................................................... 42
3
Memory Map ........................................................................................................... 46
4
Interrupts ................................................................................................................. 48
5
JTAG Interface ........................................................................................................ 51
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.4.1
5.4.2
Block Diagram ..............................................................................................................
Functional Description ...................................................................................................
JTAG Interface Pins ......................................................................................................
JTAG TAP Controller .....................................................................................................
Shift Registers ..............................................................................................................
Operational Considerations ............................................................................................
Initialization and Configuration .......................................................................................
Register Descriptions ....................................................................................................
Instruction Register (IR) .................................................................................................
Data Registers ..............................................................................................................
52
52
52
54
55
55
58
58
58
60
6
System Control ....................................................................................................... 63
6.1
6.1.1
6.1.2
Functional Description ................................................................................................... 63
Device Identification ...................................................................................................... 63
Reset Control ................................................................................................................ 63
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6.1.3
6.1.4
6.1.5
6.2
6.3
6.4
Power Control ...............................................................................................................
Clock Control ................................................................................................................
System Control .............................................................................................................
Initialization and Configuration .......................................................................................
Register Map ................................................................................................................
Register Descriptions ....................................................................................................
66
68
72
73
73
75
7
Internal Memory ................................................................................................... 124
7.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.4
7.5
7.6
Block Diagram ............................................................................................................ 124
Functional Description ................................................................................................. 124
SRAM Memory ............................................................................................................ 124
Flash Memory ............................................................................................................. 125
Flash Memory Initialization and Configuration ............................................................... 126
Flash Programming ..................................................................................................... 126
Nonvolatile Register Programming ............................................................................... 127
Register Map .............................................................................................................. 128
Flash Register Descriptions (Flash Control Offset) ......................................................... 128
Flash Register Descriptions (System Control Offset) ...................................................... 136
8
General-Purpose Input/Outputs (GPIOs) ........................................................... 149
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.2
8.3
8.4
Functional Description ................................................................................................. 149
Data Control ............................................................................................................... 150
Interrupt Control .......................................................................................................... 151
Mode Control .............................................................................................................. 152
Commit Control ........................................................................................................... 152
Pad Control ................................................................................................................. 152
Identification ............................................................................................................... 152
Initialization and Configuration ..................................................................................... 152
Register Map .............................................................................................................. 153
Register Descriptions .................................................................................................. 155
9
General-Purpose Timers ...................................................................................... 190
9.1
9.2
9.2.1
9.2.2
9.2.3
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.4
9.5
Block Diagram ............................................................................................................
Functional Description .................................................................................................
GPTM Reset Conditions ..............................................................................................
32-Bit Timer Operating Modes ......................................................................................
16-Bit Timer Operating Modes ......................................................................................
Initialization and Configuration .....................................................................................
32-Bit One-Shot/Periodic Timer Mode ...........................................................................
32-Bit Real-Time Clock (RTC) Mode .............................................................................
16-Bit One-Shot/Periodic Timer Mode ...........................................................................
16-Bit Input Edge Count Mode .....................................................................................
16-Bit Input Edge Timing Mode ....................................................................................
16-Bit PWM Mode .......................................................................................................
Register Map ..............................................................................................................
Register Descriptions ..................................................................................................
190
191
192
192
193
197
197
198
198
199
199
200
200
201
10
Watchdog Timer ................................................................................................... 226
10.1
10.2
10.3
Block Diagram ............................................................................................................ 227
Functional Description ................................................................................................. 227
Initialization and Configuration ..................................................................................... 228
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10.4
10.5
Register Map .............................................................................................................. 228
Register Descriptions .................................................................................................. 229
11
Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 250
11.1
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.2.6
11.2.7
11.2.8
11.3
11.4
11.5
Block Diagram ............................................................................................................
Functional Description .................................................................................................
Transmit/Receive Logic ...............................................................................................
Baud-Rate Generation .................................................................................................
Data Transmission ......................................................................................................
Serial IR (SIR) .............................................................................................................
FIFO Operation ...........................................................................................................
Interrupts ....................................................................................................................
Loopback Operation ....................................................................................................
IrDA SIR block ............................................................................................................
Initialization and Configuration .....................................................................................
Register Map ..............................................................................................................
Register Descriptions ..................................................................................................
251
251
251
252
253
253
254
254
255
255
255
256
257
12
Synchronous Serial Interface (SSI) .................................................................... 291
12.1
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.3
12.4
12.5
Block Diagram ............................................................................................................
Functional Description .................................................................................................
Bit Rate Generation .....................................................................................................
FIFO Operation ...........................................................................................................
Interrupts ....................................................................................................................
Frame Formats ...........................................................................................................
Initialization and Configuration .....................................................................................
Register Map ..............................................................................................................
Register Descriptions ..................................................................................................
13
Inter-Integrated Circuit (I2C) Interface ................................................................ 328
13.1
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.2.5
13.3
13.4
13.5
13.6
Block Diagram ............................................................................................................
Functional Description .................................................................................................
I2C Bus Functional Overview ........................................................................................
Available Speed Modes ...............................................................................................
Interrupts ....................................................................................................................
Loopback Operation ....................................................................................................
Command Sequence Flow Charts ................................................................................
Initialization and Configuration .....................................................................................
Register Map ..............................................................................................................
Register Descriptions (I2C Master) ...............................................................................
Register Descriptions (I2C Slave) .................................................................................
291
292
292
292
292
293
300
301
302
329
329
329
331
332
333
333
340
341
342
355
14
Controller Area Network (CAN) Module ............................................................. 364
14.1
14.2
14.2.1
14.2.2
14.2.3
14.2.4
14.2.5
14.2.6
Block Diagram ............................................................................................................ 365
Functional Description ................................................................................................. 365
Initialization ................................................................................................................. 366
Operation ................................................................................................................... 367
Transmitting Message Objects ..................................................................................... 368
Configuring a Transmit Message Object ........................................................................ 368
Updating a Transmit Message Object ........................................................................... 369
Accepting Received Message Objects .......................................................................... 370
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14.2.7 Receiving a Data Frame .............................................................................................. 370
14.2.8 Receiving a Remote Frame .......................................................................................... 370
14.2.9 Receive/Transmit Priority ............................................................................................. 371
14.2.10 Configuring a Receive Message Object ........................................................................ 371
14.2.11 Handling of Received Message Objects ........................................................................ 372
14.2.12 Handling of Interrupts .................................................................................................. 375
14.2.13 Test Mode ................................................................................................................... 375
14.2.14 Bit Timing Configuration Error Considerations ............................................................... 377
14.2.15 Bit Time and Bit Rate ................................................................................................... 377
14.2.16 Calculating the Bit Timing Parameters .......................................................................... 379
14.3
Register Map .............................................................................................................. 382
14.4
CAN Register Descriptions .......................................................................................... 384
15
Ethernet Controller .............................................................................................. 412
15.1
15.2
15.2.1
15.2.2
15.2.3
15.2.4
15.3
15.3.1
15.3.2
15.4
15.5
15.6
Block Diagram ............................................................................................................ 412
Functional Description ................................................................................................. 413
MAC Operation ........................................................................................................... 413
Internal MII Operation .................................................................................................. 417
PHY Operation ............................................................................................................ 417
Interrupts .................................................................................................................... 418
Initialization and Configuration ..................................................................................... 419
Hardware Configuration ............................................................................................... 419
Software Configuration ................................................................................................ 420
Ethernet Register Map ................................................................................................. 420
Ethernet MAC Register Descriptions ............................................................................. 422
MII Management Register Descriptions ......................................................................... 440
16
Pin Diagram .......................................................................................................... 459
17
Signal Tables ........................................................................................................ 461
17.1
17.2
17.3
100-Pin LQFP Package Pin Tables ............................................................................... 461
108-Pin BGA Package Pin Tables ................................................................................ 471
Connections for Unused Signals ................................................................................... 482
18
Operating Characteristics ................................................................................... 484
19
Electrical Characteristics .................................................................................... 485
19.1
19.1.1
19.1.2
19.1.3
19.1.4
19.1.5
19.1.6
19.2
19.2.1
19.2.2
19.2.3
19.2.4
19.2.5
19.2.6
19.2.7
DC Characteristics ...................................................................................................... 485
Maximum Ratings ....................................................................................................... 485
Recommended DC Operating Conditions ...................................................................... 485
On-Chip Low Drop-Out (LDO) Regulator Characteristics ................................................ 486
GPIO Module Characteristics ....................................................................................... 486
Power Specifications ................................................................................................... 486
Flash Memory Characteristics ...................................................................................... 487
AC Characteristics ....................................................................................................... 488
Load Conditions .......................................................................................................... 488
Clocks ........................................................................................................................ 488
JTAG and Boundary Scan ............................................................................................ 489
Reset ......................................................................................................................... 491
Sleep Modes ............................................................................................................... 493
General-Purpose I/O (GPIO) ........................................................................................ 493
Synchronous Serial Interface (SSI) ............................................................................... 493
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19.2.8 Inter-Integrated Circuit (I2C) Interface ........................................................................... 495
19.2.9 Ethernet Controller ...................................................................................................... 496
A
Serial Flash Loader .............................................................................................. 499
A.1
A.2
A.2.1
A.2.2
A.3
A.3.1
A.3.2
A.3.3
A.4
A.4.1
A.4.2
A.4.3
A.4.4
A.4.5
A.4.6
Serial Flash Loader .....................................................................................................
Interfaces ...................................................................................................................
UART .........................................................................................................................
SSI .............................................................................................................................
Packet Handling ..........................................................................................................
Packet Format ............................................................................................................
Sending Packets .........................................................................................................
Receiving Packets .......................................................................................................
Commands .................................................................................................................
COMMAND_PING (0X20) ............................................................................................
COMMAND_GET_STATUS (0x23) ...............................................................................
COMMAND_DOWNLOAD (0x21) .................................................................................
COMMAND_SEND_DATA (0x24) .................................................................................
COMMAND_RUN (0x22) .............................................................................................
COMMAND_RESET (0x25) .........................................................................................
B
Register Quick Reference ................................................................................... 504
499
499
499
499
500
500
500
500
501
501
501
501
502
502
502
C
Ordering and Contact Information ..................................................................... 520
C.1
C.2
C.3
C.4
Ordering Information .................................................................................................... 520
Part Markings .............................................................................................................. 520
Kits ............................................................................................................................. 521
Support Information ..................................................................................................... 521
D
Package Information ............................................................................................ 522
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Table of Contents
List of Figures
Figure 1-1.
Figure 2-1.
Figure 2-2.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 6-1.
Figure 6-2.
Figure 6-3.
Figure 6-4.
Figure 6-5.
Figure 7-1.
Figure 8-1.
Figure 8-2.
Figure 8-3.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 9-4.
Figure 10-1.
Figure 11-1.
Figure 11-2.
Figure 11-3.
Figure 12-1.
Figure 12-2.
Figure 12-3.
Figure 12-4.
Figure 12-5.
Figure 12-6.
Figure 12-7.
Figure 12-8.
Figure 12-9.
Figure 12-10.
Figure 12-11.
Figure 12-12.
Figure 13-1.
Figure 13-2.
Figure 13-3.
Figure 13-4.
Figure 13-5.
Figure 13-6.
Figure 13-7.
Figure 13-8.
®
Stellaris LM3S8530 Microcontroller High-Level Block Diagram ............................. 33
CPU Block Diagram ............................................................................................. 41
TPIU Block Diagram ............................................................................................ 42
JTAG Module Block Diagram ................................................................................ 52
Test Access Port State Machine ........................................................................... 55
IDCODE Register Format ..................................................................................... 61
BYPASS Register Format .................................................................................... 61
Boundary Scan Register Format ........................................................................... 62
Basic RST Configuration ...................................................................................... 64
External Circuitry to Extend Power-On Reset ........................................................ 65
Reset Circuit Controlled by Switch ........................................................................ 65
Power Architecture .............................................................................................. 67
Main Clock Tree .................................................................................................. 69
Flash Block Diagram .......................................................................................... 124
GPIO Port Block Diagram ................................................................................... 150
GPIODATA Write Example ................................................................................. 151
GPIODATA Read Example ................................................................................. 151
GPTM Module Block Diagram ............................................................................ 191
16-Bit Input Edge Count Mode Example .............................................................. 195
16-Bit Input Edge Time Mode Example ............................................................... 196
16-Bit PWM Mode Example ................................................................................ 197
WDT Module Block Diagram .............................................................................. 227
UART Module Block Diagram ............................................................................. 251
UART Character Frame ..................................................................................... 252
IrDA Data Modulation ......................................................................................... 254
SSI Module Block Diagram ................................................................................. 291
TI Synchronous Serial Frame Format (Single Transfer) ........................................ 294
TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 294
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 295
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 295
Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 296
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 297
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 297
Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 298
MICROWIRE Frame Format (Single Frame) ........................................................ 299
MICROWIRE Frame Format (Continuous Transfer) ............................................. 300
MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 300
I2C Block Diagram ............................................................................................. 329
I2C Bus Configuration ........................................................................................ 329
START and STOP Conditions ............................................................................. 330
Complete Data Transfer with a 7-Bit Address ....................................................... 330
R/S Bit in First Byte ............................................................................................ 330
Data Validity During Bit Transfer on the I2C Bus ................................................... 331
Master Single SEND .......................................................................................... 334
Master Single RECEIVE ..................................................................................... 335
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Figure 13-9.
Figure 13-10.
Figure 13-11.
Figure 13-12.
Figure 13-13.
Figure 14-1.
Figure 14-2.
Figure 14-3.
Figure 14-4.
Figure 15-1.
Figure 15-2.
Figure 15-3.
Figure 15-4.
Figure 16-1.
Figure 16-2.
Figure 19-1.
Figure 19-2.
Figure 19-3.
Figure 19-4.
Figure 19-5.
Figure 19-6.
Figure 19-7.
Figure 19-8.
Figure 19-9.
Figure 19-10.
Figure 19-11.
Figure 19-12.
Figure 19-13.
Figure 19-14.
Figure D-1.
Figure D-2.
Master Burst SEND ........................................................................................... 336
Master Burst RECEIVE ...................................................................................... 337
Master Burst RECEIVE after Burst SEND ............................................................ 338
Master Burst SEND after Burst RECEIVE ............................................................ 339
Slave Command Sequence ................................................................................ 340
CAN Controller Block Diagram ............................................................................ 365
CAN Data/Remote Frame .................................................................................. 366
Message Objects in a FIFO Buffer ...................................................................... 374
CAN Bit Time .................................................................................................... 378
Ethernet Controller ............................................................................................. 413
Ethernet Controller Block Diagram ...................................................................... 413
Ethernet Frame ................................................................................................. 414
Interface to an Ethernet Jack .............................................................................. 419
100-Pin LQFP Package Pin Diagram .................................................................. 459
108-Ball BGA Package Pin Diagram (Top View) ................................................... 460
Load Conditions ................................................................................................ 488
JTAG Test Clock Input Timing ............................................................................. 490
JTAG Test Access Port (TAP) Timing .................................................................. 491
JTAG TRST Timing ............................................................................................ 491
External Reset Timing (RST) .............................................................................. 492
Power-On Reset Timing ..................................................................................... 492
Brown-Out Reset Timing .................................................................................... 492
Software Reset Timing ....................................................................................... 492
Watchdog Reset Timing ..................................................................................... 493
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 494
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 494
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 495
I2C Timing ......................................................................................................... 496
External XTLP Oscillator Characteristics ............................................................. 498
100-Pin LQFP Package ...................................................................................... 522
108-Ball BGA Package ...................................................................................... 524
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Table of Contents
List of Tables
Table 1.
Table 2.
Table 3-1.
Table 4-1.
Table 4-2.
Table 5-1.
Table 5-2.
Table 6-1.
Table 6-2.
Table 6-3.
Table 6-4.
Table 6-5.
Table 7-1.
Table 7-2.
Table 7-3.
Table 8-1.
Table 8-2.
Table 8-3.
Table 9-1.
Table 9-2.
Table 9-3.
Table 10-1.
Table 11-1.
Table 12-1.
Table 13-1.
Table 13-2.
Table 13-3.
Table 14-1.
Table 14-2.
Table 14-3.
Table 15-1.
Table 15-2.
Table 17-1.
Table 17-2.
Table 17-3.
Table 17-4.
Table 17-5.
Table 17-6.
Table 17-7.
Table 17-8.
Table 17-9.
Table 17-10.
Table 18-1.
Table 18-2.
Table 18-3.
Table 19-1.
Revision History .................................................................................................. 18
Documentation Conventions ................................................................................ 23
Memory Map ....................................................................................................... 46
Exception Types .................................................................................................. 48
Interrupts ............................................................................................................ 49
JTAG Port Pins Reset State ................................................................................. 53
JTAG Instruction Register Commands ................................................................... 58
Clock Source Options .......................................................................................... 68
Possible System Clock Frequencies Using the SYSDIV Field ................................. 70
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field ............ 70
System Control Register Map ............................................................................... 74
RCC2 Fields that Override RCC fields .................................................................. 88
Flash Protection Policy Combinations ................................................................. 125
User-Programmable Flash Memory Resident Registers ....................................... 127
Flash Register Map ............................................................................................ 128
GPIO Pad Configuration Examples ..................................................................... 153
GPIO Interrupt Configuration Example ................................................................ 153
GPIO Register Map ........................................................................................... 154
Available CCP Pins ............................................................................................ 191
16-Bit Timer With Prescaler Configurations ......................................................... 194
Timers Register Map .......................................................................................... 200
Watchdog Timer Register Map ............................................................................ 228
UART Register Map ........................................................................................... 256
SSI Register Map .............................................................................................. 301
Examples of I2C Master Timer Period versus Speed Mode ................................... 332
Inter-Integrated Circuit (I2C) Interface Register Map ............................................. 341
Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) .................................... 346
CAN Protocol Ranges ........................................................................................ 378
CANBIT Register Values .................................................................................... 378
CAN Register Map ............................................................................................. 382
TX & RX FIFO Organization ............................................................................... 415
Ethernet Register Map ....................................................................................... 421
Signals by Pin Number ....................................................................................... 461
Signals by Signal Name ..................................................................................... 465
Signals by Function, Except for GPIO ................................................................. 468
GPIO Pins and Alternate Functions ..................................................................... 470
Signals by Pin Number ....................................................................................... 471
Signals by Signal Name ..................................................................................... 475
Signals by Function, Except for GPIO ................................................................. 478
GPIO Pins and Alternate Functions ..................................................................... 481
Connections for Unused Signals (100-pin LQFP) ................................................. 482
Connections for Unused Signals, 108-pin BGA .................................................... 483
Temperature Characteristics ............................................................................... 484
Thermal Characteristics ..................................................................................... 484
ESD Absolute Maximum Ratings ........................................................................ 484
Maximum Ratings .............................................................................................. 485
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Stellaris® LM3S8530 Microcontroller
Table 19-2.
Table 19-3.
Table 19-4.
Table 19-5.
Table 19-6.
Table 19-7.
Table 19-8.
Table 19-9.
Table 19-10.
Table 19-11.
Table 19-12.
Table 19-13.
Table 19-14.
Table 19-15.
Table 19-16.
Table 19-17.
Table 19-18.
Table 19-19.
Table 19-20.
Table 19-21.
Table 19-22.
Table 19-23.
Table 19-24.
Table 19-25.
Table C-1.
Recommended DC Operating Conditions ............................................................ 485
LDO Regulator Characteristics ........................................................................... 486
GPIO Module DC Characteristics ........................................................................ 486
Detailed Power Specifications ............................................................................ 487
Flash Memory Characteristics ............................................................................ 487
Phase Locked Loop (PLL) Characteristics ........................................................... 488
Actual PLL Frequency ........................................................................................ 488
Clock Characteristics ......................................................................................... 489
Crystal Characteristics ....................................................................................... 489
JTAG Characteristics ......................................................................................... 489
Reset Characteristics ......................................................................................... 491
Sleep Modes AC Characteristics ......................................................................... 493
GPIO Characteristics ......................................................................................... 493
SSI Characteristics ............................................................................................ 493
I2C Characteristics ............................................................................................. 495
100BASE-TX Transmitter Characteristics ............................................................ 496
100BASE-TX Transmitter Characteristics (informative) ......................................... 496
100BASE-TX Receiver Characteristics ................................................................ 496
10BASE-T Transmitter Characteristics ................................................................ 496
10BASE-T Transmitter Characteristics (informative) ............................................. 497
10BASE-T Receiver Characteristics .................................................................... 497
Isolation Transformers ....................................................................................... 497
Ethernet Reference Crystal ................................................................................ 498
External XTLP Oscillator Characteristics ............................................................. 498
Part Ordering Information ................................................................................... 520
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Table of Contents
List of Registers
System Control .............................................................................................................................. 63
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Device Identification 0 (DID0), offset 0x000 ....................................................................... 76
Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 78
LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 79
Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 80
Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 81
Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 82
Reset Cause (RESC), offset 0x05C .................................................................................. 83
Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 84
XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 87
Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 88
Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 90
Device Identification 1 (DID1), offset 0x004 ....................................................................... 91
Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 93
Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 94
Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 96
Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 98
Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 99
Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 101
Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 103
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 105
Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 107
Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 109
Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 111
Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 113
Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 115
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 117
Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 119
Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 120
Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 122
Internal Memory ........................................................................................................................... 124
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Flash Memory Address (FMA), offset 0x000 .................................................................... 129
Flash Memory Data (FMD), offset 0x004 ......................................................................... 130
Flash Memory Control (FMC), offset 0x008 ..................................................................... 131
Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 133
Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 134
Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 135
USec Reload (USECRL), offset 0x140 ............................................................................ 137
Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 138
Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 139
User Debug (USER_DBG), offset 0x1D0 ......................................................................... 140
User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 141
User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 142
Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 143
Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 144
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Stellaris® LM3S8530 Microcontroller
Register 15:
Register 16:
Register 17:
Register 18:
Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ...................................
Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ...............................
Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ...............................
Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ...............................
145
146
147
148
General-Purpose Input/Outputs (GPIOs) ................................................................................... 149
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
GPIO Data (GPIODATA), offset 0x000 ............................................................................ 156
GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 157
GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 158
GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 159
GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 160
GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 161
GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 162
GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 163
GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 164
GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 165
GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 167
GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 168
GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 169
GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 170
GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 171
GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 172
GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 173
GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 174
GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 175
GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 176
GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 178
GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 179
GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 180
GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 181
GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 182
GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 183
GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 184
GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 185
GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 186
GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 187
GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 188
GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 189
General-Purpose Timers ............................................................................................................. 190
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
GPTM Configuration (GPTMCFG), offset 0x000 ..............................................................
GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................
GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................
GPTM Control (GPTMCTL), offset 0x00C ........................................................................
GPTM Interrupt Mask (GPTMIMR), offset 0x018 ..............................................................
GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C .....................................................
GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................
GPTM Interrupt Clear (GPTMICR), offset 0x024 ..............................................................
GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 .................................................
GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................
June 22, 2010
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205
207
210
212
213
214
216
217
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Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 218
GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 219
GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 220
GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 221
GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 222
GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 223
GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 224
GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 225
Watchdog Timer ........................................................................................................................... 226
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 230
Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 231
Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 232
Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 233
Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 234
Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 235
Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 236
Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 237
Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 238
Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 239
Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 240
Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 241
Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 242
Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 243
Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 244
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 245
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 246
Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 247
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 248
Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 249
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 250
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
UART Data (UARTDR), offset 0x000 ............................................................................... 258
UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 260
UART Flag (UARTFR), offset 0x018 ................................................................................ 262
UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 264
UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 265
UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 266
UART Line Control (UARTLCRH), offset 0x02C ............................................................... 267
UART Control (UARTCTL), offset 0x030 ......................................................................... 269
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 271
UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 273
UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 275
UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 276
UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 277
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 279
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 280
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 281
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 282
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 283
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Stellaris® LM3S8530 Microcontroller
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ......................................
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ......................................
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC .....................................
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................
284
285
286
287
288
289
290
Synchronous Serial Interface (SSI) ............................................................................................ 291
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 303
SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 305
SSI Data (SSIDR), offset 0x008 ...................................................................................... 307
SSI Status (SSISR), offset 0x00C ................................................................................... 308
SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 310
SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 311
SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 313
SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 314
SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 315
SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 316
SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 317
SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 318
SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 319
SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 320
SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 321
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 322
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 323
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 324
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 325
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 326
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 327
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 328
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 343
I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 344
I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 348
I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 349
I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 350
I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 351
I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 352
I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 353
I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 354
I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 356
I2C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 357
I2C Slave Data (I2CSDR), offset 0x008 ........................................................................... 359
I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 360
I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 361
I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 362
I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 363
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Controller Area Network (CAN) Module ..................................................................................... 364
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
CAN Control (CANCTL), offset 0x000 ............................................................................. 385
CAN Status (CANSTS), offset 0x004 ............................................................................... 387
CAN Error Counter (CANERR), offset 0x008 ................................................................... 390
CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 391
CAN Interrupt (CANINT), offset 0x010 ............................................................................. 393
CAN Test (CANTST), offset 0x014 .................................................................................. 394
CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 ....................................... 396
CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 397
CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 397
CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 398
CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 398
CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 400
CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 400
CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 401
CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 401
CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 402
CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 402
CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 403
CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 403
CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 405
CAN IF2 Message Control (CANIF2MCTL), offset 0x098 .................................................. 405
CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ................................................................. 407
CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................. 407
CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................. 407
CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................. 407
CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ................................................................. 407
CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ................................................................. 407
CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ................................................................. 407
CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ................................................................. 407
CAN Transmission Request 1 (CANTXRQ1), offset 0x100 ................................................ 408
CAN Transmission Request 2 (CANTXRQ2), offset 0x104 ................................................ 408
CAN New Data 1 (CANNWDA1), offset 0x120 ................................................................. 409
CAN New Data 2 (CANNWDA2), offset 0x124 ................................................................. 409
CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ..................................... 410
CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ..................................... 410
CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ....................................................... 411
CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ....................................................... 411
Ethernet Controller ...................................................................................................................... 412
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 .......
Ethernet MAC Interrupt Mask (MACIM), offset 0x004 .......................................................
Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................
Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ...............................................
Ethernet MAC Data (MACDATA), offset 0x010 .................................................................
Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 .............................................
Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 .............................................
Ethernet MAC Threshold (MACTHR), offset 0x01C ..........................................................
Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................
16
423
426
427
428
429
431
432
433
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Stellaris® LM3S8530 Microcontroller
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... 436
Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. 437
Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. 438
Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... 439
Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... 440
Ethernet PHY Management Register 0 – Control (MR0), address 0x00 ............................. 441
Ethernet PHY Management Register 1 – Status (MR1), address 0x01 .............................. 443
Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 ................. 445
Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 ................. 446
Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address
0x04 ............................................................................................................................. 447
Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability
(MR5), address 0x05 ..................................................................................................... 449
Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address
0x06 ............................................................................................................................. 450
Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 ............. 451
Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17), address
0x11 .............................................................................................................................. 453
Ethernet PHY Management Register 18 – Diagnostic (MR18), address 0x12 ..................... 455
Ethernet PHY Management Register 19 – Transceiver Control (MR19), address 0x13 ....... 456
Ethernet PHY Management Register 23 – LED Configuration (MR23), address 0x17 ......... 457
Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24), address 0x18 .......... 458
June 22, 2010
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Revision History
Revision History
The revision history table notes changes made between the indicated revisions of the LM3S8530
data sheet.
Table 1. Revision History
Date
Revision
June 2010
7393
April 2010
January 2010
7007
6712
Description
■
Corrected base address for SRAM in architectural overview chapter.
■
Clarified system clock operation, adding content to “Clock Control” on page 68.
■
Clarified CAN bit timing examples.
■
In Signal Tables chapter, added table "Connections for Unused Signals."
■
In "Thermal Characteristics" table, corrected thermal resistance value from 34 to 32.
■
In "Reset Characteristics" table, corrected value for supply voltage (VDD) rise time.
■
Additional minor data sheet clarifications and corrections.
■
Added caution note to the I2C Master Timer Period (I2CMTPR) register description and changed
field width to 7 bits.
■
Removed erroneous text about restoring the Flash Protection registers.
■
Added note about RST signal routing.
■
Clarified the function of the TnSTALL bit in the GPTMCTL register.
■
Corrected XTALNPHY pin description.
■
Additional minor data sheet clarifications and corrections.
■
In "System Control" section, clarified Debug Access Port operation after Sleep modes.
■
Clarified wording on Flash memory access errors.
■
Added section on Flash interrupts.
■
Clarified operation of SSI transmit FIFO.
■
Made these changes to the Operating Characteristics chapter:
■
–
Added storage temperature ratings to "Temperature Characteristics" table
–
Added "ESD Absolute Maximum Ratings" table
Made these changes to the Electrical Characteristics chapter:
–
In "Flash Memory Characteristics" table, corrected Mass erase time
–
Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table)
–
In "Reset Characteristics" table, corrected units for supply voltage (VDD) rise time
18
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Stellaris® LM3S8530 Microcontroller
Table 1. Revision History (continued)
Date
Revision
October 2009
6462
Description
■
Deleted reset value for 16-bit mode from GPTMTAILR, GPTMTAMATCHR, and GPTMTAR registers
because the module resets in 32-bit mode.
■
Clarified CAN bit timing and corrected examples.
■
Made these changes to the Electrical Characteristics chapter:
–
Removed VSIH and VSIL parameters from Operating Conditions table.
–
Added table showing actual PLL frequency depending on input crystal.
–
Changed the name of the tHIB_REG_WRITE parameter to tHIB_REG_ACCESS.
–
Changed SSI set up and hold times to be expressed in system clocks, not ns.
July 2009
5920
Corrected ordering numbers.
July 2009
5902
■
Clarified Power-on reset and RST pin operation; added new diagrams.
■
Clarified explanation of nonvolatile register programming in Internal Memory chapter.
■
Added explanation of reset value to FMPRE0/1/2/3, FMPPE0/1/2/3, USER_DBG, and USER_REG0/1
registers.
■
Added description for Ethernet PHY power-saving modes.
■
Corrected the reset values for bits 6 and 7 in the Ethernet MR24 register.
■
Changed buffer type for WAKE pin to TTL and HIB pin to OD.
■
In ADC characteristics table, changed Max value for GAIN parameter from ±1 to ±3 and added EIR
(Internal voltage reference error) parameter.
■
Additional minor data sheet clarifications and corrections.
■
Added JTAG/SWD clarification (see “Communication with JTAG/SWD” on page 57).
■
Added clarification that the PLL operates at 400 MHz, but is divided by two prior to the application
of the output divisor.
■
Added "GPIO Module DC Characteristics" table (see Table 19-4 on page 486).
■
Additional minor data sheet clarifications and corrections.
■
Corrected bit type for RELOAD bit field in SysTick Reload Value register; changed to R/W.
■
Clarification added as to what happens when the SSI in slave mode is required to transmit but there
is no data in the TX FIFO.
■
Corrected bit timing examples in CAN chapter.
■
Added "Hardware Configuration" section to Ethernet Controller chapter.
■
Additional minor data sheet clarifications and corrections.
■
Revised High-Level Block Diagram.
■
Additional minor data sheet clarifications and corrections were made.
April 2009
January 2009
November 2008
5367
4660
4283
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Revision History
Table 1. Revision History (continued)
Date
Revision
October 2008
4149
August 2008
July 2008
May 2008
April 2008
3447
3108
2972
2881
Description
■
Corrected values for DSOSCSRC bit field in Deep Sleep Clock Configuration (DSLPCLKCFG)
register.
■
The FMA value for the FMPRE3 register was incorrect in the Flash Resident Registers table in the
Internal Memory chapter. The correct value is 0x0000.0006.
■
In the CAN chapter, major improvements were made including a rewrite of the conceptual information
and the addition of new figures to clarify how to use the Controller Area Network (CAN) module.
■
In the Ethernet chapter, major improvements were made including a rewrite of the conceptual
information and the addition of new figures to clarify how to use the Ethernet Controller interface.
■
Added note on clearing interrupts to Interrupts chapter.
■
Added Power Architecture diagram to System Control chapter.
■
Additional minor data sheet clarifications and corrections.
■
Corrected resistor value in ERBIAS signal description.
■
Additional minor data sheet clarifications and corrections.
■
As noted in the PCN, three of the nine Ethernet LED configuration options are no longer supported:
TX Activity (0x2), RX Activity (0x3), and Collision (0x4). These values for the LED0 and LED1 bit
fields in the MR23 register are now marked as reserved.
■
As noted in the PCN, the option to provide VDD25 power from external sources was removed. Use
the LDO output as the source of VDD25 input.
■
As noted in the PCN, pin 41 (ball K3 on the BGA package) was renamed from GNDPHY to ERBIAS.
A 12.4-kΩ resistor should be connected between ERBIAS and ground to accommodate future device
revisions (see “Functional Description” on page 413).
■
Additional minor data sheet clarifications and corrections.
■
The ΘJA value was changed from 55.3 to 34 in the "Thermal Characteristics" table in the Operating
Characteristics chapter.
■
Bit 31 of the DC3 register was incorrectly described in prior versions of the data sheet. A reset of
1 indicates that an even CCP pin is present and can be used as a 32-KHz input clock.
■
Values for IDD_HIBERNATE were added to the "Detailed Power Specifications" table in the "Electrical
Characteristics" chapter.
■
The "Hibernation Module DC Electricals" table was added to the "Electrical Characteristics" chapter.
■
The maximum value on Core supply voltage (VDD25) in the "Maximum Ratings" table in the "Electrical
Characteristics" chapter was changed from 4 to 3.
■
The operational frequency of the internal 30-kHz oscillator clock source is 30 kHz ± 50% (prior data
sheets incorrectly noted it as 30 kHz ± 30%).
■
A value of 0x3 in bits 5:4 of the MISC register (OSCSRC) indicates the 30-KHz internal oscillator is
the input source for the oscillator. Prior data sheets incorrectly noted 0x3 as a reserved value.
■
The reset for bits 6:4 of the RCC2 register (OSCSRC2) is 0x1 (IOSC). Prior data sheets incorrectly
noted the reset was 0x0 (MOSC).
■
A note on high-current applications was added to the GPIO chapter:
For special high-current applications, the GPIO output buffers may be used with the following
restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may
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Table 1. Revision History (continued)
Date
Revision
Description
be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is
specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only
a maximum of two per side of the physical package or BGA pin group with the total number of
high-current GPIO outputs not exceeding four for the entire package.
■
A note on Schmitt inputs was added to the GPIO chapter:
Pins configured as digital inputs are Schmitt-triggered.
■
The Buffer type on the WAKE pin changed from OD to - in the Signal Tables.
■
The "Differential Sampling Range" figures in the ADC chapter were clarified.
■
The last revision of the data sheet (revision 2550) introduced two errors that have now been corrected:
■
March 2008
2550
–
The LQFP pin diagrams and pin tables were missing the comparator positive and negative input
pins.
–
The base address was listed incorrectly in the FMPRE0 and FMPPE0 register bit diagrams.
Additional minor data sheet clarifications and corrections.
Started tracking revision history.
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About This Document
About This Document
This data sheet provides reference information for the LM3S8530 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
®
The following related documents are available on the documentation CD or from the Stellaris web
site at www.ti.com/stellaris:
■ ARM® CoreSight Technical Reference Manual
■ ARM® Cortex™-M3 Errata
■ ARM® Cortex™-M3 Technical Reference Manual
■ ARM® v7-M Architecture Application Level Reference Manual
■ Stellaris® Graphics Library User's Guide
■ Stellaris® Peripheral Driver Library User's Guide
■ Stellaris® Errata
The following related documents are also referenced:
■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the web site for additional
documentation, including application notes and white papers.
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Documentation Conventions
This document uses the conventions shown in Table 2 on page 23.
Table 2. Documentation Conventions
Notation
Meaning
General Register Notation
REGISTER
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
bit
A single bit in a register.
bit field
Two or more consecutive and related bits.
offset 0xnnn
A hexadecimal increment to a register's address, relative to that module's base address as specified
in “Memory Map” on page 46.
Register N
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
reserved
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
yy:xx
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
Register Bit/Field
Types
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
RC
Software can read this field. The bit or field is cleared by hardware after reading the bit/field.
RO
Software can read this field. Always write the chip reset value.
R/W
Software can read or write this field.
R/W1C
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
R/W1S
Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bit
value in the register.
W1C
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
WO
Only a write by software is valid; a read of the register returns no meaningful data.
Register Bit/Field
Reset Value
This value in the register bit diagram shows the bit/field value after any reset, unless noted.
0
Bit cleared to 0 on chip reset.
1
Bit set to 1 on chip reset.
-
Nondeterministic.
Pin/Signal Notation
[]
Pin alternate function; a pin defaults to the signal without the brackets.
pin
Refers to the physical connection on the package.
signal
Refers to the electrical signal encoding of a pin.
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About This Document
Table 2. Documentation Conventions (continued)
Notation
Meaning
assert a signal
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
deassert a signal
Change the value of the signal from the logically True state to the logically False state.
SIGNAL
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
SIGNAL
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
Numbers
X
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
0x
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
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Stellaris® LM3S8530 Microcontroller
1
Architectural Overview
®
The Stellaris family of microcontrollers—the first ARM® Cortex™-M3 based controllers—brings
high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These
pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit
devices, all in a package with a small footprint.
®
The Stellaris family offers efficient performance and extensive integration, favorably positioning
the device into cost-conscious applications requiring significant control-processing and connectivity
®
capabilities. The Stellaris LM3S8000 series combines Bosch Controller Area Network technology
with both a 10/100 Ethernet Media Access Control (MAC) and Physical (PHY) layer.
The LM3S8530 microcontroller is targeted for industrial applications, including remote monitoring,
electronic point-of-sale machines, test and measurement equipment, network appliances and
switches, factory automation, HVAC and building control, gaming equipment, motion control, medical
instrumentation, and fire and security.
In addition, the LM3S8530 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S8530 microcontroller is code-compatible
®
to all members of the extensive Stellaris family; providing flexibility to fit our customers' precise
needs.
Texas Instruments offers a complete solution to get to market quickly, with evaluation and
development boards, white papers and application notes, an easy-to-use peripheral driver library,
and a strong support, sales, and distributor network. See “Ordering and Contact
®
Information” on page 520 for ordering information for Stellaris family devices.
1.1
Product Features
The LM3S8530 microcontroller includes the following product features:
■ 32-Bit RISC Performance
– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
applications
– System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
counter with a flexible control mechanism
– Thumb®-compatible Thumb-2-only instruction set processor core for high code density
– 50-MHz operation
– Hardware-division and single-cycle-multiplication
– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
– 26 interrupts with eight priority levels
– Memory protection unit (MPU), providing a privileged mode for protected operating system
functionality
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Architectural Overview
– Unaligned data access, enabling data to be efficiently packed into memory
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
■ ARM® Cortex™-M3 Processor Core
– Compact core.
– Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the
memory size usually associated with 8- and 16-bit devices; typically in the range of a few
kilobytes of memory for microcontroller class applications.
– Rapid application execution through Harvard architecture characterized by separate buses
for instruction and data.
– Exceptional interrupt handling, by implementing the register manipulations required for handling
an interrupt in hardware.
– Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
– Memory protection unit (MPU) to provide a privileged mode of operation for complex
applications.
– Migration from the ARM7™ processor family for better performance and power efficiency.
– Full-featured debug solution
•
Serial Wire JTAG Debug Port (SWJ-DP)
•
Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
•
Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
•
Instrumentation Trace Macrocell (ITM) for support of printf style debugging
•
Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
– Optimized for single-cycle flash usage
– Three sleep modes with clock gating for low power
– Single-cycle multiply instruction and hardware divide
– Atomic operations
– ARM Thumb2 mixed 16-/32-bit instruction set
– 1.25 DMIPS/MHz
■ JTAG
– IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
– Four-bit Instruction Register (IR) chain for storing JTAG instructions
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– IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST
– ARM additional instructions: APACC, DPACC and ABORT
– Integrated ARM Serial Wire Debug (SWD)
■ Internal Memory
– 96 KB single-cycle flash
•
User-managed flash block protection on a 2-KB block basis
•
User-managed flash data programming
•
User-defined and managed flash-protection block
– 64 KB single-cycle SRAM
■ GPIOs
– 8-35 GPIOs, depending on configuration
– 5-V-tolerant input/outputs
– Programmable control for GPIO interrupts
•
Interrupt generation masking
•
Edge-triggered on rising, falling, or both
•
Level-sensitive on High or Low values
– Bit masking in both read and write operations through address lines
– Pins configured as digital inputs are Schmitt-triggered.
– Programmable control for GPIO pad configuration
•
Weak pull-up or pull-down resistors
•
2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be
configured with an 18-mA pad drive for high-current applications
•
Slew rate control for the 8-mA drive
•
Open drain enables
•
Digital input enables
■ General-Purpose Timers
– Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit
timers/counters. Each GPTM can be configured to operate independently:
•
As a single 32-bit timer
•
As one 32-bit Real-Time Clock (RTC) to event capture
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Architectural Overview
•
For Pulse Width Modulation (PWM)
– 32-bit Timer modes
•
Programmable one-shot timer
•
Programmable periodic timer
•
Real-Time Clock when using an external 32.768-KHz clock as the input
•
User-enabled stalling when the controller asserts CPU Halt flag during debug
– 16-bit Timer modes
•
General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes
only)
•
Programmable one-shot timer
•
Programmable periodic timer
•
User-enabled stalling when the controller asserts CPU Halt flag during debug
– 16-bit Input Capture modes
•
Input edge count capture
•
Input edge time capture
– 16-bit PWM mode
•
Simple PWM mode with software-programmable output inversion of the PWM signal
■ ARM FiRM-compliant Watchdog Timer
– 32-bit down counter with a programmable load register
– Separate watchdog clock with an enable
– Programmable interrupt generation logic with interrupt masking
– Lock register protection from runaway software
– Reset generation logic with an enable/disable
– User-enabled stalling when the controller asserts the CPU Halt flag during debug
■ UART
– Fully programmable 16C550-type UART with IrDA support
– Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
– Programmable baud-rate generator allowing speeds up to 3.125 Mbps
– Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
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– FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
– Standard asynchronous communication bits for start, stop, and parity
– False-start bit detection
– Line-break generation and detection
– Fully programmable serial interface characteristics
•
5, 6, 7, or 8 data bits
•
Even, odd, stick, or no-parity bit generation/detection
•
1 or 2 stop bit generation
– IrDA serial-IR (SIR) encoder/decoder providing
•
Programmable use of IrDA Serial Infrared (SIR) or UART input/output
•
Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
•
Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
•
Programmable internal clock generator enabling division of reference clock by 1 to 256
for low-power mode bit duration
■ Synchronous Serial Interface (SSI)
– Two SSI modules, each with the following features:
– Master or slave operation
– Programmable clock bit rate and prescale
– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
– Programmable data frame size from 4 to 16 bits
– Internal loopback test mode for diagnostic/debug testing
■ I2C
– Devices on the I2C bus can be designated as either a master or a slave
•
Supports both sending and receiving data as either a master or a slave
•
Supports simultaneous master and slave operation
– Four I2C modes
•
Master transmit
•
Master receive
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Architectural Overview
•
Slave transmit
•
Slave receive
– Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps)
– Master and slave interrupt generation
•
Master generates interrupts when a transmit or receive operation completes (or aborts
due to an error)
•
Slave generates interrupts when data has been sent or requested by a master
– Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
■ Controller Area Network (CAN)
– Three CAN modules, each with the following features:
– CAN protocol version 2.0 part A/B
– Bit rates up to 1 Mbps
– 32 message objects with individual identifier masks
– Maskable interrupt
– Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications
– Programmable Loopback mode for self-test operation
– Programmable FIFO mode enables storage of multiple message objects
– Gluelessly attaches to an external CAN interface through the CANnTX and CANnRX signals
■ 10/100 Ethernet Controller
– Conforms to the IEEE 802.3-2002 specification
•
10BASE-T/100BASE-TX IEEE-802.3 compliant. Requires only a dual 1:1 isolation
transformer interface to the line
•
10BASE-T/100BASE-TX ENDEC, 100BASE-TX scrambler/descrambler
•
Full-featured auto-negotiation
– Multiple operational modes
•
Full- and half-duplex 100 Mbps
•
Full- and half-duplex 10 Mbps
•
Power-saving and power-down modes
– Highly configurable
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•
Programmable MAC address
•
LED activity selection
•
Promiscuous mode support
•
CRC error-rejection control
•
User-configurable interrupts
– Physical media manipulation
•
Automatic MDI/MDI-X cross-over correction
•
Register-programmable transmit amplitude
•
Automatic polarity correction and 10BASE-T signal reception
■ Power
– On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
– Low-power options on controller: Sleep and Deep-sleep modes
– Low-power options for peripherals: software controls shutdown of individual peripherals
– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Flexible Reset Sources
– Power-on reset (POR)
– Reset pin assertion
– Brown-out (BOR) detector alerts to system power drops
– Software reset
– Watchdog timer reset
– Internal low drop-out (LDO) regulator output goes unregulated
■ Industrial and extended temperature 100-pin RoHS-compliant LQFP package
■ Industrial-range 108-ball RoHS-compliant BGA package
1.2
Target Applications
■ Remote monitoring
■ Electronic point-of-sale (POS) machines
■ Test and measurement equipment
■ Network appliances and switches
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Architectural Overview
■ Factory automation
■ HVAC and building control
■ Gaming equipment
■ Motion control
■ Medical instrumentation
■ Fire and security
■ Power and energy
■ Transportation
1.3
High-Level Block Diagram
®
Figure 1-1 on page 33 depicts the features on the Stellaris LM3S8530 microcontroller.
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®
Figure 1-1. Stellaris LM3S8530 Microcontroller High-Level Block Diagram
JTAG/SWD
ARM®
Cortex™-M3
System
Control and
Clocks
DCode bus
Flash
(96 KB)
(50 MHz)
ICode bus
NVIC
MPU
System Bus
LM3S8530
Bus Matrix
SRAM
(64 KB)
SYSTEM PERIPHERALS
GeneralPurpose
Timers (4)
Watchdog
Timer
(1)
I2C
(1)
Ethernet
MAC/PHY
Advanced Peripheral Bus (APB)
GPIOs
(8-35)
SERIAL PERIPHERALS
UART
(1)
SSI
(2)
CAN
Controllers
(3)
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Architectural Overview
1.4
Functional Overview
The following sections provide an overview of the features of the LM3S8530 microcontroller. The
page number in parenthesis indicates where that feature is discussed in detail. Ordering and support
information can be found in “Ordering and Contact Information” on page 520.
1.4.1
ARM Cortex™-M3
1.4.1.1
Processor Core (see page 40)
®
All members of the Stellaris product family, including the LM3S8530 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for
a high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
“ARM Cortex-M3 Processor Core” on page 40 provides an overview of the ARM core; the core is
detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.1.2
System Timer (SysTick) (see page 43)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
1.4.1.3
Nested Vectored Interrupt Controller (NVIC) (see page 48)
The LM3S8530 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the
ARM® Cortex™-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions
are handled in Handler Mode. The processor state is automatically stored to the stack on an
exception, and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry.
The processor supports tail-chaining, which enables back-to-back interrupts to be performed without
the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions
(system handlers) and 26 interrupts.
“Interrupts” on page 48 provides an overview of the NVIC controller and the interrupt map. Exceptions
and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.2
Motor Control Peripherals
To enhance motor control, the LM3S8530 controller features Pulse Width Modulation (PWM) outputs.
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1.4.2.1
PWM
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
On the LM3S8530, PWM motion control functionality can be achieved through:
■ The motion control features of the general-purpose timers using the CCP pins
CCP Pins (see page 196)
The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable
to support a simple PWM mode with a software-programmable output inversion of the PWM signal.
1.4.3
Serial Communications Peripherals
The LM3S8530 controller supports both asynchronous and synchronous serial communications
with:
■ One fully programmable 16C550-type UART
■ Two SSI modules
■ One I2C module
■ Three CAN units
■ Ethernet controller
1.4.3.1
UART (see page 250)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The LM3S8530 controller includes one fully programmable 16C550-type UARTthat supports data
transfer speeds up to 3.125 Mbps. (Although similar in functionality to a 16C550 UART, it is not
register-compatible.) In addition, each UART is capable of supporting IrDA.
Separate 16x8 transmit (TX) and receive (RX) FIFOs reduce CPU interrupt service loading. The
UART can generate individually masked interrupts from the RX, TX, modem status, and error
conditions. The module provides a single combined interrupt when any of the interrupts are asserted
and are unmasked.
1.4.3.2
SSI (see page 291)
Synchronous Serial Interface (SSI) is a four-wire bi-directional full and low-speed communications
interface.
The LM3S8530 controller includes two SSI modules that provide the functionality for synchronous
serial communications with peripheral devices, and can be configured to use the Freescale SPI,
MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also
configurable, and can be set between 4 and 16 bits, inclusive.
Each SSI module performs serial-to-parallel conversion on data received from a peripheral device,
and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths
are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently.
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Each SSI module can be configured as either a master or slave device. As a slave device, the SSI
module can also be configured to disable its output, which allows a master device to be coupled
with multiple slave devices.
Each SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
1.4.3.3
I2C (see page 328)
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL).
The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking
devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and
diagnostic purposes in product development and manufacture.
The LM3S8530 controller includes one I2C module that provides the ability to communicate to other
IC devices over an I2C bus. The I2C bus supports devices that can both transmit and receive (write
and read) data.
Devices on the I2C bus can be designated as either a master or a slave. The I2C module supports
both sending and receiving data as either a master or a slave, and also supports the simultaneous
operation as both a master and a slave. The four I2C modes are: Master Transmit, Master Receive,
Slave Transmit, and Slave Receive.
®
A Stellaris I2C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps).
Both the I2C master and slave can generate interrupts. The I2C master generates interrupts when
a transmit or receive operation completes (or aborts due to an error). The I2C slave generates
interrupts when data has been sent or requested by a master.
1.4.3.4
Controller Area Network (see page 364)
Controller Area Network (CAN) is a multicast shared serial-bus standard for connecting electronic
control units (ECUs). CAN was specifically designed to be robust in electromagnetically noisy
environments and can utilize a differential balanced line like RS-485 or a more robust twisted-pair
wire. Originally created for automotive purposes, now it is used in many embedded control
applications (for example, industrial or medical). Bit rates up to 1Mb/s are possible at network lengths
below 40 meters. Decreased bit rates allow longer network distances (for example, 125 Kb/s at
500m).
A transmitter sends a message to all CAN nodes (broadcasting). Each node decides on the basis
of the identifier received whether it should process the message. The identifier also determines the
priority that the message enjoys in competition for bus access. Each CAN message can transmit
from 0 to 8 bytes of user information. The LM3S8530 includes three CAN units.
1.4.3.5
Ethernet Controller (see page 412)
Ethernet is a frame-based computer networking technology for local area networks (LANs). Ethernet
has been standardized as IEEE 802.3. It defines a number of wiring and signaling standards for the
physical layer, two means of network access at the Media Access Control (MAC)/Data Link Layer,
and a common addressing format.
The Stellaris® Ethernet Controller consists of a fully integrated media access controller (MAC) and
network physical (PHY) interface device. The Ethernet Controller conforms to IEEE 802.3
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specifications and fully supports 10BASE-T and 100BASE-TX standards. In addition, the Ethernet
Controller supports automatic MDI/MDI-X cross-over correction.
1.4.4
System Peripherals
1.4.4.1
Programmable GPIOs (see page 149)
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections.
®
The Stellaris GPIO module is comprised of seven physical GPIO blocks, each corresponding to
an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation
IP for Real-Time Microcontrollers specification) and supports 8-35 programmable input/output pins.
The number of GPIOs available depends on the peripherals being used (see “Signal
Tables” on page 461 for the signals available to each GPIO pin).
The GPIO module features programmable interrupt generation as either edge-triggered or
level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in
both read and write operations through address lines. Pins configured as digital inputs are
Schmitt-triggered.
1.4.4.2
Four Programmable Timers (see page 190)
Programmable timers can be used to count or time external events that drive the Timer input pins.
®
The Stellaris General-Purpose Timer Module (GPTM) contains four GPTM blocks. Each GPTM
block provides two 16-bit timers/counters that can be configured to operate independently as timers
or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or
periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can
extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event
capture or Pulse Width Modulation (PWM) generation.
1.4.4.3
Watchdog Timer (see page 226)
A watchdog timer can generate an interrupt or a reset when a time-out value is reached. The
watchdog timer is used to regain control when a system has failed due to a software error or to the
failure of an external device to respond in the expected way.
®
The Stellaris Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, and a locking register.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
1.4.5
Memory Peripherals
The LM3S8530 controller offers both single-cycle SRAM and single-cycle Flash memory.
1.4.5.1
SRAM (see page 124)
The LM3S8530 static random access memory (SRAM) controller supports 64 KB SRAM. The internal
®
SRAM of the Stellaris devices starts at base address 0x2000.0000 of the device memory map. To
reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced
bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
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Architectural Overview
1.4.5.2
Flash (see page 125)
The LM3S8530 Flash controller supports 96 KB of flash memory. The flash is organized as a set
of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the
block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually
protected. The blocks can be marked as read-only or execute-only, providing different levels of code
protection. Read-only blocks cannot be erased or programmed, protecting the contents of those
blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only
be read by the controller instruction fetch mechanism, protecting the contents of those blocks from
being read by either the controller or by a debugger.
1.4.6
Additional Features
1.4.6.1
Memory Map (see page 46)
A memory map lists the location of instructions and data in memory. The memory map for the
LM3S8530 controller can be found in “Memory Map” on page 46. Register addresses are given as
a hexadecimal increment, relative to the module's base address as shown in the memory map.
The ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory
map.
1.4.6.2
JTAG TAP Controller (see page 51)
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is composed of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is
transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of
this data is dependent on the current state of the TAP controller. For detailed information on the
operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test
Access Port and Boundary-Scan Architecture.
®
The Stellaris JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core.
This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
®
®
instructions select the ARM TDO output while Stellaris JTAG instructions select the Stellaris TDO
®
outputs. The multiplexer is controlled by the Stellaris JTAG controller, which has comprehensive
®
programming for the ARM, Stellaris , and unimplemented JTAG instructions.
1.4.6.3
System Control and Clocks (see page 63)
System control determines the overall operation of the device. It provides information about the
device, controls the clocking of the device and individual peripherals, and handles reset detection
and reporting.
1.4.7
Hardware Details
Details on the pins and package can be found in the following sections:
■ “Pin Diagram” on page 459
■ “Signal Tables” on page 461
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■ “Operating Characteristics” on page 484
■ “Electrical Characteristics” on page 485
■ “Package Information” on page 522
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ARM Cortex-M3 Processor Core
2
ARM Cortex-M3 Processor Core
The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that
meets the needs of minimal memory implementation, reduced pin count, and low power consumption,
while delivering outstanding computational performance and exceptional system response to
interrupts. Features include:
■ Compact core.
■ Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory
size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of
memory for microcontroller class applications.
■ Rapid application execution through Harvard architecture characterized by separate buses for
instruction and data.
■ Exceptional interrupt handling, by implementing the register manipulations required for handling
an interrupt in hardware.
■ Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
■ Memory protection unit (MPU) to provide a privileged mode of operation for complex applications.
■ Migration from the ARM7™ processor family for better performance and power efficiency.
■ Full-featured debug solution
– Serial Wire JTAG Debug Port (SWJ-DP)
– Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
– Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
– Instrumentation Trace Macrocell (ITM) for support of printf style debugging
– Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
■ Optimized for single-cycle flash usage
■ Three sleep modes with clock gating for low power
■ Single-cycle multiply instruction and hardware divide
■ Atomic operations
■ ARM Thumb2 mixed 16-/32-bit instruction set
■ 1.25 DMIPS/MHz
®
The Stellaris family of microcontrollers builds on this core to bring high-performance 32-bit computing
to cost-sensitive embedded microcontroller applications, such as factory automation and control,
industrial control power devices, building and home automation, and stepper motors.
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For more information on the ARM Cortex-M3 processor core, see the ARM® Cortex™-M3 Technical
Reference Manual. For information on SWJ-DP, see the ARM® CoreSight Technical Reference
Manual.
2.1
Block Diagram
Figure 2-1. CPU Block Diagram
Nested
Vectored
Interrupt
Controller
Interrupts
Sleep
ARM
Cortex-M3
CM3 Core
Debug
Instructions
Data
Trace
Port
Interface
Unit
Memory
Protection
Unit
Flash
Patch and
Breakpoint
Instrumentation
Data
Watchpoint Trace Macrocell
and Trace
2.2
Adv. HighPerf. Bus
Access Port
Private
Peripheral
Bus
(external)
ROM
Table
Private Peripheral
Bus
(internal)
Serial Wire JTAG
Debug Port
Serial
Wire
Output
Trace
Port
(SWO)
Adv. Peripheral
Bus
Bus
Matrix
I-code bus
D-code bus
System bus
Functional Description
Important: The ARM® Cortex™-M3 Technical Reference Manual describes all the features of an
ARM Cortex-M3 in detail. However, these features differ based on the implementation.
®
This section describes the Stellaris implementation.
Texas Instruments has implemented the ARM Cortex-M3 core as shown in Figure 2-1 on page 41.
As noted in the ARM® Cortex™-M3 Technical Reference Manual, several Cortex-M3 components
are flexible in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the MPU, and the
Nested Vectored Interrupt Controller (NVIC). Each of these is addressed in the sections that follow.
2.2.1
Serial Wire and JTAG Debug
Texas Instruments has replaced the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant
Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and
JTAG debug ports into one module. See the CoreSight™ Design Kit Technical Reference Manual
for details on SWJ-DP.
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ARM Cortex-M3 Processor Core
2.2.2
Embedded Trace Macrocell (ETM)
®
ETM was not implemented in the Stellaris devices. This means Chapters 15 and 16 of the ARM®
Cortex™-M3 Technical Reference Manual can be ignored.
2.2.3
Trace Port Interface Unit (TPIU)
The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace
®
Port Analyzer. The Stellaris devices have implemented TPIU as shown in Figure 2-2 on page 42.
This is similar to the non-ETM version described in the ARM® Cortex™-M3 Technical Reference
Manual, however, SWJ-DP only provides SWV output for the TPIU.
Figure 2-2. TPIU Block Diagram
2.2.4
Debug
ATB
Slave
Port
ATB
Interface
APB
Slave
Port
APB
Interface
Asynchronous FIFO
Trace Out
(serializer)
Serial Wire
Trace Port
(SWO)
ROM Table
The default ROM table was implemented as described in the ARM® Cortex™-M3 Technical
Reference Manual.
2.2.5
Memory Protection Unit (MPU)
The Memory Protection Unit (MPU) is included on the LM3S8530 controller and supports the standard
ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for
protection regions, overlapping protection regions, access permissions, and exporting memory
attributes to the system.
2.2.6
Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC):
■ Facilitates low-latency exception and interrupt handling
■ Controls power management
■ Implements system control registers
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The NVIC supports up to 240 dynamically reprioritizable interrupts each with up to 256 levels of
priority. The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge
of the stacked (nested) interrupts to enable tail-chaining of interrupts.
You can only fully access the NVIC from privileged mode, but you can pend interrupts in user-mode
if you enable the Configuration Control Register (see the ARM® Cortex™-M3 Technical Reference
Manual). Any other user-mode access causes a bus fault.
All NVIC registers are accessible using byte, halfword, and word unless otherwise stated.
2.2.6.1
Interrupts
The ARM® Cortex™-M3 Technical Reference Manual describes the maximum number of interrupts
and interrupt priorities. The LM3S8530 microcontroller supports 26 interrupts with eight priority
levels.
2.2.6.2
System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
Functional Description
The timer consists of three registers:
■ A control and status counter to configure its clock, enable the counter, enable the SysTick
interrupt, and determine counter status.
■ The reload value for the counter, used to provide the counter's wrap value.
■ The current value of the counter.
®
A fourth register, the SysTick Calibration Value Register, is not implemented in the Stellaris devices.
When enabled, the timer counts down from the reload value to zero, reloads (wraps) to the value
in the SysTick Reload Value register on the next clock edge, then decrements on subsequent clocks.
Writing a value of zero to the Reload Value register disables the counter on the next wrap. When
the counter reaches zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
Writing to the Current Value register clears the register and the COUNTFLAG status bit. The write
does not trigger the SysTick exception logic. On a read, the current value is the value of the register
at the time the register is accessed.
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ARM Cortex-M3 Processor Core
If the core is in debug state (halted), the counter will not decrement. The timer is clocked with respect
to a reference clock. The reference clock can be the core clock or an external clock source.
SysTick Control and Status Register
Use the SysTick Control and Status Register to enable the SysTick features. The reset is
0x0000.0000.
Bit/Field
Name
Type
Reset Description
31:17
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide compatibility
with future products, the value of a reserved bit should be preserved across
a read-modify-write operation.
16
COUNTFLAG
R/W
0
Count Flag
Returns 1 if timer counted to 0 since last time this was read. Clears on read
by application. If read by the debugger using the DAP, this bit is cleared on
read-only if the MasterType bit in the AHB-AP Control Register is set to 0.
Otherwise, the COUNTFLAG bit is not changed by the debugger read.
15:3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide compatibility
with future products, the value of a reserved bit should be preserved across
a read-modify-write operation.
2
CLKSOURCE
R/W
0
Clock Source
Value Description
0
External reference clock. (Not implemented for Stellaris
microcontrollers.)
1
Core clock
If no reference clock is provided, it is held at 1 and so gives the same time as
the core clock. The core clock must be at least 2.5 times faster than the
reference clock. If it is not, the count values are unpredictable.
1
TICKINT
R/W
0
Tick Interrupt
Value Description
0
ENABLE
R/W
0
0
Counting down to 0 does not generate the interrupt request to the
NVIC. Software can use the COUNTFLAG to determine if ever counted
to 0.
1
Counting down to 0 pends the SysTick handler.
Enable
Value Description
0
Counter disabled.
1
Counter operates in a multi-shot way. That is, counter loads with the
Reload value and then begins counting down. On reaching 0, it sets
the COUNTFLAG to 1 and optionally pends the SysTick handler, based
on TICKINT. It then loads the Reload value again, and begins counting.
SysTick Reload Value Register
Use the SysTick Reload Value Register to specify the start value to load into the current value
register when the counter reaches 0. It can be any value between 1 and 0x00FF.FFFF. A start value
of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated
when counting from 1 to 0.
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Therefore, as a multi-shot timer, repeated over and over, it fires every N+1 clock pulse, where N is
any value from 1 to 0x00FF.FFFF. So, if the tick interrupt is required every 100 clock pulses, 99
must be written into the RELOAD. If a new value is written on each tick interrupt, so treated as single
shot, then the actual count down must be written. For example, if a tick is next required after 400
clock pulses, 400 must be written into the RELOAD.
Bit/Field
Name
Type
Reset
Description
31:24
reserved
RO
0
Software should not rely on the value of a reserved bit. To
provide compatibility with future products, the value of a reserved
bit should be preserved across a read-modify-write operation.
23:0
RELOAD
R/W
-
Reload
Value to load into the SysTick Current Value Register when the
counter reaches 0.
SysTick Current Value Register
Use the SysTick Current Value Register to find the current value in the register.
Bit/Field
Name
Type
Reset Description
31:24
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:0
CURRENT
W1C
-
Current Value
Current value at the time the register is accessed. No read-modify-write
protection is provided, so change with care.
This register is write-clear. Writing to it with any value clears the register
to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick
Control and Status Register.
SysTick Calibration Value Register
The SysTick Calibration Value register is not implemented.
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Memory Map
3
Memory Map
The memory map for the LM3S8530 controller is provided in Table 3-1 on page 46.
In this manual, register addresses are given as a hexadecimal increment, relative to the module’s
base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM®
Cortex™-M3 Technical Reference Manual.
a
Table 3-1. Memory Map
Start
End
Description
0x0000.0000
0x0001.7FFF
On-chip flash
0x0001.8000
0x1FFF.FFFF
Reserved
For details on
registers, see
page ...
Memory
b
128
c
0x2000.0000
0x2000.FFFF
Bit-banded on-chip SRAM
128
0x2001.0000
0x21FF.FFFF
Reserved
-
0x2200.0000
0x221F.FFFF
Bit-band alias of 0x2000.0000 through 0x200F.FFFF
124
0x2220.0000
0x3FFF.FFFF
Reserved
-
0x4000.0000
0x4000.0FFF
Watchdog timer
229
0x4000.1000
0x4000.3FFF
Reserved
-
0x4000.4000
0x4000.4FFF
GPIO Port A
155
0x4000.5000
0x4000.5FFF
GPIO Port B
155
0x4000.6000
0x4000.6FFF
GPIO Port C
155
0x4000.7000
0x4000.7FFF
GPIO Port D
155
0x4000.8000
0x4000.8FFF
SSI0
302
0x4000.9000
0x4000.9FFF
SSI1
302
0x4000.A000
0x4000.BFFF
Reserved
-
0x4000.C000
0x4000.CFFF
UART0
257
0x4000.D000
0x4001.FFFF
Reserved
-
0x4002.0000
0x4002.07FF
I2C Master 0
342
0x4002.0800
0x4002.0FFF
I2C Slave 0
355
0x4002.1000
0x4002.3FFF
Reserved
-
0x4002.4000
0x4002.4FFF
GPIO Port E
155
0x4002.5000
0x4002.5FFF
GPIO Port F
155
0x4002.6000
0x4002.6FFF
GPIO Port G
155
0x4002.7000
0x4002.FFFF
Reserved
-
0x4003.0000
0x4003.0FFF
Timer0
201
0x4003.1000
0x4003.1FFF
Timer1
201
0x4003.2000
0x4003.2FFF
Timer2
201
0x4003.3000
0x4003.3FFF
Timer3
201
0x4003.4000
0x4003.FFFF
Reserved
-
0x4004.0000
0x4004.0FFF
CAN0 Controller
384
FiRM Peripherals
Peripherals
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Table 3-1. Memory Map (continued)
Start
End
Description
For details on
registers, see
page ...
0x4004.1000
0x4004.1FFF
CAN1 Controller
384
0x4004.2000
0x4004.2FFF
CAN2 Controller
384
0x4004.3000
0x4004.7FFF
Reserved
-
0x4004.8000
0x4004.8FFF
Ethernet Controller
422
0x4004.9000
0x400F.CFFF
Reserved
-
0x400F.D000
0x400F.DFFF
Flash control
128
0x400F.E000
0x400F.EFFF
System control
75
0x400F.F000
0x41FF.FFFF
Reserved
-
0x4200.0000
0x43FF.FFFF
Bit-banded alias of 0x4000.0000 through 0x400F.FFFF
-
0x4400.0000
0xDFFF.FFFF
Reserved
-
0xE000.0000
0xE000.0FFF
Instrumentation Trace Macrocell (ITM)
ARM®
Cortex™-M3
Technical
Reference
Manual
0xE000.1000
0xE000.1FFF
Data Watchpoint and Trace (DWT)
ARM®
Cortex™-M3
Technical
Reference
Manual
0xE000.2000
0xE000.2FFF
Flash Patch and Breakpoint (FPB)
ARM®
Cortex™-M3
Technical
Reference
Manual
0xE000.3000
0xE000.DFFF
Reserved
-
0xE000.E000
0xE000.EFFF
Nested Vectored Interrupt Controller (NVIC)
ARM®
Cortex™-M3
Technical
Reference
Manual
0xE000.F000
0xE003.FFFF
Reserved
-
0xE004.0000
0xE004.0FFF
Trace Port Interface Unit (TPIU)
ARM®
Cortex™-M3
Technical
Reference
Manual
0xE004.1000
0xFFFF.FFFF
Reserved
-
Private Peripheral Bus
a. All reserved space returns a bus fault when read or written.
b. The unavailable flash will bus fault throughout this range.
c. The unavailable SRAM will bus fault throughout this range.
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Interrupts
4
Interrupts
The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and
handle all exceptions. All exceptions are handled in Handler Mode. The processor state is
automatically stored to the stack on an exception, and automatically restored from the stack at the
end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which
enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back
interrupts to be performed without the overhead of state saving and restoration.
Table 4-1 on page 48 lists all exception types. Software can set eight priority levels on seven of
these exceptions (system handlers) as well as on 26 interrupts (listed in Table 4-2 on page 49).
Priorities on the system handlers are set with the NVIC System Handler Priority registers. Interrupts
are enabled through the NVIC Interrupt Set Enable register and prioritized with the NVIC Interrupt
Priority registers. You also can group priorities by splitting priority levels into pre-emption priorities
and subpriorities. All of the interrupt registers are described in Chapter 8, “Nested Vectored Interrupt
Controller” in the ARM® Cortex™-M3 Technical Reference Manual.
Internally, the highest user-settable priority (0) is treated as fourth priority, after a Reset, NMI, and
a Hard Fault. Note that 0 is the default priority for all the settable priorities.
If you assign the same priority level to two or more interrupts, their hardware priority (the lower
position number) determines the order in which the processor activates them. For example, if both
GPIO Port A and GPIO Port B are priority level 1, then GPIO Port A has higher priority.
Important: It may take several processor cycles after a write to clear an interrupt source in order
for NVIC to see the interrupt source de-assert. This means if the interrupt clear is done
as the last action in an interrupt handler, it is possible for the interrupt handler to complete
while NVIC sees the interrupt as still asserted, causing the interrupt handler to be
re-entered errantly. This can be avoided by either clearing the interrupt source at the
beginning of the interrupt handler or by performing a read or write after the write to clear
the interrupt source (and flush the write buffer).
See Chapter 5, “Exceptions” and Chapter 8, “Nested Vectored Interrupt Controller” in the ARM®
Cortex™-M3 Technical Reference Manual for more information on exceptions and interrupts.
Table 4-1. Exception Types
Exception Type
Vector
Number
a
Description
Stack top is loaded from first entry of vector table on reset.
Priority
-
0
-
Reset
1
-3 (highest)
Invoked on power up and warm reset. On first instruction, drops to
lowest priority (and then is called the base level of activation). This is
asynchronous.
Non-Maskable
Interrupt (NMI)
2
-2
Cannot be stopped or preempted by any exception but reset. This is
asynchronous.
An NMI is only producible by software, using the NVIC Interrupt
Control State register.
Hard Fault
3
-1
Memory Management
4
settable
All classes of Fault, when the fault cannot activate due to priority or
the configurable fault handler has been disabled. This is synchronous.
MPU mismatch, including access violation and no match. This is
synchronous.
The priority of this exception can be changed.
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Table 4-1. Exception Types (continued)
Exception Type
a
Vector
Number
Bus Fault
Priority
5
Description
settable
Pre-fetch fault, memory access fault, and other address/memory
related faults. This is synchronous when precise and asynchronous
when imprecise.
You can enable or disable this fault.
Usage Fault
6
-
settable
Usage fault, such as undefined instruction executed or illegal state
transition attempt. This is synchronous.
7-10
-
SVCall
11
settable
System service call with SVC instruction. This is synchronous.
Debug Monitor
12
settable
Debug monitor (when not halting). This is synchronous, but only active
when enabled. It does not activate if lower priority than the current
activation.
-
13
-
PendSV
14
settable
Pendable request for system service. This is asynchronous and only
pended by software.
SysTick
15
settable
System tick timer has fired. This is asynchronous.
16 and
above
settable
Asserted from outside the ARM Cortex-M3 core and fed through the
NVIC (prioritized). These are all asynchronous. Table 4-2 on page 49
lists the interrupts on the LM3S8530 controller.
Interrupts
Reserved.
Reserved.
a. 0 is the default priority for all the settable priorities.
Table 4-2. Interrupts
Vector Number
Interrupt Number (Bit in
Interrupt Registers)
Description
0-15
-
Processor exceptions
16
0
GPIO Port A
17
1
GPIO Port B
18
2
GPIO Port C
19
3
GPIO Port D
20
4
GPIO Port E
21
5
UART0
22
6
Reserved
23
7
SSI0
I2C0
24
8
25-33
9-17
34
18
Watchdog timer
35
19
Timer0 A
36
20
Timer0 B
37
21
Timer1 A
38
22
Timer1 B
39
23
Timer2 A
40
24
Timer2 B
41-43
25-27
Reserved
44
28
System Control
45
29
Flash Control
Reserved
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Interrupts
Table 4-2. Interrupts (continued)
Vector Number
Interrupt Number (Bit in
Interrupt Registers)
Description
46
30
GPIO Port F
GPIO Port G
47
31
48-49
32-33
50
34
SSI1
51
35
Timer3 A
52
36
Timer3 B
53-54
37-38
Reserved
55
39
CAN0
56
40
CAN1
57
41
CAN2
58
42
Ethernet Controller
59-70
43-54
Reserved
Reserved
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5
JTAG Interface
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is comprised of five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially
into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent
on the current state of the TAP controller. For detailed information on the operation of the JTAG
port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and
Boundary-Scan Architecture.
®
The Stellaris JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core.
This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
®
®
instructions select the ARM TDO output while Stellaris JTAG instructions select the Stellaris TDO
®
outputs. The multiplexer is controlled by the Stellaris JTAG controller, which has comprehensive
®
programming for the ARM, Stellaris , and unimplemented JTAG instructions.
®
The Stellaris JTAG module has the following features:
■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
■ Four-bit Instruction Register (IR) chain for storing JTAG instructions
■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST
■ ARM additional instructions: APACC, DPACC and ABORT
■ Integrated ARM Serial Wire Debug (SWD)
See the ARM® Cortex™-M3 Technical Reference Manual for more information on the ARM JTAG
controller.
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5.1
Block Diagram
Figure 5-1. JTAG Module Block Diagram
TRST
TCK
TMS
TDI
TAP Controller
Instruction Register (IR)
BYPASS Data Register
TDO
Boundary Scan Data Register
IDCODE Data Register
ABORT Data Register
DPACC Data Register
APACC Data Register
Cortex-M3
Debug
Port
5.2
Functional Description
A high-level conceptual drawing of the JTAG module is shown in Figure 5-1 on page 52. The JTAG
module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel
update registers. The TAP controller is a simple state machine controlled by the TRST, TCK and
TMS inputs. The current state of the TAP controller depends on the current value of TRST and the
sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when
the serial shift chains capture new data, shift data from TDI towards TDO, and update the parallel
load registers. The current state of the TAP controller also determines whether the Instruction
Register (IR) chain or one of the Data Register (DR) chains is being accessed.
The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR)
chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load
register determines which DR chain is captured, shifted, or updated during the sequencing of the
TAP controller.
Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not
capture, shift, or update any of the chains. Instructions that are not implemented decode to the
BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see
Table 5-2 on page 58 for a list of implemented instructions).
See “JTAG and Boundary Scan” on page 489 for JTAG timing diagrams.
5.2.1
JTAG Interface Pins
The JTAG interface consists of five standard pins: TRST,TCK, TMS, TDI, and TDO. These pins and
their associated reset state are given in Table 5-1 on page 53. Detailed information on each pin
follows.
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Table 5-1. JTAG Port Pins Reset State
5.2.1.1
Pin Name
Data Direction
Internal Pull-Up
Internal Pull-Down
Drive Strength
Drive Value
TRST
Input
Enabled
Disabled
N/A
N/A
TCK
Input
Enabled
Disabled
N/A
N/A
TMS
Input
Enabled
Disabled
N/A
N/A
TDI
Input
Enabled
Disabled
N/A
N/A
TDO
Output
Enabled
Disabled
2-mA driver
High-Z
Test Reset Input (TRST)
The TRST pin is an asynchronous active Low input signal for initializing and resetting the JTAG TAP
controller and associated JTAG circuitry. When TRST is asserted, the TAP controller resets to the
Test-Logic-Reset state and remains there while TRST is asserted. When the TAP controller enters
the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction,
IDCODE.
By default, the internal pull-up resistor on the TRST pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port B should ensure that the internal pull-up resistor remains enabled
on PB7/TRST; otherwise JTAG communication could be lost.
5.2.1.2
Test Clock Input (TCK)
The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate
independently of any other system clocks. In addition, it ensures that multiple JTAG TAP controllers
that are daisy-chained together can synchronously communicate serial test data between
components. During normal operation, TCK is driven by a free-running clock with a nominal 50%
duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK
is stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction
and Data Registers is not lost.
By default, the internal pull-up resistor on the TCK pin is enabled after reset. This assures that no
clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down
resistors can be turned off to save internal power as long as the TCK pin is constantly being driven
by an external source.
5.2.1.3
Test Mode Select (TMS)
The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge
of TCK. Depending on the current TAP state and the sampled value of TMS, the next state is entered.
Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the
value on TMS to change on the falling edge of TCK.
Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the
Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG
Instruction Register (IR) resets to the default instruction, IDCODE. Therefore, this sequence can
be used as a reset mechanism, similar to asserting TRST. The JTAG Test Access Port state machine
can be seen in its entirety in Figure 5-2 on page 55.
By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC1/TMS; otherwise JTAG communication could be lost.
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5.2.1.4
Test Data Input (TDI)
The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is
sampled on the rising edge of TCK and, depending on the current TAP state and the current
instruction, presents this data to the proper shift register chain. Because the TDI pin is sampled on
the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the falling
edge of TCK.
By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC2/TDI; otherwise JTAG communication could be lost.
5.2.1.5
Test Data Output (TDO)
The TDO pin provides an output stream of serial information from the IR chain or the DR chains.
The value of TDO depends on the current TAP state, the current instruction, and the data in the
chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin
is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected
to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects
the value on TDO to change on the falling edge of TCK.
By default, the internal pull-up resistor on the TDO pin is enabled after reset. This assures that the
pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up and
pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable
during certain TAP controller states.
5.2.2
JTAG TAP Controller
The JTAG TAP controller state machine is shown in Figure 5-2 on page 55. The TAP controller
state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR)
or the assertion of TRST. Asserting the correct sequence on the TMS pin allows the JTAG module
to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed
information on the function of the TAP controller and the operations that occur in each state, please
refer to IEEE Standard 1149.1.
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Figure 5-2. Test Access Port State Machine
Test Logic Reset
1
0
Run Test Idle
0
Select DR Scan
1
Select IR Scan
1
0
1
Capture DR
1
Capture IR
0
0
Shift DR
Shift IR
0
1
Exit 1 DR
Exit 1 IR
1
Pause IR
0
1
Exit 2 DR
0
1
0
Exit 2 IR
1
1
Update DR
5.2.3
1
0
Pause DR
1
0
1
0
0
1
0
0
Update IR
1
0
Shift Registers
The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift
register chain samples specific information during the TAP controller’s CAPTURE states and allows
this information to be shifted out of TDO during the TAP controller’s SHIFT states. While the sampled
data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register
on TDI. This new data is stored in the parallel load register during the TAP controller’s UPDATE
states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 58.
5.2.4
Operational Considerations
There are certain operational considerations when using the JTAG module. Because the JTAG pins
can be programmed to be GPIOs, board configuration and reset conditions on these pins must be
considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the
method for switching between these two operational modes is described below.
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5.2.4.1
GPIO Functionality
When the controller is reset with either a POR or RST, the JTAG/SWD port pins default to their
JTAG/SWD configurations. The default configuration includes enabling digital functionality (setting
GPIODEN to 1), enabling the pull-up resistors (setting GPIOPUR to 1), and enabling the alternate
hardware function (setting GPIOAFSEL to 1) for the PB7 and PC[3:0] JTAG/SWD pins.
It is possible for software to configure these pins as GPIOs after reset by writing 0s to PB7 and
PC[3:0] in the GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging
or board-level testing, this provides five more GPIOs for use in the design.
Caution – It is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG
pins to their GPIO functionality, the debugger may not have enough time to connect and halt the
controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This
can be avoided with a software routine that restores JTAG functionality based on an external or software
trigger.
The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is currently provided for the five JTAG/SWD pins (PB7 and
PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register
(see page 165) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see
page 175) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see
page 176) have been set to 1.
Recovering a "Locked" Device
Note:
The mass erase of the flash memory caused by the below sequence erases the entire flash
memory, regardless of the settings in the Flash Memory Protection Program Enable n
(FMPPEn) registers. Performing the sequence below does not affect the nonvolatile registers
discussed in “Nonvolatile Register Programming” on page 127.
If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate
with the debugger, there is a debug sequence that can be used to recover the device. Performing
a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the device in reset
mass erases the flash memory. The sequence to recover the device is:
1. Assert and hold the RST signal.
2. Perform the JTAG-to-SWD switch sequence.
3. Perform the SWD-to-JTAG switch sequence.
4. Perform the JTAG-to-SWD switch sequence.
5. Perform the SWD-to-JTAG switch sequence.
6. Perform the JTAG-to-SWD switch sequence.
7. Perform the SWD-to-JTAG switch sequence.
8. Perform the JTAG-to-SWD switch sequence.
9. Perform the SWD-to-JTAG switch sequence.
10. Perform the JTAG-to-SWD switch sequence.
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11. Perform the SWD-to-JTAG switch sequence.
12. Release the RST signal.
13. Wait 400 ms.
14. Power-cycle the device.
The JTAG-to-SWD and SWD-to-JTAG switch sequences are described in “ARM Serial Wire Debug
(SWD)” on page 57. When performing switch sequences for the purpose of recovering the debug
capabilities of the device, only steps 1 and 2 of the switch sequence in the section called
“JTAG-to-SWD Switching” on page 57 must be performed.
5.2.4.2
Communication with JTAG/SWD
Because the debug clock and the system clock can be running at different frequencies, care must
be taken to maintain reliable communication with the JTAG/SWD interface. In the Capture-DR state,
the result of the previous transaction, if any, is returned, together with a 3-bit ACK response. Software
should check the ACK response to see if the previous operation has completed before initiating a
new transaction. Alternatively, if the system clock is at least 8 times faster than the debug clock
(TCK or SWCLK), the previous operation has enough time to complete and the ACK bits do not have
to be checked.
5.2.4.3
ARM Serial Wire Debug (SWD)
In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire
debugger must be able to connect to the Cortex-M3 core without having to perform, or have any
knowledge of, JTAG cycles. This is accomplished with a SWD preamble that is issued before the
SWD session begins.
The switching preamble used to enable the SWD interface of the SWJ-DP module starts with the
TAP controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller
through the following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic
Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run
Test Idle, Run Test Idle, Select DR, Select IR, and Test Logic Reset states.
Stepping through this sequences of the TAP state machine enables the SWD interface and disables
the JTAG interface. For more information on this operation and the SWD interface, see the ARM®
Cortex™-M3 Technical Reference Manual and the ARM® CoreSight Technical Reference Manual.
Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG
TAP controller is not fully compliant to the IEEE Standard 1149.1. This is the only instance where
the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low
probability of this sequence occurring during normal operation of the TAP controller, it should not
affect normal performance of the JTAG interface.
JTAG-to-SWD Switching
To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the
external debug hardware must send the switching preamble to the device. The 16-bit switch sequence
for switching to SWD mode is defined as b1110011110011110, transmitted LSB first. This can also
be represented as 16'hE79E when transmitted LSB first. The complete switch sequence should
consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and
SWD are in their reset/idle states.
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2. Send the 16-bit JTAG-to-SWD switch sequence, 16'hE79E.
3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was
already in SWD mode, before sending the switch sequence, the SWD goes into the line reset
state.
SWD-to-JTAG Switching
To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the
external debug hardware must send a switch sequence to the device. The 16-bit switch sequence
for switching to JTAG mode is defined as b1110011100111100, transmitted LSB first. This can also
be represented as 16'hE73C when transmitted LSB first. The complete switch sequence should
consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and
SWD are in their reset/idle states.
2. Send the 16-bit SWD-to-JTAG switch sequence, 16'hE73C.
3. Send at least 5 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was
already in JTAG mode, before sending the switch sequence, the JTAG goes into the Test Logic
Reset state.
5.3
Initialization and Configuration
After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for
JTAG communication. No user-defined initialization or configuration is needed. However, if the user
application changes these pins to their GPIO function, they must be configured back to their JTAG
functionality before JTAG communication can be restored. This is done by enabling the five JTAG
pins (PB7 and PC[3:0]) for their alternate function using the GPIOAFSEL register. In addition to
enabling the alternate functions, any other changes to the GPIO pad configurations on the five JTAG
pins (PB7 andPC[3:0]) should be reverted to their default settings.
5.4
Register Descriptions
There are no APB-accessible registers in the JTAG TAP Controller or Shift Register chains. The
registers within the JTAG controller are all accessed serially through the TAP Controller. The registers
can be broken down into two main categories: Instruction Registers and Data Registers.
5.4.1
Instruction Register (IR)
The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain connected between the JTAG
TDI and TDO pins with a parallel load register. When the TAP Controller is placed in the correct
states, bits can be shifted into the Instruction Register. Once these bits have been shifted into the
chain and updated, they are interpreted as the current instruction. The decode of the Instruction
Register bits is shown in Table 5-2 on page 58. A detailed explanation of each instruction, along
with its associated Data Register, follows.
Table 5-2. JTAG Instruction Register Commands
IR[3:0]
Instruction
0000
EXTEST
Description
Drives the values preloaded into the Boundary Scan Chain by the
SAMPLE/PRELOAD instruction onto the pads.
0001
INTEST
Drives the values preloaded into the Boundary Scan Chain by the
SAMPLE/PRELOAD instruction into the controller.
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Table 5-2. JTAG Instruction Register Commands (continued)
5.4.1.1
IR[3:0]
Instruction
0010
SAMPLE / PRELOAD
Description
Captures the current I/O values and shifts the sampled values out of the
Boundary Scan Chain while new preload data is shifted in.
1000
ABORT
Shifts data into the ARM Debug Port Abort Register.
1010
DPACC
Shifts data into and out of the ARM DP Access Register.
1011
APACC
Shifts data into and out of the ARM AC Access Register.
1110
IDCODE
Loads manufacturing information defined by the IEEE Standard 1149.1
into the IDCODE chain and shifts it out.
1111
BYPASS
Connects TDI to TDO through a single Shift Register chain.
All Others
Reserved
Defaults to the BYPASS instruction to ensure that TDI is always connected
to TDO.
EXTEST Instruction
The EXTEST instruction is not associated with its own Data Register chain. The EXTEST instruction
uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the outputs and output
enables are used to drive the GPIO pads rather than the signals coming from the core. This allows
tests to be developed that drive known values out of the controller, which can be used to verify
connectivity. While the EXTEST instruction is present in the Instruction Register, the Boundary Scan
Data Register can be accessed to sample and shift out the current data and load new data into the
Boundary Scan Data Register.
5.4.1.2
INTEST Instruction
The INTEST instruction is not associated with its own Data Register chain. The INTEST instruction
uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the INTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive
the signals going into the core rather than the signals coming from the GPIO pads. This allows tests
to be developed that drive known values into the controller, which can be used for testing. It is
important to note that although the RST input pin is on the Boundary Scan Data Register chain, it
is only observable. While the INTEXT instruction is present in the Instruction Register, the Boundary
Scan Data Register can be accessed to sample and shift out the current data and load new data
into the Boundary Scan Data Register.
5.4.1.3
SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between
TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads
new test data. Each GPIO pad has an associated input, output, and output enable signal. When the
TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable
signals to each of the GPIO pads are captured. These samples are serially shifted out of TDO while
the TAP controller is in the Shift DR state and can be used for observation or comparison in various
tests.
While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary
Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI.
Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the
parallel load registers when the TAP controller enters the Update DR state. This update of the
parallel load register preloads data into the Boundary Scan Data Register that is associated with
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each input, output, and output enable. This preloaded data can be used with the EXTEST and
INTEST instructions to drive data into or out of the controller. Please see “Boundary Scan Data
Register” on page 61 for more information.
5.4.1.4
ABORT Instruction
The ABORT instruction connects the associated ABORT Data Register chain between TDI and
TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates
a DAP abort of a previous request. Please see the “ABORT Data Register” on page 62 for more
information.
5.4.1.5
DPACC Instruction
The DPACC instruction connects the associated DPACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to the ARM debug and status registers. Please see “DPACC
Data Register” on page 62 for more information.
5.4.1.6
APACC Instruction
The APACC instruction connects the associated APACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the APACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to internal components and buses through the Debug Port.
Please see “APACC Data Register” on page 62 for more information.
5.4.1.7
IDCODE Instruction
The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and
TDO. This instruction provides information on the manufacturer, part number, and version of the
ARM core. This information can be used by testing equipment and debuggers to automatically
configure their input and output data streams. IDCODE is the default instruction that is loaded into
the JTAG Instruction Register when a Power-On-Reset (POR) is asserted, TRST is asserted, or the
Test-Logic-Reset state is entered. Please see “IDCODE Data Register” on page 61 for more
information.
5.4.1.8
BYPASS Instruction
The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and
TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports.
The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by
allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain
by loading them with the BYPASS instruction. Please see “BYPASS Data Register” on page 61 for
more information.
5.4.2
Data Registers
The JTAG module contains six Data Registers. These include: IDCODE, BYPASS, Boundary Scan,
APACC, DPACC, and ABORT serial Data Register chains. Each of these Data Registers is discussed
in the following sections.
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5.4.2.1
IDCODE Data Register
The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 5-3 on page 61. The standard requires that every JTAG-compliant device implement either
the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE
Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB
of 0. This allows auto configuration test tools to determine which instruction is the default instruction.
The major uses of the JTAG port are for manufacturer testing of component assembly, and program
development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE
instruction outputs a value of 0x3BA0.0477. This allows the debuggers to automatically configure
themselves to work correctly with the Cortex-M3 during debug.
Figure 5-3. IDCODE Register Format
31
TDI
5.4.2.2
28 27
12 11
Version
Part Number
1 0
Manufacturer ID
1
TDO
BYPASS Data Register
The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 5-4 on page 61. The standard requires that every JTAG-compliant device implement either
the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS
Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB
of 1. This allows auto configuration test tools to determine which instruction is the default instruction.
Figure 5-4. BYPASS Register Format
0
TDI
5.4.2.3
0
TDO
Boundary Scan Data Register
The format of the Boundary Scan Data Register is shown in Figure 5-5 on page 62. Each GPIO
pin, starting with a GPIO pin next to the JTAG port pins, is included in the Boundary Scan Data
Register. Each GPIO pin has three associated digital signals that are included in the chain. These
signals are input, output, and output enable, and are arranged in that order as can be seen in the
figure.
When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the
input, output, and output enable from each digital pad are sampled and then shifted out of the chain
to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR
state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain
in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with
the EXTEST and INTEST instructions. These instructions either force data out of the controller, with
the EXTEST instruction, or into the controller, with the INTEST instruction.
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Figure 5-5. Boundary Scan Register Format
TDI
I
N
O
U
T
O
E
...
GPIO PB6
5.4.2.4
I
N
O
U
T
GPIO m
O
E
I
N
RST
I
N
O
U
T
GPIO m+1
O
E
...
I
N
O
U
T
O TDO
E
GPIO n
APACC Data Register
The format for the 35-bit APACC Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
5.4.2.5
DPACC Data Register
The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
5.4.2.6
ABORT Data Register
The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
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6
System Control
System control determines the overall operation of the device. It provides information about the
device, controls the clocking to the core and individual peripherals, and handles reset detection and
reporting.
6.1
Functional Description
The System Control module provides the following capabilities:
■ Device identification (see “Device Identification” on page 63)
■ Local control, such as reset (see “Reset Control” on page 63), power (see “Power
Control” on page 66) and clock control (see “Clock Control” on page 68)
■ System control (Run, Sleep, and Deep-Sleep modes); see “System Control” on page 72
6.1.1
Device Identification
Several read-only registers provide software with information on the microcontroller, such as version,
part number, SRAM size, flash size, and other features. See the DID0, DID1, and DC0-DC4 registers.
6.1.2
Reset Control
This section discusses aspects of hardware functions during reset as well as system software
requirements following the reset sequence.
6.1.2.1
CMOD0 and CMOD1 Test-Mode Control Pins
Two pins, CMOD0 and CMOD1, are defined for internal use for testing the microcontroller during
manufacture. They have no end-user function and should not be used. The CMOD pins should be
connected to ground.
6.1.2.2
Reset Sources
The controller has five sources of reset:
1. External reset input pin (RST) assertion; see “External RST Pin” on page 64.
2. Power-on reset (POR); see “Power-On Reset (POR)” on page 63.
3. Internal brown-out (BOR) detector; see “Brown-Out Reset (BOR)” on page 65.
4. Software-initiated reset (with the software reset registers); see “Software Reset” on page 66.
5. A watchdog timer reset condition violation; see “Watchdog Timer Reset” on page 66.
After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register
are sticky and maintain their state across multiple reset sequences, except when an internal POR
is the cause, and then all the other bits in the RESC register are cleared except for the POR indicator.
6.1.2.3
Power-On Reset (POR)
Note:
The power-on reset also resets the JTAG controller. An external reset does not.
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The internal Power-On Reset (POR) circuit monitors the power supply voltage (VDD) and generates
a reset signal to all of the internal logic including JTAG when the power supply ramp reaches a
threshold value (VTH). The microcontroller must be operating within the specified operating parameters
when the on-chip power-on reset pulse is complete. The 3.3-V power supply to the microcontroller
must reach 3.0 V within 10 msec of VDD crossing 2.0 V to guarantee proper operation. For applications
that require the use of an external reset signal to hold the microcontroller in reset longer than the
internal POR, the RST input may be used as discussed in “External RST Pin” on page 64.
The Power-On Reset sequence is as follows:
1. The microcontroller waits for internal POR to go inactive.
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, and the first instruction designated by the program counter, and then begins
execution.
The internal POR is only active on the initial power-up of the microcontroller. The Power-On Reset
timing is shown in Figure 19-6 on page 492.
6.1.2.4
External RST Pin
Note:
It is recommended that the trace for the RST signal must be kept as short as possible. Be
sure to place any components connected to the RST signal as close to the microcontroller
as possible.
If the application only uses the internal POR circuit, the RST input must be connected to the power
supply (VDD) through an optional pull-up resistor (0 to 100K Ω) as shown in Figure 6-1 on page 64.
Figure 6-1. Basic RST Configuration
VDD
Stellaris®
RPU
RST
RPU = 0 to 100 kΩ
The external reset pin (RST) resets the microcontroller including the core and all the on-chip
peripherals except the JTAG TAP controller (see “JTAG Interface” on page 51). The external reset
sequence is as follows:
1. The external reset pin (RST) is asserted for the duration specified by TMIN and then de-asserted
(see “Reset” on page 491).
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, and the first instruction designated by the program counter, and then begins
execution.
To improve noise immunity and/or to delay reset at power up, the RST input may be connected to
an RC network as shown in Figure 6-2 on page 65.
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Figure 6-2. External Circuitry to Extend Power-On Reset
VDD
Stellaris®
RPU
RST
C1
RPU = 1 kΩ to 100 kΩ
C1 = 1 nF to 10 µF
If the application requires the use of an external reset switch, Figure 6-3 on page 65 shows the
proper circuitry to use.
Figure 6-3. Reset Circuit Controlled by Switch
VDD
Stellaris®
RPU
RST
C1
RS
Typical RPU = 10 kΩ
Typical RS = 470 Ω
C1 = 10 nF
The RPU and C1 components define the power-on delay.
The external reset timing is shown in Figure 19-5 on page 492.
6.1.2.5
Brown-Out Reset (BOR)
A drop in the input voltage resulting in the assertion of the internal brown-out detector can be used
to reset the controller. This is initially disabled and may be enabled by software.
The system provides a brown-out detection circuit that triggers if the power supply (VDD) drops
below a brown-out threshold voltage (VBTH). If a brown-out condition is detected, the system may
generate a controller interrupt or a system reset.
Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL)
register. The BORIOR bit in the PBORCTL register must be set for a brown-out condition to trigger
a reset.
The brown-out reset is equivalent to an assertion of the external RST input and the reset is held
active until the proper VDD level is restored. The RESC register can be examined in the reset interrupt
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handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to
determine what actions are required to recover.
The internal Brown-Out Reset timing is shown in Figure 19-7 on page 492.
6.1.2.6
Software Reset
Software can reset a specific peripheral or generate a reset to the entire system .
Peripherals can be individually reset by software via three registers that control reset signals to each
peripheral (see the SRCRn registers). If the bit position corresponding to a peripheral is set and
subsequently cleared, the peripheral is reset. The encoding of the reset registers is consistent with
the encoding of the clock gating control for peripherals and on-chip functions (see “System
Control” on page 72). Note that all reset signals for all clocks of the specified unit are asserted as
a result of a software-initiated reset.
The entire system can be reset by software by setting the SYSRESETREQ bit in the Cortex-M3
Application Interrupt and Reset Control register resets the entire system including the core. The
software-initiated system reset sequence is as follows:
1. A software system reset is initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3
Application Interrupt and Reset Control register.
2. An internal reset is asserted.
3. The internal reset is deasserted and the controller loads from memory the initial stack pointer,
the initial program counter, and the first instruction designated by the program counter, and
then begins execution.
The software-initiated system reset timing is shown in Figure 19-8 on page 492.
6.1.2.7
Watchdog Timer Reset
The watchdog timer module's function is to prevent system hangs. The watchdog timer can be
configured to generate an interrupt to the controller on its first time-out, and to generate a reset
signal on its second time-out.
After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value. If the timer counts
down to its zero state again before the first time-out interrupt is cleared, and the reset signal has
been enabled, the watchdog timer asserts its reset signal to the system. The watchdog timer reset
sequence is as follows:
1. The watchdog timer times out for the second time without being serviced.
2. An internal reset is asserted.
3. The internal reset is released and the controller loads from memory the initial stack pointer, the
initial program counter, the first instruction designated by the program counter, and begins
execution.
The watchdog reset timing is shown in Figure 19-9 on page 493.
6.1.3
Power Control
®
The Stellaris microcontroller provides an integrated LDO regulator that may be used to provide
power to the majority of the controller's internal logic. For power reduction, the LDO regulator provides
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software a mechanism to adjust the regulated value, in small increments (VSTEP), over the range
of 2.25 V to 2.75 V (inclusive)—or 2.5 V ± 10%. The adjustment is made by changing the value of
the VADJ field in the LDO Power Control (LDOPCTL) register.
Figure 6-4 on page 67 shows the power architecture.
Note:
On the printed circuit board, use the LDO output as the source of VDD25 input. In addition,
the LDO requires decoupling capacitors. See “On-Chip Low Drop-Out (LDO) Regulator
Characteristics” on page 486.
Figure 6-4. Power Architecture
VDD
VCCPHY
VCCPHY
VCCPHY
GNDPHY
Ethernet
PHY
VCCPHY
VDD25
GNDPHY
GNDPHY
VDD25
VDD25
GNDPHY
GND
Internal
Logic and PLL
VDD25
GND
GND
GND
LDO
Low-noise
LDO
+3.3V
VDDA
VDDA
Analog circuits
(ADC, analog
comparators)
VDD
GNDA
GND
VDD
VDD
GNDA
GND
I/O Buffers
VDD
GND
GND
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6.1.4
Clock Control
System control determines the control of clocks in this part.
6.1.4.1
Fundamental Clock Sources
There are multiple clock sources for use in the device:
■ Internal Oscillator (IOSC). The internal oscillator is an on-chip clock source. It does not require
the use of any external components. The frequency of the internal oscillator is 12 MHz ± 30%.
Applications that do not depend on accurate clock sources may use this clock source to reduce
system cost. The internal oscillator is the clock source the device uses during and following POR.
If the main oscillator is required, software must enable the main oscillator following reset and
allow the main oscillator to stabilize before changing the clock reference.
■ Main Oscillator (MOSC). The main oscillator provides a frequency-accurate clock source by
one of two means: an external single-ended clock source is connected to the OSC0 input pin, or
an external crystal is connected across the OSC0 input and OSC1 output pins. If the PLL is being
used, the crystal value must be one of the supported frequencies between 3.579545 MHz through
8.192 MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported
frequencies between 1 MHz and 8.192 MHz. The single-ended clock source range is from DC
through the specified speed of the device. The supported crystals are listed in the XTAL bit field
in the RCC register (see page 84).
■ Internal 30-kHz Oscillator. The internal 30-kHz oscillator is similar to the internal oscillator,
except that it provides an operational frequency of 30 kHz ± 50%. It is intended for use during
Deep-Sleep power-saving modes. This power-savings mode benefits from reduced internal
switching and also allows the main oscillator to be powered down.
The internal system clock (SysClk), is derived from any of the above sources plus two others: the
output of the main internal PLL, and the internal oscillator divided by four (3 MHz ± 30%). The
frequency of the PLL clock reference must be in the range of 3.579545 MHz to 8.192 MHz (inclusive).
Table 6-1 on page 68 shows how the various clock sources can be used in a system.
Table 6-1. Clock Source Options
6.1.4.2
Clock Source
Drive PLL?
Internal Oscillator (12 MHz)
No
BYPASS = 1
Used as SysClk?
Yes
BYPASS = 1, OSCSRC = 0x1
Internal Oscillator divide by 4 (3
MHz)
No
BYPASS = 1
Yes
BYPASS = 1, OSCSRC = 0x2
Main Oscillator
Yes
BYPASS = 0, OSCSRC = Yes
0x0
BYPASS = 1, OSCSRC = 0x0
Internal 30-kHz Oscillator
No
BYPASS = 1
BYPASS = 1, OSCSRC = 0x3
Yes
Clock Configuration
The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2)
registers provide control for the system clock. The RCC2 register is provided to extend fields that
offer additional encodings over the RCC register. When used, the RCC2 register field values are
used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for
a larger assortment of clock configuration options. These registers control the following clock
functionality:
■ Source of clocks in sleep and deep-sleep modes
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■ System clock derived from PLL or other clock source
■ Enabling/disabling of oscillators and PLL
■ Clock divisors
■ Crystal input selection
Figure 6-5 on page 69 shows the logic for the main clock tree. The peripheral blocks are driven by
the system clock signal and can be individually enabled/disabled.
Figure 6-5. Main Clock Tree
USEPWMDIV a
PWMDW a
PWM Clock
XTALa
PWRDN b
MOSCDIS a
PLL
(400 MHz)
Main OSC
USESYSDIV a,d
÷2
IOSCDIS a
System Clock
Internal
OSC
(12 MHz)
SYSDIV b,d
÷4
BYPASS
Internal
OSC
(30 kHz)
Hibernation
Module
(32.768 kHz)
b,d
PWRDN
OSCSRC b,d
ADC Clock
÷ 25
÷ 50
CAN Clock
a. Control provided by RCC register bit/field.
b. Control provided by RCC register bit/field or RCC2 register bit/field, if overridden with RCC2 register bit USERCC2.
c. Control provided by RCC2 register bit/field.
d. Also may be controlled by DSLPCLKCFG when in deep sleep mode.
Note:
The figure above shows all features available on all Stellaris® Fury-class devices.
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In the RCC register, the SYSDIV field specifies which divisor is used to generate the system clock
from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register
is configured). When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the
divisor is applied. Table 6-2 shows how the SYSDIV encoding affects the system clock frequency,
depending on whether the PLL is used (BYPASS=0) or another clock source is used (BYPASS=1).
The divisor is equivalent to the SYSDIV encoding plus 1. For a list of possible clock sources, see
Table 6-1 on page 68.
Table 6-2. Possible System Clock Frequencies Using the SYSDIV Field
SYSDIV
Divisor
a
Frequency
(BYPASS=0)
Frequency (BYPASS=1)
StellarisWare Parameter
b
0x0
/1
reserved
Clock source frequency/2
SYSCTL_SYSDIV_1
0x1
/2
reserved
Clock source frequency/2
SYSCTL_SYSDIV_2
0x2
/3
reserved
Clock source frequency/3
SYSCTL_SYSDIV_3
0x3
/4
50 MHz
Clock source frequency/4
SYSCTL_SYSDIV_4
0x4
/5
40 MHz
Clock source frequency/5
SYSCTL_SYSDIV_5
0x5
/6
33.33 MHz
Clock source frequency/6
SYSCTL_SYSDIV_6
0x6
/7
28.57 MHz
Clock source frequency/7
SYSCTL_SYSDIV_7
0x7
/8
25 MHz
Clock source frequency/8
SYSCTL_SYSDIV_8
0x8
/9
22.22 MHz
Clock source frequency/9
SYSCTL_SYSDIV_9
0x9
/10
20 MHz
Clock source frequency/10
SYSCTL_SYSDIV_10
0xA
/11
18.18 MHz
Clock source frequency/11
SYSCTL_SYSDIV_11
0xB
/12
16.67 MHz
Clock source frequency/12
SYSCTL_SYSDIV_12
0xC
/13
15.38 MHz
Clock source frequency/13
SYSCTL_SYSDIV_13
0xD
/14
14.29 MHz
Clock source frequency/14
SYSCTL_SYSDIV_14
0xE
/15
13.33 MHz
Clock source frequency/15
SYSCTL_SYSDIV_15
0xF
/16
12.5 MHz (default)
Clock source frequency/16
SYSCTL_SYSDIV_16
a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results
in the system clock having the same frequency as the clock source.
The SYSDIV2 field in the RCC2 register is 2 bits wider than the SYSDIV field in the RCC register
so that additional larger divisors up to /64 are possible, allowing a lower system clock frequency for
improved Deep Sleep power consumption. When using the PLL, the VCO frequency of 400 MHz is
predivided by 2 before the divisor is applied. The divisor is equivalent to the SYSDIV2 encoding
plus 1. Table 6-3 shows how the SYSDIV2 encoding affects the system clock frequency, depending
on whether the PLL is used (BYPASS2=0) or another clock source is used (BYPASS2=1). For a list
of possible clock sources, see Table 6-1 on page 68.
Table 6-3. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field
SYSDIV2
Divisor
a
Frequency
(BYPASS2=0)
Frequency (BYPASS2=1)
StellarisWare Parameter
b
0x00
/1
reserved
Clock source frequency/2
SYSCTL_SYSDIV_1
0x01
/2
reserved
Clock source frequency/2
SYSCTL_SYSDIV_2
0x02
/3
reserved
Clock source frequency/3
SYSCTL_SYSDIV_3
0x03
/4
50 MHz
Clock source frequency/4
SYSCTL_SYSDIV_4
0x04
/5
40 MHz
Clock source frequency/5
SYSCTL_SYSDIV_5
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Table 6-3. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field
(continued)
SYSDIV2
Divisor
a
Frequency
(BYPASS2=0)
Frequency (BYPASS2=1)
StellarisWare Parameter
0x05
/6
33.33 MHz
Clock source frequency/6
SYSCTL_SYSDIV_6
0x06
/7
28.57 MHz
Clock source frequency/7
SYSCTL_SYSDIV_7
0x07
/8
25 MHz
Clock source frequency/8
SYSCTL_SYSDIV_8
0x08
/9
22.22 MHz
Clock source frequency/9
SYSCTL_SYSDIV_9
0x09
/10
20 MHz
Clock source frequency/10
SYSCTL_SYSDIV_10
...
...
...
...
...
0x3F
/64
3.125 MHz
Clock source frequency/64
SYSCTL_SYSDIV_64
a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results
in the system clock having the same frequency as the clock source.
6.1.4.3
Crystal Configuration for the Main Oscillator (MOSC)
The main oscillator supports the use of a select number of crystals. If the main oscillator is used by
the PLL as a reference clock, the supported range of crystals is 3.579545 to 8.192 MHz, otherwise,
the range of supported crystals is 1 to 8.192 MHz.
The XTAL bit in the RCC register (see page 84) describes the available crystal choices and default
programming values.
Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the
design, the XTAL field value is internally translated to the PLL settings.
6.1.4.4
Main PLL Frequency Configuration
The main PLL is disabled by default during power-on reset and is enabled later by software if
required. Software specifies the output divisor to set the system clock frequency, and enables the
main PLL to drive the output. The PLL operates at 400 MHz, but is divided by two prior to the
application of the output divisor.
If the main oscillator provides the clock reference to the main PLL, the translation provided by
hardware and used to program the PLL is available for software in the XTAL to PLL Translation
(PLLCFG) register (see page 87). The internal translation provides a translation within ± 1% of the
targeted PLL VCO frequency. Table 19-8 on page 488 shows the actual PLL frequency and error for
a given crystal choice.
The Crystal Value field (XTAL) in the Run-Mode Clock Configuration (RCC) register (see page 84)
describes the available crystal choices and default programming of the PLLCFG register. Any time
the XTAL field changes, the new settings are translated and the internal PLL settings are updated.
6.1.4.5
PLL Modes
The PLL has two modes of operation: Normal and Power-Down
■ Normal: The PLL multiplies the input clock reference and drives the output.
■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output.
The modes are programmed using the RCC/RCC2 register fields (see page 84 and page 88).
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6.1.4.6
PLL Operation
If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks)
to the new setting. The time between the configuration change and relock is TREADY (see Table
19-7 on page 488). During the relock time, the affected PLL is not usable as a clock reference.
PLL is changed by one of the following:
■ Change to the XTAL value in the RCC register—writes of the same value do not cause a relock.
■ Change in the PLL from Power-Down to Normal mode.
A counter is defined to measure the TREADY requirement. The counter is clocked by the main
oscillator. The range of the main oscillator has been taken into account and the down counter is set
to 0x1200 (that is, ~600 μs at an 8.192 MHz external oscillator clock). Hardware is provided to keep
the PLL from being used as a system clock until the TREADY condition is met after one of the two
changes above. It is the user's responsibility to have a stable clock source (like the main oscillator)
before the RCC/RCC2 register is switched to use the PLL.
If the main PLL is enabled and the system clock is switched to use the PLL in one step, the system
control hardware continues to clock the controller from the oscillator selected by the RCC/RCC2
register until the main PLL is stable (TREADY time met), after which it changes to the PLL. Software
can use many methods to ensure that the system is clocked from the main PLL, including periodically
polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register, and enabling the PLL Lock
interrupt.
6.1.5
System Control
For power-savings purposes, the RCGCn , SCGCn , and DCGCn registers control the clock gating
logic for each peripheral or block in the system while the controller is in Run, Sleep, and Deep-Sleep
mode, respectively.
There are four levels of operation for the device defined as:
■ Run Mode. In Run mode, the controller actively executes code. Run mode provides normal
operation of the processor and all of the peripherals that are currently enabled by the RCGCn
registers. The system clock can be any of the available clock sources including the PLL.
■ Sleep Mode. In Sleep mode, the clock frequency of the active peripherals is unchanged, but the
processor and the memory subsystem are not clocked and therefore no longer execute code.
Sleep mode is entered by the Cortex-M3 core executing a WFI(Wait for Interrupt)
instruction. Any properly configured interrupt event in the system will bring the processor back
into Run mode. See the system control NVIC section of the ARM® Cortex™-M3 Technical
Reference Manual for more details.
Peripherals are clocked that are enabled in the SCGCn register when auto-clock gating is enabled
(see the RCC register) or the RCGCn register when the auto-clock gating is disabled. The system
clock has the same source and frequency as that during Run mode.
■ Deep-Sleep Mode. In Deep-Sleep mode, the clock frequency of the active peripherals may
change (depending on the Run mode clock configuration) in addition to the processor clock being
stopped. An interrupt returns the device to Run mode from one of the sleep modes; the sleep
modes are entered on request from the code. Deep-Sleep mode is entered by first writing the
Deep Sleep Enable bit in the ARM Cortex-M3 NVIC system control register and then executing
a WFI instruction. Any properly configured interrupt event in the system will bring the processor
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back into Run mode. See the system control NVIC section of the ARM® Cortex™-M3 Technical
Reference Manual for more details.
The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are
clocked that are enabled in the DCGCn register when auto-clock gating is enabled (see the RCC
register) or the RCGCn register when auto-clock gating is disabled. The system clock source is
the main oscillator by default or the internal oscillator specified in the DSLPCLKCFG register if
one is enabled. When the DSLPCLKCFG register is used, the internal oscillator is powered up,
if necessary, and the main oscillator is powered down. If the PLL is running at the time of the
WFI instruction, hardware will power the PLL down and override the SYSDIV field of the active
RCC/RCC2 register, to be determined by the DSDIVORIDE setting in the DSLPCLKCFG register,
up to /16 or /64 respectively. When the Deep-Sleep exit event occurs, hardware brings the system
clock back to the source and frequency it had at the onset of Deep-Sleep mode before enabling
the clocks that had been stopped during the Deep-Sleep duration.
Caution – If the Cortex-M3 Debug Access Port (DAP) has been enabled, and the device wakes from a
low power sleep or deep-sleep mode, the core may start executing code before all clocks to peripherals
have been restored to their run mode configuration. The DAP is usually enabled by software tools
accessing the JTAG or SWD interface when debugging or flash programming. If this condition occurs,
a Hard Fault is triggered when software accesses a peripheral with an invalid clock.
A software delay loop can be used at the beginning of the interrupt routine that is used to wake up a
system from a WFI (Wait For Interrupt) instruction. This stalls the execution of any code that accesses
a peripheral register that might cause a fault. This loop can be removed for production software as the
DAP is most likely not enabled during normal execution.
Because the DAP is disabled by default (power on reset), the user can also power-cycle the device. The
DAP is not enabled unless it is enabled through the JTAG or SWD interface.
6.2
Initialization and Configuration
The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register
is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps
required to successfully change the PLL-based system clock are:
1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS
bit in the RCC register. This configures the system to run off a “raw” clock source and allows
for the new PLL configuration to be validated before switching the system clock to the PLL.
2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in
RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the
appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output.
3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The
SYSDIV field determines the system frequency for the microcontroller.
4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register.
5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2.
6.3
Register Map
Table 6-4 on page 74 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register's address, relative to the System Control base address of
0x400F.E000.
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System Control
Note:
Spaces in the System Control register space that are not used are reserved for future or
internal use. Software should not modify any reserved memory address.
Table 6-4. System Control Register Map
See
page
Offset
Name
Type
Reset
Description
0x000
DID0
RO
-
Device Identification 0
76
0x004
DID1
RO
-
Device Identification 1
91
0x008
DC0
RO
0x00FF.002F
Device Capabilities 0
93
0x010
DC1
RO
0x0700.309F
Device Capabilities 1
94
0x014
DC2
RO
0x000F.1031
Device Capabilities 2
96
0x018
DC3
RO
0x8300.0000
Device Capabilities 3
98
0x01C
DC4
RO
0x5000.007F
Device Capabilities 4
99
0x030
PBORCTL
R/W
0x0000.7FFD
Brown-Out Reset Control
78
0x034
LDOPCTL
R/W
0x0000.0000
LDO Power Control
79
0x040
SRCR0
R/W
0x00000000
Software Reset Control 0
119
0x044
SRCR1
R/W
0x00000000
Software Reset Control 1
120
0x048
SRCR2
R/W
0x00000000
Software Reset Control 2
122
0x050
RIS
RO
0x0000.0000
Raw Interrupt Status
80
0x054
IMC
R/W
0x0000.0000
Interrupt Mask Control
81
0x058
MISC
R/W1C
0x0000.0000
Masked Interrupt Status and Clear
82
0x05C
RESC
R/W
-
Reset Cause
83
0x060
RCC
R/W
0x0780.3AD1
Run-Mode Clock Configuration
84
0x064
PLLCFG
RO
-
XTAL to PLL Translation
87
0x070
RCC2
R/W
0x0780.2810
Run-Mode Clock Configuration 2
88
0x100
RCGC0
R/W
0x00000040
Run Mode Clock Gating Control Register 0
101
0x104
RCGC1
R/W
0x00000000
Run Mode Clock Gating Control Register 1
107
0x108
RCGC2
R/W
0x00000000
Run Mode Clock Gating Control Register 2
113
0x110
SCGC0
R/W
0x00000040
Sleep Mode Clock Gating Control Register 0
103
0x114
SCGC1
R/W
0x00000000
Sleep Mode Clock Gating Control Register 1
109
0x118
SCGC2
R/W
0x00000000
Sleep Mode Clock Gating Control Register 2
115
0x120
DCGC0
R/W
0x00000040
Deep Sleep Mode Clock Gating Control Register 0
105
0x124
DCGC1
R/W
0x00000000
Deep Sleep Mode Clock Gating Control Register 1
111
0x128
DCGC2
R/W
0x00000000
Deep Sleep Mode Clock Gating Control Register 2
117
0x144
DSLPCLKCFG
R/W
0x0780.0000
Deep Sleep Clock Configuration
90
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6.4
Register Descriptions
All addresses given are relative to the System Control base address of 0x400F.E000.
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System Control
Register 1: Device Identification 0 (DID0), offset 0x000
This register identifies the version of the device.
Device Identification 0 (DID0)
Base 0x400F.E000
Offset 0x000
Type RO, reset 31
30
28
27
26
VER
reserved
Type
Reset
29
25
24
23
22
21
20
reserved
18
17
16
CLASS
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
MAJOR
Type
Reset
19
MINOR
Bit/Field
Name
Type
Reset
31
reserved
RO
0
30:28
VER
RO
0x1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
DID0 Version
This field defines the DID0 register format version. The version number
is numeric. The value of the VER field is encoded as follows:
Value Description
0x1
Second version of the DID0 register format.
27:24
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:16
CLASS
RO
0x1
Device Class
The CLASS field value identifies the internal design from which all mask
sets are generated for all devices in a particular product line. The CLASS
field value is changed for new product lines, for changes in fab process
(for example, a remap or shrink), or any case where the MAJOR or MINOR
fields require differentiation from prior devices. The value of the CLASS
field is encoded as follows (all other encodings are reserved):
Value Description
0x1
Stellaris® Fury-class devices.
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Bit/Field
Name
Type
Reset
15:8
MAJOR
RO
-
Description
Major Revision
This field specifies the major revision number of the device. The major
revision reflects changes to base layers of the design. The major revision
number is indicated in the part number as a letter (A for first revision, B
for second, and so on). This field is encoded as follows:
Value Description
0x0
Revision A (initial device)
0x1
Revision B (first base layer revision)
0x2
Revision C (second base layer revision)
and so on.
7:0
MINOR
RO
-
Minor Revision
This field specifies the minor revision number of the device. The minor
revision reflects changes to the metal layers of the design. The MINOR
field value is reset when the MAJOR field is changed. This field is numeric
and is encoded as follows:
Value Description
0x0
Initial device, or a major revision update.
0x1
First metal layer change.
0x2
Second metal layer change.
and so on.
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System Control
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030
This register is responsible for controlling reset conditions after initial power-on reset.
Brown-Out Reset Control (PBORCTL)
Base 0x400F.E000
Offset 0x030
Type R/W, reset 0x0000.7FFD
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
BORIOR
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0
1
BORIOR
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
BOR Interrupt or Reset
This bit controls how a BOR event is signaled to the controller. If set, a
reset is signaled. Otherwise, an interrupt is signaled.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 3: LDO Power Control (LDOPCTL), offset 0x034
The VADJ field in this register adjusts the on-chip output voltage (VOUT).
LDO Power Control (LDOPCTL)
Base 0x400F.E000
Offset 0x034
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
VADJ
Bit/Field
Name
Type
Reset
31:6
reserved
RO
0
5:0
VADJ
R/W
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
LDO Output Voltage
This field sets the on-chip output voltage. The programming values for
the VADJ field are provided below.
Value
VOUT (V)
0x00
2.50
0x01
2.45
0x02
2.40
0x03
2.35
0x04
2.30
0x05
2.25
0x06-0x3F Reserved
0x1B
2.75
0x1C
2.70
0x1D
2.65
0x1E
2.60
0x1F
2.55
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System Control
Register 4: Raw Interrupt Status (RIS), offset 0x050
Central location for system control raw interrupts. These are set and cleared by hardware.
Raw Interrupt Status (RIS)
Base 0x400F.E000
Offset 0x050
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
BORRIS
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PLLLRIS
RO
0
RO
0
reserved
Bit/Field
Name
Type
Reset
Description
31:7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
PLLLRIS
RO
0
PLL Lock Raw Interrupt Status
This bit is set when the PLL TREADY Timer asserts.
5:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
BORRIS
RO
0
Brown-Out Reset Raw Interrupt Status
This bit is the raw interrupt status for any brown-out conditions. If set,
a brown-out condition is currently active. This is an unregistered signal
from the brown-out detection circuit. An interrupt is reported if the BORIM
bit in the IMC register is set and the BORIOR bit in the PBORCTL register
is cleared.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Stellaris® LM3S8530 Microcontroller
Register 5: Interrupt Mask Control (IMC), offset 0x054
Central location for system control interrupt masks.
Interrupt Mask Control (IMC)
Base 0x400F.E000
Offset 0x054
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
BORIM
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PLLLIM
RO
0
R/W
0
reserved
Bit/Field
Name
Type
Reset
Description
31:7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
PLLLIM
R/W
0
PLL Lock Interrupt Mask
This bit specifies whether a PLL Lock interrupt is promoted to a controller
interrupt. If set, an interrupt is generated if PLLLRIS in RIS is set;
otherwise, an interrupt is not generated.
5:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
BORIM
R/W
0
Brown-Out Reset Interrupt Mask
This bit specifies whether a brown-out condition is promoted to a
controller interrupt. If set, an interrupt is generated if BORRIS is set;
otherwise, an interrupt is not generated.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058
On a read, this register gives the current masked status value of the corresponding interrupt. All of
the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS register
(see page 80).
Masked Interrupt Status and Clear (MISC)
Base 0x400F.E000
Offset 0x058
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
BORMIS
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W1C
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PLLLMIS
RO
0
R/W1C
0
reserved
Bit/Field
Name
Type
Reset
Description
31:7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
PLLLMIS
R/W1C
0
PLL Lock Masked Interrupt Status
This bit is set when the PLL TREADY timer asserts. The interrupt is cleared
by writing a 1 to this bit.
5:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
BORMIS
R/W1C
0
BOR Masked Interrupt Status
The BORMIS is simply the BORRIS ANDed with the mask value, BORIM.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 7: Reset Cause (RESC), offset 0x05C
This register is set with the reset cause after reset. The bits in this register are sticky and maintain
their state across multiple reset sequences, except when an power-on reset is the cause, in which
case, all bits other than POR in the RESC register are cleared.
Reset Cause (RESC)
Base 0x400F.E000
Offset 0x05C
Type R/W, reset 31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
SW
WDT
BOR
POR
EXT
RO
0
RO
0
RO
0
RO
0
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
Description
31:5
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
SW
R/W
-
Software Reset
When set, indicates a software reset is the cause of the reset event.
3
WDT
R/W
-
Watchdog Timer Reset
When set, indicates a watchdog reset is the cause of the reset event.
2
BOR
R/W
-
Brown-Out Reset
When set, indicates a brown-out reset is the cause of the reset event.
1
POR
R/W
-
Power-On Reset
When set, indicates a power-on reset is the cause of the reset event.
0
EXT
R/W
-
External Reset
When set, indicates an external reset (RST assertion) is the cause of
the reset event.
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System Control
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060
This register is defined to provide source control and frequency speed.
Run-Mode Clock Configuration (RCC)
Base 0x400F.E000
Offset 0x060
Type R/W, reset 0x0780.3AD1
31
30
29
28
26
25
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
1
15
14
13
12
11
10
PWRDN
reserved
BYPASS
reserved
R/W
1
RO
1
R/W
1
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
27
24
23
R/W
1
R/W
1
R/W
1
9
8
R/W
1
R/W
0
ACG
21
20
19
R/W
0
RO
0
RO
0
RO
0
7
6
5
4
3
R/W
1
R/W
1
R/W
0
R/W
1
RO
0
SYSDIV
22
Name
Type
Reset
31:28
reserved
RO
0x0
27
ACG
R/W
0
17
16
RO
0
RO
0
RO
0
2
1
0
reserved
USESYSDIV
XTAL
Bit/Field
18
OSCSRC
reserved
RO
0
IOSCDIS MOSCDIS
R/W
0
R/W
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Auto Clock Gating
This bit specifies whether the system uses the Sleep-Mode Clock
Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock
Gating Control (DCGCn) registers if the controller enters a Sleep or
Deep-Sleep mode (respectively). If set, the SCGCn or DCGCn registers
are used to control the clocks distributed to the peripherals when the
controller is in a sleep mode. Otherwise, the Run-Mode Clock Gating
Control (RCGCn) registers are used when the controller enters a sleep
mode.
The RCGCn registers are always used to control the clocks in Run
mode.
This allows peripherals to consume less power when the controller is
in a sleep mode and the peripheral is unused.
26:23
SYSDIV
R/W
0xF
System Clock Divisor
Specifies which divisor is used to generate the system clock from either
the PLL output or the oscillator source (depending on how the BYPASS
bit in this register is configured). See Table 6-2 on page 70 for bit
encodings.
If the SYSDIV value is less than MINSYSDIV (see page 94), and the
PLL is being used, then the MINSYSDIV value is used as the divisor.
If the PLL is not being used, the SYSDIV value can be less than
MINSYSDIV.
22
USESYSDIV
R/W
0
Enable System Clock Divider
Use the system clock divider as the source for the system clock. The
system clock divider is forced to be used when the PLL is selected as
the source.
If the USERCC2 bit in the RCC2 register is set, then the SYSDIV2 field
in the RCC2 register is used as the system clock divider rather than the
SYSDIV field in this register.
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Bit/Field
Name
Type
Reset
Description
21:14
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13
PWRDN
R/W
1
PLL Power Down
This bit connects to the PLL PWRDN input. The reset value of 1 powers
down the PLL.
12
reserved
RO
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11
BYPASS
R/W
1
PLL Bypass
Chooses whether the system clock is derived from the PLL output or
the OSC source. If set, the clock that drives the system is the OSC
source. Otherwise, the clock that drives the system is the PLL output
clock divided by the system divider.
See Table 6-2 on page 70 for programming guidelines.
10
reserved
RO
0
9:6
XTAL
R/W
0xB
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Crystal Value
This field specifies the crystal value attached to the main oscillator. The
encoding for this field is provided below. Depending on the crystal used,
the PLL frequency may not be exactly 400 MHz (see Table
19-8 on page 488 for more information).
Value Crystal Frequency (MHz) Not
Using the PLL
Crystal Frequency (MHz) Using
the PLL
0x0
1.000
reserved
0x1
1.8432
reserved
0x2
2.000
reserved
0x3
2.4576
reserved
0x4
3.579545 MHz
0x5
3.6864 MHz
0x6
4 MHz
0x7
4.096 MHz
0x8
4.9152 MHz
0x9
5 MHz
0xA
5.12 MHz
0xB
6 MHz (reset value)
0xC
6.144 MHz
0xD
7.3728 MHz
0xE
8 MHz
0xF
8.192 MHz
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System Control
Bit/Field
Name
Type
Reset
5:4
OSCSRC
R/W
0x1
Description
Oscillator Source
Selects the input source for the OSC. The values are:
Value Input Source
0x0
MOSC
Main oscillator
0x1
IOSC
Internal oscillator (default)
0x2
IOSC/4
Internal oscillator / 4
0x3
30 kHz
30-KHz internal oscillator
For additional oscillator sources, see the RCC2 register.
3:2
reserved
RO
0x0
1
IOSCDIS
R/W
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Internal Oscillator Disable
0: Internal oscillator (IOSC) is enabled.
1: Internal oscillator is disabled.
0
MOSCDIS
R/W
1
Main Oscillator Disable
0: Main oscillator is enabled .
1: Main oscillator is disabled (default).
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Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064
This register provides a means of translating external crystal frequencies into the appropriate PLL
settings. This register is initialized during the reset sequence and updated anytime that the XTAL
field changes in the Run-Mode Clock Configuration (RCC) register (see page 84).
The PLL frequency is calculated using the PLLCFG field values, as follows:
PLLFreq = OSCFreq * F / (R + 1)
XTAL to PLL Translation (PLLCFG)
Base 0x400F.E000
Offset 0x064
Type RO, reset 31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
-
RO
-
RO
-
RO
-
RO
-
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
F
Bit/Field
Name
Type
Reset
31:14
reserved
RO
0x0
13:5
F
RO
-
R
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PLL F Value
This field specifies the value supplied to the PLL’s F input.
4:0
R
RO
-
PLL R Value
This field specifies the value supplied to the PLL’s R input.
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System Control
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070
This register overrides the RCC equivalent register fields, as shown in Table 6-5, when the USERCC2
bit is set, allowing the extended capabilities of the RCC2 register to be used while also providing a
means to be backward-compatible to previous parts. Each RCC2 field that supersedes an RCC
field is located at the same LSB bit position; however, some RCC2 fields are larger than the
corresponding RCC field.
Table 6-5. RCC2 Fields that Override RCC fields
RCC2 Field...
Overrides RCC Field
SYSDIV2, bits[28:23]
SYSDIV, bits[26:23]
PWRDN2, bit[13]
PWRDN, bit[13]
BYPASS2, bit[11]
BYPASS, bit[11]
OSCSRC2, bits[6:4]
OSCSRC, bits[5:4]
Run-Mode Clock Configuration 2 (RCC2)
Base 0x400F.E000
Offset 0x070
Type R/W, reset 0x0780.2810
31
30
USERCC2
Type
Reset
R/W
0
RO
0
15
14
reserved
Type
Reset
RO
0
29
28
27
26
reserved
RO
0
25
24
23
22
21
20
SYSDIV2
RO
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
RO
0
10
9
8
7
6
13
12
11
PWRDN2
reserved
BYPASS2
R/W
1
RO
0
R/W
1
reserved
RO
0
19
18
17
16
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
RO
0
RO
0
OSCSRC2
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31
USERCC2
R/W
0
Use RCC2
R/W
0
R/W
0
reserved
R/W
1
RO
0
RO
0
When set, overrides the RCC register fields.
30:29
reserved
RO
0x0
28:23
SYSDIV2
R/W
0x0F
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
System Clock Divisor
Specifies which divisor is used to generate the system clock from either
the PLL output or the oscillator source (depending on how the BYPASS2
bit is configured). SYSDIV2 is used for the divisor when both the
USESYSDIV bit in the RCC register and the USERCC2 bit in this register
are set. See Table 6-3 on page 70 for programming guidelines.
22:14
reserved
RO
0x0
13
PWRDN2
R/W
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Power-Down PLL
When set, powers down the PLL.
12
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
Description
11
BYPASS2
R/W
1
Bypass PLL
When set, bypasses the PLL for the clock source.
See Table 6-3 on page 70 for programming guidelines.
10:7
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6:4
OSCSRC2
R/W
0x1
Oscillator Source
Selects the input source for the OSC. The values are:
Value Description
0x0
MOSC
Main oscillator
0x1
IOSC
Internal oscillator
0x2
IOSC/4
Internal oscillator / 4
0x3
30 kHz
30-kHz internal oscillator
3:0
reserved
RO
0
0x4
Reserved
0x5
Reserved
0x6
Reserved
0x7
Reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144
This register provides configuration information for the hardware control of Deep Sleep Mode.
Deep Sleep Clock Configuration (DSLPCLKCFG)
Base 0x400F.E000
Offset 0x144
Type R/W, reset 0x0780.0000
31
30
29
28
27
26
reserved
Type
Reset
25
24
23
22
21
20
DSDIVORIDE
18
17
16
reserved
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
19
DSOSCSRC
RO
0
Bit/Field
Name
Type
Reset
31:29
reserved
RO
0x0
28:23
DSDIVORIDE
R/W
0x0F
R/W
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Divider Field Override
6-bit system divider field to override when Deep-Sleep occurs with PLL
running.
22:7
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6:4
DSOSCSRC
R/W
0x0
Clock Source
Specifies the clock source during Deep-Sleep mode.
Value Description
0x0
MOSC
Use main oscillator as source.
0x1
IOSC
Use internal 12-MHz oscillator as source.
0x2
Reserved
0x3
30 kHz
Use 30-kHz internal oscillator as source.
3:0
reserved
RO
0x0
0x4
Reserved
0x5
Reserved
0x6
Reserved
0x7
Reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Stellaris® LM3S8530 Microcontroller
Register 12: Device Identification 1 (DID1), offset 0x004
This register identifies the device family, part number, temperature range, pin count, and package
type.
Device Identification 1 (DID1)
Base 0x400F.E000
Offset 0x004
Type RO, reset 31
30
29
28
27
26
RO
0
15
25
24
23
22
21
20
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
14
13
12
11
10
9
8
7
6
5
4
RO
0
RO
0
RO
0
RO
0
RO
0
RO
-
RO
-
RO
-
VER
Type
Reset
FAM
PINCOUNT
Type
Reset
RO
0
RO
1
18
17
16
RO
0
RO
1
RO
0
RO
0
3
2
1
0
PARTNO
reserved
RO
0
19
TEMP
Bit/Field
Name
Type
Reset
31:28
VER
RO
0x1
RO
-
PKG
ROHS
RO
-
RO
1
QUAL
RO
-
RO
-
Description
DID1 Version
This field defines the DID1 register format version. The version number
is numeric. The value of the VER field is encoded as follows (all other
encodings are reserved):
Value Description
0x1
27:24
FAM
RO
0x0
Second version of the DID1 register format.
Family
This field provides the family identification of the device within the
Luminary Micro product portfolio. The value is encoded as follows (all
other encodings are reserved):
Value Description
0x0
23:16
PARTNO
RO
0x64
Stellaris family of microcontollers, that is, all devices with
external part numbers starting with LM3S.
Part Number
This field provides the part number of the device within the family. The
value is encoded as follows (all other encodings are reserved):
Value Description
0x64 LM3S8530
15:13
PINCOUNT
RO
0x2
Package Pin Count
This field specifies the number of pins on the device package. The value
is encoded as follows (all other encodings are reserved):
Value Description
0x2
100-pin or 108-ball package
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Bit/Field
Name
Type
Reset
Description
12:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:5
TEMP
RO
-
Temperature Range
This field specifies the temperature rating of the device. The value is
encoded as follows (all other encodings are reserved):
Value Description
4:3
PKG
RO
-
0x0
Commercial temperature range (0°C to 70°C)
0x1
Industrial temperature range (-40°C to 85°C)
0x2
Extended temperature range (-40°C to 105°C)
Package Type
This field specifies the package type. The value is encoded as follows
(all other encodings are reserved):
Value Description
2
ROHS
RO
1
0x0
SOIC package
0x1
LQFP package
0x2
BGA package
RoHS-Compliance
This bit specifies whether the device is RoHS-compliant. A 1 indicates
the part is RoHS-compliant.
1:0
QUAL
RO
-
Qualification Status
This field specifies the qualification status of the device. The value is
encoded as follows (all other encodings are reserved):
Value Description
0x0
Engineering Sample (unqualified)
0x1
Pilot Production (unqualified)
0x2
Fully Qualified
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Register 13: Device Capabilities 0 (DC0), offset 0x008
This register is predefined by the part and can be used to verify features.
Device Capabilities 0 (DC0)
Base 0x400F.E000
Offset 0x008
Type RO, reset 0x00FF.002F
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
0
RO
1
RO
1
RO
1
RO
1
SRAMSZ
Type
Reset
FLASHSZ
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
Description
31:16
SRAMSZ
RO
0x00FF
SRAM Size
Indicates the size of the on-chip SRAM memory.
Value
Description
0x00FF 64 KB of SRAM
15:0
FLASHSZ
RO
0x002F
Flash Size
Indicates the size of the on-chip flash memory.
Value
Description
0x002F 96 KB of Flash
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System Control
Register 14: Device Capabilities 1 (DC1), offset 0x010
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: CANs, PWM,
ADC, Watchdog timer, Hibernation module, and debug capabilities. This register also indicates the
maximum clock frequency and maximum ADC sample rate. The format of this register is consistent
with the RCGC0, SCGC0, and DCGC0 clock control registers and the SRCR0 software reset control
register.
Device Capabilities 1 (DC1)
Base 0x400F.E000
Offset 0x010
Type RO, reset 0x0700.309F
31
30
RO
0
RO
0
15
14
RO
0
RO
0
29
28
27
26
25
24
RO
0
RO
0
RO
0
CAN2
CAN1
CAN0
RO
1
RO
1
13
12
11
10
RO
1
RO
0
RO
0
reserved
Type
Reset
MINSYSDIV
Type
Reset
RO
1
23
22
21
20
RO
1
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
RO
0
RO
0
reserved
19
18
17
16
RO
0
RO
0
RO
0
RO
0
4
3
2
1
0
PLL
WDT
SWO
SWD
JTAG
RO
1
RO
1
RO
1
RO
1
RO
1
reserved
MPU
RO
1
reserved
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:27
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
26
CAN2
RO
1
CAN Module 2 Present
When set, indicates that CAN unit 2 is present.
25
CAN1
RO
1
CAN Module 1 Present
When set, indicates that CAN unit 1 is present.
24
CAN0
RO
1
CAN Module 0 Present
When set, indicates that CAN unit 0 is present.
23:16
reserved
RO
0
15:12
MINSYSDIV
RO
0x3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
System Clock Divider
Minimum 4-bit divider value for system clock. The reset value is
hardware-dependent. See the RCC register for how to change the
system clock divisor using the SYSDIV bit.
Value Description
0x3
11:8
reserved
RO
0
Specifies a 50-MHz CPU clock with a PLL divider of 4.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
7
MPU
RO
1
Description
MPU Present
When set, indicates that the Cortex-M3 Memory Protection Unit (MPU)
module is present. See the ARM Cortex-M3 Technical Reference Manual
for details on the MPU.
6:5
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
PLL
RO
1
PLL Present
When set, indicates that the on-chip Phase Locked Loop (PLL) is
present.
3
WDT
RO
1
Watchdog Timer Present
When set, indicates that a watchdog timer is present.
2
SWO
RO
1
SWO Trace Port Present
When set, indicates that the Serial Wire Output (SWO) trace port is
present.
1
SWD
RO
1
SWD Present
When set, indicates that the Serial Wire Debugger (SWD) is present.
0
JTAG
RO
1
JTAG Present
When set, indicates that the JTAG debugger interface is present.
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System Control
Register 15: Device Capabilities 2 (DC2), offset 0x014
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Analog
Comparators, General-Purpose Timers, I2Cs, QEIs, SSIs, and UARTs. The format of this register
is consistent with the RCGC1, SCGC1, and DCGC1 clock control registers and the SRCR1 software
reset control register.
Device Capabilities 2 (DC2)
Base 0x400F.E000
Offset 0x014
Type RO, reset 0x000F.1031
31
30
29
28
27
26
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
RO
0
25
24
23
22
21
20
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
10
9
8
7
6
5
4
SSI1
SSI0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
I2C0
RO
0
RO
1
reserved
19
18
17
16
TIMER3
TIMER2
TIMER1
TIMER0
RO
1
RO
1
RO
1
RO
1
3
2
1
0
reserved
RO
0
RO
0
UART0
RO
0
RO
1
Bit/Field
Name
Type
Reset
Description
31:20
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
TIMER3
RO
1
Timer 3 Present
When set, indicates that General-Purpose Timer module 3 is present.
18
TIMER2
RO
1
Timer 2 Present
When set, indicates that General-Purpose Timer module 2 is present.
17
TIMER1
RO
1
Timer 1 Present
When set, indicates that General-Purpose Timer module 1 is present.
16
TIMER0
RO
1
Timer 0 Present
When set, indicates that General-Purpose Timer module 0 is present.
15:13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
I2C0
RO
1
I2C Module 0 Present
When set, indicates that I2C module 0 is present.
11:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
SSI1
RO
1
SSI1 Present
When set, indicates that SSI module 1 is present.
4
SSI0
RO
1
SSI0 Present
When set, indicates that SSI module 0 is present.
96
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Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Bit/Field
Name
Type
Reset
Description
3:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
UART0
RO
1
UART0 Present
When set, indicates that UART module 0 is present.
June 22, 2010
97
Texas Instruments-Production Data
System Control
Register 16: Device Capabilities 3 (DC3), offset 0x018
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Analog
Comparator I/Os, CCP I/Os, ADC I/Os, and PWM I/Os.
Device Capabilities 3 (DC3)
Base 0x400F.E000
Offset 0x018
Type RO, reset 0x8300.0000
31
30
29
27
26
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
RO
0
RO
0
RO
0
RO
0
RO
0
32KHZ
Type
Reset
28
25
24
CCP1
CCP0
RO
1
10
RO
0
reserved
23
22
21
20
RO
1
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
RO
0
RO
0
RO
0
RO
0
RO
0
19
18
17
16
RO
0
RO
0
RO
0
RO
0
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31
32KHZ
RO
1
Description
32KHz Input Clock Available
When set, indicates an even CCP pin is present and can be used as a
32-KHz input clock.
30:26
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
25
CCP1
RO
1
CCP1 Pin Present
When set, indicates that Capture/Compare/PWM pin 1 is present.
24
CCP0
RO
1
CCP0 Pin Present
When set, indicates that Capture/Compare/PWM pin 0 is present.
23:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
98
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Register 17: Device Capabilities 4 (DC4), offset 0x01C
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Ethernet MAC
and PHY, GPIOs, and CCP I/Os. The format of this register is consistent with the RCGC2, SCGC2,
and DCGC2 clock control registers and the SRCR2 software reset control register.
Device Capabilities 4 (DC4)
Base 0x400F.E000
Offset 0x01C
Type RO, reset 0x5000.007F
Type
Reset
31
30
29
28
27
26
25
24
23
22
reserved
EPHY0
reserved
EMAC0
RO
0
RO
1
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
RO
0
RO
0
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
reserved
reserved
Type
Reset
21
RO
0
Bit/Field
Name
Type
Reset
Description
31
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30
EPHY0
RO
1
Ethernet PHY0 Present
When set, indicates that Ethernet PHY module 0 is present.
29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
EMAC0
RO
1
Ethernet MAC0 Present
When set, indicates that Ethernet MAC module 0 is present.
27:7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
GPIOG
RO
1
GPIO Port G Present
When set, indicates that GPIO Port G is present.
5
GPIOF
RO
1
GPIO Port F Present
When set, indicates that GPIO Port F is present.
4
GPIOE
RO
1
GPIO Port E Present
When set, indicates that GPIO Port E is present.
3
GPIOD
RO
1
GPIO Port D Present
When set, indicates that GPIO Port D is present.
2
GPIOC
RO
1
GPIO Port C Present
When set, indicates that GPIO Port C is present.
June 22, 2010
99
Texas Instruments-Production Data
System Control
Bit/Field
Name
Type
Reset
1
GPIOB
RO
1
Description
GPIO Port B Present
When set, indicates that GPIO Port B is present.
0
GPIOA
RO
1
GPIO Port A Present
When set, indicates that GPIO Port A is present.
100
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 0 (RCGC0)
Base 0x400F.E000
Offset 0x100
Type R/W, reset 0x00000040
31
30
RO
0
RO
0
15
RO
0
29
28
27
RO
0
RO
0
RO
0
14
13
12
11
RO
0
RO
0
RO
0
reserved
Type
Reset
26
25
24
23
22
21
20
CAN2
CAN1
CAN0
R/W
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
10
9
8
7
6
5
4
RO
0
RO
0
RO
0
RO
0
reserved
RO
0
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
reserved
reserved
Type
Reset
19
RO
1
reserved
RO
0
RO
0
WDT
R/W
0
reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:27
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
26
CAN2
R/W
0
CAN2 Clock Gating Control
This bit controls the clock gating for CAN unit 2. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled.
25
CAN1
R/W
0
CAN1 Clock Gating Control
This bit controls the clock gating for CAN unit 1. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled.
24
CAN0
R/W
0
CAN0 Clock Gating Control
This bit controls the clock gating for CAN unit 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled.
23:7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
reserved
RO
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 22, 2010
101
Texas Instruments-Production Data
System Control
Bit/Field
Name
Type
Reset
3
WDT
R/W
0
Description
WDT Clock Gating Control
This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
2:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
102
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset
0x110
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 0 (SCGC0)
Base 0x400F.E000
Offset 0x110
Type R/W, reset 0x00000040
31
30
29
28
27
26
25
24
CAN2
CAN1
CAN0
RO
0
R/W
0
R/W
0
R/W
0
RO
0
11
10
9
8
7
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
15
14
13
12
23
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
20
RO
0
RO
0
RO
0
6
5
4
reserved
RO
0
21
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
reserved
reserved
Type
Reset
22
RO
0
RO
1
reserved
RO
0
RO
0
WDT
R/W
0
reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:27
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
26
CAN2
R/W
0
CAN2 Clock Gating Control
This bit controls the clock gating for CAN unit 2. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled.
25
CAN1
R/W
0
CAN1 Clock Gating Control
This bit controls the clock gating for CAN unit 1. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled.
24
CAN0
R/W
0
CAN0 Clock Gating Control
This bit controls the clock gating for CAN unit 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled.
23:7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
reserved
RO
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 22, 2010
103
Texas Instruments-Production Data
System Control
Bit/Field
Name
Type
Reset
3
WDT
R/W
0
Description
WDT Clock Gating Control
This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
2:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
104
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0),
offset 0x120
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0)
Base 0x400F.E000
Offset 0x120
Type R/W, reset 0x00000040
31
30
29
28
27
26
25
24
CAN2
CAN1
CAN0
RO
0
R/W
0
R/W
0
R/W
0
RO
0
11
10
9
8
7
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
15
14
13
12
23
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
20
RO
0
RO
0
RO
0
6
5
4
reserved
RO
0
21
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
reserved
reserved
Type
Reset
22
RO
0
RO
1
reserved
RO
0
RO
0
WDT
R/W
0
reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:27
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
26
CAN2
R/W
0
CAN2 Clock Gating Control
This bit controls the clock gating for CAN unit 2. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled.
25
CAN1
R/W
0
CAN1 Clock Gating Control
This bit controls the clock gating for CAN unit 1. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled.
24
CAN0
R/W
0
CAN0 Clock Gating Control
This bit controls the clock gating for CAN unit 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled.
23:7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
reserved
RO
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 22, 2010
105
Texas Instruments-Production Data
System Control
Bit/Field
Name
Type
Reset
3
WDT
R/W
0
Description
WDT Clock Gating Control
This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
2:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
106
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 1 (RCGC1)
Base 0x400F.E000
Offset 0x104
Type R/W, reset 0x00000000
31
30
29
28
27
26
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
RO
0
25
24
23
22
21
20
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
10
9
8
7
6
5
4
SSI1
SSI0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
I2C0
RO
0
R/W
0
reserved
19
18
17
16
TIMER3
TIMER2
TIMER1
TIMER0
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
reserved
RO
0
RO
0
UART0
RO
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:20
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
TIMER3
R/W
0
Timer 3 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 3.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
18
TIMER2
R/W
0
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
17
TIMER1
R/W
0
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
16
TIMER0
R/W
0
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
June 22, 2010
107
Texas Instruments-Production Data
System Control
Bit/Field
Name
Type
Reset
Description
15:13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
I2C0
R/W
0
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
11:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
SSI1
R/W
0
SSI1 Clock Gating Control
This bit controls the clock gating for SSI module 1. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4
SSI0
R/W
0
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
3:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
UART0
R/W
0
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
108
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset
0x114
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 1 (SCGC1)
Base 0x400F.E000
Offset 0x114
Type R/W, reset 0x00000000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TIMER3
TIMER2
TIMER1
TIMER0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
reserved
Type
Reset
RO
0
15
RO
0
RO
0
14
13
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
12
11
10
9
8
7
6
I2C0
RO
0
R/W
0
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
SSI1
SSI0
R/W
0
R/W
0
reserved
RO
0
RO
0
0
UART0
RO
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:20
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
TIMER3
R/W
0
Timer 3 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 3.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
18
TIMER2
R/W
0
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
17
TIMER1
R/W
0
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
June 22, 2010
109
Texas Instruments-Production Data
System Control
Bit/Field
Name
Type
Reset
16
TIMER0
R/W
0
Description
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
15:13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
I2C0
R/W
0
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
11:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
SSI1
R/W
0
SSI1 Clock Gating Control
This bit controls the clock gating for SSI module 1. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4
SSI0
R/W
0
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
3:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
UART0
R/W
0
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
110
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1),
offset 0x124
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 1 (DCGC1)
Base 0x400F.E000
Offset 0x124
Type R/W, reset 0x00000000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TIMER3
TIMER2
TIMER1
TIMER0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
reserved
Type
Reset
RO
0
15
RO
0
RO
0
14
13
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
12
11
10
9
8
7
6
I2C0
RO
0
R/W
0
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
SSI1
SSI0
R/W
0
R/W
0
reserved
RO
0
RO
0
0
UART0
RO
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:20
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
TIMER3
R/W
0
Timer 3 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 3.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
18
TIMER2
R/W
0
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
17
TIMER1
R/W
0
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
June 22, 2010
111
Texas Instruments-Production Data
System Control
Bit/Field
Name
Type
Reset
16
TIMER0
R/W
0
Description
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
15:13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
I2C0
R/W
0
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
11:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
SSI1
R/W
0
SSI1 Clock Gating Control
This bit controls the clock gating for SSI module 1. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4
SSI0
R/W
0
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
3:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
UART0
R/W
0
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
112
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 2 (RCGC2)
Base 0x400F.E000
Offset 0x108
Type R/W, reset 0x00000000
Type
Reset
31
30
29
28
27
26
25
24
23
22
reserved
EPHY0
reserved
EMAC0
RO
0
R/W
0
RO
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
RO
0
RO
0
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
reserved
Type
Reset
21
RO
0
Bit/Field
Name
Type
Reset
Description
31
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30
EPHY0
R/W
0
PHY0 Clock Gating Control
This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
EMAC0
R/W
0
MAC0 Clock Gating Control
This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
27:7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
GPIOG
R/W
0
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
June 22, 2010
113
Texas Instruments-Production Data
System Control
Bit/Field
Name
Type
Reset
5
GPIOF
R/W
0
Description
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4
GPIOE
R/W
0
Port E Clock Gating Control
This bit controls the clock gating for Port E. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
3
GPIOD
R/W
0
Port D Clock Gating Control
This bit controls the clock gating for Port D. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
2
GPIOC
R/W
0
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
1
GPIOB
R/W
0
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0
GPIOA
R/W
0
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
114
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset
0x118
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 2 (SCGC2)
Base 0x400F.E000
Offset 0x118
Type R/W, reset 0x00000000
Type
Reset
31
30
29
28
reserved
EPHY0
reserved
EMAC0
RO
0
R/W
0
RO
0
R/W
0
15
14
13
12
27
26
25
24
23
RO
0
RO
0
RO
0
RO
0
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
11
10
9
8
7
reserved
Type
Reset
22
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
6
5
4
3
2
1
0
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30
EPHY0
R/W
0
PHY0 Clock Gating Control
This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
EMAC0
R/W
0
MAC0 Clock Gating Control
This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
27:7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 22, 2010
115
Texas Instruments-Production Data
System Control
Bit/Field
Name
Type
Reset
6
GPIOG
R/W
0
Description
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
5
GPIOF
R/W
0
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4
GPIOE
R/W
0
Port E Clock Gating Control
This bit controls the clock gating for Port E. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
3
GPIOD
R/W
0
Port D Clock Gating Control
This bit controls the clock gating for Port D. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
2
GPIOC
R/W
0
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
1
GPIOB
R/W
0
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0
GPIOA
R/W
0
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
116
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2),
offset 0x128
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2)
Base 0x400F.E000
Offset 0x128
Type R/W, reset 0x00000000
Type
Reset
31
30
29
28
reserved
EPHY0
reserved
EMAC0
RO
0
R/W
0
RO
0
R/W
0
15
14
13
12
27
26
25
24
23
RO
0
RO
0
RO
0
RO
0
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
11
10
9
8
7
reserved
Type
Reset
22
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
6
5
4
3
2
1
0
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30
EPHY0
R/W
0
PHY0 Clock Gating Control
This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
EMAC0
R/W
0
MAC0 Clock Gating Control
This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
27:7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 22, 2010
117
Texas Instruments-Production Data
System Control
Bit/Field
Name
Type
Reset
6
GPIOG
R/W
0
Description
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
5
GPIOF
R/W
0
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
4
GPIOE
R/W
0
Port E Clock Gating Control
This bit controls the clock gating for Port E. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
3
GPIOD
R/W
0
Port D Clock Gating Control
This bit controls the clock gating for Port D. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
2
GPIOC
R/W
0
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
1
GPIOB
R/W
0
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0
GPIOA
R/W
0
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
118
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Register 27: Software Reset Control 0 (SRCR0), offset 0x040
Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register.
Software Reset Control 0 (SRCR0)
Base 0x400F.E000
Offset 0x040
Type R/W, reset 0x00000000
31
30
RO
0
RO
0
15
RO
0
29
28
27
26
25
24
RO
0
RO
0
RO
0
CAN2
CAN1
CAN0
R/W
0
R/W
0
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
23
22
21
20
R/W
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
reserved
reserved
Type
Reset
19
WDT
R/W
0
reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:27
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
26
CAN2
R/W
0
CAN2 Reset Control
Reset control for CAN unit 2.
25
CAN1
R/W
0
CAN1 Reset Control
Reset control for CAN unit 1.
24
CAN0
R/W
0
CAN0 Reset Control
Reset control for CAN unit 0.
23:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
WDT
R/W
0
WDT Reset Control
Reset control for Watchdog unit.
2:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Register 28: Software Reset Control 1 (SRCR1), offset 0x044
Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register.
Software Reset Control 1 (SRCR1)
Base 0x400F.E000
Offset 0x044
Type R/W, reset 0x00000000
31
30
29
28
27
26
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
RO
0
25
24
23
22
21
20
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
10
9
8
7
6
5
4
SSI1
SSI0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
I2C0
RO
0
R/W
0
reserved
19
18
17
16
TIMER3
TIMER2
TIMER1
TIMER0
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
reserved
RO
0
RO
0
UART0
RO
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:20
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
TIMER3
R/W
0
Timer 3 Reset Control
Reset control for General-Purpose Timer module 3.
18
TIMER2
R/W
0
Timer 2 Reset Control
Reset control for General-Purpose Timer module 2.
17
TIMER1
R/W
0
Timer 1 Reset Control
Reset control for General-Purpose Timer module 1.
16
TIMER0
R/W
0
Timer 0 Reset Control
Reset control for General-Purpose Timer module 0.
15:13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
I2C0
R/W
0
I2C0 Reset Control
Reset control for I2C unit 0.
11:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
SSI1
R/W
0
SSI1 Reset Control
Reset control for SSI unit 1.
4
SSI0
R/W
0
SSI0 Reset Control
Reset control for SSI unit 0.
3:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
0
UART0
R/W
0
Description
UART0 Reset Control
Reset control for UART unit 0.
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System Control
Register 29: Software Reset Control 2 (SRCR2), offset 0x048
Writes to this register are masked by the bits in the Device Capabilities 4 (DC4) register.
Software Reset Control 2 (SRCR2)
Base 0x400F.E000
Offset 0x048
Type R/W, reset 0x00000000
Type
Reset
31
30
29
28
27
26
25
24
23
22
reserved
EPHY0
reserved
EMAC0
RO
0
R/W
0
RO
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
RO
0
RO
0
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
reserved
Type
Reset
21
RO
0
Bit/Field
Name
Type
Reset
Description
31
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30
EPHY0
R/W
0
PHY0 Reset Control
Reset control for Ethernet PHY unit 0.
29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
EMAC0
R/W
0
MAC0 Reset Control
Reset control for Ethernet MAC unit 0.
27:7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
GPIOG
R/W
0
Port G Reset Control
Reset control for GPIO Port G.
5
GPIOF
R/W
0
Port F Reset Control
Reset control for GPIO Port F.
4
GPIOE
R/W
0
Port E Reset Control
Reset control for GPIO Port E.
3
GPIOD
R/W
0
Port D Reset Control
Reset control for GPIO Port D.
2
GPIOC
R/W
0
Port C Reset Control
Reset control for GPIO Port C.
1
GPIOB
R/W
0
Port B Reset Control
Reset control for GPIO Port B.
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Bit/Field
Name
Type
Reset
0
GPIOA
R/W
0
Description
Port A Reset Control
Reset control for GPIO Port A.
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7
Internal Memory
The LM3S8530 microcontroller comes with 64 KB of bit-banded SRAM and 96 KB of flash memory.
The flash controller provides a user-friendly interface, making flash programming a simple task.
Flash protection can be applied to the flash memory on a 2-KB block basis.
7.1
Block Diagram
Figure 7-1 on page 124 illustrates the Flash functions. The dashed boxes in the figure indicate
registers residing in the System Control module rather than the Flash Control module.
Figure 7-1. Flash Block Diagram
Flash Control
Icode
Bus
Cortex-M3
FMA
FMD
FMC
FCRIS
FCIM
FCMISC
System
Bus
Dcode
Bus
Flash Array
Flash Protection
Bridge
FMPREn
FMPPEn
Flash Timing
USECRL
User Registers
USER_DBG
USER_REG0
USER_REG1
SRAM Array
7.2
Functional Description
This section describes the functionality of the SRAM and Flash memories.
7.2.1
SRAM Memory
®
The internal SRAM of the Stellaris devices is located at address 0x2000.0000 of the device memory
map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM has
introduced bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor,
certain regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
The bit-band alias is calculated by using the formula:
bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4)
For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as:
0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C
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With the alias address calculated, an instruction performing a read/write to address 0x2202.000C
allows direct access to only bit 3 of the byte at address 0x2000.1000.
For details about bit-banding, please refer to Chapter 4, “Memory Map” in the ARM® Cortex™-M3
Technical Reference Manual.
7.2.2
Flash Memory
The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block
causes the entire contents of the block to be reset to all 1s. An individual 32-bit word can be
programmed to change bits that are currently 1 to a 0. These blocks are paired into a set of 2-KB
blocks that can be individually protected. The protection allows blocks to be marked as read-only
or execute-only, providing different levels of code protection. Read-only blocks cannot be erased
or programmed, protecting the contents of those blocks from being modified. Execute-only blocks
cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism,
protecting the contents of those blocks from being read by either the controller or by a debugger.
See also “Serial Flash Loader” on page 499 for a preprogrammed flash-resident utility used to
download code to the flash memory of a device without the use of a debug interface.
7.2.2.1
Flash Memory Timing
The timing for the flash is automatically handled by the flash controller. However, in order to do so,
it must know the clock rate of the system in order to time its internal signals properly. The number
of clock cycles per microsecond must be provided to the flash controller for it to accomplish this
timing. It is software's responsibility to keep the flash controller updated with this information via the
USec Reload (USECRL) register.
On reset, the USECRL register is loaded with a value that configures the flash timing so that it works
with the maximum clock rate of the part. If software changes the system operating frequency, the
new operating frequency minus 1 (in MHz) must be loaded into USECRL before any flash
modifications are attempted. For example, if the device is operating at a speed of 20 MHz, a value
of 0x13 (20-1) must be written to the USECRL register.
7.2.2.2
Flash Memory Protection
The user is provided two forms of flash protection per 2-KB flash blocks in two pairs of 32-bit wide
registers. The protection policy for each form is controlled by individual bits (per policy per block)
in the FMPPEn and FMPREn registers.
■ Flash Memory Protection Program Enable (FMPPEn): If set, the block may be programmed
(written) or erased. If cleared, the block may not be changed.
■ Flash Memory Protection Read Enable (FMPREn): If a bit is set, the corresponding block may
be executed or read by software or debuggers. If a bit is cleared, the corresponding block may
only be executed, and contents of the memory block are prohibited from being read as data.
The policies may be combined as shown in Table 7-1 on page 125.
Table 7-1. Flash Protection Policy Combinations
FMPPEn
FMPREn
Protection
0
0
Execute-only protection. The block may only be executed and may not be written or erased.
This mode is used to protect code.
1
0
The block may be written, erased or executed, but not read. This combination is unlikely to
be used.
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Table 7-1. Flash Protection Policy Combinations (continued)
FMPPEn
FMPREn
Protection
0
1
Read-only protection. The block may be read or executed but may not be written or erased.
This mode is used to lock the block from further modification while allowing any read or
execute access.
1
1
No protection. The block may be written, erased, executed or read.
A Flash memory access that attempts to read a read-protected block (FMPREn bit is set) is prohibited
and generates a bus fault. A Flash memory access that attempts to program or erase a
program-protected block (FMPPEn bit is set) is prohibited and can optionally generate an interrupt
(by setting the AMASK bit in the Flash Controller Interrupt Mask (FCIM) register) to alert software
developers of poorly behaving software during the development and debug phases.
The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented
banks. These settings create a policy of open access and programmability. The register bits may
be changed by clearing the specific register bit. The changes are not permanent until the register
is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a
0 and not committed, it may be restored by executing a power-on reset sequence. The changes
are committed using the Flash Memory Control (FMC) register. Details on programming these bits
are discussed in “Nonvolatile Register Programming” on page 127.
7.2.2.3
Interrupts
The Flash memory controller can generate interrupts when the following conditions are observed:
■ Programming Interrupt - signals when a program or erase action is complete.
■ Access Interrupt - signals when a program or erase action has been attempted on a 2-kB block
of memory that is protected by its corresponding FMPPEn bit.
The interrupt events that can trigger a controller-level interrupt are defined in the Flash Controller
Masked Interrupt Status (FCMIS) register (see page 134) by setting the corresponding MASK bits.
If interrupts are not used, the raw interrupt status is always visible via the Flash Controller Raw
Interrupt Status (FCRIS) register (see page 133).
Interrupts are always cleared (for both the FCMIS and FCRIS registers) by writing a 1 to the
corresponding bit in the Flash Controller Masked Interrupt Status and Clear (FCMISC) register
(see page 135).
7.3
Flash Memory Initialization and Configuration
7.3.1
Flash Programming
®
The Stellaris devices provide a user-friendly interface for flash programming. All erase/program
operations are handled via three registers: FMA, FMD, and FMC.
7.3.1.1
To program a 32-bit word
1. Write source data to the FMD register.
2. Write the target address to the FMA register.
3. Write the flash write key and the WRITE bit (a value of 0xA442.0001) to the FMC register.
4. Poll the FMC register until the WRITE bit is cleared.
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7.3.1.2
To perform an erase of a 1-KB page
1. Write the page address to the FMA register.
2. Write the flash write key and the ERASE bit (a value of 0xA442.0002) to the FMC register.
3. Poll the FMC register until the ERASE bit is cleared.
7.3.1.3
To perform a mass erase of the flash
1. Write the flash write key and the MERASE bit (a value of 0xA442.0004) to the FMC register.
2. Poll the FMC register until the MERASE bit is cleared.
7.3.2
Nonvolatile Register Programming
This section discusses how to update registers that are resident within the Flash memory itself.
These registers exist in a separate space from the main Flash memory array and are not affected
by an ERASE or MASS ERASE operation. The bits in these registers can be changed from 1 to 0
with a write operation. Prior to being committed, the register contents are unaffected by any reset
condition except power-on reset, which returns the register contents to the original value. By
committing the register values using the COMT bit in the FMC register, the register contents become
nonvolatile and are therefore retained following power cycling. Once the register contents are
committed, the contents are permanent, and they cannot be restored to their factory default values.
With the exception of the USER_DBG register, the settings in these registers can be tested before
committing them to Flash memory. For the USER_DBG register, the data to be written is loaded
into the FMD register before it is committed. The FMD register is read only and does not allow the
USER_DBG operation to be tried before committing it to nonvolatile memory.
Important: These registers can only have bits changed from 1 to 0 by user programming. Once
committed, these registers cannot be restored to their factory default values.
In addition, the USER_REG0, USER_REG1, USER_REG2, USER_REG3, and USER_DBG registers
each use bit 31 (NW) to indicate that they have not been committed and bits in the register may be
changed from 1 to 0. These five registers can only be committed once whereas the Flash memory
protection registers may be committed multiple times. Table 7-2 on page 127 provides the FMA
address required for commitment of each of the registers and the source of the data to be written
when the FMC register is written with a value of 0xA442.0008. After writing the COMT bit, the user
may poll the FMC register to wait for the commit operation to complete.
Table 7-2. User-Programmable Flash Memory Resident Registers
Register to be Committed
FMA Value
Data Source
0x0000.0000
FMPRE0
FMPRE1
0x0000.0002
FMPRE1
FMPPE0
0x0000.0001
FMPPE0
FMPRE0
FMPPE1
0x0000.0003
FMPPE1
USER_REG0
0x8000.0000
USER_REG0
USER_REG1
0x8000.0001
USER_REG1
USER_REG2
0x8000.0002
USER_REG2
USER_REG3
0x8000.0003
USER_REG3
USER_DBG
0x7510.0000
FMD
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7.4
Register Map
Table 7-3 on page 128 lists the Flash memory and control registers. The offset listed is a hexadecimal
increment to the register's address. The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC register
offsets are relative to the Flash memory control base address of 0x400F.D000. The Flash memory
protection register offsets are relative to the System Control base address of 0x400F.E000.
Table 7-3. Flash Register Map
Offset
Name
Type
Reset
See
page
Description
Flash Memory Control Registers (Flash Control Offset)
0x000
FMA
R/W
0x0000.0000
Flash Memory Address
129
0x004
FMD
R/W
0x0000.0000
Flash Memory Data
130
0x008
FMC
R/W
0x0000.0000
Flash Memory Control
131
0x00C
FCRIS
RO
0x0000.0000
Flash Controller Raw Interrupt Status
133
0x010
FCIM
R/W
0x0000.0000
Flash Controller Interrupt Mask
134
0x014
FCMISC
R/W1C
0x0000.0000
Flash Controller Masked Interrupt Status and Clear
135
Flash Memory Protection Registers (System Control Offset)
0x130
FMPRE0
R/W
0xFFFF.FFFF
Flash Memory Protection Read Enable 0
138
0x200
FMPRE0
R/W
0xFFFF.FFFF
Flash Memory Protection Read Enable 0
138
0x134
FMPPE0
R/W
0xFFFF.FFFF
Flash Memory Protection Program Enable 0
139
0x400
FMPPE0
R/W
0xFFFF.FFFF
Flash Memory Protection Program Enable 0
139
0x140
USECRL
R/W
0x31
USec Reload
137
0x1D0
USER_DBG
R/W
0xFFFF.FFFE
User Debug
140
0x1E0
USER_REG0
R/W
0xFFFF.FFFF
User Register 0
141
0x1E4
USER_REG1
R/W
0xFFFF.FFFF
User Register 1
142
0x204
FMPRE1
R/W
0x0000.FFFF
Flash Memory Protection Read Enable 1
143
0x208
FMPRE2
R/W
0x0000.0000
Flash Memory Protection Read Enable 2
144
0x20C
FMPRE3
R/W
0x0000.0000
Flash Memory Protection Read Enable 3
145
0x404
FMPPE1
R/W
0x0000.FFFF
Flash Memory Protection Program Enable 1
146
0x408
FMPPE2
R/W
0x0000.0000
Flash Memory Protection Program Enable 2
147
0x40C
FMPPE3
R/W
0x0000.0000
Flash Memory Protection Program Enable 3
148
7.5
Flash Register Descriptions (Flash Control Offset)
This section lists and describes the Flash Memory registers, in numerical order by address offset.
Registers in this section are relative to the Flash control base address of 0x400F.D000.
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Register 1: Flash Memory Address (FMA), offset 0x000
During a write operation, this register contains a 4-byte-aligned address and specifies where the
data is written. During erase operations, this register contains a 1 KB-aligned address and specifies
which page is erased. Note that the alignment requirements must be met by software or the results
of the operation are unpredictable.
Flash Memory Address (FMA)
Base 0x400F.D000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
24
23
22
21
20
19
18
17
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
16
OFFSET
OFFSET
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:17
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16:0
OFFSET
R/W
0x0
Address Offset
Address offset in flash where operation is performed, except for
nonvolatile registers (see “Nonvolatile Register
Programming” on page 127 for details on values for this field).
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Register 2: Flash Memory Data (FMD), offset 0x004
This register contains the data to be written during the programming cycle or read during the read
cycle. Note that the contents of this register are undefined for a read access of an execute-only
block. This register is not used during the erase cycles.
Flash Memory Data (FMD)
Base 0x400F.D000
Offset 0x004
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DATA
Type
Reset
DATA
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:0
DATA
R/W
0x0
Data Value
Data value for write operation.
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Register 3: Flash Memory Control (FMC), offset 0x008
When this register is written, the flash controller initiates the appropriate access cycle for the location
specified by the Flash Memory Address (FMA) register (see page 129). If the access is a write
access, the data contained in the Flash Memory Data (FMD) register (see page 130) is written.
This is the final register written and initiates the memory operation. There are four control bits in the
lower byte of this register that, when set, initiate the memory operation. The most used of these
register bits are the ERASE and WRITE bits.
It is a programming error to write multiple control bits and the results of such an operation are
unpredictable.
Flash Memory Control (FMC)
Base 0x400F.D000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
COMT
MERASE
ERASE
WRITE
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
WRKEY
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:16
WRKEY
WO
0x0
Description
Flash Write Key
This field contains a write key, which is used to minimize the incidence
of accidental flash writes. The value 0xA442 must be written into this
field for a write to occur. Writes to the FMC register without this WRKEY
value are ignored. A read of this field returns the value 0.
15:4
reserved
RO
0x0
3
COMT
R/W
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Commit Register Value
Commit (write) of register value to nonvolatile storage. A write of 0 has
no effect on the state of this bit.
If read, the state of the previous commit access is provided. If the
previous commit access is complete, a 0 is returned; otherwise, if the
commit access is not complete, a 1 is returned.
This can take up to 50 μs.
2
MERASE
R/W
0
Mass Erase Flash Memory
If this bit is set, the flash main memory of the device is all erased. A
write of 0 has no effect on the state of this bit.
If read, the state of the previous mass erase access is provided. If the
previous mass erase access is complete, a 0 is returned; otherwise, if
the previous mass erase access is not complete, a 1 is returned.
This can take up to 250 ms.
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Bit/Field
Name
Type
Reset
1
ERASE
R/W
0
Description
Erase a Page of Flash Memory
If this bit is set, the page of flash main memory as specified by the
contents of FMA is erased. A write of 0 has no effect on the state of this
bit.
If read, the state of the previous erase access is provided. If the previous
erase access is complete, a 0 is returned; otherwise, if the previous
erase access is not complete, a 1 is returned.
This can take up to 25 ms.
0
WRITE
R/W
0
Write a Word into Flash Memory
If this bit is set, the data stored in FMD is written into the location as
specified by the contents of FMA. A write of 0 has no effect on the state
of this bit.
If read, the state of the previous write update is provided. If the previous
write access is complete, a 0 is returned; otherwise, if the write access
is not complete, a 1 is returned.
This can take up to 50 µs.
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Stellaris® LM3S8530 Microcontroller
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C
This register indicates that the flash controller has an interrupt condition. An interrupt is only signaled
if the corresponding FCIM register bit is set.
Flash Controller Raw Interrupt Status (FCRIS)
Base 0x400F.D000
Offset 0x00C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
PRIS
ARIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0
1
PRIS
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Programming Raw Interrupt Status
This bit provides status on programming cycles which are write or erase
actions generated through the FMC register bits (see page 131).
Value Description
1
The programming cycle has completed.
0
The programming cycle has not completed.
This status is sent to the interrupt controller when the PMASK bit in the
FCIM register is set.
This bit is cleared by writing a 1 to the PMISC bit in the FCMISC register.
0
ARIS
RO
0
Access Raw Interrupt Status
Value Description
1
A program or erase action was attempted on a block of Flash
memory that contradicts the protection policy for that block as
set in the FMPPEn registers.
0
No access has tried to improperly program or erase the Flash
memory.
This status is sent to the interrupt controller when the AMASK bit in the
FCIM register is set.
This bit is cleared by writing a 1 to the AMISC bit in the FCMISC register.
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Internal Memory
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010
This register controls whether the flash controller generates interrupts to the controller.
Flash Controller Interrupt Mask (FCIM)
Base 0x400F.D000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
PMASK
AMASK
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0
1
PMASK
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Programming Interrupt Mask
This bit controls the reporting of the programming raw interrupt status
to the interrupt controller.
Value Description
0
AMASK
R/W
0
1
An interrupt is sent to the interrupt controller when the PRIS bit
is set.
0
The PRIS interrupt is suppressed and not sent to the interrupt
controller.
Access Interrupt Mask
This bit controls the reporting of the access raw interrupt status to the
interrupt controller.
Value Description
1
An interrupt is sent to the interrupt controller when the ARIS bit
is set.
0
The ARIS interrupt is suppressed and not sent to the interrupt
controller.
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Stellaris® LM3S8530 Microcontroller
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC),
offset 0x014
This register provides two functions. First, it reports the cause of an interrupt by indicating which
interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the
interrupt reporting.
Flash Controller Masked Interrupt Status and Clear (FCMISC)
Base 0x400F.D000
Offset 0x014
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0
1
PMISC
R/W1C
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
PMISC
AMISC
R/W1C
0
R/W1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Programming Masked Interrupt Status and Clear
Value Description
1
When read, a 1 indicates that an unmasked interrupt was
signaled because a programming cycle completed.
Writing a 1 to this bit clears PMISC and also the PRIS bit in the
FCRIS register (see page 133).
0
When read, a 0 indicates that a programming cycle complete
interrupt has not occurred.
A write of 0 has no effect on the state of this bit.
0
AMISC
R/W1C
0
Access Masked Interrupt Status and Clear
Value Description
1
When read, a 1 indicates that an unmasked interrupt was
signaled because a program or erase action was attempted on
a block of Flash memory that contradicts the protection policy
for that block as set in the FMPPEn registers.
Writing a 1 to this bit clears AMISC and also the ARIS bit in the
FCRIS register (see page 133).
0
When read, a 0 indicates that no improper accesses have
occurred.
A write of 0 has no effect on the state of this bit.
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7.6
Flash Register Descriptions (System Control Offset)
The remainder of this section lists and describes the Flash Memory registers, in numerical order by
address offset. Registers in this section are relative to the System Control base address of
0x400F.E000.
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Register 7: USec Reload (USECRL), offset 0x140
Note:
Offset is relative to System Control base address of 0x400F.E000
This register is provided as a means of creating a 1-μs tick divider reload value for the flash controller.
The internal flash has specific minimum and maximum requirements on the length of time the high
voltage write pulse can be applied. It is required that this register contain the operating frequency
(in MHz -1) whenever the flash is being erased or programmed. The user is required to change this
value if the clocking conditions are changed for a flash erase/program operation.
USec Reload (USECRL)
Base 0x400F.E000
Offset 0x140
Type R/W, reset 0x31
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
USEC
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
USEC
R/W
0x31
Microsecond Reload Value
MHz -1 of the controller clock when the flash is being erased or
programmed.
If the maximum system frequency is being used, USEC should be set to
0x31 (50 MHz) whenever the flash is being erased or programmed.
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Internal Memory
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130
and 0x200
Note:
This register is aliased for backwards compatability.
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. For additional information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 0 (FMPRE0)
Base 0x400F.E000
Offset 0x130 and 0x200
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
READ_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
READ_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
31:0
READ_ENABLE
R/W
R/W
1
Reset
R/W
1
R/W
1
Description
0xFFFFFFFF Flash Read Enable. Enables 2-KB Flash memory blocks to be executed
or read. The policies may be combined as shown in the table “Flash
Protection Policy Combinations”.
Value
Description
0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of
Flash memory up to the total of 64 KB.
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Stellaris® LM3S8530 Microcontroller
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset
0x134 and 0x400
Note:
This register is aliased for backwards compatability.
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. For additional information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 0 (FMPPE0)
Base 0x400F.E000
Offset 0x134 and 0x400
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PROG_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
PROG_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
31:0
PROG_ENABLE
R/W
R/W
1
Reset
R/W
1
R/W
1
Description
0xFFFFFFFF Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value
Description
0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of
Flash memory up to the total of 64 KB.
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Internal Memory
Register 10: User Debug (USER_DBG), offset 0x1D0
Note:
Offset is relative to System Control base address of 0x400FE000.
This register provides a write-once mechanism to disable external debugger access to the device
in addition to 27 additional bits of user-defined data. The DBG0 bit (bit 0) is set to 0 from the factory
and the DBG1 bit (bit 1) is set to 1, which enables external debuggers. Changing the DBG1 bit to
0 disables any external debugger access to the device permanently, starting with the next power-up
cycle of the device. The NW bit (bit 31) indicates that the register has not yet been committed and
is controlled through hardware to ensure that the register is only committed once. Prior to being
committed, bits can only be changed from 1 to 0. The reset value shown only applies to power-on
reset; any other type of reset does not affect this register. Once committed, this register cannot be
restored to the factory default value.
User Debug (USER_DBG)
Base 0x400F.E000
Offset 0x1D0
Type R/W, reset 0xFFFF.FFFE
31
30
29
28
27
26
25
24
NW
Type
Reset
23
22
21
20
19
18
17
16
R/W
1
R/W
1
DATA
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
8
7
6
5
4
3
2
DATA
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
31
NW
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
1
0
DBG1
DBG0
R/W
1
R/W
0
Description
User Debug Not Written
When set, this bit indicates that this 32-bit register has not been
committed. When clear, this bit specifies that this register has been
committed and may not be committed again.
30:2
DATA
R/W
0x1FFFFFFF User Data
Contains the user data value. This field is initialized to all 1s and can
only be committed once.
1
DBG1
R/W
1
Debug Control 1
The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available.
0
DBG0
R/W
0
Debug Control 0
The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available.
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Stellaris® LM3S8530 Microcontroller
Register 11: User Register 0 (USER_REG0), offset 0x1E0
Note:
Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be committed
once. Bit 31 indicates that the register is available to be committed and is controlled through hardware
to ensure that the register is only committed once. Prior to being committed, bits can only be changed
from 1 to 0. The reset value shown only applies to power-on reset; any other type of reset does not
affect this register. The write-once characteristics of this register are useful for keeping static
information like communication addresses that need to be unique per part and would otherwise
require an external EEPROM or other non-volatile device. Once committed, this register cannot be
restored to the factory default value.
User Register 0 (USER_REG0)
Base 0x400F.E000
Offset 0x1E0
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
NW
Type
Reset
23
22
21
20
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
DATA
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
DATA
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
Description
31
NW
R/W
1
Not Written
When set, this bit indicates that this 32-bit register has not been
committed. When clear, this bit specifies that this register has been
committed and may not be committed again.
30:0
DATA
R/W
0x7FFFFFFF User Data
Contains the user data value. This field is initialized to all 1s and can
only be committed once.
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Internal Memory
Register 12: User Register 1 (USER_REG1), offset 0x1E4
Note:
Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be committed
once. Bit 31 indicates that the register is available to be committed and is controlled through hardware
to ensure that the register is only committed once. Prior to being committed, bits can only be changed
from 1 to 0. The reset value shown only applies to power-on reset; any other type of reset does not
affect this register. The write-once characteristics of this register are useful for keeping static
information like communication addresses that need to be unique per part and would otherwise
require an external EEPROM or other non-volatile device. Once committed, this register cannot be
restored to the factory default value.
User Register 1 (USER_REG1)
Base 0x400F.E000
Offset 0x1E4
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
NW
Type
Reset
23
22
21
20
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
DATA
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
DATA
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
Description
31
NW
R/W
1
Not Written
When set, this bit indicates that this 32-bit register has not been
committed. When clear, this bit specifies that this register has been
committed and may not be committed again.
30:0
DATA
R/W
0x7FFFFFFF User Data
Contains the user data value. This field is initialized to all 1s and can
only be committed once.
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Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. If the Flash memory size on the device is less than 64 KB, this register usually
reads as zeroes, but software should not rely on these bits to be zero. For additional information,
see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 1 (FMPRE1)
Base 0x400F.E000
Offset 0x204
Type R/W, reset 0x0000.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
READ_ENABLE
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
READ_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
31:0
READ_ENABLE
R/W
R/W
1
Reset
R/W
1
R/W
1
Description
0x0000FFFF Flash Read Enable. Enables 2-KB Flash memory blocks to be executed
or read. The policies may be combined as shown in the table “Flash
Protection Policy Combinations”.
Value
Description
0x0000FFFF Bits [31:0] each enable protection on a 2-KB block of
Flash memory in memory range from 65 to 128 KB.
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Internal Memory
Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). For additional information, see the "Flash Memory
Protection" section.
Flash Memory Protection Read Enable 2 (FMPRE2)
Base 0x400F.E000
Offset 0x208
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
READ_ENABLE
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
READ_ENABLE
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
31:0
READ_ENABLE
R/W
R/W
0
Reset
R/W
0
R/W
0
Description
0x00000000 Flash Read Enable
Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value
Description
0x00000000 Enables 96 KB of flash.
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Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 3 (FMPRE3)
Base 0x400F.E000
Offset 0x20C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
READ_ENABLE
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
READ_ENABLE
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
31:0
READ_ENABLE
R/W
R/W
0
Reset
R/W
0
R/W
0
Description
0x00000000 Flash Read Enable
Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value
Description
0x00000000 Enables 96 KB of flash.
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Internal Memory
Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset
0x404
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. If the Flash memory size on the device is less than 64 KB, this register usually
reads as zeroes, but software should not rely on these bits to be zero. For additional information,
see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 1 (FMPPE1)
Base 0x400F.E000
Offset 0x404
Type R/W, reset 0x0000.FFFF
31
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
PROG_ENABLE
Type
Reset
PROG_ENABLE
Type
Reset
Bit/Field
Name
Type
31:0
PROG_ENABLE
R/W
Reset
R/W
1
R/W
1
Description
0x0000FFFF Flash Programming Enable
Value
Description
0x0000FFFF Bits [31:0] each enable protection on a 2-KB block of
Flash memory in memory range from 65 to 128 KB.
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Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset
0x408
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 2 (FMPPE2)
Base 0x400F.E000
Offset 0x408
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
PROG_ENABLE
Type
Reset
PROG_ENABLE
Type
Reset
Bit/Field
Name
Type
31:0
PROG_ENABLE
R/W
Reset
R/W
0
R/W
0
Description
0x00000000 Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value
Description
0x00000000 Enables 96 KB of flash.
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Internal Memory
Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset
0x40C
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 3 (FMPPE3)
Base 0x400F.E000
Offset 0x40C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
PROG_ENABLE
Type
Reset
PROG_ENABLE
Type
Reset
Bit/Field
Name
Type
31:0
PROG_ENABLE
R/W
Reset
R/W
0
R/W
0
Description
0x00000000 Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value
Description
0x00000000 Enables 96 KB of flash.
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8
General-Purpose Input/Outputs (GPIOs)
The GPIO module is composed of seven physical GPIO blocks, each corresponding to an individual
GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, Port G). The GPIO module supports 8-35
programmable input/output pins, depending on the peripherals being used.
The GPIO module has the following features:
■ 8-35 GPIOs, depending on configuration
■ 5-V-tolerant input/outputs
■ Programmable control for GPIO interrupts
– Interrupt generation masking
– Edge-triggered on rising, falling, or both
– Level-sensitive on High or Low values
■ Bit masking in both read and write operations through address lines
■ Pins configured as digital inputs are Schmitt-triggered.
■ Programmable control for GPIO pad configuration
– Weak pull-up or pull-down resistors
– 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be configured
with an 18-mA pad drive for high-current applications
– Slew rate control for the 8-mA drive
– Open drain enables
– Digital input enables
8.1
Functional Description
Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1,
GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both
groups of pins back to their default state.
Each GPIO port is a separate hardware instantiation of the same physical block (see Figure
8-1 on page 150). The LM3S8530 microcontroller contains seven ports and thus seven of these
physical GPIO blocks.
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Figure 8-1. GPIO Port Block Diagram
Commit
Control
Mode
Control
GPIOLOCK
GPIOCR
GPIOAFSEL
DEMUX
Alternate Input
Alternate Output
Pad Input
Alternate Output Enable
Pad Output
MUX
Pad Output Enable
Digital
I/O Pad
Package I/O Pin
GPIO Output
GPIODATA
GPIODIR
Interrupt
MUX
GPIO Input
Data
Control
GPIO Output Enable
Interrupt
Control
Pad
Control
GPIOIS
GPIOIBE
GPIOIEV
GPIOIM
GPIORIS
GPIOMIS
GPIOICR
GPIODR2R
GPIODR4R
GPIODR8R
GPIOSLR
GPIOPUR
GPIOPDR
GPIOODR
GPIODEN
Identification Registers
GPIOPeriphID0
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
8.1.1
GPIOPeriphID4
GPIOPeriphID5
GPIOPeriphID6
GPIOPeriphID7
GPIOPCellID0
GPIOPCellID1
GPIOPCellID2
GPIOPCellID3
Data Control
The data control registers allow software to configure the operational modes of the GPIOs. The data
direction register configures the GPIO as an input or an output while the data register either captures
incoming data or drives it out to the pads.
8.1.1.1
Data Direction Operation
The GPIO Direction (GPIODIR) register (see page 157) is used to configure each individual pin as
an input or output. When the data direction bit is set to 0, the GPIO is configured as an input and
the corresponding data register bit will capture and store the value on the GPIO port. When the data
direction bit is set to 1, the GPIO is configured as an output and the corresponding data register bit
will be driven out on the GPIO port.
8.1.1.2
Data Register Operation
To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the
GPIO Data (GPIODATA) register (see page 156) by using bits [9:2] of the address bus as a mask.
This allows software drivers to modify individual GPIO pins in a single instruction, without affecting
the state of the other pins. This is in contrast to the "typical" method of doing a read-modify-write
operation to set or clear an individual GPIO pin. To accommodate this feature, the GPIODATA
register covers 256 locations in the memory map.
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During a write, if the address bit associated with that data bit is set to 1, the value of the GPIODATA
register is altered. If it is cleared to 0, it is left unchanged.
For example, writing a value of 0xEB to the address GPIODATA + 0x098 would yield as shown in
Figure 8-2 on page 151, where u is data unchanged by the write.
Figure 8-2. GPIODATA Write Example
ADDR[9:2]
0x098
9
8
7
6
5
4
3
2
1
0
0
0
1
0
0
1
1
0
0
0
0xEB
1
1
1
0
1
0
1
1
GPIODATA
u
u
1
u
u
0
1
u
7
6
5
4
3
2
1
0
During a read, if the address bit associated with the data bit is set to 1, the value is read. If the
address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value.
For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 8-3 on page 151.
Figure 8-3. GPIODATA Read Example
8.1.2
ADDR[9:2]
0x0C4
9
8
7
6
5
4
3
2
1
0
0
0
1
1
0
0
0
1
0
0
GPIODATA
1
0
1
1
1
1
1
0
Returned Value
0
0
1
1
0
0
0
0
7
6
5
4
3
2
1
0
Interrupt Control
The interrupt capabilities of each GPIO port are controlled by a set of seven registers. With these
registers, it is possible to select the source of the interrupt, its polarity, and the edge properties.
When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt
controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt
to enable any further interrupts. For a level-sensitive interrupt, it is assumed that the external source
holds the level constant for the interrupt to be recognized by the controller.
Three registers are required to define the edge or sense that causes interrupts:
■ GPIO Interrupt Sense (GPIOIS) register (see page 158)
■ GPIO Interrupt Both Edges (GPIOIBE) register (see page 159)
■ GPIO Interrupt Event (GPIOIEV) register (see page 160)
Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 161).
When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations:
the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers
(see page 162 and page 163). As the name implies, the GPIOMIS register only shows interrupt
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conditions that are allowed to be passed to the controller. The GPIORIS register indicates that a
GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the controller.
Interrupts are cleared by writing a 1 to the appropriate bit of the GPIO Interrupt Clear (GPIOICR)
register (see page 164).
When programming the following interrupt control registers, the interrupts should be masked (GPIOIM
set to 0). Writing any value to an interrupt control register (GPIOIS, GPIOIBE, or GPIOIEV) can
generate a spurious interrupt if the corresponding bits are enabled.
8.1.3
Mode Control
The GPIO pins can be controlled by either hardware or software. When hardware control is enabled
via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 165), the pin state is
controlled by its alternate function (that is, the peripheral). Software control corresponds to GPIO
mode, where the GPIODATA register is used to read/write the corresponding pins.
8.1.4
Commit Control
The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is currently provided for the five JTAG/SWD pins (PB7 and
PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register
(see page 165) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see
page 175) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see
page 176) have been set to 1.
8.1.5
Pad Control
The pad control registers allow for GPIO pad configuration by software based on the application
requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR,
GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. These registers control drive strength,
open-drain configuration, pull-up and pull-down resistors, slew-rate control and digital input enable.
For special high-current applications, the GPIO output buffers may be used with the following
restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may
be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is
specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only
a maximum of two per side of the physical package or BGA pin group with the total number of
high-current GPIO outputs not exceeding four for the entire package.
8.1.6
Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as
well as the GPIOPCellID0-GPIOPCellID3 registers.
8.2
Initialization and Configuration
To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit
field (GPIOn) in the RCGC2 register.
On reset, all GPIO pins (except for the five JTAG pins) are configured out of reset to be undriven
(tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 8-1 on page 153
shows all possible configurations of the GPIO pads and the control register settings required to
achieve them. Table 8-2 on page 153 shows how a rising edge interrupt would be configured for pin
2 of a GPIO port.
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Table 8-1. GPIO Pad Configuration Examples
a
Configuration
GPIO Register Bit Value
AFSEL
Digital Input (GPIO)
DIR
0
ODR
0
DEN
0
PUR
1
PDR
?
?
DR2R
DR4R
DR8R
X
X
X
SLR
X
Digital Output (GPIO)
0
1
0
1
?
?
?
?
?
?
Open Drain Output
(GPIO)
0
1
1
1
X
X
?
?
?
?
Open Drain
Input/Output (I2C)
1
X
1
1
X
X
?
?
?
?
Digital Input (Timer
CCP)
1
X
0
1
?
?
X
X
X
X
Digital Output (Timer
PWM)
1
X
0
1
?
?
?
?
?
?
Digital Input/Output
(SSI)
1
X
0
1
?
?
?
?
?
?
Digital Input/Output
(UART)
1
X
0
1
?
?
?
?
?
?
a. X=Ignored (don’t care bit)
?=Can be either 0 or 1, depending on the configuration
Table 8-2. GPIO Interrupt Configuration Example
Register
Desired
Interrupt
Event
Trigger
GPIOIS
a
Pin 2 Bit Value
7
0=edge
6
5
4
3
2
1
0
X
X
X
X
X
0
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
1
X
X
0
0
0
0
0
1
0
0
1=level
GPIOIBE
0=single
edge
1=both
edges
GPIOIEV
0=Low level,
or negative
edge
1=High level,
or positive
edge
GPIOIM
0=masked
1=not
masked
a. X=Ignored (don’t care bit)
8.3
Register Map
Table 8-3 on page 154 lists the GPIO registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that GPIO port’s base address:
■ GPIO Port A: 0x4000.4000
■ GPIO Port B: 0x4000.5000
■ GPIO Port C: 0x4000.6000
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■
■
■
■
GPIO Port D: 0x4000.7000
GPIO Port E: 0x4002.4000
GPIO Port F: 0x4002.5000
GPIO Port G: 0x4002.6000
Important: The GPIO registers in this chapter are duplicated in each GPIO block; however,
depending on the block, all eight bits may not be connected to a GPIO pad. In those
cases, writing to those unconnected bits has no effect, and reading those unconnected
bits returns no meaningful data.
Note:
The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are
0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and
PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default
reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value
for Port C is 0x0000.000F.
The default register type for the GPIOCR register is RO for all GPIO pins with the exception
of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only
GPIOs that are protected by the GPIOCR register. Because of this, the register type for
GPIO Port B7 and GPIO Port C[3:0] is R/W.
The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the
exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port
is not accidentally programmed as a GPIO, these five pins default to non-committable.
Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while
the default reset value of GPIOCR for Port C is 0x0000.00F0.
Table 8-3. GPIO Register Map
Description
See
page
Offset
Name
Type
Reset
0x000
GPIODATA
R/W
0x0000.0000
GPIO Data
156
0x400
GPIODIR
R/W
0x0000.0000
GPIO Direction
157
0x404
GPIOIS
R/W
0x0000.0000
GPIO Interrupt Sense
158
0x408
GPIOIBE
R/W
0x0000.0000
GPIO Interrupt Both Edges
159
0x40C
GPIOIEV
R/W
0x0000.0000
GPIO Interrupt Event
160
0x410
GPIOIM
R/W
0x0000.0000
GPIO Interrupt Mask
161
0x414
GPIORIS
RO
0x0000.0000
GPIO Raw Interrupt Status
162
0x418
GPIOMIS
RO
0x0000.0000
GPIO Masked Interrupt Status
163
0x41C
GPIOICR
W1C
0x0000.0000
GPIO Interrupt Clear
164
0x420
GPIOAFSEL
R/W
-
GPIO Alternate Function Select
165
0x500
GPIODR2R
R/W
0x0000.00FF
GPIO 2-mA Drive Select
167
0x504
GPIODR4R
R/W
0x0000.0000
GPIO 4-mA Drive Select
168
0x508
GPIODR8R
R/W
0x0000.0000
GPIO 8-mA Drive Select
169
0x50C
GPIOODR
R/W
0x0000.0000
GPIO Open Drain Select
170
0x510
GPIOPUR
R/W
-
GPIO Pull-Up Select
171
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Table 8-3. GPIO Register Map (continued)
Name
Type
Reset
0x514
GPIOPDR
R/W
0x0000.0000
GPIO Pull-Down Select
172
0x518
GPIOSLR
R/W
0x0000.0000
GPIO Slew Rate Control Select
173
0x51C
GPIODEN
R/W
-
GPIO Digital Enable
174
0x520
GPIOLOCK
R/W
0x0000.0001
GPIO Lock
175
0x524
GPIOCR
-
-
GPIO Commit
176
0xFD0
GPIOPeriphID4
RO
0x0000.0000
GPIO Peripheral Identification 4
178
0xFD4
GPIOPeriphID5
RO
0x0000.0000
GPIO Peripheral Identification 5
179
0xFD8
GPIOPeriphID6
RO
0x0000.0000
GPIO Peripheral Identification 6
180
0xFDC
GPIOPeriphID7
RO
0x0000.0000
GPIO Peripheral Identification 7
181
0xFE0
GPIOPeriphID0
RO
0x0000.0061
GPIO Peripheral Identification 0
182
0xFE4
GPIOPeriphID1
RO
0x0000.0000
GPIO Peripheral Identification 1
183
0xFE8
GPIOPeriphID2
RO
0x0000.0018
GPIO Peripheral Identification 2
184
0xFEC
GPIOPeriphID3
RO
0x0000.0001
GPIO Peripheral Identification 3
185
0xFF0
GPIOPCellID0
RO
0x0000.000D
GPIO PrimeCell Identification 0
186
0xFF4
GPIOPCellID1
RO
0x0000.00F0
GPIO PrimeCell Identification 1
187
0xFF8
GPIOPCellID2
RO
0x0000.0005
GPIO PrimeCell Identification 2
188
0xFFC
GPIOPCellID3
RO
0x0000.00B1
GPIO PrimeCell Identification 3
189
8.4
Description
See
page
Offset
Register Descriptions
The remainder of this section lists and describes the GPIO registers, in numerical order by address
offset.
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Register 1: GPIO Data (GPIODATA), offset 0x000
The GPIODATA register is the data register. In software control mode, values written in the
GPIODATA register are transferred onto the GPIO port pins if the respective pins have been
configured as outputs through the GPIO Direction (GPIODIR) register (see page 157).
In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus
bits [9:2], must be High. Otherwise, the bit values remain unchanged by the write.
Similarly, the values read from this register are determined for each bit by the mask bit derived from
the address used to access the data register, bits [9:2]. Bits that are 1 in the address mask cause
the corresponding bits in GPIODATA to be read, and bits that are 0 in the address mask cause the
corresponding bits in GPIODATA to be read as 0, regardless of their value.
A read from GPIODATA returns the last bit value written if the respective pins are configured as
outputs, or it returns the value on the corresponding input pin when these are configured as inputs.
All bits are cleared by a reset.
GPIO Data (GPIODATA)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
DATA
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
DATA
R/W
0x00
GPIO Data
This register is virtually mapped to 256 locations in the address space.
To facilitate the reading and writing of data to these registers by
independent drivers, the data read from and the data written to the
registers are masked by the eight address lines ipaddr[9:2]. Reads
from this register return its current state. Writes to this register only affect
bits that are not masked by ipaddr[9:2] and are configured as
outputs. See “Data Register Operation” on page 150 for examples of
reads and writes.
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Register 2: GPIO Direction (GPIODIR), offset 0x400
The GPIODIR register is the data direction register. Bits set to 1 in the GPIODIR register configure
the corresponding pin to be an output, while bits set to 0 configure the pins to be inputs. All bits are
cleared by a reset, meaning all GPIO pins are inputs by default.
GPIO Direction (GPIODIR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x400
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
DIR
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
DIR
R/W
0x00
GPIO Data Direction
The DIR values are defined as follows:
Value Description
0
Pins are inputs.
1
Pins are outputs.
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Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404
The GPIOIS register is the interrupt sense register. Bits set to 1 in GPIOIS configure the
corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. All bits
are cleared by a reset.
GPIO Interrupt Sense (GPIOIS)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x404
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
IS
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
IS
R/W
0x00
GPIO Interrupt Sense
The IS values are defined as follows:
Value Description
0
Edge on corresponding pin is detected (edge-sensitive).
1
Level on corresponding pin is detected (level-sensitive).
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Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408
The GPIOIBE register is the interrupt both-edges register. When the corresponding bit in the GPIO
Interrupt Sense (GPIOIS) register (see page 158) is set to detect edges, bits set to High in GPIOIBE
configure the corresponding pin to detect both rising and falling edges, regardless of the
corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 160). Clearing a bit
configures the pin to be controlled by GPIOIEV. All bits are cleared by a reset.
GPIO Interrupt Both Edges (GPIOIBE)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x408
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
IBE
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
IBE
R/W
0x00
GPIO Interrupt Both Edges
The IBE values are defined as follows:
Value Description
0
Interrupt generation is controlled by the GPIO Interrupt Event
(GPIOIEV) register (see page 160).
1
Both edges on the corresponding pin trigger an interrupt.
Note:
Single edge is determined by the corresponding bit
in GPIOIEV.
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Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C
The GPIOIEV register is the interrupt event register. Bits set to High in GPIOIEV configure the
corresponding pin to detect rising edges or high levels, depending on the corresponding bit value
in the GPIO Interrupt Sense (GPIOIS) register (see page 158). Clearing a bit configures the pin to
detect falling edges or low levels, depending on the corresponding bit value in GPIOIS. All bits are
cleared by a reset.
GPIO Interrupt Event (GPIOIEV)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x40C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
IEV
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
IEV
R/W
0x00
GPIO Interrupt Event
The IEV values are defined as follows:
Value Description
0
Falling edge or Low levels on corresponding pins trigger
interrupts.
1
Rising edge or High levels on corresponding pins trigger
interrupts.
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Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410
The GPIOIM register is the interrupt mask register. Bits set to High in GPIOIM allow the corresponding
pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing a bit disables
interrupt triggering on that pin. All bits are cleared by a reset.
GPIO Interrupt Mask (GPIOIM)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x410
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
IME
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
IME
R/W
0x00
GPIO Interrupt Mask Enable
The IME values are defined as follows:
Value Description
0
Corresponding pin interrupt is masked.
1
Corresponding pin interrupt is not masked.
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Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414
The GPIORIS register is the raw interrupt status register. Bits read High in GPIORIS reflect the
status of interrupt trigger conditions detected (raw, prior to masking), indicating that all the
requirements have been met, before they are finally allowed to trigger by the GPIO Interrupt Mask
(GPIOIM) register (see page 161). Bits read as zero indicate that corresponding input pins have not
initiated an interrupt. All bits are cleared by a reset.
GPIO Raw Interrupt Status (GPIORIS)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x414
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
RIS
RO
0x00
GPIO Interrupt Raw Status
Reflects the status of interrupt trigger condition detection on pins (raw,
prior to masking).
The RIS values are defined as follows:
Value Description
0
Corresponding pin interrupt requirements not met.
1
Corresponding pin interrupt has met requirements.
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Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418
The GPIOMIS register is the masked interrupt status register. Bits read High in GPIOMIS reflect
the status of input lines triggering an interrupt. Bits read as Low indicate that either no interrupt has
been generated, or the interrupt is masked.
GPIOMIS is the state of the interrupt after masking.
GPIO Masked Interrupt Status (GPIOMIS)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x418
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
MIS
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
MIS
RO
0x00
GPIO Masked Interrupt Status
Masked value of interrupt due to corresponding pin.
The MIS values are defined as follows:
Value Description
0
Corresponding GPIO line interrupt not active.
1
Corresponding GPIO line asserting interrupt.
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Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C
The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the
corresponding interrupt edge detection logic register. Writing a 0 has no effect.
GPIO Interrupt Clear (GPIOICR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x41C
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
W1C
0
W1C
0
W1C
0
W1C
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
IC
RO
0
RO
0
RO
0
RO
0
W1C
0
W1C
0
W1C
0
W1C
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
IC
W1C
0x00
GPIO Interrupt Clear
The IC values are defined as follows:
Value Description
0
Corresponding interrupt is unaffected.
1
Corresponding interrupt is cleared.
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Stellaris® LM3S8530 Microcontroller
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420
The GPIOAFSEL register is the mode control select register. Writing a 1 to any bit in this register
selects the hardware control for the corresponding GPIO line. All bits are cleared by a reset, therefore
no GPIO line is set to hardware control by default.
The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is currently provided for the five JTAG/SWD pins (PB7 and
PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register
(see page 165) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see
page 175) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see
page 176) have been set to 1.
Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1,
GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both
groups of pins back to their default state.
Caution – It is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG
pins to their GPIO functionality, the debugger may not have enough time to connect and halt the
controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This
can be avoided with a software routine that restores JTAG functionality based on an external or software
trigger.
GPIO Alternate Function Select (GPIOAFSEL)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x420
Type R/W, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
-
R/W
-
R/W
-
R/W
-
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
AFSEL
RO
0
RO
0
RO
0
RO
0
R/W
-
R/W
-
R/W
-
R/W
-
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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General-Purpose Input/Outputs (GPIOs)
Bit/Field
Name
Type
Reset
7:0
AFSEL
R/W
-
Description
GPIO Alternate Function Select
The AFSEL values are defined as follows:
Value Description
0
Software control of corresponding GPIO line (GPIO mode).
1
Hardware control of corresponding GPIO line (alternate
hardware function).
Note:
The default reset value for the GPIOAFSEL,
GPIOPUR, and GPIODEN registers are 0x0000.0000
for all GPIO pins, with the exception of the five
JTAG/SWD pins (PB7 and PC[3:0]). These five pins
default to JTAG/SWD functionality. Because of this,
the default reset value of these registers for GPIO
Port B is 0x0000.0080 while the default reset value
for Port C is 0x0000.000F.
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Stellaris® LM3S8530 Microcontroller
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500
The GPIODR2R register is the 2-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing a DRV2 bit for a GPIO
signal, the corresponding DRV4 bit in the GPIODR4R register and the DRV8 bit in the GPIODR8R
register are automatically cleared by hardware.
GPIO 2-mA Drive Select (GPIODR2R)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x500
Type R/W, reset 0x0000.00FF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
DRV2
RO
0
RO
0
RO
0
RO
0
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
DRV2
R/W
0xFF
Output Pad 2-mA Drive Enable
A write of 1 to either GPIODR4[n] or GPIODR8[n] clears the
corresponding 2-mA enable bit. The change is effective on the second
clock cycle after the write.
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General-Purpose Input/Outputs (GPIOs)
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504
The GPIODR4R register is the 4-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing the DRV4 bit for a GPIO
signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV8 bit in the GPIODR8R
register are automatically cleared by hardware.
GPIO 4-mA Drive Select (GPIODR4R)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x504
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
DRV4
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
DRV4
R/W
0x00
Output Pad 4-mA Drive Enable
A write of 1 to either GPIODR2[n] or GPIODR8[n] clears the
corresponding 4-mA enable bit. The change is effective on the second
clock cycle after the write.
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Stellaris® LM3S8530 Microcontroller
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508
The GPIODR8R register is the 8-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing the DRV8 bit for a GPIO
signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV4 bit in the GPIODR4R
register are automatically cleared by hardware.
GPIO 8-mA Drive Select (GPIODR8R)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x508
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
DRV8
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
DRV8
R/W
0x00
Output Pad 8-mA Drive Enable
A write of 1 to either GPIODR2[n] or GPIODR4[n] clears the
corresponding 8-mA enable bit. The change is effective on the second
clock cycle after the write.
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General-Purpose Input/Outputs (GPIOs)
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C
The GPIOODR register is the open drain control register. Setting a bit in this register enables the
open drain configuration of the corresponding GPIO pad. When open drain mode is enabled, the
corresponding bit should also be set in the GPIO Digital Input Enable (GPIODEN) register (see
page 174). Corresponding bits in the drive strength registers (GPIODR2R, GPIODR4R, GPIODR8R,
and GPIOSLR ) can be set to achieve the desired rise and fall times. The GPIO acts as an open-drain
input if the corresponding bit in the GPIODIR register is cleared. If open drain is selected while the
GPIO is configured as an input, the GPIO will remain an input and the open-drain selection has no
effect until the GPIO is changed to an output.
When using the I2C module, in addition to configuring the pin to open drain, the GPIO Alternate
Function Select (GPIOAFSEL) register bits for the I2C clock and data pins should be set to 1 (see
examples in “Initialization and Configuration” on page 152).
GPIO Open Drain Select (GPIOODR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x50C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
ODE
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
ODE
R/W
0x00
Output Pad Open Drain Enable
The ODE values are defined as follows:
Value Description
0
Open drain configuration is disabled.
1
Open drain configuration is enabled.
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Stellaris® LM3S8530 Microcontroller
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510
The GPIOPUR register is the pull-up control register. When a bit is set to 1, it enables a weak pull-up
resistor on the corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the
corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 172).
GPIO Pull-Up Select (GPIOPUR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x510
Type R/W, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
-
R/W
-
R/W
-
R/W
-
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PUE
RO
0
RO
0
RO
0
RO
0
R/W
-
R/W
-
R/W
-
R/W
-
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PUE
R/W
-
Pad Weak Pull-Up Enable
A write of 1 to GPIOPDR[n] clears the corresponding GPIOPUR[n]
enables. The change is effective on the second clock cycle after the
write.
Note:
The default reset value for the GPIOAFSEL, GPIOPUR, and
GPIODEN registers are 0x0000.0000 for all GPIO pins, with
the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
These five pins default to JTAG/SWD functionality. Because
of this, the default reset value of these registers for GPIO Port
B is 0x0000.0080 while the default reset value for Port C is
0x0000.000F.
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General-Purpose Input/Outputs (GPIOs)
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514
The GPIOPDR register is the pull-down control register. When a bit is set to 1, it enables a weak
pull-down resistor on the corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears
the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 171).
GPIO Pull-Down Select (GPIOPDR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x514
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PDE
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PDE
R/W
0x00
Pad Weak Pull-Down Enable
A write of 1 to GPIOPUR[n] clears the corresponding GPIOPDR[n]
enables. The change is effective on the second clock cycle after the
write.
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Stellaris® LM3S8530 Microcontroller
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518
The GPIOSLR register is the slew rate control register. Slew rate control is only available when
using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register (see
page 169).
GPIO Slew Rate Control Select (GPIOSLR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x518
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
SRL
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
SRL
R/W
0x00
Slew Rate Limit Enable (8-mA drive only)
The SRL values are defined as follows:
Value Description
0
Slew rate control disabled.
1
Slew rate control enabled.
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General-Purpose Input/Outputs (GPIOs)
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C
Note:
Pins configured as digital inputs are Schmitt-triggered.
The GPIODEN register is the digital enable register. By default, with the exception of the GPIO
signals used for JTAG/SWD function, all other GPIO signals are configured out of reset to be undriven
(tristate). Their digital function is disabled; they do not drive a logic value on the pin and they do not
allow the pin voltage into the GPIO receiver. To use the pin in a digital function (either GPIO or
alternate function), the corresponding GPIODEN bit must be set.
GPIO Digital Enable (GPIODEN)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x51C
Type R/W, reset 31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
reserved
Type
Reset
reserved
Type
Reset
DEN
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
DEN
R/W
-
Digital Enable
The DEN values are defined as follows:
Value Description
0
Digital functions disabled.
1
Digital functions enabled.
Note:
The default reset value for the GPIOAFSEL,
GPIOPUR, and GPIODEN registers are 0x0000.0000
for all GPIO pins, with the exception of the five
JTAG/SWD pins (PB7 and PC[3:0]). These five pins
default to JTAG/SWD functionality. Because of this,
the default reset value of these registers for GPIO
Port B is 0x0000.0080 while the default reset value
for Port C is 0x0000.000F.
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Stellaris® LM3S8530 Microcontroller
Register 19: GPIO Lock (GPIOLOCK), offset 0x520
The GPIOLOCK register enables write access to the GPIOCR register (see page 176). Writing
0x1ACC.E551 to the GPIOLOCK register will unlock the GPIOCR register. Writing any other value
to the GPIOLOCK register re-enables the locked state. Reading the GPIOLOCK register returns
the lock status rather than the 32-bit value that was previously written. Therefore, when write accesses
are disabled, or locked, reading the GPIOLOCK register returns 0x00000001. When write accesses
are enabled, or unlocked, reading the GPIOLOCK register returns 0x00000000.
GPIO Lock (GPIOLOCK)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x520
Type R/W, reset 0x0000.0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
LOCK
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
LOCK
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
31:0
LOCK
R/W
R/W
0
Reset
R/W
0
Description
0x0000.0001 GPIO Lock
A write of the value 0x1ACC.E551 unlocks the GPIO Commit (GPIOCR)
register for write access.
A write of any other value or a write to the GPIOCR register reapplies
the lock, preventing any register updates. A read of this register returns
the following values:
Value
Description
0x0000.0001 locked
0x0000.0000 unlocked
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General-Purpose Input/Outputs (GPIOs)
Register 20: GPIO Commit (GPIOCR), offset 0x524
The GPIOCR register is the commit register. The value of the GPIOCR register determines which
bits of the GPIOAFSEL register are committed when a write to the GPIOAFSEL register is performed.
If a bit in the GPIOCR register is a zero, the data being written to the corresponding bit in the
GPIOAFSEL register will not be committed and will retain its previous value. If a bit in the GPIOCR
register is a one, the data being written to the corresponding bit of the GPIOAFSEL register will be
committed to the register and will reflect the new value.
The contents of the GPIOCR register can only be modified if the GPIOLOCK register is unlocked.
Writes to the GPIOCR register are ignored if the GPIOLOCK register is locked.
Important: This register is designed to prevent accidental programming of the registers that control
connectivity to the JTAG/SWD debug hardware. By initializing the bits of the GPIOCR
register to 0 for PB7 and PC[3:0], the JTAG/SWD debug port can only be converted
to GPIOs through a deliberate set of writes to the GPIOLOCK, GPIOCR, and the
corresponding registers.
Because this protection is currently only implemented on the JTAG/SWD pins on PB7
and PC[3:0], all of the other bits in the GPIOCR registers cannot be written with 0x0.
These bits are hardwired to 0x1, ensuring that it is always possible to commit new
values to the GPIOAFSELregister bits of these other pins.
GPIO Commit (GPIOCR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x524
Type -, reset 31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
-
-
-
-
-
-
-
-
reserved
Type
Reset
reserved
Type
Reset
CR
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
7:0
CR
-
-
Description
GPIO Commit
On a bit-wise basis, any bit set allows the corresponding GPIOAFSEL
bit to be set to its alternate function.
Note:
The default register type for the GPIOCR register is RO for
all GPIO pins with the exception of the five JTAG/SWD pins
(PB7 and PC[3:0]). These five pins are currently the only
GPIOs that are protected by the GPIOCR register. Because
of this, the register type for GPIO Port B7 and GPIO Port
C[3:0] is R/W.
The default reset value for the GPIOCR register is
0x0000.00FF for all GPIO pins, with the exception of the five
JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the
JTAG port is not accidentally programmed as a GPIO, these
five pins default to non-committable. Because of this, the
default reset value of GPIOCR for GPIO Port B is
0x0000.007F while the default reset value of GPIOCR for Port
C is 0x0000.00F0.
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Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 4 (GPIOPeriphID4)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFD0
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID4
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID4
RO
0x00
GPIO Peripheral ID Register[7:0]
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Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 5 (GPIOPeriphID5)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFD4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID5
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID5
RO
0x00
GPIO Peripheral ID Register[15:8]
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Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 6 (GPIOPeriphID6)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFD8
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID6
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID6
RO
0x00
GPIO Peripheral ID Register[23:16]
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Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 7 (GPIOPeriphID7)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFDC
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID7
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID7
RO
0x00
GPIO Peripheral ID Register[31:24]
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Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 0 (GPIOPeriphID0)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFE0
Type RO, reset 0x0000.0061
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID0
RO
0x61
GPIO Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
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Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 1 (GPIOPeriphID1)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFE4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID1
RO
0x00
GPIO Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
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General-Purpose Input/Outputs (GPIOs)
Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 2 (GPIOPeriphID2)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFE8
Type RO, reset 0x0000.0018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
1
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID2
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID2
RO
0x18
GPIO Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
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Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 3 (GPIOPeriphID3)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFEC
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID3
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID3
RO
0x01
GPIO Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
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General-Purpose Input/Outputs (GPIOs)
Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 0 (GPIOPCellID0)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFF0
Type RO, reset 0x0000.000D
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
1
RO
1
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
CID0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID0
RO
0x0D
GPIO PrimeCell ID Register[7:0]
Provides software a standard cross-peripheral identification system.
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Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 1 (GPIOPCellID1)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
CID1
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
1
RO
1
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID1
RO
0xF0
GPIO PrimeCell ID Register[15:8]
Provides software a standard cross-peripheral identification system.
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Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 2 (GPIOPCellID2)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFF8
Type RO, reset 0x0000.0005
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
1
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
CID2
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID2
RO
0x05
GPIO PrimeCell ID Register[23:16]
Provides software a standard cross-peripheral identification system.
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Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 3 (GPIOPCellID3)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
CID3
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
RO
1
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID3
RO
0xB1
GPIO PrimeCell ID Register[31:24]
Provides software a standard cross-peripheral identification system.
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9
General-Purpose Timers
Programmable timers can be used to count or time external events that drive the Timer input pins.
®
The Stellaris General-Purpose Timer Module (GPTM) contains four GPTM blocks (Timer0, Timer1,
Timer 2, and Timer 3). Each GPTM block provides two 16-bit timers/counters (referred to as TimerA
and TimerB) that can be configured to operate independently as timers or event counters, or
configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
®
The GPT Module is one timing resource available on the Stellaris microcontrollers. Other timer
resources include the System Timer (SysTick) (see “System Timer (SysTick)” on page 43).
The General-Purpose Timers provide the following features:
■ Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers/counters.
Each GPTM can be configured to operate independently:
– As a single 32-bit timer
– As one 32-bit Real-Time Clock (RTC) to event capture
– For Pulse Width Modulation (PWM)
■ 32-bit Timer modes
– Programmable one-shot timer
– Programmable periodic timer
– Real-Time Clock when using an external 32.768-KHz clock as the input
– User-enabled stalling when the controller asserts CPU Halt flag during debug
■ 16-bit Timer modes
– General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only)
– Programmable one-shot timer
– Programmable periodic timer
– User-enabled stalling when the controller asserts CPU Halt flag during debug
■ 16-bit Input Capture modes
– Input edge count capture
– Input edge time capture
■ 16-bit PWM mode
– Simple PWM mode with software-programmable output inversion of the PWM signal
9.1
Block Diagram
Note:
®
In Figure 9-1 on page 191, the specific CCP pins available depend on the Stellaris device.
See Table 9-1 on page 191 for the available CCPs.
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Figure 9-1. GPTM Module Block Diagram
0x0000 (Down Counter Modes)
TimerA Control
GPTMTAPMR
TA Comparator
GPTMTAPR
Clock / Edge
Detect
GPTMTAMATCHR
Interrupt / Config
TimerA
Interrupt
GPTMCFG
GPTMTAILR
GPTMAR
En
GPTMTAMR
GPTMCTL
GPTMIMR
TimerB
Interrupt
32 KHz or
Even CCP Pin
RTC Divider
GPTMRIS
GPTMMIS
TimerB Control
GPTMICR
GPTMTBPMR
GPTMTBR En
Clock / Edge
Detect
GPTMTBPR
GPTMTBMATCHR
GPTMTBILR
Odd CCP Pin
TB Comparator
GPTMTBMR
0x0000 (Down Counter Modes)
System
Clock
Table 9-1. Available CCP Pins
Timer
16-Bit Up/Down Counter
Even CCP Pin
Odd CCP Pin
Timer 0
TimerA
CCP0
-
TimerB
-
CCP1
TimerA
-
-
TimerB
-
-
TimerA
-
-
TimerB
-
-
TimerA
-
-
TimerB
-
-
Timer 1
Timer 2
Timer 3
9.2
Functional Description
The main components of each GPTM block are two free-running 16-bit up/down counters (referred
to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two 16-bit
load/initialization registers and their associated control functions. The exact functionality of each
GPTM is controlled by software and configured through the register interface.
Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 202),
the GPTM TimerA Mode (GPTMTAMR) register (see page 203), and the GPTM TimerB Mode
(GPTMTBMR) register (see page 205). When in one of the 32-bit modes, the timer can only act as
a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers
configured in any combination of the 16-bit modes.
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9.2.1
GPTM Reset Conditions
After reset has been applied to the GPTM module, the module is in an inactive state, and all control
registers are cleared and in their default states. Counters TimerA and TimerB are initialized to
0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load
(GPTMTAILR) register (see page 216) and the GPTM TimerB Interval Load (GPTMTBILR) register
(see page 217). The prescale counters are initialized to 0x00: the GPTM TimerA Prescale
(GPTMTAPR) register (see page 220) and the GPTM TimerB Prescale (GPTMTBPR) register (see
page 221).
9.2.2
32-Bit Timer Operating Modes
This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and their
configuration.
The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1
(RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain GPTM
registers are concatenated to form pseudo 32-bit registers. These registers include:
■ GPTM TimerA Interval Load (GPTMTAILR) register [15:0], see page 216
■ GPTM TimerB Interval Load (GPTMTBILR) register [15:0], see page 217
■ GPTM TimerA (GPTMTAR) register [15:0], see page 224
■ GPTM TimerB (GPTMTBR) register [15:0], see page 225
In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access
to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is:
GPTMTBILR[15:0]:GPTMTAILR[15:0]
Likewise, a read access to GPTMTAR returns the value:
GPTMTBR[15:0]:GPTMTAR[15:0]
9.2.2.1
32-Bit One-Shot/Periodic Timer Mode
In 32-bit one-shot and periodic timer modes, the concatenated versions of the TimerA and TimerB
registers are configured as a 32-bit down-counter. The selection of one-shot or periodic mode is
determined by the value written to the TAMR field of the GPTM TimerA Mode (GPTMTAMR) register
(see page 203), and there is no need to write to the GPTM TimerB Mode (GPTMTBMR) register.
When software writes the TAEN bit in the GPTM Control (GPTMCTL) register (see page 207), the
timer begins counting down from its preloaded value. Once the 0x0000.0000 state is reached, the
timer reloads its start value from the concatenated GPTMTAILR on the next cycle. If configured to
be a one-shot timer, the timer stops counting and clears the TAEN bit in the GPTMCTL register. If
configured as a periodic timer, it continues counting.
In addition to reloading the count value, the GPTM generates interrupts and triggers when it reaches
the 0x000.0000 state. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt Status
(GPTMRIS) register (see page 212), and holds it until it is cleared by writing the GPTM Interrupt
Clear (GPTMICR) register (see page 214). If the time-out interrupt is enabled in the GPTM Interrupt
Mask (GPTIMR) register (see page 210), the GPTM also sets the TATOMIS bit in the GPTM Masked
Interrupt Status (GPTMMIS) register (see page 213).
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If software reloads the GPTMTAILR register while the counter is running, the counter loads the new
value on the next clock cycle and continues counting from the new value.
If the TASTALL bit in the GPTMCTL register is set, the timer freezes counting while the processor
is halted by the debugger. The timer resumes counting when the processor resumes execution.
9.2.2.2
32-Bit Real-Time Clock Timer Mode
In Real-Time Clock (RTC) mode, the concatenated versions of the TimerA and TimerB registers
are configured as a 32-bit up-counter. When RTC mode is selected for the first time, the counter is
loaded with a value of 0x0000.0001. All subsequent load values must be written to the GPTM TimerA
Match (GPTMTAMATCHR) register (see page 218) by the controller.
The input clock on an even CCP input is required to be 32.768 KHz in RTC mode. The clock signal
is then divided down to a 1 Hz rate and is passed along to the input of the 32-bit counter.
When software writes the TAEN bit inthe GPTMCTL register, the counter starts counting up from its
preloaded value of 0x0000.0001. When the current count value matches the preloaded value in the
GPTMTAMATCHR register, it rolls over to a value of 0x0000.0000 and continues counting until
either a hardware reset, or it is disabled by software (clearing the TAEN bit). When a match occurs,
the GPTM asserts the RTCRIS bit in GPTMRIS. If the RTC interrupt is enabled in GPTIMR, the
GPTM also sets the RTCMIS bit in GPTMISR and generates a controller interrupt. The status flags
are cleared by writing the RTCCINT bit in GPTMICR.
If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if
the RTCEN bit is set in GPTMCTL.
9.2.3
16-Bit Timer Operating Modes
The GPTM is placed into global 16-bit mode by writing a value of 0x4 to the GPTM Configuration
(GPTMCFG) register (see page 202). This section describes each of the GPTM 16-bit modes of
operation. TimerA and TimerB have identical modes, so a single description is given using an n to
reference both.
9.2.3.1
16-Bit One-Shot/Periodic Timer Mode
In 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with
an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits. The
selection of one-shot or periodic mode is determined by the value written to the TnMR field of the
GPTMTnMR register. The optional prescaler is loaded into the GPTM Timern Prescale (GPTMTnPR)
register.
When software writes the TnEN bit in the GPTMCTL register, the timer begins counting down from
its preloaded value. Once the 0x0000 state is reached, the timer reloads its start value from
GPTMTnILR and GPTMTnPR on the next cycle. If configured to be a one-shot timer, the timer stops
counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, it
continues counting.
In addition to reloading the count value, the timer generates interrupts and triggers when it reaches
the 0x0000 state. The GPTM sets the TnTORIS bit in the GPTMRIS register, and holds it until it is
cleared by writing the GPTMICR register. If the time-out interrupt is enabled in GPTIMR, the GPTM
also sets the TnTOMIS bit in GPTMISR and generates a controller interrupt.
If software reloads the GPTMTAILR register while the counter is running, the counter loads the new
value on the next clock cycle and continues counting from the new value.
If the TnSTALL bit in the GPTMCTL register is set, the timer freezes counting while the processor
is halted by the debugger. The timer resumes counting when the processor resumes execution.
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The following example shows a variety of configurations for a 16-bit free running timer while using
the prescaler. All values assume a 50-MHz clock with Tc=20 ns (clock period).
Table 9-2. 16-Bit Timer With Prescaler Configurations
a
Prescale
#Clock (T c)
Max Time
Units
00000000
1
1.3107
mS
00000001
2
2.6214
mS
00000010
3
3.9322
mS
------------
--
--
--
11111101
254
332.9229
mS
11111110
255
334.2336
mS
11111111
256
335.5443
mS
a. Tc is the clock period.
9.2.3.2
16-Bit Input Edge Count Mode
Note:
For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling-edge detection, the input signal must be Low
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is 1/4 of the system frequency.
Note:
The prescaler is not available in 16-Bit Input Edge Count mode.
In Edge Count mode, the timer is configured as a down-counter capable of capturing three types
of events: rising edge, falling edge, or both. To place the timer in Edge Count mode, the TnCMR bit
of the GPTMTnMR register must be set to 0. The type of edge that the timer counts is determined
by the TnEVENT fields of the GPTMCTL register. During initialization, the GPTM Timern Match
(GPTMTnMATCHR) register is configured so that the difference between the value in the
GPTMTnILR register and the GPTMTnMATCHR register equals the number of edge events that
must be counted.
When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled
for event capture. Each input event on the CCP pin decrements the counter by 1 until the event count
matches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit in the
GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked).
The counter is then reloaded using the value in GPTMTnILR, and stopped since the GPTM
automatically clears the TnEN bit in the GPTMCTL register. Once the event count has been reached,
all further events are ignored until TnEN is re-enabled by software.
Figure 9-2 on page 195 shows how input edge count mode works. In this case, the timer start value
is set to GPTMnILR =0x000A and the match value is set to GPTMnMATCHR =0x0006 so that four
edge events are counted. The counter is configured to detect both edges of the input signal.
Note that the last two edges are not counted since the timer automatically clears the TnEN bit after
the current count matches the value in the GPTMnMR register.
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Figure 9-2. 16-Bit Input Edge Count Mode Example
Timer stops,
flags
asserted
Count
Timer reload
on next cycle
Ignored
Ignored
0x000A
0x0009
0x0008
0x0007
0x0006
Input Signal
9.2.3.3
16-Bit Input Edge Time Mode
Note:
For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling edge detection, the input signal must be Low
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is 1/4 of the system frequency.
Note:
The prescaler is not available in 16-Bit Input Edge Time mode.
In Edge Time mode, the timer is configured as a free-running down-counter initialized to the value
loaded in the GPTMTnILR register (or 0xFFFF at reset). This mode allows for event capture of
either rising or falling edges, but not both. The timer is placed into Edge Time mode by setting the
TnCMR bit in the GPTMTnMR register, and the type of event that the timer captures is determined
by the TnEVENT fields of the GPTMCnTL register.
When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture.
When the selected input event is detected, the current Tn counter value is captured in the GPTMTnR
register and is available to be read by the controller. The GPTM then asserts the CnERIS bit (and
the CnEMIS bit, if the interrupt is not masked).
After an event has been captured, the timer does not stop counting. It continues to count until the
TnEN bit is cleared. When the timer reaches the 0x0000 state, it is reloaded with the value from the
GPTMnILR register.
Figure 9-3 on page 196 shows how input edge timing mode works. In the diagram, it is assumed that
the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture
rising edge events.
Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR
register, and is held there until another rising edge is detected (at which point the new count value
is loaded into GPTMTnR).
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Figure 9-3. 16-Bit Input Edge Time Mode Example
Count
0xFFFF
GPTMTnR=X
GPTMTnR=Y
GPTMTnR=Z
Z
X
Y
Time
Input Signal
9.2.3.4
16-Bit PWM Mode
Note:
The prescaler is not available in 16-Bit PWM mode.
The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a
down-counter with a start value (and thus period) defined by GPTMTnILR. In this mode, the PWM
frequency and period are synchronous events and therefore guaranteed to be glitch free. PWM
mode is enabled with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to
0x0, and the TnMR field to 0x2.
When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down
until it reaches the 0x0000 state. On the next counter cycle, the counter reloads its start value from
GPTMTnILR and continues counting until disabled by software clearing the TnEN bit in the GPTMCTL
register. No interrupts or status bits are asserted in PWM mode.
The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its
start state), and is deasserted when the counter value equals the value in the GPTM Timern Match
Register (GPTMnMATCHR). Software has the capability of inverting the output PWM signal by
setting the TnPWML bit in the GPTMCTL register.
Figure 9-4 on page 197 shows how to generate an output PWM with a 1-ms period and a 66% duty
cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML
=1 configuration). For this example, the start value is GPTMnIRL=0xC350 and the match value is
GPTMnMR=0x411A.
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Figure 9-4. 16-Bit PWM Mode Example
Count
GPTMTnR=GPTMnMR
GPTMTnR=GPTMnMR
0xC350
0x411A
Time
TnEN set
TnPWML = 0
Output
Signal
TnPWML = 1
9.3
Initialization and Configuration
To use the general-purpose timers, the peripheral clock must be enabled by setting the TIMER0,
TIMER1, TIMER2, and TIMER3 bits in the RCGC1 register.
This section shows module initialization and configuration examples for each of the supported timer
modes.
9.3.1
32-Bit One-Shot/Periodic Timer Mode
The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making
any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0.
3. Set the TAMR field in the GPTM TimerA Mode Register (GPTMTAMR):
a. Write a value of 0x1 for One-Shot mode.
b. Write a value of 0x2 for Periodic mode.
4. Load the start value into the GPTM TimerA Interval Load Register (GPTMTAILR).
5. If interrupts are required, set the TATOIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
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7. Poll the TATORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the TATOCINT bit of the GPTM
Interrupt Clear Register (GPTMICR).
In One-Shot mode, the timer stops counting after step 7 on page 198. To re-enable the timer, repeat
the sequence. A timer configured in Periodic mode does not stop counting after it times out.
9.3.2
32-Bit Real-Time Clock (RTC) Mode
To use the RTC mode, the timer must have a 32.768-KHz input signal on an even CCP input. To
enable the RTC feature, follow these steps:
1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x1.
3. Write the desired match value to the GPTM TimerA Match Register (GPTMTAMATCHR).
4. Set/clear the RTCEN bit in the GPTM Control Register (GPTMCTL) as desired.
5. If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
When the timer count equals the value in the GPTMTAMATCHR register, the counter is re-loaded
with 0x0000.0000 and begins counting. If an interrupt is enabled, it does not have to be cleared.
9.3.3
16-Bit One-Shot/Periodic Timer Mode
A timer is configured for 16-bit One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x4.
3. Set the TnMR field in the GPTM Timer Mode (GPTMTnMR) register:
a. Write a value of 0x1 for One-Shot mode.
b. Write a value of 0x2 for Periodic mode.
4. If a prescaler is to be used, write the prescale value to the GPTM Timern Prescale Register
(GPTMTnPR).
5. Load the start value into the GPTM Timer Interval Load Register (GPTMTnILR).
6. If interrupts are required, set the TnTOIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
7. Set the TnEN bit in the GPTM Control Register (GPTMCTL) to enable the timer and start
counting.
8. Poll the TnTORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the TnTOCINT bit of the GPTM
Interrupt Clear Register (GPTMICR).
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In One-Shot mode, the timer stops counting after step 8 on page 198. To re-enable the timer, repeat
the sequence. A timer configured in Periodic mode does not stop counting after it times out.
9.3.4
16-Bit Input Edge Count Mode
A timer is configured to Input Edge Count mode by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR
field to 0x3.
4. Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. Load the desired event count into the GPTM Timern Match (GPTMTnMATCHR) register.
7. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
8. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events.
9. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM
Interrupt Clear (GPTMICR) register.
In Input Edge Count Mode, the timer stops after the desired number of edge events has been
detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat step 4 on page 199
through step 9 on page 199.
9.3.5
16-Bit Input Edge Timing Mode
A timer is configured to Input Edge Timing mode by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR
field to 0x3.
4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting.
8. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM
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Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained
by reading the GPTM Timern (GPTMTnR) register.
In Input Edge Timing mode, the timer continues running after an edge event has been detected,
but the timer interval can be changed at any time by writing the GPTMTnILR register. The change
takes effect at the next cycle after the write.
9.3.6
16-Bit PWM Mode
A timer is configured to PWM mode using the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to
0x0, and the TnMR field to 0x2.
4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnEVENT field
of the GPTM Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. Load the GPTM Timern Match (GPTMTnMATCHR) register with the desired value.
7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin
generation of the output PWM signal.
In PWM Timing mode, the timer continues running after the PWM signal has been generated. The
PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes
effect at the next cycle after the write.
9.4
Register Map
Table 9-3 on page 200 lists the GPTM registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that timer’s base address:
■
■
■
■
Timer0: 0x4003.0000
Timer1: 0x4003.1000
Timer2: 0x4003.2000
Timer3: 0x4003.3000
Table 9-3. Timers Register Map
Description
See
page
Offset
Name
Type
Reset
0x000
GPTMCFG
R/W
0x0000.0000
GPTM Configuration
202
0x004
GPTMTAMR
R/W
0x0000.0000
GPTM TimerA Mode
203
0x008
GPTMTBMR
R/W
0x0000.0000
GPTM TimerB Mode
205
0x00C
GPTMCTL
R/W
0x0000.0000
GPTM Control
207
0x018
GPTMIMR
R/W
0x0000.0000
GPTM Interrupt Mask
210
0x01C
GPTMRIS
RO
0x0000.0000
GPTM Raw Interrupt Status
212
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Table 9-3. Timers Register Map (continued)
Offset
Name
0x020
Reset
GPTMMIS
RO
0x0000.0000
GPTM Masked Interrupt Status
213
0x024
GPTMICR
W1C
0x0000.0000
GPTM Interrupt Clear
214
0x028
GPTMTAILR
R/W
0xFFFF.FFFF
GPTM TimerA Interval Load
216
0x02C
GPTMTBILR
R/W
0x0000.FFFF
GPTM TimerB Interval Load
217
0x030
GPTMTAMATCHR
R/W
0xFFFF.FFFF
GPTM TimerA Match
218
0x034
GPTMTBMATCHR
R/W
0x0000.FFFF
GPTM TimerB Match
219
0x038
GPTMTAPR
R/W
0x0000.0000
GPTM TimerA Prescale
220
0x03C
GPTMTBPR
R/W
0x0000.0000
GPTM TimerB Prescale
221
0x040
GPTMTAPMR
R/W
0x0000.0000
GPTM TimerA Prescale Match
222
0x044
GPTMTBPMR
R/W
0x0000.0000
GPTM TimerB Prescale Match
223
0x048
GPTMTAR
RO
0xFFFF.FFFF
GPTM TimerA
224
0x04C
GPTMTBR
RO
0x0000.FFFF
GPTM TimerB
225
9.5
Description
See
page
Type
Register Descriptions
The remainder of this section lists and describes the GPTM registers, in numerical order by address
offset.
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Register 1: GPTM Configuration (GPTMCFG), offset 0x000
This register configures the global operation of the GPTM module. The value written to this register
determines whether the GPTM is in 32- or 16-bit mode.
GPTM Configuration (GPTMCFG)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
GPTMCFG
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:3
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2:0
GPTMCFG
R/W
0x0
GPTM Configuration
The GPTMCFG values are defined as follows:
Value
Description
0x0
32-bit timer configuration.
0x1
32-bit real-time clock (RTC) counter configuration.
0x2
Reserved
0x3
Reserved
0x4-0x7 16-bit timer configuration, function is controlled by bits 1:0 of
GPTMTAMR and GPTMTBMR.
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Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TAAMS bit to 0x1, the TACMR bit to 0x0, and the TAMR field to
0x2.
GPTM TimerA Mode (GPTMTAMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x004
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
TAAMS
TACMR
R/W
0
R/W
0
0
TAMR
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
TAAMS
R/W
0
GPTM TimerA Alternate Mode Select
The TAAMS values are defined as follows:
Value Description
0
Capture mode is enabled.
1
PWM mode is enabled.
Note:
2
TACMR
R/W
0
To enable PWM mode, you must also clear the TACMR
bit and set the TAMR field to 0x2.
GPTM TimerA Capture Mode
The TACMR values are defined as follows:
Value Description
0
Edge-Count mode
1
Edge-Time mode
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Bit/Field
Name
Type
Reset
1:0
TAMR
R/W
0x0
Description
GPTM TimerA Mode
The TAMR values are defined as follows:
Value Description
0x0 Reserved
0x1 One-Shot Timer mode
0x2 Periodic Timer mode
0x3 Capture mode
The Timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register (16-or 32-bit).
In 16-bit timer configuration, TAMR controls the 16-bit timer modes for
TimerA.
In 32-bit timer configuration, this register controls the mode and the
contents of GPTMTBMR are ignored.
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Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TBAMS bit to 0x1, the TBCMR bit to 0x0, and the TBMR field to
0x2.
GPTM TimerB Mode (GPTMTBMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
TBAMS
TBCMR
R/W
0
R/W
0
0
TBMR
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
TBAMS
R/W
0
GPTM TimerB Alternate Mode Select
The TBAMS values are defined as follows:
Value Description
0
Capture mode is enabled.
1
PWM mode is enabled.
Note:
2
TBCMR
R/W
0
To enable PWM mode, you must also clear the TBCMR
bit and set the TBMR field to 0x2.
GPTM TimerB Capture Mode
The TBCMR values are defined as follows:
Value Description
0
Edge-Count mode
1
Edge-Time mode
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Bit/Field
Name
Type
Reset
1:0
TBMR
R/W
0x0
Description
GPTM TimerB Mode
The TBMR values are defined as follows:
Value Description
0x0 Reserved
0x1 One-Shot Timer mode
0x2 Periodic Timer mode
0x3 Capture mode
The timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register.
In 16-bit timer configuration, these bits control the 16-bit timer modes
for TimerB.
In 32-bit timer configuration, this register’s contents are ignored and
GPTMTAMR is used.
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Register 4: GPTM Control (GPTMCTL), offset 0x00C
This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer
configuration, and to enable other features such as timer stall.
GPTM Control (GPTMCTL)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x00C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
reserved
Type
Reset
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
13
12
11
10
15
14
reserved
TBPWML
RO
0
R/W
0
reserved
RO
0
RO
0
TBEVENT
R/W
0
R/W
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
TBSTALL
TBEN
reserved
TAPWML
reserved
RTCEN
R/W
0
R/W
0
RO
0
R/W
0
RO
0
R/W
0
TAEVENT
R/W
0
R/W
0
1
0
TASTALL
TAEN
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:15
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14
TBPWML
R/W
0
GPTM TimerB PWM Output Level
The TBPWML values are defined as follows:
Value Description
13:12
reserved
RO
0
11:10
TBEVENT
R/W
0x0
0
Output is unaffected.
1
Output is inverted.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM TimerB Event Mode
The TBEVENT values are defined as follows:
Value Description
0x0 Positive edge
0x1 Negative edge
0x2 Reserved
0x3 Both edges
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Bit/Field
Name
Type
Reset
9
TBSTALL
R/W
0
Description
GPTM Timer B Stall Enable
The TBSTALL values are defined as follows:
Value Description
0
Timer B continues counting while the processor is halted by the
debugger.
1
Timer B freezes counting while the processor is halted by the
debugger.
If the processor is executing normally, the TBSTALL bit is ignored.
8
TBEN
R/W
0
GPTM TimerB Enable
The TBEN values are defined as follows:
Value Description
0
TimerB is disabled.
1
TimerB is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
TAPWML
R/W
0
GPTM TimerA PWM Output Level
The TAPWML values are defined as follows:
Value Description
0
Output is unaffected.
1
Output is inverted.
5
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
RTCEN
R/W
0
GPTM RTC Enable
The RTCEN values are defined as follows:
Value Description
3:2
TAEVENT
R/W
0x0
0
RTC counting is disabled.
1
RTC counting is enabled.
GPTM TimerA Event Mode
The TAEVENT values are defined as follows:
Value Description
0x0 Positive edge
0x1 Negative edge
0x2 Reserved
0x3 Both edges
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Bit/Field
Name
Type
Reset
1
TASTALL
R/W
0
Description
GPTM Timer A Stall Enable
The TASTALL values are defined as follows:
Value Description
0
Timer A continues counting while the processor is halted by the
debugger.
1
Timer A freezes counting while the processor is halted by the
debugger.
If the processor is executing normally, the TASTALL bit is ignored.
0
TAEN
R/W
0
GPTM TimerA Enable
The TAEN values are defined as follows:
Value Description
0
TimerA is disabled.
1
TimerA is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
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Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018
This register allows software to enable/disable GPTM controller-level interrupts. Writing a 1 enables
the interrupt, while writing a 0 disables it.
GPTM Interrupt Mask (GPTMIMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x018
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
15
14
RO
0
RO
0
RO
0
13
12
11
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
10
9
8
CBEIM
CBMIM
TBTOIM
R/W
0
R/W
0
R/W
0
RO
0
reserved
RO
0
RO
0
RO
0
3
2
1
0
RTCIM
CAEIM
CAMIM
TATOIM
R/W
0
R/W
0
R/W
0
R/W
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:11
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
CBEIM
R/W
0
GPTM CaptureB Event Interrupt Mask
The CBEIM values are defined as follows:
Value Description
9
CBMIM
R/W
0
0
Interrupt is disabled.
1
Interrupt is enabled.
GPTM CaptureB Match Interrupt Mask
The CBMIM values are defined as follows:
Value Description
8
TBTOIM
R/W
0
0
Interrupt is disabled.
1
Interrupt is enabled.
GPTM TimerB Time-Out Interrupt Mask
The TBTOIM values are defined as follows:
Value Description
7:4
reserved
RO
0
0
Interrupt is disabled.
1
Interrupt is enabled.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
3
RTCIM
R/W
0
Description
GPTM RTC Interrupt Mask
The RTCIM values are defined as follows:
Value Description
2
CAEIM
R/W
0
0
Interrupt is disabled.
1
Interrupt is enabled.
GPTM CaptureA Event Interrupt Mask
The CAEIM values are defined as follows:
Value Description
1
CAMIM
R/W
0
0
Interrupt is disabled.
1
Interrupt is enabled.
GPTM CaptureA Match Interrupt Mask
The CAMIM values are defined as follows:
Value Description
0
TATOIM
R/W
0
0
Interrupt is disabled.
1
Interrupt is enabled.
GPTM TimerA Time-Out Interrupt Mask
The TATOIM values are defined as follows:
Value Description
0
Interrupt is disabled.
1
Interrupt is enabled.
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Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C
This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or
not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its
corresponding bit in GPTMICR.
GPTM Raw Interrupt Status (GPTMRIS)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x01C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
1
0
reserved
Type
Reset
RO
0
RO
0
15
14
RO
0
RO
0
RO
0
13
12
11
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
10
CBERIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
CBMRIS TBTORIS
RO
0
RO
0
reserved
RO
0
RO
0
RO
0
3
2
RTCRIS
CAERIS
RO
0
RO
0
RO
0
CAMRIS TATORIS
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:11
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
CBERIS
RO
0
GPTM CaptureB Event Raw Interrupt
This is the CaptureB Event interrupt status prior to masking.
9
CBMRIS
RO
0
GPTM CaptureB Match Raw Interrupt
This is the CaptureB Match interrupt status prior to masking.
8
TBTORIS
RO
0
GPTM TimerB Time-Out Raw Interrupt
This is the TimerB time-out interrupt status prior to masking.
7:4
reserved
RO
0x0
3
RTCRIS
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM RTC Raw Interrupt
This is the RTC Event interrupt status prior to masking.
2
CAERIS
RO
0
GPTM CaptureA Event Raw Interrupt
This is the CaptureA Event interrupt status prior to masking.
1
CAMRIS
RO
0
GPTM CaptureA Match Raw Interrupt
This is the CaptureA Match interrupt status prior to masking.
0
TATORIS
RO
0
GPTM TimerA Time-Out Raw Interrupt
This the TimerA time-out interrupt status prior to masking.
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Stellaris® LM3S8530 Microcontroller
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020
This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in
GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is
set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR.
GPTM Masked Interrupt Status (GPTMMIS)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x020
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
2
1
0
reserved
Type
Reset
RO
0
RO
0
15
14
RO
0
RO
0
RO
0
13
12
11
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
10
9
8
7
6
5
4
CBEMIS CBMMIS TBTOMIS
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
RO
0
RO
0
RO
0
3
RTCMIS
RO
0
RO
0
CAEMIS CAMMIS TATOMIS
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:11
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
CBEMIS
RO
0
GPTM CaptureB Event Masked Interrupt
This is the CaptureB event interrupt status after masking.
9
CBMMIS
RO
0
GPTM CaptureB Match Masked Interrupt
This is the CaptureB match interrupt status after masking.
8
TBTOMIS
RO
0
GPTM TimerB Time-Out Masked Interrupt
This is the TimerB time-out interrupt status after masking.
7:4
reserved
RO
0x0
3
RTCMIS
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM RTC Masked Interrupt
This is the RTC event interrupt status after masking.
2
CAEMIS
RO
0
GPTM CaptureA Event Masked Interrupt
This is the CaptureA event interrupt status after masking.
1
CAMMIS
RO
0
GPTM CaptureA Match Masked Interrupt
This is the CaptureA match interrupt status after masking.
0
TATOMIS
RO
0
GPTM TimerA Time-Out Masked Interrupt
This is the TimerA time-out interrupt status after masking.
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Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024
This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1
to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers.
GPTM Interrupt Clear (GPTMICR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x024
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
reserved
Type
Reset
RO
0
RO
0
15
14
RO
0
RO
0
RO
0
13
12
11
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
10
9
8
7
6
5
4
CBECINT CBMCINT TBTOCINT
RO
0
RO
0
W1C
0
W1C
0
W1C
0
reserved
RO
0
RO
0
RO
0
RTCCINT CAECINT CAMCINT TATOCINT
RO
0
W1C
0
W1C
0
W1C
0
W1C
0
Bit/Field
Name
Type
Reset
Description
31:11
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
CBECINT
W1C
0
GPTM CaptureB Event Interrupt Clear
The CBECINT values are defined as follows:
Value Description
9
CBMCINT
W1C
0
0
The interrupt is unaffected.
1
The interrupt is cleared.
GPTM CaptureB Match Interrupt Clear
The CBMCINT values are defined as follows:
Value Description
8
TBTOCINT
W1C
0
0
The interrupt is unaffected.
1
The interrupt is cleared.
GPTM TimerB Time-Out Interrupt Clear
The TBTOCINT values are defined as follows:
Value Description
7:4
reserved
RO
0x0
0
The interrupt is unaffected.
1
The interrupt is cleared.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
3
RTCCINT
W1C
0
Description
GPTM RTC Interrupt Clear
The RTCCINT values are defined as follows:
Value Description
2
CAECINT
W1C
0
0
The interrupt is unaffected.
1
The interrupt is cleared.
GPTM CaptureA Event Interrupt Clear
The CAECINT values are defined as follows:
Value Description
1
CAMCINT
W1C
0
0
The interrupt is unaffected.
1
The interrupt is cleared.
GPTM CaptureA Match Raw Interrupt
This is the CaptureA match interrupt status after masking.
0
TATOCINT
W1C
0
GPTM TimerA Time-Out Raw Interrupt
The TATOCINT values are defined as follows:
Value Description
0
The interrupt is unaffected.
1
The interrupt is cleared.
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Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028
This register is used to load the starting count value into the timer. When GPTM is configured to
one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond
to the contents of the GPTM TimerB Interval Load (GPTMTBILR) register). In 16-bit mode, the
upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR.
GPTM TimerA Interval Load (GPTMTAILR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x028
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TAILRH
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
TAILRL
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
31:16
TAILRH
R/W
0xFFFF
R/W
1
Description
GPTM TimerA Interval Load Register High
When configured for 32-bit mode via the GPTMCFG register, the GPTM
TimerB Interval Load (GPTMTBILR) register loads this value on a
write. A read returns the current value of GPTMTBILR.
In 16-bit mode, this field reads as 0 and does not have an effect on the
state of GPTMTBILR.
15:0
TAILRL
R/W
0xFFFF
GPTM TimerA Interval Load Register Low
For both 16- and 32-bit modes, writing this field loads the counter for
TimerA. A read returns the current value of GPTMTAILR.
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Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C
This register is used to load the starting count value into TimerB. When the GPTM is configured to
a 32-bit mode, GPTMTBILR returns the current value of TimerB and ignores writes.
GPTM TimerB Interval Load (GPTMTBILR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x02C
Type R/W, reset 0x0000.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
TBILRL
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
TBILRL
R/W
0xFFFF
GPTM TimerB Interval Load Register
When the GPTM is not configured as a 32-bit timer, a write to this field
updates GPTMTBILR. In 32-bit mode, writes are ignored, and reads
return the current value of GPTMTBILR.
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Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030
This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes.
GPTM TimerA Match (GPTMTAMATCHR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x030
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TAMRH
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
TAMRL
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
31:16
TAMRH
R/W
0xFFFF
R/W
1
Description
GPTM TimerA Match Register High
When configured for 32-bit Real-Time Clock (RTC) mode via the
GPTMCFG register, this value is compared to the upper half of
GPTMTAR, to determine match events.
In 16-bit mode, this field reads as 0 and does not have an effect on the
state of GPTMTBMATCHR.
15:0
TAMRL
R/W
0xFFFF
GPTM TimerA Match Register Low
When configured for 32-bit Real-Time Clock (RTC) mode via the
GPTMCFG register, this value is compared to the lower half of
GPTMTAR, to determine match events.
When configured for PWM mode, this value along with GPTMTAILR,
determines the duty cycle of the output PWM signal.
When configured for Edge Count mode, this value along with
GPTMTAILR, determines how many edge events are counted. The total
number of edge events counted is equal to the value in GPTMTAILR
minus this value.
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Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034
This register is used in 16-bit PWM and Input Edge Count modes.
GPTM TimerB Match (GPTMTBMATCHR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x034
Type R/W, reset 0x0000.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
TBMRL
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
TBMRL
R/W
0xFFFF
GPTM TimerB Match Register Low
When configured for PWM mode, this value along with GPTMTBILR,
determines the duty cycle of the output PWM signal.
When configured for Edge Count mode, this value along with
GPTMTBILR, determines how many edge events are counted. The total
number of edge events counted is equal to the value in GPTMTBILR
minus this value.
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Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038
This register allows software to extend the range of the 16-bit timers when operating in one-shot or
periodic mode.
GPTM TimerA Prescale (GPTMTAPR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x038
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
TAPSR
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
TAPSR
R/W
0x00
GPTM TimerA Prescale
The register loads this value on a write. A read returns the current value
of the register.
Refer to Table 9-2 on page 194 for more details and an example.
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Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C
This register allows software to extend the range of the 16-bit timers when operating in one-shot or
periodic mode.
GPTM TimerB Prescale (GPTMTBPR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x03C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
TBPSR
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
TBPSR
R/W
0x00
GPTM TimerB Prescale
The register loads this value on a write. A read returns the current value
of this register.
Refer to Table 9-2 on page 194 for more details and an example.
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Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040
This register effectively extends the range of GPTMTAMATCHR to 24 bits when operating in 16-bit
one-shot or periodic mode.
GPTM TimerA Prescale Match (GPTMTAPMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x040
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
TAPSMR
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
TAPSMR
R/W
0x00
GPTM TimerA Prescale Match
This value is used alongside GPTMTAMATCHR to detect timer match
events while using a prescaler.
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Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044
This register effectively extends the range of GPTMTBMATCHR to 24 bits when operating in 16-bit
one-shot or periodic mode.
GPTM TimerB Prescale Match (GPTMTBPMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x044
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
TBPSMR
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
TBPSMR
R/W
0x00
GPTM TimerB Prescale Match
This value is used alongside GPTMTBMATCHR to detect timer match
events while using a prescaler.
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Register 17: GPTM TimerA (GPTMTAR), offset 0x048
This register shows the current value of the TimerA counter in all cases except for Input Edge Count
mode. When in this mode, this register contains the time at which the last edge event took place.
GPTM TimerA (GPTMTAR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x048
Type RO, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
7
6
5
4
3
2
1
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
TARH
Type
Reset
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
15
14
13
12
11
10
9
8
TARL
Type
Reset
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
Bit/Field
Name
Type
Reset
31:16
TARH
RO
0xFFFF
RO
1
Description
GPTM TimerA Register High
If the GPTMCFG is in a 32-bit mode, TimerB value is read. If the
GPTMCFG is in a 16-bit mode, this is read as zero.
15:0
TARL
RO
0xFFFF
GPTM TimerA Register Low
A read returns the current value of the GPTM TimerA Count Register,
except in Input Edge Count mode, when it returns the timestamp from
the last edge event.
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Register 18: GPTM TimerB (GPTMTBR), offset 0x04C
This register shows the current value of the TimerB counter in all cases except for Input Edge Count
mode. When in this mode, this register contains the time at which the last edge event took place.
GPTM TimerB (GPTMTBR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x04C
Type RO, reset 0x0000.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
TBRL
Type
Reset
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
TBRL
RO
0xFFFF
GPTM TimerB
A read returns the current value of the GPTM TimerB Count Register,
except in Input Edge Count mode, when it returns the timestamp from
the last edge event.
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Watchdog Timer
10
Watchdog Timer
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or due to the failure of an external device to respond in the expected way.
®
The Stellaris Watchdog Timer module has the following features:
■ 32-bit down counter with a programmable load register
■ Separate watchdog clock with an enable
■ Programmable interrupt generation logic with interrupt masking
■ Lock register protection from runaway software
■ Reset generation logic with an enable/disable
■ User-enabled stalling when the controller asserts the CPU Halt flag during debug
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
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10.1
Block Diagram
Figure 10-1. WDT Module Block Diagram
WDTLOAD
Control / Clock /
Interrupt
Generation
WDTCTL
WDTICR
Interrupt
WDTRIS
32-Bit Down
Counter
WDTMIS
0x00000000
WDTLOCK
System Clock
WDTTEST
Comparator
WDTVALUE
Identification Registers
10.2
WDTPCellID0
WDTPeriphID0
WDTPeriphID4
WDTPCellID1
WDTPeriphID1
WDTPeriphID5
WDTPCellID2
WDTPeriphID2
WDTPeriphID6
WDTPCellID3
WDTPeriphID3
WDTPeriphID7
Functional Description
The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches
the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt.
After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value. Once the
Watchdog Timer has been configured, the Watchdog Timer Lock (WDTLOCK) register is written,
which prevents the timer configuration from being inadvertently altered by software.
If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the
reset signal has been enabled (via the WatchdogResetEnable function), the Watchdog timer
asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its
second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting
resumes from that value.
If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the
counter is loaded with the new value and continues counting.
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Watchdog Timer
Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared
by writing to the Watchdog Interrupt Clear (WDTICR) register.
The Watchdog module interrupt and reset generation can be enabled or disabled as required. When
the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its
last state.
10.3
Initialization and Configuration
To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register.
The Watchdog Timer is configured using the following sequence:
1. Load the WDTLOAD register with the desired timer load value.
2. If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL register.
3. Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control register.
If software requires that all of the watchdog registers are locked, the Watchdog Timer module can
be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write
a value of 0x1ACC.E551.
10.4
Register Map
Table 10-1 on page 228 lists the Watchdog registers. The offset listed is a hexadecimal increment
to the register’s address, relative to the Watchdog Timer base address of 0x4000.0000.
Table 10-1. Watchdog Timer Register Map
Description
See
page
Offset
Name
Type
Reset
0x000
WDTLOAD
R/W
0xFFFF.FFFF
Watchdog Load
230
0x004
WDTVALUE
RO
0xFFFF.FFFF
Watchdog Value
231
0x008
WDTCTL
R/W
0x0000.0000
Watchdog Control
232
0x00C
WDTICR
WO
-
Watchdog Interrupt Clear
233
0x010
WDTRIS
RO
0x0000.0000
Watchdog Raw Interrupt Status
234
0x014
WDTMIS
RO
0x0000.0000
Watchdog Masked Interrupt Status
235
0x418
WDTTEST
R/W
0x0000.0000
Watchdog Test
236
0xC00
WDTLOCK
R/W
0x0000.0000
Watchdog Lock
237
0xFD0
WDTPeriphID4
RO
0x0000.0000
Watchdog Peripheral Identification 4
238
0xFD4
WDTPeriphID5
RO
0x0000.0000
Watchdog Peripheral Identification 5
239
0xFD8
WDTPeriphID6
RO
0x0000.0000
Watchdog Peripheral Identification 6
240
0xFDC
WDTPeriphID7
RO
0x0000.0000
Watchdog Peripheral Identification 7
241
0xFE0
WDTPeriphID0
RO
0x0000.0005
Watchdog Peripheral Identification 0
242
0xFE4
WDTPeriphID1
RO
0x0000.0018
Watchdog Peripheral Identification 1
243
0xFE8
WDTPeriphID2
RO
0x0000.0018
Watchdog Peripheral Identification 2
244
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Table 10-1. Watchdog Timer Register Map (continued)
Offset
Name
0xFEC
Reset
WDTPeriphID3
RO
0x0000.0001
Watchdog Peripheral Identification 3
245
0xFF0
WDTPCellID0
RO
0x0000.000D
Watchdog PrimeCell Identification 0
246
0xFF4
WDTPCellID1
RO
0x0000.00F0
Watchdog PrimeCell Identification 1
247
0xFF8
WDTPCellID2
RO
0x0000.0005
Watchdog PrimeCell Identification 2
248
0xFFC
WDTPCellID3
RO
0x0000.00B1
Watchdog PrimeCell Identification 3
249
10.5
Description
See
page
Type
Register Descriptions
The remainder of this section lists and describes the WDT registers, in numerical order by address
offset.
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Watchdog Timer
Register 1: Watchdog Load (WDTLOAD), offset 0x000
This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the
value is immediately loaded and the counter restarts counting down from the new value. If the
WDTLOAD register is loaded with 0x0000.0000, an interrupt is immediately generated.
Watchdog Load (WDTLOAD)
Base 0x4000.0000
Offset 0x000
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
23
22
21
20
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
WDTLoad
Type
Reset
WDTLoad
Type
Reset
Bit/Field
Name
Type
31:0
WDTLoad
R/W
Reset
R/W
1
Description
0xFFFF.FFFF Watchdog Load Value
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Register 2: Watchdog Value (WDTVALUE), offset 0x004
This register contains the current count value of the timer.
Watchdog Value (WDTVALUE)
Base 0x4000.0000
Offset 0x004
Type RO, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
15
14
13
12
11
10
9
8
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
23
22
21
20
19
18
17
16
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
7
6
5
4
3
2
1
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
WDTValue
Type
Reset
WDTValue
Type
Reset
Bit/Field
Name
Type
31:0
WDTValue
RO
Reset
RO
1
Description
0xFFFF.FFFF Watchdog Value
Current value of the 32-bit down counter.
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Watchdog Timer
Register 3: Watchdog Control (WDTCTL), offset 0x008
This register is the watchdog control register. The watchdog timer can be configured to generate a
reset signal (on second time-out) or an interrupt on time-out.
When the watchdog interrupt has been enabled, all subsequent writes to the control register are
ignored. The only mechanism that can re-enable writes is a hardware reset.
Watchdog Control (WDTCTL)
Base 0x4000.0000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
RESEN
INTEN
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:2
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
RESEN
R/W
0
Watchdog Reset Enable
The RESEN values are defined as follows:
Value Description
0
INTEN
R/W
0
0
Disabled.
1
Enable the Watchdog module reset output.
Watchdog Interrupt Enable
The INTEN values are defined as follows:
Value Description
0
Interrupt event disabled (once this bit is set, it can only be
cleared by a hardware reset).
1
Interrupt event enabled. Once enabled, all writes are ignored.
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Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C
This register is the interrupt clear register. A write of any value to this register clears the Watchdog
interrupt and reloads the 32-bit counter from the WDTLOAD register. Value for a read or reset is
indeterminate.
Watchdog Interrupt Clear (WDTICR)
Base 0x4000.0000
Offset 0x00C
Type WO, reset 31
30
29
28
27
26
25
24
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
15
14
13
12
11
10
9
8
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
23
22
21
20
19
18
17
16
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
7
6
5
4
3
2
1
0
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WDTIntClr
Type
Reset
WDTIntClr
Type
Reset
Bit/Field
Name
Type
Reset
31:0
WDTIntClr
WO
-
WO
-
Description
Watchdog Interrupt Clear
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Watchdog Timer
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010
This register is the raw interrupt status register. Watchdog interrupt events can be monitored via
this register if the controller interrupt is masked.
Watchdog Raw Interrupt Status (WDTRIS)
Base 0x4000.0000
Offset 0x010
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
WDTRIS
RO
0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
WDTRIS
RO
0
Watchdog Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of WDTINTR.
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Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014
This register is the masked interrupt status register. The value of this register is the logical AND of
the raw interrupt bit and the Watchdog interrupt enable bit.
Watchdog Masked Interrupt Status (WDTMIS)
Base 0x4000.0000
Offset 0x014
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
WDTMIS
RO
0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
WDTMIS
RO
0
Watchdog Masked Interrupt Status
Gives the masked interrupt state (after masking) of the WDTINTR
interrupt.
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Watchdog Timer
Register 7: Watchdog Test (WDTTEST), offset 0x418
This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag
during debug.
Watchdog Test (WDTTEST)
Base 0x4000.0000
Offset 0x418
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
STALL
R/W
0
reserved
Bit/Field
Name
Type
Reset
Description
31:9
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8
STALL
R/W
0
Watchdog Stall Enable
®
When set to 1, if the Stellaris microcontroller is stopped with a
debugger, the watchdog timer stops counting. Once the microcontroller
is restarted, the watchdog timer resumes counting.
7:0
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 8: Watchdog Lock (WDTLOCK), offset 0xC00
Writing 0x1ACC.E551 to the WDTLOCK register enables write access to all other registers. Writing
any other value to the WDTLOCK register re-enables the locked state for register writes to all the
other registers. Reading the WDTLOCK register returns the lock status rather than the 32-bit value
written. Therefore, when write accesses are disabled, reading the WDTLOCK register returns
0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)).
Watchdog Lock (WDTLOCK)
Base 0x4000.0000
Offset 0xC00
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
WDTLock
Type
Reset
WDTLock
Type
Reset
Bit/Field
Name
Type
Reset
31:0
WDTLock
R/W
0x0000
R/W
0
Description
Watchdog Lock
A write of the value 0x1ACC.E551 unlocks the watchdog registers for
write access. A write of any other value reapplies the lock, preventing
any register updates.
A read of this register returns the following values:
Value
Description
0x0000.0001 Locked
0x0000.0000 Unlocked
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Watchdog Timer
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 4 (WDTPeriphID4)
Base 0x4000.0000
Offset 0xFD0
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID4
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID4
RO
0x00
WDT Peripheral ID Register[7:0]
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Stellaris® LM3S8530 Microcontroller
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset
0xFD4
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 5 (WDTPeriphID5)
Base 0x4000.0000
Offset 0xFD4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID5
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID5
RO
0x00
WDT Peripheral ID Register[15:8]
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Watchdog Timer
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset
0xFD8
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 6 (WDTPeriphID6)
Base 0x4000.0000
Offset 0xFD8
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID6
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID6
RO
0x00
WDT Peripheral ID Register[23:16]
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Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset
0xFDC
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 7 (WDTPeriphID7)
Base 0x4000.0000
Offset 0xFDC
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID7
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID7
RO
0x00
WDT Peripheral ID Register[31:24]
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Watchdog Timer
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset
0xFE0
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 0 (WDTPeriphID0)
Base 0x4000.0000
Offset 0xFE0
Type RO, reset 0x0000.0005
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
1
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID0
RO
0x05
Watchdog Peripheral ID Register[7:0]
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Stellaris® LM3S8530 Microcontroller
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset
0xFE4
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 1 (WDTPeriphID1)
Base 0x4000.0000
Offset 0xFE4
Type RO, reset 0x0000.0018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
1
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID1
RO
0x18
Watchdog Peripheral ID Register[15:8]
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Watchdog Timer
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset
0xFE8
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 2 (WDTPeriphID2)
Base 0x4000.0000
Offset 0xFE8
Type RO, reset 0x0000.0018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
1
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID2
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID2
RO
0x18
Watchdog Peripheral ID Register[23:16]
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Stellaris® LM3S8530 Microcontroller
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset
0xFEC
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 3 (WDTPeriphID3)
Base 0x4000.0000
Offset 0xFEC
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID3
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID3
RO
0x01
Watchdog Peripheral ID Register[31:24]
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Watchdog Timer
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 0 (WDTPCellID0)
Base 0x4000.0000
Offset 0xFF0
Type RO, reset 0x0000.000D
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
CID0
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID0
RO
0x0D
Watchdog PrimeCell ID Register[7:0]
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Stellaris® LM3S8530 Microcontroller
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 1 (WDTPCellID1)
Base 0x4000.0000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
1
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
CID1
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID1
RO
0xF0
Watchdog PrimeCell ID Register[15:8]
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Watchdog Timer
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 2 (WDTPCellID2)
Base 0x4000.0000
Offset 0xFF8
Type RO, reset 0x0000.0005
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
CID2
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID2
RO
0x05
Watchdog PrimeCell ID Register[23:16]
248
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Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 3 (WDTPCellID3)
Base 0x4000.0000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
CID3
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID3
RO
0xB1
Watchdog PrimeCell ID Register[31:24]
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Universal Asynchronous Receivers/Transmitters (UARTs)
11
Universal Asynchronous Receivers/Transmitters
(UARTs)
®
The Stellaris Universal Asynchronous Receiver/Transmitter (UART) has the following features:
■ Fully programmable 16C550-type UART with IrDA support
■ Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
■ Programmable baud-rate generator allowing speeds up to 3.125 Mbps
■ Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
■ Standard asynchronous communication bits for start, stop, and parity
■ False-start bit detection
■ Line-break generation and detection
■ Fully programmable serial interface characteristics
– 5, 6, 7, or 8 data bits
– Even, odd, stick, or no-parity bit generation/detection
– 1 or 2 stop bit generation
■ IrDA serial-IR (SIR) encoder/decoder providing
– Programmable use of IrDA Serial Infrared (SIR) or UART input/output
– Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
– Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
– Programmable internal clock generator enabling division of reference clock by 1 to 256 for
low-power mode bit duration
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Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
11.1
Block Diagram
Figure 11-1. UART Module Block Diagram
System Clock
Interrupt
Interrupt Control
UARTIFLS
UARTIM
UARTMIS
UARTRIS
UARTICR
Identification
Registers
UARTPCellID0
UARTPCellID1
UARTPCellID2
UARTPCellID3
UARTPeriphID0
UARTPeriphID1
UARTPeriphID2
UARTPeriphID3
UARTPeriphID4
UARTPeriphID5
UARTPeriphID6
UARTPeriphID7
11.2
TxFIFO
16 x 8
.
.
.
Baud Rate
Generator
UARTDR
Transmitter
(with SIR
Transmit
Encoder)
UnTx
UARTIBRD
UARTFBRD
Control/Status
RxFIFO
16 x 8
UARTRSR/ECR
UARTFR
UARTLCRH
UARTCTL
UARTILPR
.
.
.
Receiver
(with SIR
Receive
Decoder)
UnRx
Functional Description
®
Each Stellaris UART performs the functions of parallel-to-serial and serial-to-parallel conversions.
It is similar in functionality to a 16C550 UART, but is not register compatible.
The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control
(UARTCTL) register (see page 269). Transmit and receive are both enabled out of reset. Before any
control registers are programmed, the UART must be disabled by clearing the UARTEN bit in
UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed
prior to the UART stopping.
The UART peripheral also includes a serial IR (SIR) encoder/decoder block that can be connected
to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed
using the UARTCTL register.
11.2.1
Transmit/Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO.
The control logic outputs the serial bit stream beginning with a start bit, and followed by the data
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Universal Asynchronous Receivers/Transmitters (UARTs)
bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control
registers. See Figure 11-2 on page 252 for details.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start
pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also
performed, and their status accompanies the data that is written to the receive FIFO.
Figure 11-2. UART Character Frame
UnTX
LSB
1
5-8 data bits
0
n
Parity bit
if enabled
Start
11.2.2
1-2
stop bits
MSB
Baud-Rate Generation
The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part.
The number formed by these two values is used by the baud-rate generator to determine the bit
period. Having a fractional baud-rate divider allows the UART to generate all the standard baud
rates.
The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register
(see page 265) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor
(UARTFBRD) register (see page 266). The baud-rate divisor (BRD) has the following relationship
to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part,
separated by a decimal place.)
BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate)
where UARTSysClk is the system clock connected to the UART.
The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register)
can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and
adding 0.5 to account for rounding errors:
UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred to as
Baud16). This reference clock is divided by 16 to generate the transmit clock, and is used for error
detection during receive operations.
Along with the UART Line Control, High Byte (UARTLCRH) register (see page 267), the UARTIBRD
and UARTFBRD registers form an internal 30-bit register. This internal register is only updated
when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must
be followed by a write to the UARTLCRH register for the changes to take effect.
To update the baud-rate registers, there are four possible sequences:
■ UARTIBRD write, UARTFBRD write, and UARTLCRH write
■ UARTFBRD write, UARTIBRD write, and UARTLCRH write
■ UARTIBRD write and UARTLCRH write
■ UARTFBRD write and UARTLCRH write
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Stellaris® LM3S8530 Microcontroller
11.2.3
Data Transmission
Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra
four bits per character for status information. For transmission, data is written into the transmit FIFO.
If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated
in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit
FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 262) is asserted as soon as
data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while
data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the
last character has been transmitted from the shift register, including the stop bits. The UART can
indicate that it is busy even though the UART may no longer be enabled.
When the receiver is idle (the UnRx is continuously 1) and the data input goes Low (a start bit has
been received), the receive counter begins running and data is sampled on the eighth cycle of
Baud16 (described in “Transmit/Receive Logic” on page 251).
The start bit is valid if UnRx is still low on the eighth cycle of Baud16, otherwise a false start bit is
detected and it is ignored. Start bit errors can be viewed in the UART Receive Status (UARTRSR)
register (see page 260). If the start bit was valid, successive data bits are sampled on every 16th
cycle of Baud16 (that is, one bit period later) according to the programmed length of the data
characters. The parity bit is then checked if parity mode was enabled. Data length and parity are
defined in the UARTLCRH register.
Lastly, a valid stop bit is confirmed if UnRx is High, otherwise a framing error has occurred. When
a full word is received, the data is stored in the receive FIFO, with any error bits associated with
that word.
11.2.4
Serial IR (SIR)
The UART peripheral includes an IrDA serial-IR (SIR) encoder/decoder block. The IrDA SIR block
provides functionality that converts between an asynchronous UART data stream, and half-duplex
serial SIR interface. No analog processing is performed on-chip. The role of the SIR block is to
provide a digital encoded output and decoded input to the UART. The UART signal pins can be
connected to an infrared transceiver to implement an IrDA SIR physical layer link. The SIR block
has two modes of operation:
■ In normal IrDA mode, a zero logic level is transmitted as high pulse of 3/16th duration of the
selected baud rate bit period on the output pin, while logic one levels are transmitted as a static
LOW signal. These levels control the driver of an infrared transmitter, sending a pulse of light
for each zero. On the reception side, the incoming light pulses energize the photo transistor base
of the receiver, pulling its output LOW. This drives the UART input pin LOW.
■ In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the
period of the internally generated IrLPBaud16 signal (1.63 µs, assuming a nominal 1.8432 MHz
frequency) by changing the appropriate bit in the UARTCR register. See page 264 for more
information on IrDA low-power pulse-duration configuration.
Figure 11-3 on page 254 shows the UART transmit and receive signals, with and without IrDA
modulation.
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Figure 11-3. IrDA Data Modulation
Data bits
Start
bit
UnTx
1
0
0
0
1
Stop
bit
0
0
1
1
1
UnTx with IrDA
3
16 Bit period
Bit period
UnRx with IrDA
UnRx
0
1
0
Start
1
0
0
1
1
Data bits
0
1
Stop
In both normal and low-power IrDA modes:
■ During transmission, the UART data bit is used as the base for encoding
■ During reception, the decoded bits are transferred to the UART receive logic
The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10 ms delay
between transmission and reception. This delay must be generated by software because it is not
automatically supported by the UART. The delay is required because the infrared receiver electronics
might become biased, or even saturated from the optical power coupled from the adjacent transmitter
LED. This delay is known as latency, or receiver setup time.
If the application does not require the use of the UnRx signal, the GPIO pin that has the UnRx signal
as an alternate function must be configured as the UnRx signal and pulled High.
11.2.5
FIFO Operation
The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed
via the UART Data (UARTDR) register (see page 258). Read operations of the UARTDR register
return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data
in the transmit FIFO.
Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are
enabled by setting the FEN bit in UARTLCRH (page 267).
FIFO status can be monitored via the UART Flag (UARTFR) register (see page 262) and the UART
Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The
UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits) and the
UARTRSR register shows overrun status via the OE bit.
The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO
Level Select (UARTIFLS) register (see page 271). Both FIFOs can be individually configured to
trigger interrupts at different levels. Available configurations include 1/8, ¼, ½, ¾, and 7/8. For
example, if the ¼ option is selected for the receive FIFO, the UART generates a receive interrupt
after 4 data bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the
½ mark.
11.2.6
Interrupts
The UART can generate interrupts when the following conditions are observed:
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■ Overrun Error
■ Break Error
■ Parity Error
■ Framing Error
■ Receive Timeout
■ Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met)
■ Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met)
All of the interrupt events are ORed together before being sent to the interrupt controller, so the
UART can only generate a single interrupt request to the controller at any given time. Software can
service multiple interrupt events in a single interrupt service routine by reading the UART Masked
Interrupt Status (UARTMIS) register (see page 276).
The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt
Mask (UARTIM ) register (see page 273) by setting the corresponding IM bit to 1. If interrupts are
not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS)
register (see page 275).
Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by setting the
corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 277).
The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data
is received over a 32-bit period. The receive timeout interrupt is cleared either when the FIFO
becomes empty through reading all the data (or by reading the holding register), or when a 1 is
written to the corresponding bit in the UARTICR register.
11.2.7
Loopback Operation
The UART can be placed into an internal loopback mode for diagnostic or debug work. This is
accomplished by setting the LBE bit in the UARTCTL register (see page 269). In loopback mode,
data transmitted on UnTx is received on the UnRx input.
11.2.8
IrDA SIR block
The IrDA SIR block contains an IrDA serial IR (SIR) protocol encoder/decoder. When enabled, the
SIR block uses the UnTx and UnRx pins for the SIR protocol, which should be connected to an IR
transceiver.
The SIR block can receive and transmit, but it is only half-duplex so it cannot do both at the same
time. Transmission must be stopped before data can be received. The IrDA SIR physical layer
specifies a minimum 10-ms delay between transmission and reception.
11.3
Initialization and Configuration
To use the UART, the peripheral clock must be enabled by setting the UART0 bit in the RCGC1
register.
This section discusses the steps that are required to use a UART module. For this example, the
UART clock is assumed to be 20 MHz and the desired UART configuration is:
■ 115200 baud rate
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■ Data length of 8 bits
■ One stop bit
■ No parity
■ FIFOs disabled
■ No interrupts
The first thing to consider when programming the UART is the baud-rate divisor (BRD), since the
UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using the
equation described in “Baud-Rate Generation” on page 252, the BRD can be calculated:
BRD = 20,000,000 / (16 * 115,200) = 10.8507
which means that the DIVINT field of the UARTIBRD register (see page 265) should be set to 10.
The value to be loaded into the UARTFBRD register (see page 266) is calculated by the equation:
UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54
With the BRD values in hand, the UART configuration is written to the module in the following order:
1. Disable the UART by clearing the UARTEN bit in the UARTCTL register.
2. Write the integer portion of the BRD to the UARTIBRD register.
3. Write the fractional portion of the BRD to the UARTFBRD register.
4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of
0x0000.0060).
5. Enable the UART by setting the UARTEN bit in the UARTCTL register.
11.4
Register Map
Table 11-1 on page 256 lists the UART registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that UART’s base address:
■ UART0: 0x4000.C000
Note:
The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 269)
before any of the control registers are reprogrammed. When the UART is disabled during
a TX or RX operation, the current transaction is completed prior to the UART stopping.
Table 11-1. UART Register Map
Offset
Name
Type
Reset
Description
See
page
0x000
UARTDR
R/W
0x0000.0000
UART Data
258
0x004
UARTRSR/UARTECR
R/W
0x0000.0000
UART Receive Status/Error Clear
260
0x018
UARTFR
RO
0x0000.0090
UART Flag
262
0x020
UARTILPR
R/W
0x0000.0000
UART IrDA Low-Power Register
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Table 11-1. UART Register Map (continued)
Name
Type
Reset
0x024
UARTIBRD
R/W
0x0000.0000
UART Integer Baud-Rate Divisor
265
0x028
UARTFBRD
R/W
0x0000.0000
UART Fractional Baud-Rate Divisor
266
0x02C
UARTLCRH
R/W
0x0000.0000
UART Line Control
267
0x030
UARTCTL
R/W
0x0000.0300
UART Control
269
0x034
UARTIFLS
R/W
0x0000.0012
UART Interrupt FIFO Level Select
271
0x038
UARTIM
R/W
0x0000.0000
UART Interrupt Mask
273
0x03C
UARTRIS
RO
0x0000.000F
UART Raw Interrupt Status
275
0x040
UARTMIS
RO
0x0000.0000
UART Masked Interrupt Status
276
0x044
UARTICR
W1C
0x0000.0000
UART Interrupt Clear
277
0xFD0
UARTPeriphID4
RO
0x0000.0000
UART Peripheral Identification 4
279
0xFD4
UARTPeriphID5
RO
0x0000.0000
UART Peripheral Identification 5
280
0xFD8
UARTPeriphID6
RO
0x0000.0000
UART Peripheral Identification 6
281
0xFDC
UARTPeriphID7
RO
0x0000.0000
UART Peripheral Identification 7
282
0xFE0
UARTPeriphID0
RO
0x0000.0011
UART Peripheral Identification 0
283
0xFE4
UARTPeriphID1
RO
0x0000.0000
UART Peripheral Identification 1
284
0xFE8
UARTPeriphID2
RO
0x0000.0018
UART Peripheral Identification 2
285
0xFEC
UARTPeriphID3
RO
0x0000.0001
UART Peripheral Identification 3
286
0xFF0
UARTPCellID0
RO
0x0000.000D
UART PrimeCell Identification 0
287
0xFF4
UARTPCellID1
RO
0x0000.00F0
UART PrimeCell Identification 1
288
0xFF8
UARTPCellID2
RO
0x0000.0005
UART PrimeCell Identification 2
289
0xFFC
UARTPCellID3
RO
0x0000.00B1
UART PrimeCell Identification 3
290
11.5
Description
See
page
Offset
Register Descriptions
The remainder of this section lists and describes the UART registers, in numerical order by address
offset.
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Register 1: UART Data (UARTDR), offset 0x000
Important: Use caution when reading this register. Performing a read may change bit status.
This register is the data register (the interface to the FIFOs).
When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs
are disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO).
A write to this register initiates a transmission from the UART.
For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity,
and overrun) is pushed onto the 12-bit wide receive FIFO. If FIFOs are disabled, the data byte and
status are stored in the receiving holding register (the bottom word of the receive FIFO). The received
data can be retrieved by reading this register.
UART Data (UARTDR)
UART0 base: 0x4000.C000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
OE
BE
PE
FE
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
DATA
Bit/Field
Name
Type
Reset
Description
31:12
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11
OE
RO
0
UART Overrun Error
The OE values are defined as follows:
Value Description
10
BE
RO
0
0
There has been no data loss due to a FIFO overrun.
1
New data was received when the FIFO was full, resulting in
data loss.
UART Break Error
This bit is set to 1 when a break condition is detected, indicating that
the receive data input was held Low for longer than a full-word
transmission time (defined as start, data, parity, and stop bits).
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the received data input
goes to a 1 (marking state) and the next valid start bit is received.
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Bit/Field
Name
Type
Reset
9
PE
RO
0
Description
UART Parity Error
This bit is set to 1 when the parity of the received data character does
not match the parity defined by bits 2 and 7 of the UARTLCRH register.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
8
FE
RO
0
UART Framing Error
This bit is set to 1 when the received character does not have a valid
stop bit (a valid stop bit is 1).
7:0
DATA
R/W
0
Data Transmitted or Received
When written, the data that is to be transmitted via the UART. When
read, the data that was received by the UART.
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Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset
0x004
The UARTRSR/UARTECR register is the receive status register/error clear register.
In addition to the UARTDR register, receive status can also be read from the UARTRSR register.
If the status is read from this register, then the status information corresponds to the entry read from
UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when
an overrun condition occurs.
The UARTRSR register cannot be written.
A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors.
All the bits are cleared to 0 on reset.
Reads
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
Offset 0x004
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
0
OE
BE
PE
FE
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
OE
RO
0
UART Overrun Error
When this bit is set to 1, data is received and the FIFO is already full.
This bit is cleared to 0 by a write to UARTECR.
The FIFO contents remain valid since no further data is written when
the FIFO is full, only the contents of the shift register are overwritten.
The CPU must now read the data in order to empty the FIFO.
2
BE
RO
0
UART Break Error
This bit is set to 1 when a break condition is detected, indicating that
the received data input was held Low for longer than a full-word
transmission time (defined as start, data, parity, and stop bits).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the receive data input
goes to a 1 (marking state) and the next valid start bit is received.
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Bit/Field
Name
Type
Reset
1
PE
RO
0
Description
UART Parity Error
This bit is set to 1 when the parity of the received data character does
not match the parity defined by bits 2 and 7 of the UARTLCRH register.
This bit is cleared to 0 by a write to UARTECR.
0
FE
RO
0
UART Framing Error
This bit is set to 1 when the received character does not have a valid
stop bit (a valid stop bit is 1).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
Writes
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
Offset 0x004
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
15
14
13
12
11
10
9
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
23
22
21
20
19
18
17
16
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
8
7
6
5
4
3
2
1
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
reserved
Type
Reset
reserved
Type
Reset
DATA
WO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
WO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
DATA
WO
0
Error Clear
A write to this register of any data clears the framing, parity, break, and
overrun flags.
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Register 3: UART Flag (UARTFR), offset 0x018
The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and
TXFE and RXFE bits are 1.
UART Flag (UARTFR)
UART0 base: 0x4000.C000
Offset 0x018
Type RO, reset 0x0000.0090
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
TXFE
RXFF
TXFF
RXFE
BUSY
RO
1
RO
0
RO
0
RO
1
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
TXFE
RO
1
UART Transmit FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled (FEN is 0), this bit is set when the transmit holding
register is empty.
If the FIFO is enabled (FEN is 1), this bit is set when the transmit FIFO
is empty.
6
RXFF
RO
0
UART Receive FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding register
is full.
If the FIFO is enabled, this bit is set when the receive FIFO is full.
5
TXFF
RO
0
UART Transmit FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the transmit holding register
is full.
If the FIFO is enabled, this bit is set when the transmit FIFO is full.
4
RXFE
RO
1
UART Receive FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding register
is empty.
If the FIFO is enabled, this bit is set when the receive FIFO is empty.
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Bit/Field
Name
Type
Reset
Description
3
BUSY
RO
0
UART Busy
When this bit is 1, the UART is busy transmitting data. This bit remains
set until the complete byte, including all stop bits, has been sent from
the shift register.
This bit is set as soon as the transmit FIFO becomes non-empty
(regardless of whether UART is enabled).
2:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020
The UARTILPR register is an 8-bit read/write register that stores the low-power counter divisor
value used to derive the low-power SIR pulse width clock by dividing down the system clock (SysClk).
All the bits are cleared to 0 when reset.
The internal IrLPBaud16 clock is generated by dividing down SysClk according to the low-power
divisor value written to UARTILPR. The duration of SIR pulses generated when low-power mode
is enabled is three times the period of the IrLPBaud16 clock. The low-power divisor value is
calculated as follows:
ILPDVSR = SysClk / FIrLPBaud16
where FIrLPBaud16 is nominally 1.8432 MHz.
You must choose the divisor so that 1.42 MHz < FIrLPBaud16 < 2.12 MHz, which results in a low-power
pulse duration of 1.41–2.11 μs (three times the period of IrLPBaud16). The minimum frequency
of IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but that
pulses greater than 1.4 μs are accepted as valid pulses.
Note:
Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being
generated.
UART IrDA Low-Power Register (UARTILPR)
UART0 base: 0x4000.C000
Offset 0x020
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
ILPDVSR
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0
7:0
ILPDVSR
R/W
0x00
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
IrDA Low-Power Divisor
This is an 8-bit low-power divisor value.
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Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024
The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared
on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD
register is ignored. When changing the UARTIBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 252
for configuration details.
UART Integer Baud-Rate Divisor (UARTIBRD)
UART0 base: 0x4000.C000
Offset 0x024
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
DIVINT
Type
Reset
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0
15:0
DIVINT
R/W
0x0000
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Integer Baud-Rate Divisor
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Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028
The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared
on reset. When changing the UARTFBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 252
for configuration details.
UART Fractional Baud-Rate Divisor (UARTFBRD)
UART0 base: 0x4000.C000
Offset 0x028
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
DIVFRAC
R/W
0
Bit/Field
Name
Type
Reset
Description
31:6
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:0
DIVFRAC
R/W
0x000
Fractional Baud-Rate Divisor
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Register 7: UART Line Control (UARTLCRH), offset 0x02C
The UARTLCRH register is the line control register. Serial parameters such as data length, parity,
and stop bit selection are implemented in this register.
When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register
must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH
register.
UART Line Control (UARTLCRH)
UART0 base: 0x4000.C000
Offset 0x02C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
SPS
RO
0
RO
0
RO
0
RO
0
R/W
0
5
WLEN
R/W
0
R/W
0
4
3
2
1
0
FEN
STP2
EPS
PEN
BRK
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
SPS
R/W
0
UART Stick Parity Select
When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted
and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the
parity bit is transmitted and checked as a 1.
When this bit is cleared, stick parity is disabled.
6:5
WLEN
R/W
0
UART Word Length
The bits indicate the number of data bits transmitted or received in a
frame as follows:
Value Description
0x3 8 bits
0x2 7 bits
0x1 6 bits
0x0 5 bits (default)
4
FEN
R/W
0
UART Enable FIFOs
If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO
mode).
When cleared to 0, FIFOs are disabled (Character mode). The FIFOs
become 1-byte-deep holding registers.
3
STP2
R/W
0
UART Two Stop Bits Select
If this bit is set to 1, two stop bits are transmitted at the end of a frame.
The receive logic does not check for two stop bits being received.
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Bit/Field
Name
Type
Reset
2
EPS
R/W
0
Description
UART Even Parity Select
If this bit is set to 1, even parity generation and checking is performed
during transmission and reception, which checks for an even number
of 1s in data and parity bits.
When cleared to 0, then odd parity is performed, which checks for an
odd number of 1s.
This bit has no effect when parity is disabled by the PEN bit.
1
PEN
R/W
0
UART Parity Enable
If this bit is set to 1, parity checking and generation is enabled; otherwise,
parity is disabled and no parity bit is added to the data frame.
0
BRK
R/W
0
UART Send Break
If this bit is set to 1, a Low level is continually output on the UnTX output,
after completing transmission of the current character. For the proper
execution of the break command, the software must set this bit for at
least two frames (character periods). For normal use, this bit must be
cleared to 0.
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Register 8: UART Control (UARTCTL), offset 0x030
The UARTCTL register is the control register. All the bits are cleared on reset except for the
Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1.
To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration
change in the module, the UARTEN bit must be cleared before the configuration changes are written.
If the UART is disabled during a transmit or receive operation, the current transaction is completed
prior to the UART stopping.
Note:
The UARTCTL register should not be changed while the UART is enabled or else the results
are unpredictable. The following sequence is recommended for making changes to the
UARTCTL register.
1. Disable the UART.
2. Wait for the end of transmission or reception of the current character.
3. Flush the transmit FIFO by disabling bit 4 (FEN) in the line control register (UARTLCRH).
4. Reprogram the control register.
5. Enable the UART.
UART Control (UARTCTL)
UART0 base: 0x4000.C000
Offset 0x030
Type R/W, reset 0x0000.0300
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RXE
TXE
LBE
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
1
R/W
1
R/W
0
SIRLP
SIREN
UARTEN
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
reserved
Bit/Field
Name
Type
Reset
Description
31:10
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
9
RXE
R/W
1
UART Receive Enable
If this bit is set to 1, the receive section of the UART is enabled. When
the UART is disabled in the middle of a receive, it completes the current
character before stopping.
Note:
8
TXE
R/W
1
To enable reception, the UARTEN bit must also be set.
UART Transmit Enable
If this bit is set to 1, the transmit section of the UART is enabled. When
the UART is disabled in the middle of a transmission, it completes the
current character before stopping.
Note:
To enable transmission, the UARTEN bit must also be set.
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Bit/Field
Name
Type
Reset
7
LBE
R/W
0
Description
UART Loop Back Enable
If this bit is set to 1, the UnTX path is fed through the UnRX path.
6:3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
SIRLP
R/W
0
UART SIR Low Power Mode
This bit selects the IrDA encoding mode. If this bit is cleared to 0,
low-level bits are transmitted as an active High pulse with a width of
3/16th of the bit period. If this bit is set to 1, low-level bits are transmitted
with a pulse width which is 3 times the period of the IrLPBaud16 input
signal, regardless of the selected bit rate. Setting this bit uses less power,
but might reduce transmission distances. See page 264 for more
information.
1
SIREN
R/W
0
UART SIR Enable
If this bit is set to 1, the IrDA SIR block is enabled, and the UART will
transmit and receive data using SIR protocol.
0
UARTEN
R/W
0
UART Enable
If this bit is set to 1, the UART is enabled. When the UART is disabled
in the middle of transmission or reception, it completes the current
character before stopping.
270
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Stellaris® LM3S8530 Microcontroller
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034
The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define
the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered.
The interrupts are generated based on a transition through a level rather than being based on the
level. That is, the interrupts are generated when the fill level progresses through the trigger level.
For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the
module is receiving the 9th character.
Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt
at the half-way mark.
UART Interrupt FIFO Level Select (UARTIFLS)
UART0 base: 0x4000.C000
Offset 0x034
Type R/W, reset 0x0000.0012
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RXIFLSEL
R/W
1
TXIFLSEL
R/W
1
R/W
0
Bit/Field
Name
Type
Reset
Description
31:6
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:3
RXIFLSEL
R/W
0x2
UART Receive Interrupt FIFO Level Select
The trigger points for the receive interrupt are as follows:
Value
Description
0x0
RX FIFO ≥ 1/8 full
0x1
RX FIFO ≥ ¼ full
0x2
RX FIFO ≥ ½ full (default)
0x3
RX FIFO ≥ ¾ full
0x4
RX FIFO ≥ 7/8 full
0x5-0x7 Reserved
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Bit/Field
Name
Type
Reset
2:0
TXIFLSEL
R/W
0x2
Description
UART Transmit Interrupt FIFO Level Select
The trigger points for the transmit interrupt are as follows:
Value
Description
0x0
TX FIFO ≤ 1/8 full
0x1
TX FIFO ≤ ¼ full
0x2
TX FIFO ≤ ½ full (default)
0x3
TX FIFO ≤ ¾ full
0x4
TX FIFO ≤ 7/8 full
0x5-0x7 Reserved
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Register 10: UART Interrupt Mask (UARTIM), offset 0x038
The UARTIM register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Writing a 1 to
a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Writing a
0 prevents the raw interrupt signal from being sent to the interrupt controller.
UART Interrupt Mask (UARTIM)
UART0 base: 0x4000.C000
Offset 0x038
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
15
14
RO
0
RO
0
RO
0
13
12
11
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
10
9
8
7
6
5
4
OEIM
BEIM
PEIM
FEIM
RTIM
TXIM
RXIM
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
RO
0
reserved
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:11
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
OEIM
R/W
0
UART Overrun Error Interrupt Mask
On a read, the current mask for the OEIM interrupt is returned.
Setting this bit to 1 promotes the OEIM interrupt to the interrupt controller.
9
BEIM
R/W
0
UART Break Error Interrupt Mask
On a read, the current mask for the BEIM interrupt is returned.
Setting this bit to 1 promotes the BEIM interrupt to the interrupt controller.
8
PEIM
R/W
0
UART Parity Error Interrupt Mask
On a read, the current mask for the PEIM interrupt is returned.
Setting this bit to 1 promotes the PEIM interrupt to the interrupt controller.
7
FEIM
R/W
0
UART Framing Error Interrupt Mask
On a read, the current mask for the FEIM interrupt is returned.
Setting this bit to 1 promotes the FEIM interrupt to the interrupt controller.
6
RTIM
R/W
0
UART Receive Time-Out Interrupt Mask
On a read, the current mask for the RTIM interrupt is returned.
Setting this bit to 1 promotes the RTIM interrupt to the interrupt controller.
5
TXIM
R/W
0
UART Transmit Interrupt Mask
On a read, the current mask for the TXIM interrupt is returned.
Setting this bit to 1 promotes the TXIM interrupt to the interrupt controller.
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Bit/Field
Name
Type
Reset
4
RXIM
R/W
0
Description
UART Receive Interrupt Mask
On a read, the current mask for the RXIM interrupt is returned.
Setting this bit to 1 promotes the RXIM interrupt to the interrupt controller.
3:0
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
274
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Stellaris® LM3S8530 Microcontroller
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C
The UARTRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt. A write has no effect.
UART Raw Interrupt Status (UARTRIS)
UART0 base: 0x4000.C000
Offset 0x03C
Type RO, reset 0x0000.000F
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
OERIS
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
BERIS
PERIS
FERIS
RTRIS
TXRIS
RXRIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
1
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
reserved
Bit/Field
Name
Type
Reset
Description
31:11
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
OERIS
RO
0
UART Overrun Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
9
BERIS
RO
0
UART Break Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
8
PERIS
RO
0
UART Parity Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
7
FERIS
RO
0
UART Framing Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
6
RTRIS
RO
0
UART Receive Time-Out Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
5
TXRIS
RO
0
UART Transmit Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
4
RXRIS
RO
0
UART Receive Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
3:0
reserved
RO
0xF
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040
The UARTMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
UART Masked Interrupt Status (UARTMIS)
UART0 base: 0x4000.C000
Offset 0x040
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
OEMIS
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
BEMIS
PEMIS
FEMIS
RTMIS
TXMIS
RXMIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
reserved
Bit/Field
Name
Type
Reset
Description
31:11
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
OEMIS
RO
0
UART Overrun Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
9
BEMIS
RO
0
UART Break Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
8
PEMIS
RO
0
UART Parity Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
7
FEMIS
RO
0
UART Framing Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
6
RTMIS
RO
0
UART Receive Time-Out Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
5
TXMIS
RO
0
UART Transmit Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
4
RXMIS
RO
0
UART Receive Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
3:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
276
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Stellaris® LM3S8530 Microcontroller
Register 13: UART Interrupt Clear (UARTICR), offset 0x044
The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
UART Interrupt Clear (UARTICR)
UART0 base: 0x4000.C000
Offset 0x044
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
OEIC
RO
0
RO
0
RO
0
RO
0
W1C
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
BEIC
PEIC
FEIC
RTIC
TXIC
RXIC
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
reserved
Bit/Field
Name
Type
Reset
Description
31:11
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
10
OEIC
W1C
0
Overrun Error Interrupt Clear
The OEIC values are defined as follows:
Value Description
9
BEIC
W1C
0
0
No effect on the interrupt.
1
Clears interrupt.
Break Error Interrupt Clear
The BEIC values are defined as follows:
Value Description
8
PEIC
W1C
0
0
No effect on the interrupt.
1
Clears interrupt.
Parity Error Interrupt Clear
The PEIC values are defined as follows:
Value Description
7
FEIC
W1C
0
0
No effect on the interrupt.
1
Clears interrupt.
Framing Error Interrupt Clear
The FEIC values are defined as follows:
Value Description
0
No effect on the interrupt.
1
Clears interrupt.
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Bit/Field
Name
Type
Reset
6
RTIC
W1C
0
Description
Receive Time-Out Interrupt Clear
The RTIC values are defined as follows:
Value Description
5
TXIC
W1C
0
0
No effect on the interrupt.
1
Clears interrupt.
Transmit Interrupt Clear
The TXIC values are defined as follows:
Value Description
4
RXIC
W1C
0
0
No effect on the interrupt.
1
Clears interrupt.
Receive Interrupt Clear
The RXIC values are defined as follows:
Value Description
3:0
reserved
RO
0x00
0
No effect on the interrupt.
1
Clears interrupt.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 4 (UARTPeriphID4)
UART0 base: 0x4000.C000
Offset 0xFD0
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID4
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID4
RO
0x0000
UART Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 5 (UARTPeriphID5)
UART0 base: 0x4000.C000
Offset 0xFD4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID5
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID5
RO
0x0000
UART Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
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Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 6 (UARTPeriphID6)
UART0 base: 0x4000.C000
Offset 0xFD8
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID6
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID6
RO
0x0000
UART Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 7 (UARTPeriphID7)
UART0 base: 0x4000.C000
Offset 0xFDC
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID7
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0
7:0
PID7
RO
0x0000
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
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Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 0 (UARTPeriphID0)
UART0 base: 0x4000.C000
Offset 0xFE0
Type RO, reset 0x0000.0011
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
PID0
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID0
RO
0x11
UART Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 1 (UARTPeriphID1)
UART0 base: 0x4000.C000
Offset 0xFE4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID1
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID1
RO
0x00
UART Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
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Stellaris® LM3S8530 Microcontroller
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 2 (UARTPeriphID2)
UART0 base: 0x4000.C000
Offset 0xFE8
Type RO, reset 0x0000.0018
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID2
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID2
RO
0x18
UART Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
June 22, 2010
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 3 (UARTPeriphID3)
UART0 base: 0x4000.C000
Offset 0xFEC
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
PID3
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID3
RO
0x01
UART Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
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Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 0 (UARTPCellID0)
UART0 base: 0x4000.C000
Offset 0xFF0
Type RO, reset 0x0000.000D
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
CID0
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID0
RO
0x0D
UART PrimeCell ID Register[7:0]
Provides software a standard cross-peripheral identification system.
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 1 (UARTPCellID1)
UART0 base: 0x4000.C000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
1
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
CID1
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID1
RO
0xF0
UART PrimeCell ID Register[15:8]
Provides software a standard cross-peripheral identification system.
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Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 2 (UARTPCellID2)
UART0 base: 0x4000.C000
Offset 0xFF8
Type RO, reset 0x0000.0005
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
CID2
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID2
RO
0x05
UART PrimeCell ID Register[23:16]
Provides software a standard cross-peripheral identification system.
June 22, 2010
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 3 (UARTPCellID3)
UART0 base: 0x4000.C000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
CID3
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID3
RO
0xB1
UART PrimeCell ID Register[31:24]
Provides software a standard cross-peripheral identification system.
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12
Synchronous Serial Interface (SSI)
®
The Stellaris microcontroller includes two Synchronous Serial Interface (SSI) modules. Each SSI
is a master or slave interface for synchronous serial communication with peripheral devices that
have either Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces.
®
Each Stellaris SSI module has the following features:
■ Two SSI modules, each with the following features:
■ Master or slave operation
■ Programmable clock bit rate and prescale
■ Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
■ Programmable data frame size from 4 to 16 bits
■ Internal loopback test mode for diagnostic/debug testing
12.1
Block Diagram
Figure 12-1. SSI Module Block Diagram
Interrupt
Interrupt Control
SSIIM
SSIMIS
Control/ Status
SSICR0
SSIRIS
SSIICR
SSICR1
TxFIFO
8 x16
.
.
.
SSITx
SSISR
SSIRx
SSIDR
RxFIFO
8 x16
System Clock
SSIPCellID0
Identification
Registers
SSIPeriphID0 SSIPeriphID 4
SSIPCellID1
SSIPeriphID 1 SSIPeriphID 5
SSIPCellID2
SSIPeriphID 2 SSIPeriphID 6
SSIPCellID3
SSIPeriphID 3 SSIPeriphID7
Clock
Prescaler
Transmit /
Receive
Logic
SSIClk
SSIFss
.
.
.
SSICPSR
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Synchronous Serial Interface (SSI)
12.2
Functional Description
The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU
accesses data, control, and status information. The transmit and receive paths are buffered with
internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit
and receive modes.
12.2.1
Bit Rate Generation
The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output
clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by
peripheral devices.
The serial bit rate is derived by dividing down the input clock (FSysClk). The clock is first divided
by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
(SSICPSR) register (see page 310). The clock is further divided by a value from 1 to 256, which is
1 + SCR, where SCR is the value programmed in the SSI Control0 (SSICR0) register (see page 303).
The frequency of the output clock SSIClk is defined by:
SSIClk = FSysClk / (CPSDVSR * (1 + SCR))
Note:
For master mode, the system clock must be at least two times faster than the SSIClk. For
slave mode, the system clock must be at least 12 times faster than the SSIClk.
See “Synchronous Serial Interface (SSI)” on page 493 to view SSI timing parameters.
12.2.2
FIFO Operation
12.2.2.1
Transmit FIFO
The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The
CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 307), and data is
stored in the FIFO until it is read out by the transmission logic.
When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial
conversion and transmission to the attached slave or master, respectively, through the SSITx pin.
In slave mode, the SSI transmits data each time the master initiates a transaction. If the transmit
FIFO is empty and the master initiates, the slave transmits the 8th most recent value in the transmit
FIFO. If less than 8 values have been written to the transmit FIFO since the SSI module clock was
enabled using the SSI bit in the RGCG1 register, then 0 is transmitted. Care should be taken to
ensure that valid data is in the FIFO as needed. The SSI can be configured to generate an interrupt
or a µDMA request when the FIFO is empty.
12.2.2.2
Receive FIFO
The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer.
Received data from the serial interface is stored in the buffer until read out by the CPU, which
accesses the read FIFO by reading the SSIDR register.
When configured as a master or slave, serial data received through the SSIRx pin is registered
prior to parallel loading into the attached slave or master receive FIFO, respectively.
12.2.3
Interrupts
The SSI can generate interrupts when the following conditions are observed:
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■ Transmit FIFO service
■ Receive FIFO service
■ Receive FIFO time-out
■ Receive FIFO overrun
All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI
can only generate a single interrupt request to the controller at any given time. You can mask each
of the four individual maskable interrupts by setting the appropriate bits in the SSI Interrupt Mask
(SSIIM) register (see page 311). Setting the appropriate mask bit to 1 enables the interrupt.
Provision of the individual outputs, as well as a combined interrupt output, allows use of either a
global interrupt service routine, or modular device drivers to handle interrupts. The transmit and
receive dynamic dataflow interrupts have been separated from the status interrupts so that data
can be read or written in response to the FIFO trigger levels. The status of the individual interrupt
sources can be read from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status
(SSIMIS) registers (see page 313 and page 314, respectively).
12.2.4
Frame Formats
Each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is
transmitted starting with the MSB. There are three basic frame types that can be selected:
■ Texas Instruments synchronous serial
■ Freescale SPI
■ MICROWIRE
For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk
transitions at the programmed frequency only during active transmission or reception of data. The
idle state of SSIClk is utilized to provide a receive timeout indication that occurs when the receive
FIFO still contains data after a timeout period.
For Freescale SPI and MICROWIRE frame formats, the serial frame (SSIFss ) pin is active Low,
and is asserted (pulled down) during the entire transmission of the frame.
For Texas Instruments synchronous serial frame format, the SSIFss pin is pulsed for one serial
clock period starting at its rising edge, prior to the transmission of each frame. For this frame format,
both the SSI and the off-chip slave device drive their output data on the rising edge of SSIClk, and
latch data from the other device on the falling edge.
Unlike the full-duplex transmission of the other two frame formats, the MICROWIRE format uses a
special master-slave messaging technique, which operates at half-duplex. In this mode, when a
frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, no
incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes
it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent,
responds with the requested data. The returned data can be 4 to 16 bits in length, making the total
frame length anywhere from 13 to 25 bits.
12.2.4.1
Texas Instruments Synchronous Serial Frame Format
Figure 12-2 on page 294 shows the Texas Instruments synchronous serial frame format for a single
transmitted frame.
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Figure 12-2. TI Synchronous Serial Frame Format (Single Transfer)
SSIClk
SSIFss
SSITx/SSIRx
MSB
LSB
4 to 16 bits
In this mode, SSIClk and SSIFss are forced Low, and the transmit data line SSITx is tristated
whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSIFss is
pulsed High for one SSIClk period. The value to be transmitted is also transferred from the transmit
FIFO to the serial shift register of the transmit logic. On the next rising edge of SSIClk, the MSB
of the 4 to 16-bit data frame is shifted out on the SSITx pin. Likewise, the MSB of the received data
is shifted onto the SSIRx pin by the off-chip serial slave device.
Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on
the falling edge of each SSIClk. The received data is transferred from the serial shifter to the receive
FIFO on the first rising edge of SSIClk after the LSB has been latched.
Figure 12-3 on page 294 shows the Texas Instruments synchronous serial frame format when
back-to-back frames are transmitted.
Figure 12-3. TI Synchronous Serial Frame Format (Continuous Transfer)
SSIClk
SSIFss
SSITx/SSIRx
MSB
LSB
4 to 16 bits
12.2.4.2
Freescale SPI Frame Format
The Freescale SPI interface is a four-wire interface where the SSIFss signal behaves as a slave
select. The main feature of the Freescale SPI format is that the inactive state and phase of the
SSIClk signal are programmable through the SPO and SPH bits within the SSISCR0 control register.
SPO Clock Polarity Bit
When the SPO clock polarity control bit is Low, it produces a steady state Low value on the SSIClk
pin. If the SPO bit is High, a steady state High value is placed on the SSIClk pin when data is not
being transferred.
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SPH Phase Control Bit
The SPH phase control bit selects the clock edge that captures data and allows it to change state.
It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition
before the first data capture edge. When the SPH phase control bit is Low, data is captured on the
first clock edge transition. If the SPH bit is High, data is captured on the second clock edge transition.
12.2.4.3
Freescale SPI Frame Format with SPO=0 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and
SPH=0 are shown in Figure 12-4 on page 295 and Figure 12-5 on page 295.
Figure 12-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0
SSIClk
SSIFss
SSIRx
LSB
MSB
Q
4 to 16 bits
SSITx
MSB
Note:
LSB
Q is undefined.
Figure 12-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0
SSIClk
SSIFss
SSIRx LSB
LSB
MSB
MSB
4 to16 bits
SSITx LSB
MSB
LSB
MSB
In this configuration, during idle periods:
■ SSIClk is forced Low
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. This causes slave data to be enabled onto
the SSIRx input line of the master. The master SSITx output pad is enabled.
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One half SSIClk period later, valid master data is transferred to the SSITx pin. Now that both the
master and slave data have been set, the SSIClk master clock pin goes High after one further half
SSIClk period.
The data is now captured on the rising and propagated on the falling edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word have been transferred, the
SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed
High between each data word transfer. This is because the slave select pin freezes the data in its
serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore,
the master device must raise the SSIFss pin of the slave device between each data transfer to
enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin
is returned to its idle state one SSIClk period after the last bit has been captured.
12.2.4.4
Freescale SPI Frame Format with SPO=0 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in Figure
12-6 on page 296, which covers both single and continuous transfers.
Figure 12-6. Freescale SPI Frame Format with SPO=0 and SPH=1
SSIClk
SSIFss
SSIRx
Q
Q
MSB
LSB
Q
4 to 16 bits
SSITx
LSB
MSB
Note:
Q is undefined.
In this configuration, during idle periods:
■ SSIClk is forced Low
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. The master SSITx output is enabled. After
a further one half SSIClk period, both master and slave valid data is enabled onto their respective
transmission lines. At the same time, the SSIClk is enabled with a rising edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the SSIClk signal.
In the case of a single word transfer, after all bits have been transferred, the SSIFss line is returned
to its idle High state one SSIClk period after the last bit has been captured.
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For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.
12.2.4.5
Freescale SPI Frame Format with SPO=1 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and
SPH=0 are shown in Figure 12-7 on page 297 and Figure 12-8 on page 297.
Figure 12-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0
SSIClk
SSIFss
SSIRx
MSB
LSB
Q
4 to 16 bits
SSITx
LSB
MSB
Note:
Q is undefined.
Figure 12-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0
SSIClk
SSIFss
SSITx/SSIRx
MSB
LSB
LSB
MSB
4 to 16 bits
In this configuration, during idle periods:
■ SSIClk is forced High
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low, which causes slave data to be immediately
transferred onto the SSIRx line of the master. The master SSITx output pad is enabled.
One half period later, valid master data is transferred to the SSITx line. Now that both the master
and slave data have been set, the SSIClk master clock pin becomes Low after one further half
SSIClk period. This means that data is captured on the falling edges and propagated on the rising
edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word are transferred, the SSIFss
line is returned to its idle High state one SSIClk period after the last bit has been captured.
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However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed
High between each data word transfer. This is because the slave select pin freezes the data in its
serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore,
the master device must raise the SSIFss pin of the slave device between each data transfer to
enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin
is returned to its idle state one SSIClk period after the last bit has been captured.
12.2.4.6
Freescale SPI Frame Format with SPO=1 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in Figure
12-9 on page 298, which covers both single and continuous transfers.
Figure 12-9. Freescale SPI Frame Format with SPO=1 and SPH=1
SSIClk
SSIFss
SSIRx
Q
MSB
LSB
Q
4 to 16 bits
MSB
SSITx
Note:
LSB
Q is undefined.
In this configuration, during idle periods:
■ SSIClk is forced High
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. The master SSITx output pad is enabled.
After a further one-half SSIClk period, both master and slave data are enabled onto their respective
transmission lines. At the same time, SSIClk is enabled with a falling edge transition. Data is then
captured on the rising edges and propagated on the falling edges of the SSIClk signal.
After all bits have been transferred, in the case of a single word transmission, the SSIFss line is
returned to its idle high state one SSIClk period after the last bit has been captured.
For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state, until
the final bit of the last word has been captured, and then returns to its idle state as described above.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.
12.2.4.7
MICROWIRE Frame Format
Figure 12-10 on page 299 shows the MICROWIRE frame format, again for a single frame. Figure
12-11 on page 300 shows the same format when back-to-back frames are transmitted.
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Figure 12-10. MICROWIRE Frame Format (Single Frame)
SSIClk
SSIFss
SSITx
LSB
MSB
8-bit control
0
SSIRx
MSB
LSB
4 to 16 bits
output data
MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead of
full-duplex, using a master-slave message passing technique. Each serial transmission begins with
an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this
transmission, no incoming data is received by the SSI. After the message has been sent, the off-chip
slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has
been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the
total frame length anywhere from 13 to 25 bits.
In this configuration, during idle periods:
■ SSIClk is forced Low
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSIFss
causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial
shift register of the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the
SSITx pin. SSIFss remains Low for the duration of the frame transmission. The SSIRx pin remains
tristated during this transmission.
The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of
each SSIClk. After the last bit is latched by the slave device, the control byte is decoded during a
one clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is driven
onto the SSIRx line on the falling edge of SSIClk. The SSI in turn latches each bit on the rising
edge of SSIClk. At the end of the frame, for single transfers, the SSIFss signal is pulled High one
clock period after the last bit has been latched in the receive serial shifter, which causes the data
to be transferred to the receive FIFO.
Note:
The off-chip slave device can tristate the receive line either on the falling edge of SSIClk
after the LSB has been latched by the receive shifter, or when the SSIFss pin goes High.
For continuous transfers, data transmission begins and ends in the same manner as a single transfer.
However, the SSIFss line is continuously asserted (held Low) and transmission of data occurs
back-to-back. The control byte of the next frame follows directly after the LSB of the received data
from the current frame. Each of the received values is transferred from the receive shifter on the
falling edge of SSIClk, after the LSB of the frame has been latched into the SSI.
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Figure 12-11. MICROWIRE Frame Format (Continuous Transfer)
SSIClk
SSIFss
SSITx
LSB
MSB
LSB
8-bit control
SSIRx
0
MSB
MSB
LSB
4 to 16 bits
output data
In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of
SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that
the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of SSIClk.
Figure 12-12 on page 300 illustrates these setup and hold time requirements. With respect to the
SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss
must have a setup of at least two times the period of SSIClk on which the SSI operates. With
respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one
SSIClk period.
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements
tSetup=(2*tSSIClk)
tHold=tSSIClk
SSIClk
SSIFss
SSIRx
First RX data to be
sampled by SSI slave
12.3
Initialization and Configuration
To use the SSI, its peripheral clock must be enabled by setting the SSI bit in the RCGC1 register.
For each of the frame formats, the SSI is configured using the following steps:
1. Ensure that the SSE bit in the SSICR1 register is disabled before making any configuration
changes.
2. Select whether the SSI is a master or slave:
a. For master operations, set the SSICR1 register to 0x0000.0000.
b. For slave mode (output enabled), set the SSICR1 register to 0x0000.0004.
c. For slave mode (output disabled), set the SSICR1 register to 0x0000.000C.
3. Configure the clock prescale divisor by writing the SSICPSR register.
4. Write the SSICR0 register with the following configuration:
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■ Serial clock rate (SCR)
■ Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO)
■ The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF)
■ The data size (DSS)
5. Enable the SSI by setting the SSE bit in the SSICR1 register.
As an example, assume the SSI must be configured to operate with the following parameters:
■ Master operation
■ Freescale SPI mode (SPO=1, SPH=1)
■ 1 Mbps bit rate
■ 8 data bits
Assuming the system clock is 20 MHz, the bit rate calculation would be:
FSSIClk = FSysClk / (CPSDVSR * (1 + SCR))
1x106 = 20x106 / (CPSDVSR * (1 + SCR))
In this case, if CPSDVSR=2, SCR must be 9.
The configuration sequence would be as follows:
1. Ensure that the SSE bit in the SSICR1 register is disabled.
2. Write the SSICR1 register with a value of 0x0000.0000.
3. Write the SSICPSR register with a value of 0x0000.0002.
4. Write the SSICR0 register with a value of 0x0000.09C7.
5. The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1.
12.4
Register Map
Table 12-1 on page 301 lists the SSI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that SSI module’s base address:
■ SSI0: 0x4000.8000
■ SSI1: 0x4000.9000
Note:
The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control
registers are reprogrammed.
Table 12-1. SSI Register Map
Offset
Name
Type
Reset
Description
See
page
0x000
SSICR0
R/W
0x0000.0000
SSI Control 0
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Table 12-1. SSI Register Map (continued)
Offset
Name
Type
Reset
Description
See
page
0x004
SSICR1
R/W
0x0000.0000
SSI Control 1
305
0x008
SSIDR
R/W
0x0000.0000
SSI Data
307
0x00C
SSISR
RO
0x0000.0003
SSI Status
308
0x010
SSICPSR
R/W
0x0000.0000
SSI Clock Prescale
310
0x014
SSIIM
R/W
0x0000.0000
SSI Interrupt Mask
311
0x018
SSIRIS
RO
0x0000.0008
SSI Raw Interrupt Status
313
0x01C
SSIMIS
RO
0x0000.0000
SSI Masked Interrupt Status
314
0x020
SSIICR
W1C
0x0000.0000
SSI Interrupt Clear
315
0xFD0
SSIPeriphID4
RO
0x0000.0000
SSI Peripheral Identification 4
316
0xFD4
SSIPeriphID5
RO
0x0000.0000
SSI Peripheral Identification 5
317
0xFD8
SSIPeriphID6
RO
0x0000.0000
SSI Peripheral Identification 6
318
0xFDC
SSIPeriphID7
RO
0x0000.0000
SSI Peripheral Identification 7
319
0xFE0
SSIPeriphID0
RO
0x0000.0022
SSI Peripheral Identification 0
320
0xFE4
SSIPeriphID1
RO
0x0000.0000
SSI Peripheral Identification 1
321
0xFE8
SSIPeriphID2
RO
0x0000.0018
SSI Peripheral Identification 2
322
0xFEC
SSIPeriphID3
RO
0x0000.0001
SSI Peripheral Identification 3
323
0xFF0
SSIPCellID0
RO
0x0000.000D
SSI PrimeCell Identification 0
324
0xFF4
SSIPCellID1
RO
0x0000.00F0
SSI PrimeCell Identification 1
325
0xFF8
SSIPCellID2
RO
0x0000.0005
SSI PrimeCell Identification 2
326
0xFFC
SSIPCellID3
RO
0x0000.00B1
SSI PrimeCell Identification 3
327
12.5
Register Descriptions
The remainder of this section lists and describes the SSI registers, in numerical order by address
offset.
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Register 1: SSI Control 0 (SSICR0), offset 0x000
SSICR0 is control register 0 and contains bit fields that control various functions within the SSI
module. Functionality such as protocol mode, clock rate, and data size are configured in this register.
SSI Control 0 (SSICR0)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
SPH
SPO
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
SCR
Type
Reset
FRF
R/W
0
DSS
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:8
SCR
R/W
0x0000
SSI Serial Clock Rate
The value SCR is used to generate the transmit and receive bit rate of
the SSI. The bit rate is:
BR=FSSIClk/(CPSDVSR * (1 + SCR))
where CPSDVSR is an even value from 2-254 programmed in the
SSICPSR register, and SCR is a value from 0-255.
7
SPH
R/W
0
SSI Serial Clock Phase
This bit is only applicable to the Freescale SPI Format.
The SPH control bit selects the clock edge that captures data and allows
it to change state. It has the most impact on the first bit transmitted by
either allowing or not allowing a clock transition before the first data
capture edge.
When the SPH bit is 0, data is captured on the first clock edge transition.
If SPH is 1, data is captured on the second clock edge transition.
6
SPO
R/W
0
SSI Serial Clock Polarity
This bit is only applicable to the Freescale SPI Format.
When the SPO bit is 0, it produces a steady state Low value on the
SSIClk pin. If SPO is 1, a steady state High value is placed on the
SSIClk pin when data is not being transferred.
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Bit/Field
Name
Type
Reset
5:4
FRF
R/W
0x0
Description
SSI Frame Format Select
The FRF values are defined as follows:
Value Frame Format
0x0 Freescale SPI Frame Format
0x1 Texas Instruments Synchronous Serial Frame Format
0x2 MICROWIRE Frame Format
0x3 Reserved
3:0
DSS
R/W
0x00
SSI Data Size Select
The DSS values are defined as follows:
Value
Data Size
0x0-0x2 Reserved
0x3
4-bit data
0x4
5-bit data
0x5
6-bit data
0x6
7-bit data
0x7
8-bit data
0x8
9-bit data
0x9
10-bit data
0xA
11-bit data
0xB
12-bit data
0xC
13-bit data
0xD
14-bit data
0xE
15-bit data
0xF
16-bit data
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Register 2: SSI Control 1 (SSICR1), offset 0x004
SSICR1 is control register 1 and contains bit fields that control various functions within the SSI
module. Master and slave mode functionality is controlled by this register.
SSI Control 1 (SSICR1)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x004
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
SOD
MS
SSE
LBM
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
SOD
R/W
0
SSI Slave Mode Output Disable
This bit is relevant only in the Slave mode (MS=1). In multiple-slave
systems, it is possible for the SSI master to broadcast a message to all
slaves in the system while ensuring that only one slave drives data onto
the serial output line. In such systems, the TXD lines from multiple slaves
could be tied together. To operate in such a system, the SOD bit can be
configured so that the SSI slave does not drive the SSITx pin.
The SOD values are defined as follows:
Value Description
2
MS
R/W
0
0
SSI can drive SSITx output in Slave Output mode.
1
SSI must not drive the SSITx output in Slave mode.
SSI Master/Slave Select
This bit selects Master or Slave mode and can be modified only when
SSI is disabled (SSE=0).
The MS values are defined as follows:
Value Description
0
Device configured as a master.
1
Device configured as a slave.
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Bit/Field
Name
Type
Reset
1
SSE
R/W
0
Description
SSI Synchronous Serial Port Enable
Setting this bit enables SSI operation.
The SSE values are defined as follows:
Value Description
0
SSI operation disabled.
1
SSI operation enabled.
Note:
0
LBM
R/W
0
This bit must be set to 0 before any control registers
are reprogrammed.
SSI Loopback Mode
Setting this bit enables Loopback Test mode.
The LBM values are defined as follows:
Value Description
0
Normal serial port operation enabled.
1
Output of the transmit serial shift register is connected internally
to the input of the receive serial shift register.
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Register 3: SSI Data (SSIDR), offset 0x008
Important: Use caution when reading this register. Performing a read may change bit status.
SSIDR is the data register and is 16-bits wide. When SSIDR is read, the entry in the receive FIFO
(pointed to by the current FIFO read pointer) is accessed. As data values are removed by the SSI
receive logic from the incoming data frame, they are placed into the entry in the receive FIFO (pointed
to by the current FIFO write pointer).
When SSIDR is written to, the entry in the transmit FIFO (pointed to by the write pointer) is written
to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is
loaded into the transmit serial shifter, then serially shifted out onto the SSITx pin at the programmed
bit rate.
When a data size of less than 16 bits is selected, the user must right-justify data written to the
transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is
automatically right-justified in the receive buffer.
When the SSI is programmed for MICROWIRE frame format, the default size for transmit data is
eight bits (the most significant byte is ignored). The receive data size is controlled by the programmer.
The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in the SSICR1
register is set to zero. This allows the software to fill the transmit FIFO before enabling the SSI.
SSI Data (SSIDR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
DATA
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
DATA
R/W
0x0000
SSI Receive/Transmit Data
A read operation reads the receive FIFO. A write operation writes the
transmit FIFO.
Software must right-justify data when the SSI is programmed for a data
size that is less than 16 bits. Unused bits at the top are ignored by the
transmit logic. The receive logic automatically right-justifies the data.
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Synchronous Serial Interface (SSI)
Register 4: SSI Status (SSISR), offset 0x00C
SSISR is a status register that contains bits that indicate the FIFO fill status and the SSI busy status.
SSI Status (SSISR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x00C
Type RO, reset 0x0000.0003
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
BSY
RFF
RNE
TNF
TFE
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
R0
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
Description
31:5
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
BSY
RO
0
SSI Busy Bit
The BSY values are defined as follows:
Value Description
3
RFF
RO
0
0
SSI is idle.
1
SSI is currently transmitting and/or receiving a frame, or the
transmit FIFO is not empty.
SSI Receive FIFO Full
The RFF values are defined as follows:
Value Description
2
RNE
RO
0
0
Receive FIFO is not full.
1
Receive FIFO is full.
SSI Receive FIFO Not Empty
The RNE values are defined as follows:
Value Description
0
Receive FIFO is empty.
1
Receive FIFO is not empty.
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Bit/Field
Name
Type
Reset
1
TNF
RO
1
Description
SSI Transmit FIFO Not Full
The TNF values are defined as follows:
Value Description
0
TFE
R0
1
0
Transmit FIFO is full.
1
Transmit FIFO is not full.
SSI Transmit FIFO Empty
The TFE values are defined as follows:
Value Description
0
Transmit FIFO is not empty.
1
Transmit FIFO is empty.
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Register 5: SSI Clock Prescale (SSICPSR), offset 0x010
SSICPSR is the clock prescale register and specifies the division factor by which the system clock
must be internally divided before further use.
The value programmed into this register must be an even number between 2 and 254. The
least-significant bit of the programmed number is hard-coded to zero. If an odd number is written
to this register, data read back from this register has the least-significant bit as zero.
SSI Clock Prescale (SSICPSR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
CPSDVSR
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CPSDVSR
R/W
0x00
SSI Clock Prescale Divisor
This value must be an even number from 2 to 254, depending on the
frequency of SSIClk. The LSB always returns 0 on reads.
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Register 6: SSI Interrupt Mask (SSIIM), offset 0x014
The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits
are cleared to 0 on reset.
On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to
the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding
mask.
SSI Interrupt Mask (SSIIM)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x014
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
0
TXIM
RXIM
RTIM
RORIM
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
TXIM
R/W
0
SSI Transmit FIFO Interrupt Mask
The TXIM values are defined as follows:
Value Description
2
RXIM
R/W
0
0
TX FIFO half-full or less condition interrupt is masked.
1
TX FIFO half-full or less condition interrupt is not masked.
SSI Receive FIFO Interrupt Mask
The RXIM values are defined as follows:
Value Description
1
RTIM
R/W
0
0
RX FIFO half-full or more condition interrupt is masked.
1
RX FIFO half-full or more condition interrupt is not masked.
SSI Receive Time-Out Interrupt Mask
The RTIM values are defined as follows:
Value Description
0
RX FIFO time-out interrupt is masked.
1
RX FIFO time-out interrupt is not masked.
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Bit/Field
Name
Type
Reset
0
RORIM
R/W
0
Description
SSI Receive Overrun Interrupt Mask
The RORIM values are defined as follows:
Value Description
0
RX FIFO overrun interrupt is masked.
1
RX FIFO overrun interrupt is not masked.
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Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018
The SSIRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt prior to masking. A write has no effect.
SSI Raw Interrupt Status (SSIRIS)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x018
Type RO, reset 0x0000.0008
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
TXRIS
RXRIS
RTRIS
RORRIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
TXRIS
RO
1
SSI Transmit FIFO Raw Interrupt Status
Indicates that the transmit FIFO is half full or less, when set.
2
RXRIS
RO
0
SSI Receive FIFO Raw Interrupt Status
Indicates that the receive FIFO is half full or more, when set.
1
RTRIS
RO
0
SSI Receive Time-Out Raw Interrupt Status
Indicates that the receive time-out has occurred, when set.
0
RORRIS
RO
0
SSI Receive Overrun Raw Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
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Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C
The SSIMIS register is the masked interrupt status register. On a read, this register gives the current
masked status value of the corresponding interrupt. A write has no effect.
SSI Masked Interrupt Status (SSIMIS)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x01C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
TXMIS
RXMIS
RTMIS
RORMIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
TXMIS
RO
0
SSI Transmit FIFO Masked Interrupt Status
Indicates that the transmit FIFO is half full or less, when set.
2
RXMIS
RO
0
SSI Receive FIFO Masked Interrupt Status
Indicates that the receive FIFO is half full or more, when set.
1
RTMIS
RO
0
SSI Receive Time-Out Masked Interrupt Status
Indicates that the receive time-out has occurred, when set.
0
RORMIS
RO
0
SSI Receive Overrun Masked Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
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Register 9: SSI Interrupt Clear (SSIICR), offset 0x020
The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is
cleared. A write of 0 has no effect.
SSI Interrupt Clear (SSIICR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x020
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RTIC
RORIC
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
W1C
0
W1C
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:2
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
RTIC
W1C
0
SSI Receive Time-Out Interrupt Clear
The RTIC values are defined as follows:
Value Description
0
RORIC
W1C
0
0
No effect on interrupt.
1
Clears interrupt.
SSI Receive Overrun Interrupt Clear
The RORIC values are defined as follows:
Value Description
0
No effect on interrupt.
1
Clears interrupt.
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Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 4 (SSIPeriphID4)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFD0
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID4
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID4
RO
0x00
SSI Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
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Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 5 (SSIPeriphID5)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFD4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID5
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID5
RO
0x00
SSI Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
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Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 6 (SSIPeriphID6)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFD8
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID6
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID6
RO
0x00
SSI Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
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Stellaris® LM3S8530 Microcontroller
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 7 (SSIPeriphID7)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFDC
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID7
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID7
RO
0x00
SSI Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
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Synchronous Serial Interface (SSI)
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 0 (SSIPeriphID0)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFE0
Type RO, reset 0x0000.0022
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
1
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0
7:0
PID0
RO
0x22
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
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Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 1 (SSIPeriphID1)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFE4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID1
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID1
RO
0x00
SSI Peripheral ID Register [15:8]
Can be used by software to identify the presence of this peripheral.
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Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 2 (SSIPeriphID2)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFE8
Type RO, reset 0x0000.0018
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID2
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID2
RO
0x18
SSI Peripheral ID Register [23:16]
Can be used by software to identify the presence of this peripheral.
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Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 3 (SSIPeriphID3)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFEC
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
PID3
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
PID3
RO
0x01
SSI Peripheral ID Register [31:24]
Can be used by software to identify the presence of this peripheral.
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Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 0 (SSIPCellID0)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFF0
Type RO, reset 0x0000.000D
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
CID0
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID0
RO
0x0D
SSI PrimeCell ID Register [7:0]
Provides software a standard cross-peripheral identification system.
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Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 1 (SSIPCellID1)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
1
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
CID1
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID1
RO
0xF0
SSI PrimeCell ID Register [15:8]
Provides software a standard cross-peripheral identification system.
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Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 2 (SSIPCellID2)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFF8
Type RO, reset 0x0000.0005
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
CID2
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID2
RO
0x05
SSI PrimeCell ID Register [23:16]
Provides software a standard cross-peripheral identification system.
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Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC
The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset
value.
SSI PrimeCell Identification 3 (SSIPCellID3)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
CID3
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID3
RO
0xB1
SSI PrimeCell ID Register [31:24]
Provides software a standard cross-peripheral identification system.
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Inter-Integrated Circuit (I2C) Interface
13
Inter-Integrated Circuit (I2C) Interface
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL), and interfaces to external I2C devices such as
serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C
bus may also be used for system testing and diagnostic purposes in product development and
manufacture. The LM3S8530 microcontroller includes one I2C module, providing the ability to interact
(both send and receive) with other I2C devices on the bus.
®
The Stellaris I2C interface has the following features:
■ Devices on the I2C bus can be designated as either a master or a slave
– Supports both sending and receiving data as either a master or a slave
– Supports simultaneous master and slave operation
■ Four I2C modes
– Master transmit
– Master receive
– Slave transmit
– Slave receive
■ Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps)
■ Master and slave interrupt generation
– Master generates interrupts when a transmit or receive operation completes (or aborts due
to an error)
– Slave generates interrupts when data has been sent or requested by a master
■ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
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13.1
Block Diagram
Figure 13-1. I2C Block Diagram
I2CSCL
I2C Control
Interrupt
I2CMSA
I2CSOAR
I2CMCS
I2CSCSR
I2CMDR
I2CSDR
I2CMTPR
I2CSIM
I2CMIMR
I2CSRIS
I2CMRIS
I2CSMIS
I2CMMIS
I2CSICR
I2C Master Core
I2CSDA
I2CSCL
I2C I/O Select
I2CSDA
I2CSCL
I2C Slave Core
I2CMICR
I2CSDA
I2CMCR
13.2
Functional Description
The I2C module is comprised of both master and slave functions which are implemented as separate
peripherals. For proper operation, the SDA and SCL pins must be connected to bi-directional
open-drain pads. A typical I2C bus configuration is shown in Figure 13-2 on page 329.
See “Inter-Integrated Circuit (I2C) Interface” on page 495 for I2C timing diagrams.
Figure 13-2. I2C Bus Configuration
RPUP
SCL
SDA
I2C Bus
I2CSCL
I2CSDA
StellarisTM
13.2.1
RPUP
SCL
SDA
3rd Party Device
with I2C Interface
SCL
SDA
3rd Party Device
with I2C Interface
I2C Bus Functional Overview
®
The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris
microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock
line. The bus is considered idle when both lines are High.
Every transaction on the I2C bus is nine bits long, consisting of eight data bits and a single
acknowledge bit. The number of bytes per transfer (defined as the time between a valid START
and STOP condition, described in “START and STOP Conditions” on page 330) is unrestricted, but
each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When
a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the
transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL.
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13.2.1.1
START and STOP Conditions
The protocol of the I2C bus defines two states to begin and end a transaction: START and STOP.
A High-to-Low transition on the SDA line while the SCL is High is defined as a START condition,
and a Low-to-High transition on the SDA line while SCL is High is defined as a STOP condition.
The bus is considered busy after a START condition and free after a STOP condition. See Figure
13-3 on page 330.
Figure 13-3. START and STOP Conditions
SDA
SDA
SCL
SCL
START
condition
13.2.1.2
STOP
condition
Data Format with 7-Bit Address
Data transfers follow the format shown in Figure 13-4 on page 330. After the START condition, a
slave address is sent. This address is 7-bits long followed by an eighth bit, which is a data direction
bit (R/S bit in the I2CMSA register). A zero indicates a transmit operation (send), and a one indicates
a request for data (receive). A data transfer is always terminated by a STOP condition generated
by the master, however, a master can initiate communications with another device on the bus by
generating a repeated START condition and addressing another slave without first generating a
STOP condition. Various combinations of receive/send formats are then possible within a single
transfer.
Figure 13-4. Complete Data Transfer with a 7-Bit Address
SDA
MSB
SCL
1
2
LSB
R/S
ACK
7
8
9
MSB
1
2
Slave address
7
LSB
ACK
8
9
Data
The first seven bits of the first byte make up the slave address (see Figure 13-5 on page 330). The
eighth bit determines the direction of the message. A zero in the R/S position of the first byte means
that the master will write (send) data to the selected slave, and a one in this position means that
the master will receive data from the slave.
Figure 13-5. R/S Bit in First Byte
MSB
LSB
R/S
Slave address
13.2.1.3
Data Validity
The data on the SDA line must be stable during the high period of the clock, and the data line can
only change when SCL is Low (see Figure 13-6 on page 331).
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Figure 13-6. Data Validity During Bit Transfer on the I2C Bus
SDA
SCL
Data line Change
stable
of data
allowed
13.2.1.4
Acknowledge
All bus transactions have a required acknowledge clock cycle that is generated by the master. During
the acknowledge cycle, the transmitter (which can be the master or slave) releases the SDA line.
To acknowledge the transaction, the receiver must pull down SDA during the acknowledge clock
cycle. The data sent out by the receiver during the acknowledge cycle must comply with the data
validity requirements described in “Data Validity” on page 330.
When a slave receiver does not acknowledge the slave address, SDA must be left High by the slave
so that the master can generate a STOP condition and abort the current transfer. If the master
device is acting as a receiver during a transfer, it is responsible for acknowledging each transfer
made by the slave. Since the master controls the number of bytes in the transfer, it signals the end
of data to the slave transmitter by not generating an acknowledge on the last data byte. The slave
transmitter must then release SDA to allow the master to generate the STOP or a repeated START
condition.
13.2.1.5
Arbitration
A master may start a transfer only if the bus is idle. It's possible for two or more masters to generate
a START condition within minimum hold time of the START condition. In these situations, an
arbitration scheme takes place on the SDA line, while SCL is High. During arbitration, the first of
the competing master devices to place a '1' (High) on SDA while another master transmits a '0'
(Low) will switch off its data output stage and retire until the bus is idle again.
Arbitration can take place over several bits. Its first stage is a comparison of address bits, and if
both masters are trying to address the same device, arbitration continues on to the comparison of
data bits.
13.2.2
Available Speed Modes
The I2C clock rate is determined by the parameters: CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP.
where:
CLK_PRD is the system clock period
SCL_LP is the low phase of SCL (fixed at 6)
SCL_HP is the high phase of SCL (fixed at 4)
TIMER_PRD is the programmed value in the I2C Master Timer Period (I2CMTPR) register (see
page 349).
The I2C clock period is calculated as follows:
SCL_PERIOD = 2*(1 + TIMER_PRD)*(SCL_LP + SCL_HP)*CLK_PRD
For example:
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CLK_PRD = 50 ns
TIMER_PRD = 2
SCL_LP=6
SCL_HP=4
yields a SCL frequency of:
1/T = 333 Khz
Table 13-1 on page 332 gives examples of timer period, system clock, and speed mode (Standard
or Fast).
Table 13-1. Examples of I2C Master Timer Period versus Speed Mode
System Clock
13.2.3
Timer Period
Standard Mode
4 MHz
0x01
100 Kbps
Timer Period
-
Fast Mode
-
6 MHz
0x02
100 Kbps
-
-
12.5 MHz
0x06
89 Kbps
0x01
312 Kbps
16.7 MHz
0x08
93 Kbps
0x02
278 Kbps
20 MHz
0x09
100 Kbps
0x02
333 Kbps
25 MHz
0x0C
96.2 Kbps
0x03
312 Kbps
33 MHz
0x10
97.1 Kbps
0x04
330 Kbps
40 MHz
0x13
100 Kbps
0x04
400 Kbps
50 MHz
0x18
100 Kbps
0x06
357 Kbps
Interrupts
The I2C can generate interrupts when the following conditions are observed:
■ Master transaction completed
■ Master transaction error
■ Slave transaction received
■ Slave transaction requested
There is a separate interrupt signal for the I2C master and I2C slave modules. While both modules
can generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt
controller.
13.2.3.1
I2C Master Interrupts
The I2C master module generates an interrupt when a transaction completes (either transmit or
receive), or when an error occurs during a transaction. To enable the I2C master interrupt, software
must write a '1' to the I2C Master Interrupt Mask (I2CMIMR) register. When an interrupt condition
is met, software must check the ERROR bit in the I2C Master Control/Status (I2CMCS) register to
verify that an error didn't occur during the last transaction. An error condition is asserted if the last
transaction wasn't acknowledge by the slave or if the master was forced to give up ownership of
the bus due to a lost arbitration round with another master. If an error is not detected, the application
can proceed with the transfer. The interrupt is cleared by writing a '1' to the I2C Master Interrupt
Clear (I2CMICR) register.
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If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I2C Master Raw Interrupt Status (I2CMRIS) register.
13.2.3.2
I2C Slave Interrupts
The slave module can generate an interrupt when data has been received or requested. This interrupt
is enabled by writing a 1 to the DATAIM bit in the I2C Slave Interrupt Mask (I2CSIMR) register.
Software determines whether the module should write (transmit) or read (receive) data from the I2C
Slave Data (I2CSDR) register, by checking the RREQ and TREQ bits of the I2C Slave Control/Status
(I2CSCSR) register. If the slave module is in receive mode and the first byte of a transfer is received,
the FBR bit is set along with the RREQ bit. The interrupt is cleared by writing a 1 to the DATAIC bit
in the I2C Slave Interrupt Clear (I2CSICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I2C Slave Raw Interrupt Status (I2CSRIS) register.
13.2.4
Loopback Operation
The I2C modules can be placed into an internal loopback mode for diagnostic or debug work. This
is accomplished by setting the LPBK bit in the I2C Master Configuration (I2CMCR) register. In
loopback mode, the SDA and SCL signals from the master and slave modules are tied together.
13.2.5
Command Sequence Flow Charts
This section details the steps required to perform the various I2C transfer types in both master and
slave mode.
13.2.5.1
I2C Master Command Sequences
The figures that follow show the command sequences available for the I2C master.
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Figure 13-7. Master Single SEND
Idle
Write Slave
Address to
I2CMSA
Sequence
may be
omitted in a
Single Master
system
Write data to
I2CMDR
Read I2CMCS
NO
BUSBSY bit=0?
YES
Write ---0-111 to
I2CMCS
Read I2CMCS
NO
BUSY bit=0?
YES
Error Service
NO
ERROR bit=0?
YES
Idle
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Figure 13-8. Master Single RECEIVE
Idle
Write Slave
Address to
I2CMSA
Sequence may be
omitted in a Single
Master system
Read I2CMCS
NO
BUSBSY bit=0?
YES
Write ---00111 to
I2CMCS
Read I2CMCS
NO
BUSY bit=0?
YES
Error Service
NO
ERROR bit=0?
YES
Read data from
I2CMDR
Idle
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Figure 13-9. Master Burst SEND
Idle
Write Slave
Address to
I2CMSA
Sequence
may be
omitted in a
Single Master
system
Read I2CMCS
Write data to
I2CMDR
BUSY bit=0?
YES
Read I2CMCS
ERROR bit=0?
NO
NO
NO
BUSBSY bit=0?
YES
Write data to
I2CMDR
YES
Write ---0-011 to
I2CMCS
NO
ARBLST bit=1?
YES
Write ---0-001 to
I2CMCS
NO
Index=n?
YES
Write ---0-101 to
I2CMCS
Write ---0-100 to
I2CMCS
Error Service
Idle
Read I2CMCS
NO
BUSY bit=0?
YES
Error Service
NO
ERROR bit=0?
YES
Idle
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Figure 13-10. Master Burst RECEIVE
Idle
Write Slave
Address to
I2CMSA
Sequence
may be
omitted in a
Single Master
system
Read I2CMCS
BUSY bit=0?
Read I2CMCS
NO
YES
NO
BUSBSY bit=0?
ERROR bit=0?
NO
YES
Write ---01011 to
I2CMCS
NO
Read data from
I2CMDR
ARBLST bit=1?
YES
Write ---01001 to
I2CMCS
NO
Write ---0-100 to
I2CMCS
Index=m-1?
Error Service
YES
Write ---00101 to
I2CMCS
Idle
Read I2CMCS
BUSY bit=0?
NO
YES
NO
ERROR bit=0?
YES
Error Service
Read data from
I2CMDR
Idle
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Figure 13-11. Master Burst RECEIVE after Burst SEND
Idle
Master operates in
Master Transmit mode
STOP condition is not
generated
Write Slave
Address to
I2CMSA
Write ---01011 to
I2CMCS
Master operates in
Master Receive mode
Repeated START
condition is generated
with changing data
direction
Idle
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Figure 13-12. Master Burst SEND after Burst RECEIVE
Idle
Master operates in
Master Receive mode
STOP condition is not
generated
Write Slave
Address to
I2CMSA
Write ---0-011 to
I2CMCS
Master operates in
Master Transmit mode
Repeated START
condition is generated
with changing data
direction
Idle
13.2.5.2
I2C Slave Command Sequences
Figure 13-13 on page 340 presents the command sequence available for the I2C slave.
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Figure 13-13. Slave Command Sequence
Idle
Write OWN Slave
Address to
I2CSOAR
Write -------1 to
I2CSCSR
Read I2CSCSR
NO
TREQ bit=1?
YES
Write data to
I2CSDR
13.3
NO
RREQ bit=1?
FBR is
also valid
YES
Read data from
I2CSDR
Initialization and Configuration
The following example shows how to configure the I2C module to send a single byte as a master.
This assumes the system clock is 20 MHz.
1. Enable the I2C clock by writing a value of 0x0000.1000 to the RCGC1 register in the System
Control module.
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register. Also, be sure to enable the same pins for Open Drain operation.
4. Initialize the I2C Master by writing the I2CMCR register with a value of 0x0000.0020.
5. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct
value. The value written to the I2CMTPR register represents the number of system clock periods
in one SCL clock period. The TPR value is determined by the following equation:
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TPR = (System Clock / (2 * (SCL_LP + SCL_HP) * SCL_CLK)) - 1;
TPR = (20MHz / (2 * (6 + 4) * 100000)) - 1;
TPR = 9
Write the I2CMTPR register with the value of 0x0000.0009.
6. Specify the slave address of the master and that the next operation will be a Send by writing
the I2CMSA register with a value of 0x0000.0076. This sets the slave address to 0x3B.
7. Place data (byte) to be sent in the data register by writing the I2CMDR register with the desired
data.
8. Initiate a single byte send of the data from Master to Slave by writing the I2CMCS register with
a value of 0x0000.0007 (STOP, START, RUN).
9. Wait until the transmission completes by polling the I2CMCS register’s BUSBSY bit until it has
been cleared.
13.4
Register Map
Table 13-2 on page 341 lists the I2C registers. All addresses given are relative to the I2C base
addresses for the master and slave:
■ I2C Master 0: 0x4002.0000
■ I2C Slave 0: 0x4002.0800
Table 13-2. Inter-Integrated Circuit (I2C) Interface Register Map
Offset
Description
See
page
Name
Type
Reset
0x000
I2CMSA
R/W
0x0000.0000
I2C Master Slave Address
343
0x004
I2CMCS
R/W
0x0000.0000
I2C Master Control/Status
344
0x008
I2CMDR
R/W
0x0000.0000
I2C Master Data
348
0x00C
I2CMTPR
R/W
0x0000.0001
I2C Master Timer Period
349
0x010
I2CMIMR
R/W
0x0000.0000
I2C Master Interrupt Mask
350
0x014
I2CMRIS
RO
0x0000.0000
I2C Master Raw Interrupt Status
351
0x018
I2CMMIS
RO
0x0000.0000
I2C Master Masked Interrupt Status
352
0x01C
I2CMICR
WO
0x0000.0000
I2C Master Interrupt Clear
353
0x020
I2CMCR
R/W
0x0000.0000
I2C Master Configuration
354
0x000
I2CSOAR
R/W
0x0000.0000
I2C Slave Own Address
356
0x004
I2CSCSR
RO
0x0000.0000
I2C Slave Control/Status
357
0x008
I2CSDR
R/W
0x0000.0000
I2C Slave Data
359
0x00C
I2CSIMR
R/W
0x0000.0000
I2C Slave Interrupt Mask
360
I2C Master
I2C Slave
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Table 13-2. Inter-Integrated Circuit (I2C) Interface Register Map (continued)
Offset
Name
0x010
Reset
I2CSRIS
RO
0x0000.0000
I2C Slave Raw Interrupt Status
361
0x014
I2CSMIS
RO
0x0000.0000
I2C Slave Masked Interrupt Status
362
0x018
I2CSICR
WO
0x0000.0000
I2C Slave Interrupt Clear
363
13.5
Description
See
page
Type
Register Descriptions (I2C Master)
The remainder of this section lists and describes the I2C master registers, in numerical order by
address offset. See also “Register Descriptions (I2C Slave)” on page 355.
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Register 1: I2C Master Slave Address (I2CMSA), offset 0x000
This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which
determines if the next operation is a Receive (High), or Send (Low).
I2C Master Slave Address (I2CMSA)
I2C Master 0 base: 0x4002.0000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
SA
RO
0
R/S
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:1
SA
R/W
0
I2C Slave Address
This field specifies bits A6 through A0 of the slave address.
0
R/S
R/W
0
Receive/Send
The R/S bit specifies if the next operation is a Receive (High) or Send
(Low).
Value Description
0
Send.
1
Receive.
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Register 2: I2C Master Control/Status (I2CMCS), offset 0x004
This register accesses four control bits when written, and accesses seven status bits when read.
The status register consists of seven bits, which when read determine the state of the I2C bus
controller.
The control register consists of four bits: the RUN, START, STOP, and ACK bits. The START bit causes
the generation of the START, or REPEATED START condition.
The STOP bit determines if the cycle stops at the end of the data cycle, or continues on to a burst.
To generate a single send cycle, the I2C Master Slave Address (I2CMSA) register is written with
the desired address, the R/S bit is set to 0, and the Control register is written with ACK=X (0 or 1),
STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation is completed
(or aborted due an error), the interrupt pin becomes active and the data may be read from the
I2CMDR register. When the I2C module operates in Master receiver mode, the ACK bit must be set
normally to logic 1. This causes the I2C bus controller to send an acknowledge automatically after
each byte. This bit must be reset when the I2C bus controller requires no further data to be sent
from the slave transmitter.
Reads
I2C Master Control/Status (I2CMCS)
I2C Master 0 base: 0x4002.0000
Offset 0x004
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
BUSBSY
IDLE
ARBLST
ERROR
BUSY
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
DATACK ADRACK
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:7
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
BUSBSY
RO
0
Bus Busy
This bit specifies the state of the I2C bus. If set, the bus is busy;
otherwise, the bus is idle. The bit changes based on the START and
STOP conditions.
5
IDLE
RO
0
I2C Idle
This bit specifies the I2C controller state. If set, the controller is idle;
otherwise the controller is not idle.
4
ARBLST
RO
0
Arbitration Lost
This bit specifies the result of bus arbitration. If set, the controller lost
arbitration; otherwise, the controller won arbitration.
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Bit/Field
Name
Type
Reset
3
DATACK
RO
0
Description
Acknowledge Data
This bit specifies the result of the last data operation. If set, the
transmitted data was not acknowledged; otherwise, the data was
acknowledged.
2
ADRACK
RO
0
Acknowledge Address
This bit specifies the result of the last address operation. If set, the
transmitted address was not acknowledged; otherwise, the address was
acknowledged.
1
ERROR
RO
0
Error
This bit specifies the result of the last bus operation. If set, an error
occurred on the last operation; otherwise, no error was detected. The
error can be from the slave address not being acknowledged, the
transmit data not being acknowledged, or because the controller lost
arbitration.
0
BUSY
RO
0
I2C Busy
This bit specifies the state of the controller. If set, the controller is busy;
otherwise, the controller is idle. When the BUSY bit is set, the other status
bits are not valid.
Writes
I2C Master Control/Status (I2CMCS)
I2C Master 0 base: 0x4002.0000
Offset 0x004
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WO
0
WO
0
WO
0
WO
0
reserved
Type
Reset
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
3
2
1
0
ACK
STOP
START
RUN
WO
0
WO
0
WO
0
WO
0
Bit/Field
Name
Type
Reset
Description
31:4
reserved
WO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
ACK
WO
0
Data Acknowledge Enable
When set, causes received data byte to be acknowledged automatically
by the master. See field decoding in Table 13-3 on page 346.
2
STOP
WO
0
Generate STOP
When set, causes the generation of the STOP condition. See field
decoding in Table 13-3 on page 346.
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Bit/Field
Name
Type
Reset
1
START
WO
0
Description
Generate START
When set, causes the generation of a START or repeated START
condition. See field decoding in Table 13-3 on page 346.
0
RUN
WO
I2C Master Enable
0
When set, allows the master to send or receive data. See field decoding
in Table 13-3 on page 346.
Table 13-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3)
Current I2CMSA[0]
State
R/S
Idle
I2CMCS[3:0]
ACK
Description
STOP
START
RUN
0
X
a
0
1
1
0
X
1
1
1
START condition followed by a SEND and STOP
condition (master remains in Idle state).
1
0
0
1
1
START condition followed by RECEIVE operation with
negative ACK (master goes to the Master Receive state).
1
0
1
1
1
START condition followed by RECEIVE and STOP
condition (master remains in Idle state).
1
1
0
1
1
START condition followed by RECEIVE (master goes
to the Master Receive state).
1
1
1
1
1
Illegal.
All other combinations not listed are non-operations.
Master
Transmit
START condition followed by SEND (master goes to the
Master Transmit state).
NOP.
X
X
0
0
1
SEND operation (master remains in Master Transmit
state).
X
X
1
0
0
STOP condition (master goes to Idle state).
X
X
1
0
1
SEND followed by STOP condition (master goes to Idle
state).
0
X
0
1
1
Repeated START condition followed by a SEND (master
remains in Master Transmit state).
0
X
1
1
1
Repeated START condition followed by SEND and STOP
condition (master goes to Idle state).
1
0
0
1
1
Repeated START condition followed by a RECEIVE
operation with a negative ACK (master goes to Master
Receive state).
1
0
1
1
1
Repeated START condition followed by a SEND and
STOP condition (master goes to Idle state).
1
1
0
1
1
Repeated START condition followed by RECEIVE
(master goes to Master Receive state).
1
1
1
1
1
Illegal.
All other combinations not listed are non-operations.
NOP.
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Table 13-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) (continued)
Current I2CMSA[0]
State
R/S
Master
Receive
I2CMCS[3:0]
Description
ACK
STOP
START
RUN
X
0
0
0
1
RECEIVE operation with negative ACK (master remains
in Master Receive state).
X
X
1
0
0
STOP condition (master goes to Idle state).
X
0
1
0
1
RECEIVE followed by STOP condition (master goes to
Idle state).
X
1
0
0
1
RECEIVE operation (master remains in Master Receive
state).
X
1
1
0
1
Illegal.
1
0
0
1
1
Repeated START condition followed by RECEIVE
operation with a negative ACK (master remains in Master
Receive state).
1
0
1
1
1
Repeated START condition followed by RECEIVE and
STOP condition (master goes to Idle state).
1
1
0
1
1
Repeated START condition followed by RECEIVE
(master remains in Master Receive state).
0
X
0
1
1
Repeated START condition followed by SEND (master
goes to Master Transmit state).
0
X
1
1
1
Repeated START condition followed by SEND and STOP
condition (master goes to Idle state).
All other combinations not listed are non-operations.
b
NOP.
a. An X in a table cell indicates the bit can be 0 or 1.
b. In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by
the master or an Address Negative Acknowledge executed by the slave.
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Register 3: I2C Master Data (I2CMDR), offset 0x008
Important: Use caution when reading this register. Performing a read may change bit status.
This register contains the data to be transmitted when in the Master Transmit state, and the data
received when in the Master Receive state.
I2C Master Data (I2CMDR)
I2C Master 0 base: 0x4002.0000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
DATA
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
DATA
R/W
0x00
Data Transferred
Data transferred during transaction.
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Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C
This register specifies the period of the SCL clock.
Caution – Take care not to set bit 7 when accessing this register as unpredictable behavior can occur.
I2C Master Timer Period (I2CMTPR)
I2C Master 0 base: 0x4002.0000
Offset 0x00C
Type R/W, reset 0x0000.0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
15
14
13
12
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
TPR
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:7
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6:0
TPR
R/W
0x1
SCL Clock Period
This field specifies the period of the SCL clock.
SCL_PRD = 2*(1 + TPR)*(SCL_LP + SCL_HP)*CLK_PRD
where:
SCL_PRD is the SCL line period (I2C clock).
TPR is the Timer Period register value (range of 1 to 127).
SCL_LP is the SCL Low period (fixed at 6).
SCL_HP is the SCL High period (fixed at 4).
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Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Master Interrupt Mask (I2CMIMR)
I2C Master 0 base: 0x4002.0000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
IM
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
IM
R/W
0
Interrupt Mask
This bit controls whether a raw interrupt is promoted to a controller
interrupt. If set, the interrupt is not masked and the interrupt is promoted;
otherwise, the interrupt is masked.
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Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014
This register specifies whether an interrupt is pending.
I2C Master Raw Interrupt Status (I2CMRIS)
I2C Master 0 base: 0x4002.0000
Offset 0x014
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RIS
RO
0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RIS
RO
0
Raw Interrupt Status
This bit specifies the raw interrupt state (prior to masking) of the I2C
master block. If set, an interrupt is pending; otherwise, an interrupt is
not pending.
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Inter-Integrated Circuit (I2C) Interface
Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018
This register specifies whether an interrupt was signaled.
I2C Master Masked Interrupt Status (I2CMMIS)
I2C Master 0 base: 0x4002.0000
Offset 0x018
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
MIS
RO
0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
MIS
RO
0
Masked Interrupt Status
This bit specifies the raw interrupt state (after masking) of the I2C master
block. If set, an interrupt was signaled; otherwise, an interrupt has not
been generated since the bit was last cleared.
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Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C
This register clears the raw interrupt.
I2C Master Interrupt Clear (I2CMICR)
I2C Master 0 base: 0x4002.0000
Offset 0x01C
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
WO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
IC
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
IC
WO
0
Interrupt Clear
This bit controls the clearing of the raw interrupt. A write of 1 clears the
interrupt; otherwise, a write of 0 has no affect on the interrupt state. A
read of this register returns no meaningful data.
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Inter-Integrated Circuit (I2C) Interface
Register 9: I2C Master Configuration (I2CMCR), offset 0x020
This register configures the mode (Master or Slave) and sets the interface for test mode loopback.
I2C Master Configuration (I2CMCR)
I2C Master 0 base: 0x4002.0000
Offset 0x020
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
SFE
MFE
RO
0
RO
0
RO
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
reserved
RO
0
RO
0
LPBK
RO
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:6
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
SFE
R/W
0
I2C Slave Function Enable
This bit specifies whether the interface may operate in Slave mode. If
set, Slave mode is enabled; otherwise, Slave mode is disabled.
4
MFE
R/W
0
I2C Master Function Enable
This bit specifies whether the interface may operate in Master mode. If
set, Master mode is enabled; otherwise, Master mode is disabled and
the interface clock is disabled.
3:1
reserved
RO
0x00
0
LPBK
R/W
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C Loopback
This bit specifies whether the interface is operating normally or in
Loopback mode. If set, the device is put in a test mode loopback
configuration; otherwise, the device operates normally.
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13.6
Register Descriptions (I2C Slave)
The remainder of this section lists and describes the I2C slave registers, in numerical order by
address offset. See also “Register Descriptions (I2C Master)” on page 342.
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Inter-Integrated Circuit (I2C) Interface
Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000
®
This register consists of seven address bits that identify the Stellaris I2C device on the I2C bus.
I2C Slave Own Address (I2CSOAR)
I2C Slave 0 base: 0x4002.0800
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
15
14
13
12
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
OAR
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:7
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6:0
OAR
R/W
0x00
I2C Slave Own Address
This field specifies bits A6 through A0 of the slave address.
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Stellaris® LM3S8530 Microcontroller
Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004
This register accesses one control bit when written, and three status bits when read.
The read-only Status register consists of three bits: the FBR, RREQ, and TREQ bits. The First
®
Byte Received (FBR) bit is set only after the Stellaris device detects its own slave address
and receives the first data byte from the I2C master. The Receive Request (RREQ) bit indicates
®
that the Stellaris I2C device has received a data byte from an I2C master. Read one data byte from
2
the I C Slave Data (I2CSDR) register to clear the RREQ bit. The Transmit Request (TREQ) bit
®
indicates that the Stellaris I2C device is addressed as a Slave Transmitter. Write one data byte
into the I2C Slave Data (I2CSDR) register to clear the TREQ bit.
The write-only Control register consists of one bit: the DA bit. The DA bit enables and disables the
®
Stellaris I2C slave operation.
Reads
I2C Slave Control/Status (I2CSCSR)
I2C Slave 0 base: 0x4002.0800
Offset 0x004
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
FBR
TREQ
RREQ
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
Description
31:3
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
FBR
RO
0
First Byte Received
Indicates that the first byte following the slave’s own address is received.
This bit is only valid when the RREQ bit is set, and is automatically cleared
when data has been read from the I2CSDR register.
Note:
1
TREQ
RO
0
This bit is not used for slave transmit operations.
Transmit Request
This bit specifies the state of the I2C slave with regards to outstanding
transmit requests. If set, the I2C unit has been addressed as a slave
transmitter and uses clock stretching to delay the master until data has
been written to the I2CSDR register. Otherwise, there is no outstanding
transmit request.
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Bit/Field
Name
Type
Reset
0
RREQ
RO
0
Description
Receive Request
This bit specifies the status of the I2C slave with regards to outstanding
receive requests. If set, the I2C unit has outstanding receive data from
the I2C master and uses clock stretching to delay the master until the
data has been read from the I2CSDR register. Otherwise, no receive
data is outstanding.
Writes
I2C Slave Control/Status (I2CSCSR)
I2C Slave 0 base: 0x4002.0800
Offset 0x004
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
WO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
DA
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
DA
WO
0
Device Active
Value Description
0
Disables the I2C slave operation.
1
Enables the I2C slave operation.
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Register 12: I2C Slave Data (I2CSDR), offset 0x008
Important: Use caution when reading this register. Performing a read may change bit status.
This register contains the data to be transmitted when in the Slave Transmit state, and the data
received when in the Slave Receive state.
I2C Slave Data (I2CSDR)
I2C Slave 0 base: 0x4002.0800
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
DATA
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
DATA
R/W
0x0
Data for Transfer
This field contains the data for transfer during a slave receive or transmit
operation.
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Inter-Integrated Circuit (I2C) Interface
Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Slave Interrupt Mask (I2CSIMR)
I2C Slave 0 base: 0x4002.0800
Offset 0x00C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
DATAIM
R/W
0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
DATAIM
R/W
0
Data Interrupt Mask
This bit controls whether the raw interrupt for data received and data
requested is promoted to a controller interrupt. If set, the interrupt is not
masked and the interrupt is promoted; otherwise, the interrupt is masked.
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Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010
This register specifies whether an interrupt is pending.
I2C Slave Raw Interrupt Status (I2CSRIS)
I2C Slave 0 base: 0x4002.0800
Offset 0x010
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
DATARIS
RO
0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
DATARIS
RO
0
Data Raw Interrupt Status
This bit specifies the raw interrupt state for data received and data
requested (prior to masking) of the I2C slave block. If set, an interrupt
is pending; otherwise, an interrupt is not pending.
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Inter-Integrated Circuit (I2C) Interface
Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014
This register specifies whether an interrupt was signaled.
I2C Slave Masked Interrupt Status (I2CSMIS)
I2C Slave 0 base: 0x4002.0800
Offset 0x014
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
DATAMIS
RO
0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
DATAMIS
RO
0
Data Masked Interrupt Status
This bit specifies the interrupt state for data received and data requested
(after masking) of the I2C slave block. If set, an interrupt was signaled;
otherwise, an interrupt has not been generated since the bit was last
cleared.
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Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018
This register clears the raw interrupt. A read of this register returns no meaningful data.
I2C Slave Interrupt Clear (I2CSICR)
I2C Slave 0 base: 0x4002.0800
Offset 0x018
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
DATAIC
WO
0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
DATAIC
WO
0
Data Interrupt Clear
This bit controls the clearing of the raw interrupt for data received and
data requested. When set, it clears the DATARIS interrupt bit; otherwise,
it has no effect on the DATARIS bit value.
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Controller Area Network (CAN) Module
14
Controller Area Network (CAN) Module
Controller Area Network (CAN) is a multicast, shared serial bus standard for connecting electronic
control units (ECUs). CAN was specifically designed to be robust in electromagnetically-noisy
environments and can utilize a differential balanced line like RS-485 or a more robust twisted-pair
wire. Originally created for automotive purposes, it is also used in many embedded control
applications (such as industrial and medical). Bit rates up to 1Mbps are possible at network lengths
less than 40 meters. Decreased bit rates allow longer network distances (for example, 125 Kbps at
500 meters).
®
Each Stellaris CAN controller supports the following features:
■ Three CAN modules, each with the following features:
■ CAN protocol version 2.0 part A/B
■ Bit rates up to 1 Mbps
■ 32 message objects with individual identifier masks
■ Maskable interrupt
■ Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications
■ Programmable Loopback mode for self-test operation
■ Programmable FIFO mode enables storage of multiple message objects
■ Gluelessly attaches to an external CAN interface through the CANnTX and CANnRX signals
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14.1
Block Diagram
Figure 14-1. CAN Controller Block Diagram
CAN Control
CANCTL
CANSTS
CANERR
CANBIT
CANINT
CANTST
CANBRPE
ABP
Pins
APB
Interface
CAN Interface 1
CANIF1CRQ
CANIF1CMSK
CANIF1MSK1
CANIF1MSK2
CANIF1ARB1
CANIF1ARB2
CANIF1MCTL
CANIF1DA1
CANIF1DA2
CANIF1DB1
CANIF1DB2
CAN Interface 2
CANIF2CRQ
CANIF2CMSK
CANIF2MSK1
CANIF2MSK2
CANIF2ARB1
CANIF2ARB2
CANIF2MCTL
CANIF2DA1
CANIF2DA2
CANIF2DB1
CANIF2DB2
CAN Tx
CAN Core
CAN Rx
Message Object
Registers
CANTXRQ1
CANTXRQ2
CANNWDA1
CANNWDA2
CANMSG1INT
CANMSG2INT
CANMSG1VAL
CANMSG2VAL
Message RAM
32 Message Objects
14.2
Functional Description
®
The Stellaris CAN controller conforms to the CAN protocol version 2.0 (parts A and B). Message
transfers that include data, remote, error, and overload frames with an 11-bit identifier (standard)
or a 29-bit identifier (extended) are supported. Transfer rates can be programmed up to 1 Mbps.
The CAN module consists of three major parts:
■ CAN protocol controller and message handler
■ Message memory
■ CAN register interface
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A data frame contains data for transmission, whereas a remote frame contains no data and is used
to request the transmission of a specific message object. The CAN data/remote frame is constructed
as shown in Figure 14-2 on page 366.
Figure 14-2. CAN Data/Remote Frame
Remote
Transmission
Request
Start
Of Frame
Bus
Idle
R
S
Control
O Message Delimiter T Field
R
F
Number 1
Of Bits
11 or 29
1
6
Delimiter
Bits
Data Field
CRC
Sequence
A
C
K
EOP
IFS
0 . . . 64
15
1 1 1
7
3
CRC Sequence
End of
Frame
Field
CRC
Field
Arbitration Field
Bit Stuffing
Bus
Idle
Interframe
Field
Acknowledgement
Field
CAN Data Frame
The protocol controller transfers and receives the serial data from the CAN bus and passes the data
on to the message handler. The message handler then loads this information into the appropriate
message object based on the current filtering and identifiers in the message object memory. The
message handler is also responsible for generating interrupts based on events on the CAN bus.
The message object memory is a set of 32 identical memory blocks that hold the current configuration,
status, and actual data for each message object. These are accessed via either of the CAN message
object register interfaces.
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The message memory is not directly accessible in the Stellaris memory map, so the Stellaris CAN
controller provides an interface to communicate with the message memory via two CAN interface
register sets for communicating with the message objects. As there is no direct access to the
message object memory, these two interfaces must be used to read or write to each message object.
The two message object interfaces allow parallel access to the CAN controller message objects
when multiple objects may have new information that must be processed. In general, one interface
is used for transmit data and one for receive data.
14.2.1
Initialization
Software initialization is started by setting the INIT bit in the CAN Control (CANCTL) register (with
software or by a hardware reset) or by going bus-off, which occurs when the transmitter's error
counter exceeds a count of 255. While INIT is set, all message transfers to and from the CAN bus
are stopped and the CANnTX signal is held High. Entering the initialization state does not change
the configuration of the CAN controller, the message objects, or the error counters. However, some
configuration registers are only accessible while in the initialization state.
To initialize the CAN controller, set the CAN Bit Timing (CANBIT) register and configure each
message object. If a message object is not needed, label it as not valid by clearing the MSGVAL bit
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in the CAN IFn Arbitration 2 (CANIFnARB2) register. Otherwise, the whole message object must
be initialized, as the fields of the message object may not have valid information, causing unexpected
results. Both the INIT and CCE bits in the CANCTL register must be set in order to access the
CANBIT register and the CAN Baud Rate Prescaler Extension (CANBRPE) register to configure
the bit timing. To leave the initialization state, the INIT bit must be cleared. Afterwards, the internal
Bit Stream Processor (BSP) synchronizes itself to the data transfer on the CAN bus by waiting for
the occurrence of a sequence of 11 consecutive recessive bits (indicating a bus idle condition)
before it takes part in bus activities and starts message transfers. Message object initialization does
not require the CAN to be in the initialization state and can be done on the fly. However, message
objects should all be configured to particular identifiers or set to not valid before message transfer
starts. To change the configuration of a message object during normal operation, clear the MSGVAL
bit in the CANIFnARB2 register to indicate that the message object is not valid during the change.
When the configuration is completed, set the MSGVAL bit again to indicate that the message object
is once again valid.
14.2.2
Operation
There are two sets of CAN Interface Registers (CANIF1x and CANIF2x), which are used to access
the message objects in the Message RAM. The CAN controller coordinates transfers to and from
the Message RAM to and from the registers. The two sets are independent and identical and can
be used to queue transactions. Generally, one interface is used to transmit data and one is used to
receive data.
Once the CAN module is initialized and the INIT bit in the CANCTL register is cleared, the CAN
module synchronizes itself to the CAN bus and starts the message transfer. As each message is
received, it goes through the message handler's filtering process, and if it passes through the filter,
is stored in the message object specified by the MNUM bit in the CAN IFn Command Request
(CANIFnCRQ) register. The whole message (including all arbitration bits, data-length code, and
eight data bytes) is stored in the message object. If the Identifier Mask (the MSK bits in the CAN IFn
Mask 1 and CAN IFn Mask 2 (CANIFnMSKn) registers) is used, the arbitration bits that are masked
to "don't care" may be overwritten in the message object.
The CPU may read or write each message at any time via the CAN Interface Registers. The message
handler guarantees data consistency in case of concurrent accesses.
The transmission of message objects is under the control of the software that is managing the CAN
hardware. These can be message objects used for one-time data transfers, or permanent message
objects used to respond in a more periodic manner. Permanent message objects have all arbitration
and control set up, and only the data bytes are updated. At the start of transmission, the appropriate
TXRQST bit in the CAN Transmission Request n (CANTXRQn) register and the NEWDAT bit in the
CAN New Data n (CANNWDAn) register are set. If several transmit messages are assigned to the
same message object (when the number of message objects is not sufficient), the whole message
object has to be configured before the transmission of this message is requested.
The transmission of any number of message objects may be requested at the same time; they are
transmitted according to their internal priority, which is based on the message identifier (MNUM) for
the message object, with 1 being the highest priority and 32 being the lowest priority. Messages
may be updated or set to not valid any time, even when their requested transmission is still pending.
The old data is discarded when a message is updated before its pending transmission has started.
Depending on the configuration of the message object, the transmission of a message may be
requested autonomously by the reception of a remote frame with a matching identifier.
Transmission can be automatically started by the reception of a matching remote frame. To enable
this mode, set the RMTEN bit in the CAN IFn Message Control (CANIFnMCTL) register. A matching
received remote frame causes the TXRQST bit to be set and the message object automatically
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transfers its data or generates an interrupt indicating a remote frame was requested. This can be
strictly a single message identifier, or it can be a range of values specified in the message object.
The CAN mask registers, CANIFnMSKn, configure which groups of frames are identified as remote
frame requests. The UMASK bit in the CANIFnMCTL register enables the MSK bits in the
CANIFnMSKn register to filter which frames are identified as a remote frame request. The MXTD
bit in the CANIFnMSK2 register should be set if a remote frame request is expected to be triggered
by 29-bit extended identifiers.
14.2.3
Transmitting Message Objects
If the internal transmit shift register of the CAN module is ready for loading, and if there is no data
transfer occurring between the CAN Interface Registers and message RAM, the valid message
object with the highest priority that has a pending transmission request is loaded into the transmit
shift register by the message handler and the transmission is started. The message object's NEWDAT
bit in the CANNWDAn register is cleared. After a successful transmission, and if no new data was
written to the message object since the start of the transmission, the TXRQST bit in the CANTXRQn
register is cleared. If the CAN controller is set up to interrupt upon a successful transmission of a
message object, (the TXIE bit in the CAN IFn Message Control (CANIFnMCTL) register is set),
the INTPND bit in the CANIFnMCTL register is set after a successful transmission. If the CAN
module has lost the arbitration or if an error occurred during the transmission, the message is
re-transmitted as soon as the CAN bus is free again. If, meanwhile, the transmission of a message
with higher priority has been requested, the messages are transmitted in the order of their priority.
14.2.4
Configuring a Transmit Message Object
The following steps illustrate how to configure a transmit message object.
1. In the CAN IFn Command Mask (CANIFnCMASK) register:
■ Set the WRNRD bit to specify a write to the CANIFnCMASK register; specify whether to
transfer the IDMASK, DIR, and MXTD of the message object into the CAN IFn registers using
the MASK bit
■ Specify whether to transfer the ID, DIR, XTD, and MSGVAL of the message object into the
interface registers using the ARB bit
■ Specify whether to transfer the control bits into the interface registers using the CONTROL
bit
■ Specify whether to clear the INTPND bit in the CANIFnMCTL register using the CLRINTPND
bit
■ Specify whether to clear the NEWDAT bit in the CANNWDAn register using the NEWDAT bit
■ Specify which bits to transfer using the DATAA and DATAB bits
2. In the CANIFnMSK1 register, use the MSK[15:0] bits to specify which of the bits in the 29-bit
or 11-bit message identifier are used for acceptance filtering. Note that MSK[15:0] in this
register are used for bits [15:0] of the 29-bit message identifier and are not used for an 11-bit
identifier. A value of 0x00 enables all messages to pass through the acceptance filtering. Also
note that in order for these bits to be used for acceptance filtering, they must be enabled by
setting the UMASK bit in the CANIFnMCTL register.
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3. In the CANIFnMSK2 register, use the MSK[12:0] bits to specify which of the bits in the 29-bit
or 11-bit message identifier are used for acceptance filtering. Note that MSK[12:0] are used
for bits [28:16] of the 29-bit message identifier; whereas MSK[12:2] are used for bits [10:0] of
the 11-bit message identifier. Use the MXTD and MDIR bits to specify whether to use XTD and
DIR for acceptance filtering. A value of 0x00 enables all messages to pass through the
acceptance filtering. Also note that in order for these bits to be used for acceptance filtering,
they must be enabled by setting the UMASK bit in the CANIFnMCTL register.
4. For a 29-bit identifier, configure ID[15:0] in the CANIFnARB1 register to are used for bits
[15:0] of the message identifier and ID[12:0] in the CANIFnARB2 register to are used for
bits [28:16] of the message identifier. Set the XTD bit to indicate an extended identifier; set the
DIR bit to indicate transmit; and set the MSGVAL bit to indicate that the message object is valid.
5. For an 11-bit identifier, disregard the CANIFnARB1 register and configure ID[12:2] in the
CANIFnARB2 register to are used for bits [10:0] of the message identifier. Clear the XTD bit to
indicate a standard identifier; set the DIR bit to indicate transmit; and set the MSGVAL bit to
indicate that the message object is valid.
6. In the CANIFnMCTL register:
■ Optionally set the UMASK bit to enable the mask (MSK, MXTD, and MDIR specified in the
CANIFnMSK1 and CANIFnMSK2 registers) for acceptance filtering
■ Optionally set the TXIE bit to enable the INTPND bit to be set after a successful transmission
■ Optionally set the RMTEN bit to enable the TXRQST bit to be set upon the reception of a
matching remote frame allowing automatic transmission
■ Set the EOB bit for a single message object;
■ Set the DLC[3:0] field to specify the size of the data frame. Take care during this
configuration not to set the NEWDAT, MSGLST, INTPND or TXRQST bits.
7. Load the data to be transmitted into the CAN IFn Data (CANIFnDA1, CANIFnDA2, CANIFnDB1,
CANIFnDB2) or (CANIFnDATAA and CANIFnDATAB) registers. Byte 0 of the CAN data frame
is stored in DATA[7:0] in the CANIFnDA1 register.
8. Program the number of the message object to be transmitted in the MNUM field in the CAN IFn
Command Request (CANIFnCRQ) register.
9. When everything is properly configured, set the TXRQST bit in the CANIFnMCTL register. Once
this bit is set, the message object is available to be transmitted, depending on priority and bus
availability. Note that setting the RMTEN bit in the CANIFnMCTL register can also start message
transmission if a matching remote frame has been received.
14.2.5
Updating a Transmit Message Object
The CPU may update the data bytes of a Transmit Message Object any time via the CAN Interface
Registers and neither the MSGVAL bit in the CANIFnARB2 register nor the TXRQST bits in the
CANIFnMCTL register have to be cleared before the update.
Even if only some of the data bytes are to be updated, all four bytes of the corresponding
CANIFnDAn/CANIFnDBn register have to be valid before the content of that register is transferred
to the message object. Either the CPU must write all four bytes into the CANIFnDAn/CANIFnDBn
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register or the message object is transferred to the CANIFnDAn/CANIFnDBn register before the
CPU writes the new data bytes.
In order to only update the data in a message object, the WRNRD, DATAA and DATAB bits in the
CANIFnMSKn register are set, followed by writing the updated data into CANIFnDA1, CANIFnDA2,
CANIFnDB1, and CANIFnDB2 registers, and then the number of the message object is written to
the MNUM field in the CAN IFn Command Request (CANIFnCRQ) register. To begin transmission
of the new data as soon as possible, set the TXRQST bit in the CANIFnMSKn register.
To prevent the clearing of the TXRQST bit in the CANIFnMCTL register at the end of a transmission
that may already be in progress while the data is updated, the NEWDAT and TXRQST bits have to be
set at the same time in the CANIFnMCTL register. When these bits are set at the same time, NEWDAT
is cleared as soon as the new transmission has started.
14.2.6
Accepting Received Message Objects
When the arbitration and control field (the ID and XTD bits in the CANIFnARB2 and the RMTEN and
DLC[3:0] bits of the CANIFnMCTL register) of an incoming message is completely shifted into
the CAN controller, the message handling capability of the controller starts scanning the message
RAM for a matching valid message object. To scan the message RAM for a matching message
object, the controller uses the acceptance filtering programmed through the mask bits in the
CANIFnMSKn register and enabled using the UMASK bit in the CANIFnMCTL register. Each valid
message object, starting with object 1, is compared with the incoming message to locate a matching
message object in the message RAM. If a match occurs, the scanning is stopped and the message
handler proceeds depending on whether it is a data frame or remote frame that was received.
14.2.7
Receiving a Data Frame
The message handler stores the message from the CAN controller receive shift register into the
matching message object in the message RAM. The data bytes, all arbitration bits, and the DLC bits
are all stored into the corresponding message object. In this manner, the data bytes are connected
with the identifier even if arbitration masks are used. The NEWDAT bit of the CANIFnMCTL register
is set to indicate that new data has been received. The CPU should clear this bit when it reads the
message object to indicate to the controller that the message has been received, and the buffer is
free to receive more messages. If the CAN controller receives a message and the NEWDAT bit is
already set, the MSGLST bit in the CANIFnMCTL register is set to indicate that the previous data
was lost. If the system requires an interrupt upon successful reception of a frame, the RXIE bit of
the CANIFnMCTL register should be set. In this case, the INTPND bit of the same register is set,
causing the CANINT register to point to the message object that just received a message. The
TXRQST bit of this message object should be cleared to prevent the transmission of a remote frame.
14.2.8
Receiving a Remote Frame
A remote frame contains no data, but instead specifies which object should be transmitted. When
a remote frame is received, three different configurations of the matching message object have to
be considered:
Configuration in CANIFnMCTL
■
Description
■
DIR = 1 (direction = transmit); programmed in the At the reception of a matching remote frame, the TXRQST bit of this
CANIFnARB2 register
message object is set. The rest of the message object remains
unchanged, and the controller automatically transfers the data in
RMTEN = 1 (set the TXRQST bit of the
the message object as soon as possible.
CANIFnMCTL register at reception of the frame
to enable transmission)
■
UMASK = 1 or 0
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Configuration in CANIFnMCTL
■
■
■
UMASK = 0 (ignore mask in the CANIFnMSKn
register)
■
DIR = 1 (direction = transmit); programmed in the At the reception of a matching remote frame, the TXRQST bit of this
CANIFnARB2 register
message object is cleared. The arbitration and control field (ID +
XTD + RMTEN + DLC) from the shift register is stored into the
RMTEN = 0 (do not change the TXRQST bit of the message object in the message RAM and the NEWDAT bit of this
CANIFnMCTL register at reception of the frame) message object is set. The data field of the message object remains
unchanged; the remote frame is treated similar to a received data
UMASK = 1 (use mask (MSK, MXTD, and MDIR in
frame. This is useful for a remote data request from another CAN
the CANIFnMSKn register) for acceptance filtering)
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device for which the Stellaris controller does not have readily
available data. The software must fill the data and answer the frame
manually.
■
■
14.2.9
Description
DIR = 1 (direction = transmit); programmed in the At the reception of a matching remote frame, the TXRQST bit of this
CANIFnARB2 register
message object remains unchanged, and the remote frame is
ignored. This remote frame is disabled, the data is not transferred
RMTEN = 0 (do not change the TXRQST bit of the and there is no indication that the remote frame ever happened.
CANIFnMCTL register at reception of the frame)
Receive/Transmit Priority
The receive/transmit priority for the message objects is controlled by the message number. Message
object 1 has the highest priority, while message object 32 has the lowest priority. If more than one
transmission request is pending, the message objects are transmitted in order based on the message
object with the lowest message number. This should not be confused with the message identifier
as that priority is enforced by the CAN bus. This means that if message object 1 and message object
2 both have valid messages that need to be transmitted, message object 1 will always be transmitted
first regardless of the message identifier in the message object itself.
14.2.10
Configuring a Receive Message Object
The following steps illustrate how to configure a receive message object.
1. Program the CAN IFn Command Mask (CANIFnCMASK) register as described in the
“Configuring a Transmit Message Object” on page 368 section, except that the WRNRD bit is set
to specify a write to the message RAM.
2. Program the CANIFnMSK1and CANIFnMSK2 registers as described in the “Configuring a
Transmit Message Object” on page 368 section to configure which bits are used for acceptance
filtering. Note that in order for these bits to be used for acceptance filtering, they must be enabled
by setting the UMASK bit in the CANIFnMCTL register.
3. In the CANIFnMSK2 register, use the MSK[12:0] bits to specify which of the bits in the 29-bit
or 11-bit message identifier are used for acceptance filtering. Note that MSK[12:0] are used
for bits [28:16] of the 29-bit message identifier; whereas MSK[12:2] are used for bits [10:0] of
the 11-bit message identifier. Use the MXTD and MDIR bits to specify whether to use XTD and
DIR for acceptance filtering. A value of 0x00 enables all messages to pass through the
acceptance filtering. Also note that in order for these bits to be used for acceptance filtering,
they must be enabled by setting the UMASK bit in the CANIFnMCTL register.
4. Program the CANIFnARB1 and CANIFnARB2 registers as described in the “Configuring a
Transmit Message Object” on page 368 section to program XTD and ID bits for the message
identifier to be received; set the MSGVAL bit to indicate a valid message; and clear the DIR bit
to specify receive.
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5. In the CANIFnMCTL register:
■ Optionally set the UMASK bit to enable the mask (MSK, MXTD, and MDIR specified in the
CANIFnMSK1 and CANIFnMSK2 registers) for acceptance filtering
■ Optionally set the RXIE bit to enable the INTPND bit to be set after a successful reception
■ Clear the RMTEN bit to leave the TXRQST bit unchanged
■ Set the EOB bit for a single message object
■ Set the DLC[3:0] field to specify the size of the data frame
Take care during this configuration not to set the NEWDAT, MSGLST, INTPND or TXRQST bits.
6. Program the number of the message object to be received in the MNUM field in the CAN IFn
Command Request (CANIFnCRQ) register. Reception of the message object begins as soon
as a matching frame is available on the CAN bus.
When the message handler stores a data frame in the message object, it stores the received Data
Length Code and eight data bytes in the CANIFnDA1, CANIFnDA2, CANIFnDB1, and CANIFnDB2
register. Byte 0 of the CAN data frame is stored in DATA[7:0] in the CANIFnDA1 register. If the
Data Length Code is less than 8, the remaining bytes of the message object are overwritten by
unspecified values.
The CAN mask registers can be used to allow groups of data frames to be received by a message
object. The CAN mask registers, CANIFnMSKn, configure which groups of frames are received by
a message object. The UMASK bit in the CANIFnMCTL register enables the MSK bits in the
CANIFnMSKn register to filter which frames are received. The MXTD bit in the CANIFnMSK2 register
should be set if only 29-bit extended identifiers are expected by this message object.
14.2.11
Handling of Received Message Objects
The CPU may read a received message any time via the CAN Interface registers because the data
consistency is guaranteed by the message handler state machine.
Typically, the CPU first writes 0x007F to the CANIFnCMSK register and then writes the number of
the message object to the CANIFnCRQ register. That combination transfers the whole received
message from the message RAM into the Message Buffer registers (CANIFnMSKn, CANIFnARBn,
and CANIFnMCTL). Additionally, the NEWDAT and INTPND bits are cleared in the message RAM,
acknowledging that the message has been read and clearing the pending interrupt generated by
this message object.
If the message object uses masks for acceptance filtering, the CANIFnARBn registers show the
full, unmasked ID for the received message.
The NEWDAT bit in the CANIFnMCTL register shows whether a new message has been received
since the last time this message object was read. The MSGLST bit in the CANIFnMCTL register
shows whether more than one message has been received since the last time this message object
was read. MSGLST is not automatically cleared, and should be cleared by software after reading its
status.
Using a remote frame, the CPU may request new data from another CAN node on the CAN bus.
Setting the TXRQST bit of a receive object causes the transmission of a remote frame with the receive
object's identifier. This remote frame triggers the other CAN node to start the transmission of the
matching data frame. If the matching data frame is received before the remote frame could be
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transmitted, the TXRQST bit is automatically reset. This prevents the possible loss of data when the
other device on the CAN bus has already transmitted the data slightly earlier than expected.
14.2.11.1 Configuration of a FIFO Buffer
With the exception of the EOB bit in the CANIFnMCTL register, the configuration of receive message
objects belonging to a FIFO buffer is the same as the configuration of a single receive message
object (see “Configuring a Receive Message Object” on page 371). To concatenate two or more
message objects into a FIFO buffer, the identifiers and masks (if used) of these message objects
have to be programmed to matching values. Due to the implicit priority of the message objects, the
message object with the lowest message object number is the first message object in a FIFO buffer.
The EOB bit of all message objects of a FIFO buffer except the last one must be cleared. The EOB
bit of the last message object of a FIFO buffer is set, indicating it is the last entry in the buffer.
14.2.11.2 Reception of Messages with FIFO Buffers
Received messages with identifiers matching to a FIFO buffer are stored starting with the message
object with the lowest message number. When a message is stored into a message object of a
FIFO buffer, the NEWDAT of the CANIFnMCTL register bit of this message object is set. By setting
NEWDAT while EOB is clear, the message object is locked and cannot be written to by the message
handler until the CPU has cleared the NEWDAT bit. Messages are stored into a FIFO buffer until the
last message object of this FIFO buffer is reached. If none of the preceding message objects has
been released by clearing the NEWDAT bit, all further messages for this FIFO buffer will be written
into the last message object of the FIFO buffer and therefore overwrite previous messages.
14.2.11.3 Reading from a FIFO Buffer
When the CPU transfers the contents of a message object from a FIFO buffer by writing its number
to the CANIFnCRQ, the TXRQST and CLRINTPND bits in the CANIFnCMSK register should be set
such that the NEWDAT and INTPEND bits in the CANIFnMCTL register are cleared after the read.
The values of these bits in the CANIFnMCTL register always reflect the status of the message
object before the bits are cleared. To assure the correct function of a FIFO buffer, the CPU should
read out the message objects starting with the message object with the lowest message number.
When reading from the FIFO buffer, the user should be aware that a new received message could
be placed in the location of any message object for which the NEWDAT bit of the CANIFnMCTL
register. As a result, the order of the received messages in the FIFO is not guaranteed. Figure
14-3 on page 374 shows how a set of message objects which are concatenated to a FIFO Buffer
can be handled by the CPU.
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Figure 14-3. Message Objects in a FIFO Buffer
START
Message Interrupt
Read Interrupt Pointer
0x0000
Case Interrupt Pointer
else
0x8000
END
Status Change
Interrupt Handling
MNUM = Interrupt Pointer
Write MNUM to IFn Command Request
(Read Message to IFn Registers,
Reset NEWDAT = 0,
Reset INTPND = 0
Read IFn Message Control
Yes
No
NEWDAT = 1
Read Data from IFn Data A,B
EOB = 1
Yes
No
MNUM = MNUM + 1
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14.2.12
Handling of Interrupts
If several interrupts are pending, the CAN Interrupt (CANINT) register points to the pending interrupt
with the highest priority, disregarding their chronological order. The status interrupt has the highest
priority. Among the message interrupts, the message object's interrupt with the lowest message
number has the highest priority. A message interrupt is cleared by clearing the message object's
INTPND bit in the CANIFnMCTL register or by reading the CAN Status (CANSTS) register. The
status Interrupt is cleared by reading the CANSTS register.
The interrupt identifier INTID in the CANINT register indicates the cause of the interrupt. When no
interrupt is pending, the register reads as 0x0000. If the value of the INTID field is different from 0,
then there is an interrupt pending. If the IE bit is set in the CANCTL register, the interrupt line to
the CPU is active. The interrupt line remains active until the INTID field is 0, meaning that all interrupt
sources have been cleared (the cause of the interrupt is reset), or until IE is cleared, which disables
interrupts from the CAN controller.
The INTID field of the CANINT register points to the pending message interrupt with the highest
interrupt priority. The SIE bit in the CANCTL register controls whether a change of the RXOK, TXOK,
and LEC bits in the CANSTS can cause an interrupt. The EIE bit in the CANCTLregister controls
whether a change of the BOFF and EWARN bits in the CANSTS can cause an interrupt. The IE bit
in the CANCTL controls whether any interrupt from the CAN controller actually generates an interrupt
to the microcontroller's interrupt controller. The CANINT register is updated even when the IE bit
in the CANCTL register is clear, but the interrupt will not be indicated to the CPU.
A value of 0x8000 in the CANINT register indicates that an interrupt is pending because the CAN
module has updated, but not necessarily changed, the CANSTS , indicating that either an error or
status interrupt has been generated. A write access to the CANSTS register can clear the RXOK,
TXOK, and LEC bits in that same register; however, the only way to clear the source of a status
interrupt is to read the CANSTS register.
There are two ways to determine the source of an interrupt during interrupt handling. The first is to
read the INTID bit in the CANINT register to determine the highest priority interrupt that is pending,
and the second is to read the CAN Message Interrupt Pending (CANMSGnINT) register to see
all of the message objects that have pending interrupts.
An interrupt service routine reading the message that is the source of the interrupt may read the
message and clear the message object's INTPND bit at the same time by setting the CLRINTPND
bit in the CANIFnCMSK register. Once the INTPND bit has been cleared, the CANINT register
contains the message number for the next message object with a pending interrupt.
14.2.13
Test Mode
A Test Mode is provided, which allows various diagnostics to be performed. Test Mode is entered
by setting the TEST bit CANCTL register. Once in Test Mode, the TX[1:0], LBACK, SILENT and
BASIC bits in the CAN Test (CANTST) register can be used to put the CAN controller into the
various diagnostic modes. The RX bit in the CANTST register allows monitoring of the CANnRX
signal. All CANTST register functions are disabled when the TEST bit is cleared.
14.2.13.1 Silent Mode
Silent Mode can be used to analyze the traffic on a CAN bus without affecting it by the transmission
of dominant bits (Acknowledge Bits, Error Frames). The CAN Controller is put in Silent Mode setting
the SILENT bit in the CANTST register. In Silent Mode, the CAN controller is able to receive valid
data frames and valid remote frames, but it sends only recessive bits on the CAN bus and it cannot
start a transmission. If the CAN Controller is required to send a dominant bit (ACK bit, overload flag,
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or active error flag), the bit is rerouted internally so that the CAN Controller monitors this dominant
bit, although the CAN bus remains in recessive state.
14.2.13.2 Loopback Mode
Loopback mode is useful for self-test functions. In Loopback Mode, the CAN Controller internally
routes the CANnTX signal on to the CANnRX signal and treats its own transmitted messages as
received messages and stores them (if they pass acceptance filtering) into the message buffer. The
CAN Controller is put in Loopback Mode by setting the LBACK bit in the CANTST register. To be
independent from external stimulation, the CAN Controller ignores acknowledge errors (a recessive
bit sampled in the acknowledge slot of a data/remote frame) in Loopback Mode. The actual value
of the CANnRX signal is disregarded by the CAN Controller. The transmitted messages can be
monitored on the CANnTX signal.
14.2.13.3 Loopback Combined with Silent Mode
Loopback Mode and Silent Mode can be combined to allow the CAN Controller to be tested without
affecting a running CAN system connected to the CANnTX and CANnRX signals. In this mode, the
CANnRX signal is disconnected from the CAN Controller and the CANnTX signal is held recessive.
This mode is enabled by setting both the LBACK and SILENT bits in the CANTST register.
14.2.13.4 Basic Mode
Basic Mode allows the CAN Controller to be operated without the Message RAM. In Basic Mode,
The CANIF1 registers are used as the transmit buffer. The transmission of the contents of the IF1
registers is requested by setting the BUSY bit of the CANIF1CRQ register. The CANIF1 registers
are locked while the BUSY bit is set. The BUSY bit indicates that a transmission is pending. As soon
the CAN bus is idle, the CANIF1 registers are loaded into the shift register of the CAN Controller
and transmission is started. When the transmission has completed, the BUSY bit is cleared and the
locked CANIF1 registers are released. A pending transmission can be aborted at any time by clearing
the BUSY bit in the CANIF1CRQ register while the CANIF1 registers are locked. If the CPU has
cleared the BUSY bit, a possible retransmission in case of lost arbitration or an error is disabled.
The CANIF2 Registers are used as a receive buffer. After the reception of a message, the contents
of the shift register is stored into the CANIF2 registers, without any acceptance filtering. Additionally,
the actual contents of the shift register can be monitored during the message transfer. Each time a
read message object is initiated by setting the BUSY bit of the CANIF2CRQ register, the contents
of the shift register are stored into the CANIF2 registers.
In Basic Mode, all message-object-related control and status bits and of the control bits of the
CANIFnCMSK registers are not evaluated. The message number of the CANIFnCRQ registers is
also not evaluated. In the CANIF2MCTL register, the NEWDAT and MSGLST bits retain their function,
the DLC[3:0] field shows the received DLC, the other control bits are cleared.
Basic Mode is enabled by setting the BASIC bit in the CANTST register.
14.2.13.5 Transmit Control
Software can directly override control of the CANnTX signal in four different ways.
■ CANnTX is controlled by the CAN Controller
■ The sample point is driven on the CANnTX signal to monitor the bit timing
■ CANnTX drives a low value
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■ CANnTX drives a high value
The last two functions, combined with the readable CAN receive pin CANnRX, can be used to check
the physical layer of the CAN bus.
The Transmit Control function is enabled by programming the TX[1:0] field in the CANTST register.
The three test functions for the CANnTX signal interfere with all CAN protocol functions. TX[1:0]
must be cleared when CAN message transfer or Loopback Mode, Silent Mode, or Basic Mode are
selected.
14.2.14
Bit Timing Configuration Error Considerations
Even if minor errors in the configuration of the CAN bit timing do not result in immediate failure, the
performance of a CAN network can be reduced significantly. In many cases, the CAN bit
synchronization amends a faulty configuration of the CAN bit timing to such a degree that only
occasionally an error frame is generated. In the case of arbitration, however, when two or more
CAN nodes simultaneously try to transmit a frame, a misplaced sample point may cause one of the
transmitters to become error passive. The analysis of such sporadic errors requires a detailed
knowledge of the CAN bit synchronization inside a CAN node and of the CAN nodes' interaction on
the CAN bus.
14.2.15
Bit Time and Bit Rate
The CAN system supports bit rates in the range of lower than 1 Kbps up to 1000 Kbps. Each member
of the CAN network has its own clock generator. The timing parameter of the bit time can be
configured individually for each CAN node, creating a common bit rate even though the CAN nodes'
oscillator periods may be different.
Because of small variations in frequency caused by changes in temperature or voltage and by
deteriorating components, these oscillators are not absolutely stable. As long as the variations
remain inside a specific oscillator's tolerance range, the CAN nodes are able to compensate for the
different bit rates by periodically resynchronizing to the bit stream.
According to the CAN specification, the bit time is divided into four segments (see Figure
14-4 on page 378): the Synchronization Segment, the Propagation Time Segment, the Phase Buffer
Segment 1, and the Phase Buffer Segment 2. Each segment consists of a specific, programmable
number of time quanta (see Table 14-1 on page 378). The length of the time quantum (tq), which is
the basic time unit of the bit time, is defined by the CAN controller's input clock (fsys) and the Baud
Rate Prescaler (BRP):
tq = BRP / fsys
The fsys input clock is 8 MHz.
The Synchronization Segment Sync is that part of the bit time where edges of the CAN bus level
are expected to occur; the distance between an edge that occurs outside of Sync and the Sync is
called the phase error of that edge.
The Propagation Time Segment Prop is intended to compensate for the physical delay times within
the CAN network.
The Phase Buffer Segments Phase1 and Phase2 surround the Sample Point.
The (Re-)Synchronization Jump Width (SJW) defines how far a resynchronization may move the
Sample Point inside the limits defined by the Phase Buffer Segments to compensate for edge phase
errors.
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A given bit rate may be met by different bit-time configurations, but for the proper function of the
CAN network, the physical delay times and the oscillator's tolerance range have to be considered.
Figure 14-4. CAN Bit Time
Nominal CAN Bit Time
a
b
TSEG1
Sync
Prop
TSEG2
Phase1
c
1 Time
Quantum
q)
(tq
Phase2
Sample
Point
a. TSEG1 = Prop + Phase1
b. TSEG2 = Phase2
c. Phase1 = Phase2 or Phase1 + 1 = Phase2
a
Table 14-1. CAN Protocol Ranges
Parameter
Range
Remark
BRP
[1 .. 64]
Defines the length of the time quantum tq. The CANBRPE register can
be used to extend the range to 1024.
Sync
1 tq
Fixed length, synchronization of bus input to system clock
Prop
[1 .. 8] tq
Compensates for the physical delay times
Phase1
[1 .. 8] tq
May be lengthened temporarily by synchronization
Phase2
[1 .. 8] tq
May be shortened temporarily by synchronization
SJW
[1 .. 4] tq
May not be longer than either Phase Buffer Segment
a. This table describes the minimum programmable ranges required by the CAN protocol.
The bit timing configuration is programmed in two register bytes in the CANBIT register. In the
CANBIT register, the four components TSEG2, TSEG1, SJW, and BRP have to be programmed to a
numerical value that is one less than its functional value; so instead of values in the range of [1..n],
values in the range of [0..n-1] are programmed. That way, for example, SJW (functional range of
[1..4]) is represented by only two bits in the SJW bit field. Table 14-2 shows the relationship between
the CANBIT register values and the parameters.
Table 14-2. CANBIT Register Values
CANBIT Register Field
Setting
TSEG2
Phase2 - 1
TSEG1
Prop + Phase1 - 1
SJW
SJW - 1
BRP
BRP
Therefore, the length of the bit time is (programmed values):
[TSEG1 + TSEG2 + 3] × tq
or (functional values):
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[Sync + Prop + Phase1 + Phase2] × tq
The data in the CANBIT register is the configuration input of the CAN protocol controller. The baud
rate prescaler (configured by the BRP field) defines the length of the time quantum, the basic time
unit of the bit time; the bit timing logic (configured by TSEG1, TSEG2, and SJW) defines the number
of time quanta in the bit time.
The processing of the bit time, the calculation of the position of the sample point, and occasional
synchronizations are controlled by the CAN controller and are evaluated once per time quantum.
The CAN controller translates messages to and from frames. In addition, the controller generates
and discards the enclosing fixed format bits, inserts and extracts stuff bits, calculates and checks
the CRC code, performs the error management, and decides which type of synchronization is to be
used. The bit value is received or transmitted at the sample point. The information processing time
(IPT) is the time after the sample point needed to calculate the next bit to be transmitted on the CAN
bus. The IPT includes any of the following: retrieving the next data bit, handling a CRC bit, determining
if bit stuffing is required, generating an error flag or simply going idle.
The IPT is application-specific but may not be longer than 2 tq; the CAN's IPT is 0 tq. Its length is
the lower limit of the programmed length of Phase2. In case of synchronization, Phase2 may be
shortened to a value less than IPT, which does not affect bus timing.
14.2.16
Calculating the Bit Timing Parameters
Usually, the calculation of the bit timing configuration starts with a required bit rate or bit time. The
resulting bit time (1/bit rate) must be an integer multiple of the system clock period.
The bit time may consist of 4 to 25 time quanta. Several combinations may lead to the required bit
time, allowing iterations of the following steps.
The first part of the bit time to be defined is Prop. Its length depends on the delay times measured
in the system. A maximum bus length as well as a maximum node delay has to be defined for
expandable CAN bus systems. The resulting time for Prop is converted into time quanta (rounded
up to the nearest integer multiple of tq).
Sync is 1 tq long (fixed), which leaves (bit time - Prop - 1) tq for the two Phase Buffer Segments. If
the number of remaining tq is even, the Phase Buffer Segments have the same length, that is,
Phase2 = Phase1, else Phase2 = Phase1 + 1.
The minimum nominal length of Phase2 has to be regarded as well. Phase2 may not be shorter
than the CAN controller's Information Processing Time, which is, depending on the actual
implementation, in the range of [0..2] tq.
The length of the synchronization jump width is set to the least of 4, Phase1 or Phase2.
The oscillator tolerance range necessary for the resulting configuration is calculated by the formula
given below:
(1 − df ) × fnom ≤ fosc ≤ (1 + df ) × fnom
where:
df
≤
(Phase _ seg1, Phase _ seg2) min
2 × (13 × tbit − Phase _ Seg 2)
■ df = Maximum tolerance of oscillator frequency
■ fosc
Actual=oscillator
df =max
2 × dffrequency
× fnom
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■ fnom = Nominal oscillator frequency
− )df
× fnom
≤ fosc
+ account
× the
fnom
frequency
tolerance
must
following formulas:
(Maximum
)df
1 −(1df
× )fnom
≤ fosc
≤ (take
1≤ +(1into
df
× )fnom
(Phase
_ seg
1, Phase
_ seg
2) min
(Phase
_ seg
1, Phase
_ seg
2) min
df df
≤ ≤ 2 × (13 × tbit − Phase _ Seg 2)
2 × (13 × tbit − Phase _ Seg 2)
× df
× fnom
df df
maxmax
= 2=× 2df
× fnom
where:
■ Phase1 and Phase2 are from Table 14-1 on page 378
■ tbit = Bit Time
■ dfmax = Maximum difference between two oscillators
If more than one configuration is possible, that configuration allowing the highest oscillator tolerance
range should be chosen.
CAN nodes with different system clocks require different configurations to come to the same bit
rate. The calculation of the propagation time in the CAN network, based on the nodes with the
longest delay times, is done once for the whole network.
The CAN system's oscillator tolerance range is limited by the node with the lowest tolerance range.
The calculation may show that bus length or bit rate have to be decreased or that the oscillator
frequencies' stability has to be increased in order to find a protocol-compliant configuration of the
CAN bit timing.
14.2.16.1 Example for Bit Timing at High Baud Rate
In this example, the frequency of CAN clock is 8 MHz, and the bit rate is 1 Mbps.
bit time = 1 µs = n * tq = 8 *
tq = 125 ns
tq = (Baud rate Prescaler)/CAN
Baud rate Prescaler = tq * CAN
Baud rate Prescaler = 125E-9 *
tq
Clock
Clock
8E6 = 1
tSync = 1 * tq = 125 ns
\\fixed at 1 time quanta
delay
delay
delay
tProp
\\375 is next integer multiple of tq
of bus driver 50 ns
of receiver circuit 30 ns
of bus line (40m) 220 ns
375 ns = 3 * tq
bit time
bit time
tPhase 1
tPhase 1
tPhase 1
=
=
+
+
+
tSync +
tSync +
tPhase2
tPhase2
tPhase2
tTSeg1 + tTSeg2 = 8 * tq
tProp + tPhase 1 + tPhase2
= bit time - tSync - tProp
= (8 * tq) - (1 * tq) - (3 * tq)
= 4 * tq
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tPhase1 = 2 * tq
tPhase2 = 2 * tq
tTSeg1
tTSeg1
tTSeg1
tTSeg2
tTSeg2
tTSeg2
=
=
=
=
=
=
\\tPhase2 = tPhase1
tProp + tPhase1
(3 * tq) + (2 * tq)
5 * tq
tPhase2
(Information Processing Time + 2) × tq
2 * tq
\\Assumes IPT=0
tSJW = 2 * tq
\\Least of 4, Phase1 and Phase2 = 1
In the above example, the bit field values for the CANBIT register are:
= TSeg2 -1
TSEG2
= 2-1
=1
= TSeg1 -1
TSEG1
= 5-1
=4
= SJW -1
SJW
= 2-1
=1
= Baud rate prescaler - 1
BRP
= 1-1
=0
The final value programmed into the CANBIT register = 0x1440.
14.2.16.2 Example for Bit Timing at Low Baud Rate
In this example, the frequency of the CAN clock is 8 MHz, and the bit rate is 100 Kbps.
bit time = 10 µs = n * tq = 10 * tq
tq = 1 µs
tq = (Baud rate Prescaler)/CAN Clock
Baud rate Prescaler = tq * CAN Clock
Baud rate Prescaler = 1E-6 * 8E6 = 8
tSync = 1 * tq = 1 µs
\\fixed at 1 time quanta
delay
delay
delay
tProp
\\1 µs is next integer multiple of tq
of bus driver 200 ns
of receiver circuit 80 ns
of bus line (40m) 220 ns
1 µs = 1 * tq
bit time
bit time
tPhase 1
tPhase 1
tPhase 1
=
=
+
+
+
tSync +
tSync +
tPhase2
tPhase2
tPhase2
tTSeg1 + tTSeg2 = 10 * tq
tProp + tPhase 1 + tPhase2
= bit time - tSync - tProp
= (10 * tq) - (1 * tq) - (1 * tq)
= 8 * tq
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tPhase1 = 4 * tq
tPhase2 = 4 * tq
tTSeg1
tTSeg1
tTSeg1
tTSeg2
tTSeg2
tTSeg2
=
=
=
=
=
=
\\tPhase2 = tPhase1
tProp + tPhase1
(1 * tq) + (4 * tq)
5 * tq
tPhase2
(Information Processing Time + 4) * tq
4 * tq
\\Assumes IPT=0
tSJW = 4 * tq
\\Least of 4, Phase1, and Phase2
= TSeg2 -1
TSEG2
= 4-1
=3
= TSeg1 -1
TSEG1
= 5-1
=4
= SJW -1
SJW
= 4-1
=3
= Baud rate prescaler - 1
BRP
= 8-1
=7
The final value programmed into the CANBIT register = 0x34C7.
14.3
Register Map
Table 14-3 on page 382 lists the registers. All addresses given are relative to the CAN base address
of:
■ CAN0: 0x4004.0000
■ CAN1: 0x4004.1000
■ CAN2: 0x4004.2000
Table 14-3. CAN Register Map
Offset
Name
Type
Reset
Description
See
page
0x000
CANCTL
R/W
0x0000.0001
CAN Control
385
0x004
CANSTS
R/W
0x0000.0000
CAN Status
387
0x008
CANERR
RO
0x0000.0000
CAN Error Counter
390
0x00C
CANBIT
R/W
0x0000.2301
CAN Bit Timing
391
0x010
CANINT
RO
0x0000.0000
CAN Interrupt
393
0x014
CANTST
R/W
0x0000.0000
CAN Test
394
0x018
CANBRPE
R/W
0x0000.0000
CAN Baud Rate Prescaler Extension
396
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Table 14-3. CAN Register Map (continued)
Description
See
page
Offset
Name
Type
Reset
0x020
CANIF1CRQ
R/W
0x0000.0001
CAN IF1 Command Request
397
0x024
CANIF1CMSK
R/W
0x0000.0000
CAN IF1 Command Mask
398
0x028
CANIF1MSK1
R/W
0x0000.FFFF
CAN IF1 Mask 1
400
0x02C
CANIF1MSK2
R/W
0x0000.FFFF
CAN IF1 Mask 2
401
0x030
CANIF1ARB1
R/W
0x0000.0000
CAN IF1 Arbitration 1
402
0x034
CANIF1ARB2
R/W
0x0000.0000
CAN IF1 Arbitration 2
403
0x038
CANIF1MCTL
R/W
0x0000.0000
CAN IF1 Message Control
405
0x03C
CANIF1DA1
R/W
0x0000.0000
CAN IF1 Data A1
407
0x040
CANIF1DA2
R/W
0x0000.0000
CAN IF1 Data A2
407
0x044
CANIF1DB1
R/W
0x0000.0000
CAN IF1 Data B1
407
0x048
CANIF1DB2
R/W
0x0000.0000
CAN IF1 Data B2
407
0x080
CANIF2CRQ
R/W
0x0000.0001
CAN IF2 Command Request
397
0x084
CANIF2CMSK
R/W
0x0000.0000
CAN IF2 Command Mask
398
0x088
CANIF2MSK1
R/W
0x0000.FFFF
CAN IF2 Mask 1
400
0x08C
CANIF2MSK2
R/W
0x0000.FFFF
CAN IF2 Mask 2
401
0x090
CANIF2ARB1
R/W
0x0000.0000
CAN IF2 Arbitration 1
402
0x094
CANIF2ARB2
R/W
0x0000.0000
CAN IF2 Arbitration 2
403
0x098
CANIF2MCTL
R/W
0x0000.0000
CAN IF2 Message Control
405
0x09C
CANIF2DA1
R/W
0x0000.0000
CAN IF2 Data A1
407
0x0A0
CANIF2DA2
R/W
0x0000.0000
CAN IF2 Data A2
407
0x0A4
CANIF2DB1
R/W
0x0000.0000
CAN IF2 Data B1
407
0x0A8
CANIF2DB2
R/W
0x0000.0000
CAN IF2 Data B2
407
0x100
CANTXRQ1
RO
0x0000.0000
CAN Transmission Request 1
408
0x104
CANTXRQ2
RO
0x0000.0000
CAN Transmission Request 2
408
0x120
CANNWDA1
RO
0x0000.0000
CAN New Data 1
409
0x124
CANNWDA2
RO
0x0000.0000
CAN New Data 2
409
0x140
CANMSG1INT
RO
0x0000.0000
CAN Message 1 Interrupt Pending
410
0x144
CANMSG2INT
RO
0x0000.0000
CAN Message 2 Interrupt Pending
410
0x160
CANMSG1VAL
RO
0x0000.0000
CAN Message 1 Valid
411
0x164
CANMSG2VAL
RO
0x0000.0000
CAN Message 2 Valid
411
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14.4
CAN Register Descriptions
The remainder of this section lists and describes the CAN registers, in numerical order by address
offset. There are two sets of Interface Registers that are used to access the Message Objects in
the Message RAM: CANIF1x and CANIF2x. The function of the two sets are identical and are used
to queue transactions.
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Register 1: CAN Control (CANCTL), offset 0x000
This control register initializes the module and enables test mode and interrupts.
The bus-off recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by setting
or clearing INIT. If the device goes bus-off, it sets INIT, stopping all bus activities. Once INIT
has been cleared by the CPU, the device then waits for 129 occurrences of Bus Idle (129 * 11
consecutive High bits) before resuming normal operations. At the end of the bus-off recovery
sequence, the Error Management Counters are reset.
During the waiting time after INIT is cleared, each time a sequence of 11 High bits has been
monitored, a BITERROR0 code is written to the CANSTS register (the LEC field = 0x5), enabling
the CPU to readily check whether the CAN bus is stuck Low or continuously disturbed, and to monitor
the proceeding of the bus-off recovery sequence.
CAN Control (CANCTL)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
CAN2 base: 0x4004.2000
Offset 0x000
Type R/W, reset 0x0000.0001
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
TEST
CCE
DAR
reserved
EIE
SIE
IE
INIT
R/W
0
R/W
0
R/W
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
TEST
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Test Mode Enable
0: Normal operation
1: Test mode
6
CCE
R/W
0
Configuration Change Enable
0: Do not allow write access to the CANBIT register.
1: Allow write access to the CANBIT register if the INIT bit is 1.
5
DAR
R/W
0
Disable Automatic-Retransmission
0: Auto-retransmission of disturbed messages is enabled.
1: Auto-retransmission is disabled.
4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
3
EIE
R/W
0
Description
Error Interrupt Enable
0: Disabled. No error status interrupt is generated.
1: Enabled. A change in the BOFF or EWARN bits in the CANSTS register
generates an interrupt.
2
SIE
R/W
0
Status Interrupt Enable
0: Disabled. No status interrupt is generated.
1: Enabled. An interrupt is generated when a message has successfully
been transmitted or received, or a CAN bus error has been detected. A
change in the TXOK, RXOK or LEC bits in the CANSTS register generates
an interrupt.
1
IE
R/W
0
CAN Interrupt Enable
0: Interrupts disabled.
1: Interrupts enabled.
0
INIT
R/W
1
Initialization
0: Normal operation.
1: Initialization started.
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Register 2: CAN Status (CANSTS), offset 0x004
Important: Use caution when reading this register. Performing a read may change bit status.
The status register contains information for interrupt servicing such as Bus-Off, error count threshold,
and error types.
The LEC field holds the code that indicates the type of the last error to occur on the CAN bus. This
field is cleared when a message has been transferred (reception or transmission) without error. The
unused error code 7 may be written by the CPU to manually set this field to an invalid error so that
it can be checked for a change later.
An error interrupt is generated by the BOFF and EWARN bits and a status interrupt is generated by
the RXOK, TXOK, and LEC bits, if the corresponding enable bits in the CAN Control (CANCTL)
register are set. A change of the EPASS bit or a write to the RXOK, TXOK, or LEC bits does not
generate an interrupt.
Reading the CAN Status (CANSTS) register clears the CAN Interrupt (CANINT) register, if it is
pending.
CAN Status (CANSTS)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
CAN2 base: 0x4004.2000
Offset 0x004
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
BOFF
RO
0
RO
0
RO
0
7
6
5
4
3
BOFF
EWARN
EPASS
RXOK
TXOK
RO
0
RO
0
RO
0
R/W
0
R/W
0
LEC
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Bus-Off Status
0: CAN controller is not in bus-off state.
1: CAN controller is in bus-off state.
6
EWARN
RO
0
Warning Status
0: Both error counters are below the error warning limit of 96.
1: At least one of the error counters has reached the error warning limit
of 96.
5
EPASS
RO
0
Error Passive
0: The CAN module is in the Error Active state, that is, the receive or
transmit error count is less than or equal to 127.
1: The CAN module is in the Error Passive state, that is, the receive or
transmit error count is greater than 127.
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Bit/Field
Name
Type
Reset
4
RXOK
R/W
0
Description
Received a Message Successfully
0: Since this bit was last cleared, no message has been successfully
received.
1: Since this bit was last cleared, a message has been successfully
received, independent of the result of the acceptance filtering.
This bit is never cleared by the CAN module.
3
TXOK
R/W
0
Transmitted a Message Successfully
0: Since this bit was last cleared, no message has been successfully
transmitted.
1: Since this bit was last cleared, a message has been successfully
transmitted error-free and acknowledged by at least one other node.
This bit is never cleared by the CAN module.
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Stellaris® LM3S8530 Microcontroller
Bit/Field
Name
Type
Reset
2:0
LEC
R/W
0x0
Description
Last Error Code
This is the type of the last error to occur on the CAN bus.
Value
Definition
0x0
No Error
0x1
Stuff Error
More than 5 equal bits in a sequence have occurred in a part
of a received message where this is not allowed.
0x2
Format Error
A fixed format part of the received frame has the wrong
format.
0x3
ACK Error
The message transmitted was not acknowledged by another
node.
0x4
Bit 1 Error
When a message is transmitted, the CAN controller monitors
the data lines to detect any conflicts. When the arbitration
field is transmitted, data conflicts are a part of the arbitration
protocol. When other frame fields are transmitted, data
conflicts are considered errors.
A Bit 1 Error indicates that the device wanted to send a High
level (logical 1) but the monitored bus value was Low (logical
0).
0x5
Bit 0 Error
A Bit 0 Error indicates that the device wanted to send a Low
level (logical 0), but the monitored bus value was High (logical
1).
During bus-off recovery, this status is set each time a
sequence of 11 High bits has been monitored. This enables
the CPU to monitor the proceeding of the bus-off recovery
sequence without any disturbances to the bus.
0x6
CRC Error
The CRC checksum was incorrect in the received message,
indicating that the calculated value received did not match
the calculated CRC of the data.
0x7
No Event
When the LEC bit shows this value, no CAN bus event was
detected since the CPU wrote this value to LEC.
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Controller Area Network (CAN) Module
Register 3: CAN Error Counter (CANERR), offset 0x008
This register contains the error counter values, which can be used to analyze the cause of an error.
CAN Error Counter (CANERR)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
CAN2 base: 0x4004.2000
Offset 0x008
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RP
Type
Reset
RO
0
REC
TEC
RO
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
RP
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Received Error Passive
0: The Receive Error counter is below the Error Passive level (127 or
less).
1: The Receive Error counter has reached the Error Passive level (128
or greater).
14:8
REC
RO
0x00
Receive Error Counter
State of the receiver error counter (0 to 127).
7:0
TEC
RO
0x00
Transmit Error Counter
State of the transmit error counter (0 to 255).
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Stellaris® LM3S8530 Microcontroller
Register 4: CAN Bit Timing (CANBIT), offset 0x00C
This register is used to program the bit width and bit quantum. Values are programmed to the system
clock frequency. This register is write-enabled by setting the CCE and INIT bits in the CANCTL
register. See “Bit Time and Bit Rate” on page 377 for more information.
CAN Bit Timing (CANBIT)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
CAN2 base: 0x4004.2000
Offset 0x00C
Type R/W, reset 0x0000.2301
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
R/W
0
R/W
0
R/W
0
R/W
1
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
reserved
Type
Reset
TSEG2
reserved
Type
Reset
RO
0
R/W
0
R/W
1
TSEG1
Bit/Field
Name
Type
Reset
31:15
reserved
RO
0x0000
14:12
TSEG2
R/W
0x2
SJW
BRP
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Time Segment after Sample Point
0x00-0x07: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
So, for example, a reset value of 0x2 defines that there is 3 (2+1) bit
time quanta defined for Phase_Seg2 (see Figure 14-4 on page 378).
The bit time quanta is defined by the BRP field.
11:8
TSEG1
R/W
0x3
Time Segment Before Sample Point
0x00-0x0F: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
So, for example, the reset value of 0x3 defines that there is 4 (3+1) bit
time quanta defined for Phase_Seg1 (see Figure 14-4 on page 378).
The bit time quanta is define by the BRP field.
7:6
SJW
R/W
0x0
(Re)Synchronization Jump Width
0x00-0x03: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
During the start of frame (SOF), if the CAN controller detects a phase
error (misalignment), it can adjust the length of TSEG2 or TSEG1 by the
value in SJW. So the reset value of 0 adjusts the length by 1 bit time
quanta.
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Bit/Field
Name
Type
Reset
5:0
BRP
R/W
0x1
Description
Baud Rate Prescaler
The value by which the oscillator frequency is divided for generating the
bit time quanta. The bit time is built up from a multiple of this quantum.
0x00-0x03F: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
BRP defines the number of CAN clock periods that make up 1 bit time
quanta, so the reset value is 2 bit time quanta (1+1).
The CANBRPE register can be used to further divide the bit time.
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Stellaris® LM3S8530 Microcontroller
Register 5: CAN Interrupt (CANINT), offset 0x010
This register indicates the source of the interrupt.
If several interrupts are pending, the CAN Interrupt (CANINT) register points to the pending interrupt
with the highest priority, disregarding the order in which the interrupts occurred. An interrupt remains
pending until the CPU has cleared it. If the INTID field is not 0x0000 (the default) and the IE bit in
the CANCTL register is set, the interrupt is active. The interrupt line remains active until the INTID
field is cleared by reading the CANSTS register, or until the IE bit in the CANCTL register is cleared.
Note:
Reading the CAN Status (CANSTS) register clears the CAN Interrupt (CANINT) register,
if it is pending.
CAN Interrupt (CANINT)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
CAN2 base: 0x4004.2000
Offset 0x010
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
INTID
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
INTID
RO
0x0000
Interrupt Identifier
The number in this field indicates the source of the interrupt.
Value
Definition
0x0000
No interrupt pending
0x0001-0x0020
Number of the message object that
caused the interrupt
0x0021-0x7FFF
Reserved
0x8000
Status Interrupt
0x8001-0xFFFF
Reserved
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Register 6: CAN Test (CANTST), offset 0x014
This is the test mode register for self-test and external pin access. It is write-enabled by setting the
TEST bit in the CANCTL register. Different test functions may be combined, however, CAN transfers
will be affected if the TX bits in this register are not zero.
CAN Test (CANTST)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
CAN2 base: 0x4004.2000
Offset 0x014
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
LBACK
SILENT
BASIC
RO
0
RO
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RX
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
RX
RO
0
TX
R/W
0
R/W
0
reserved
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Receive Observation
Displays the value on the CANnRx pin.
6:5
TX
R/W
0x0
Transmit Control
Overrides control of the CANnTx pin.
Value
Description
0x0
CAN Module Control
CANnTx is controlled by the CAN module; default
operation
0x1
Sample Point
The sample point is driven on the CANnTx signal. This
mode is useful to monitor bit timing.
0x2
Driven Low
CANnTx drives a low value. This mode is useful for
checking the physical layer of the CAN bus.
0x3
Driven High
CANnTx drives a high value. This mode is useful for
checking the physical layer of the CAN bus.
4
LBACK
R/W
0
Loopback Mode
0: Disabled.
1: Enabled. In loopback mode, the data from the transmitter is routed
into the receiver. Any data on the receive input is ignored.
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Bit/Field
Name
Type
Reset
Description
3
SILENT
R/W
0
Silent Mode
Do not transmit data; monitor the bus. Also known as Bus Monitor mode.
0: Disabled.
1: Enabled.
2
BASIC
R/W
0
Basic Mode
0: Disabled.
1: Use CANIF1 registers as transmit buffer, and use CANIF2 registers
as receive buffer.
1:0
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Controller Area Network (CAN) Module
Register 7: CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018
This register is used to further divide the bit time set with the BRP bit in the CANBIT register. It is
write-enabled by setting the CCE bit in the CANCTL register.
CAN Baud Rate Prescaler Extension (CANBRPE)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
CAN2 base: 0x4004.2000
Offset 0x018
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0x0000.000
3:0
BRPE
R/W
0x0
BRPE
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Baud Rate Prescaler Extension
0x00-0x0F: Extend the BRP bit in the CANBIT register to values up to
1023. The actual interpretation by the hardware is one more than the
value programmed by BRPE (MSBs) and BRP (LSBs).
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Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080
A message transfer is started as soon as there is a write of the message object number to the MNUM
field when the TXRQST bit in the CANIF1MCTL register is set. With this write operation, the BUSY
bit is automatically set to indicate that a transfer between the CAN Interface Registers and the
internal message RAM is in progress. After a wait time of 3 to 6 CAN_CLK periods, the transfer
between the interface register and the message RAM completes, which then clears the BUSY bit.
CAN IF1 Command Request (CANIF1CRQ)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
CAN2 base: 0x4004.2000
Offset 0x020
Type R/W, reset 0x0000.0001
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
reserved
Type
Reset
BUSY
Type
Reset
RO
0
reserved
RO
0
MNUM
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
BUSY
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Busy Flag
0: Cleared when read/write action has finished.
1: Set when a write occurs to the message number in this register.
14:6
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:0
MNUM
R/W
0x01
Message Number
Selects one of the 32 message objects in the message RAM for data
transfer. The message objects are numbered from 1 to 32.
Value
Description
0x00
Reserved
0 is not a valid message number; it is interpreted
as 0x20, or object 32.
0x01-0x20
Message Number
Indicates specified message object 1 to 32.
0x21-0x3F
Reserved
Not a valid message number; values are shifted and
it is interpreted as 0x01-0x1F.
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Controller Area Network (CAN) Module
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084
Reading the Command Mask registers provides status for various functions. Writing to the Command
Mask registers specifies the transfer direction and selects which buffer registers are the source or
target of the data transfer.
Note that when a read from the message object buffer occurs when the WRNRD bit is clear and the
CLRINTPND and/or NEWDAT bits are set, the interrupt pending and/or new data flags in the message
object buffer are cleared.
CAN IF1 Command Mask (CANIF1CMSK)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
CAN2 base: 0x4004.2000
Offset 0x024
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
2
1
0
DATAA
DATAB
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
WRNRD
R/W
0
WRNRD
MASK
ARB
R/W
0
R/W
0
R/W
0
RO
0
CONTROL CLRINTPND
R/W
0
R/W
0
NEWDAT /
TXRQST
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Write, Not Read
Transfer the message object address specified by the CAN Command
Request (CANIFnCRQ) register to the CAN message buffer registers.
Note:
6
MASK
R/W
0
Interrupt pending and new data conditions in the message
buffer can be cleared by reading from the buffer (WRNRD = 0)
when the CLRINTPND and/or NEWDAT bits are set.
Access Mask Bits
0: Mask bits unchanged.
1: Transfer IDMASK + DIR + MXTD of the message object into the
Interface registers.
5
ARB
R/W
0
Access Arbitration Bits
0: Arbitration bits unchanged.
1: Transfer ID + DIR + XTD + MSGVAL of the message object into the
Interface registers.
4
CONTROL
R/W
0
Access Control Bits
0: Control bits unchanged.
1: Transfer control bits from the CANIFnMCTL register into the Interface
registers.
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Bit/Field
Name
Type
Reset
3
CLRINTPND
R/W
0
Description
Clear Interrupt Pending Bit
If WRNRD is set, this bit controls whether the INTPND bit in the
CANIFnMCTL register is changed.
0: The INTPND bit in the message object remains unchanged.
1: The INTPND bit is cleared in the message object.
If WRNRD is clear and this bit is clear, the interrupt pending status is
transferred from the message buffer into the CANIFnMCTL register.
If WRNRD is clear and this bit is set, the interrupt pending status is cleared
in the message buffer. Note that the value of this bit that is transferred
to the CANIFnMCTL register always reflects the status of the bits before
clearing.
2
NEWDAT / TXRQST
R/W
0
NEWDAT / TXRQST Bit
If WRNRD is set, this bit can act as a TXRQST bit and request a
transmission. Note that when this bit is set, the TXRQST bit in the
CANIFnMCTL register is ignored.
0: Transmission is not requested
1: Begin a transmission
If WRNRD is clear and this bit is clear, the value of the new data status
is transferred from the message buffer into the CANIFnMCTL register.
If WRNRD is clear and this bit is set, the new data status is cleared in the
message buffer. Note that the value of this bit that is transferred to the
CANIFnMCTL register always reflects the status of the bits before
clearing.
1
DATAA
R/W
0
Access Data Byte 0 to 3
When WRNRD = 1:
0: Data bytes 0-3 are unchanged.
1: Transfer data bytes 0-3 in message object to CANIFnDA1 and
CANIFnDA2.
When WRNRD = 0:
0: Data bytes 0-3 are unchanged.
1: Transfer data bytes 0-3 in CANIFnDA1 and CANIFnDA2 to the
message object.
0
DATAB
R/W
0
Access Data Byte 4 to 7
When WRNRD = 1:
0: Data bytes 4-7 are unchanged.
1: Transfer data bytes 4-7 in message object to CANIFnDB1 and
CANIFnDB2.
When WRNRD = 0:
0: Data bytes 4-7 are unchanged.
1: Transfer data bytes 4-7 in CANIFnDB1 and CANIFnDB2 to the
message object.
June 22, 2010
399
Texas Instruments-Production Data
Controller Area Network (CAN) Module
Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088
The mask information provided in this register accompanies the data (CANIFnDAn), arbitration
information (CANIFnARBn), and control information (CANIFnMCTL) to the message object in the
message RAM. The mask is used with the ID bit in the CANIFnARBn register for acceptance
filtering. Additional mask information is contained in the CANIFnMSK2 register.
CAN IF1 Mask 1 (CANIF1MSK1)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
CAN2 base: 0x4004.2000
Offset 0x028
Type R/W, reset 0x0000.FFFF
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
reserved
Type
Reset
MSK
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
MSK
R/W
0xFFFF
Identifier Mask
When using a 29-bit identifier, these bits are used for bits [15:0] of the
ID. The MSK field in the CANIFnMSK2 register are used for bits [28:16]
of the ID. When using an 11-bit identifier, these bits are ignored.
0: The corresponding identifier field (ID) in the message object cannot
inhibit the match in acceptance filtering.
1: The corresponding identifier field (ID) is used for acceptance filtering.
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Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C
This register holds extended mask information that accompanies the CANIFnMSK1 register.
CAN IF1 Mask 2 (CANIF1MSK2)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
CAN2 base: 0x4004.2000
Offset 0x02C
Type R/W, reset 0x0000.FFFF
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
MXTD
MDIR
reserved
R/W
1
R/W
1
RO
1
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
reserved
Type
Reset
Type
Reset
MSK
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
MXTD
R/W
0x1
R/W
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Mask Extended Identifier
0: The extended identifier bit (XTD in the CANIFnARB2 register) has
no effect on the acceptance filtering.
1: The extended identifier bit XTD is used for acceptance filtering.
14
MDIR
R/W
0x1
Mask Message Direction
0: The message direction bit (DIR in the CANIFnARB2 register) has
no effect for acceptance filtering.
1: The message direction bit DIR is used for acceptance filtering.
13
reserved
RO
0x1
12:0
MSK
R/W
0xFF
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Identifier Mask
When using a 29-bit identifier, these bits are used for bits [28:16] of the
ID. The MSK field in the CANIFnMSK1 register are used for bits [15:0]
of the ID. When using an 11-bit identifier, MSK[12:2] are used for bits
[10:0] of the ID.
0: The corresponding identifier field (ID) in the message object cannot
inhibit the match in acceptance filtering.
1: The corresponding identifier field (ID) is used for acceptance filtering.
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Texas Instruments-Production Data
Controller Area Network (CAN) Module
Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030
Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090
These registers hold the identifiers for acceptance filtering.
CAN IF1 Arbitration 1 (CANIF1ARB1)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
CAN2 base: 0x4004.2000
Offset 0x030
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
ID
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
ID
R/W
0x0000
Message Identifier
This bit field is used with the ID field in the CANIFnARB2 register to
create the message identifier.
When using a 29-bit identifier, bits 15:0 of the CANIFnARB1 register
are [15:0] of the ID, while bits 12:0 of the CANIFnARB2 register are
[28:16] of the ID.
When using an 11-bit identifier, these bits are not used.
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June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034
Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094
These registers hold information for acceptance filtering.
CAN IF1 Arbitration 2 (CANIF1ARB2)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
CAN2 base: 0x4004.2000
Offset 0x034
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
MSGVAL
XTD
DIR
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
Type
Reset
ID
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
MSGVAL
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Message Valid
0: The message object is ignored by the message handler.
1: The message object is configured and ready to be considered by the
message handler within the CAN controller.
All unused message objects should have this bit cleared during
initialization and before clearing the INIT bit in the CANCTL register.
The MSGVAL bit must also be cleared before any of the following bits
are modified or if the message object is no longer required: the ID fields
in the CANIFnARBn registers, the XTD and DIR bits in the CANIFnARB2
register, or the DLC field in the CANIFnMCTL register.
14
XTD
R/W
0
Extended Identifier
0: An 11-bit Standard Identifier is used for this message object.
1: A 29-bit Extended Identifier is used for this message object.
13
DIR
R/W
0
Message Direction
0: Receive. When the TXRQST bit in the CANIFnMCTL register is set,
a remote frame with the identifier of this message object is received.
On reception of a data frame with matching identifier, that message is
stored in this message object.
1: Transmit. When the TXRQST bit in the CANIFnMCTL register is set,
the respective message object is transmitted as a data frame. On
reception of a remote frame with matching identifier, the TXRQST bit of
this message object is set (if RMTEN=1).
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Controller Area Network (CAN) Module
Bit/Field
Name
Type
Reset
Description
12:0
ID
R/W
0x000
Message Identifier
This bit field is used with the ID field in the CANIFnARB2 register to
create the message identifier.
When using a 29-bit identifier, ID[15:0] of the CANIFnARB1 register
are [15:0] of the ID, while these bits, ID[12:0], are [28:16] of the ID.
When using an 11-bit identifier, ID[12:2] are used for bits [10:0] of
the ID. The ID field in the CANIFnARB1 register is ignored.
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June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038
Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098
This register holds the control information associated with the message object to be sent to the
Message RAM.
CAN IF1 Message Control (CANIF1MCTL)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
CAN2 base: 0x4004.2000
Offset 0x038
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
UMASK
TXIE
RXIE
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RMTEN
TXRQST
EOB
R/W
0
R/W
0
R/W
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
NEWDAT MSGLST INTPND
Type
Reset
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15
NEWDAT
R/W
0
reserved
RO
0
RO
0
DLC
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
New Data
0: No new data has been written into the data portion of this message
object by the message handler since the last time this flag was cleared
by the CPU.
1: The message handler or the CPU has written new data into the data
portion of this message object.
14
MSGLST
R/W
0
Message Lost
0 : No message was lost since the last time this bit was cleared by the
CPU.
1: The message handler stored a new message into this object when
NEWDAT was set; the CPU has lost a message.
This bit is only valid for message objects when the DIR bit in the
CANIFnARB2 register clear (receive).
13
INTPND
R/W
0
Interrupt Pending
0: This message object is not the source of an interrupt.
1: This message object is the source of an interrupt. The interrupt
identifier in the CANINT register points to this message object if there
is not another interrupt source with a higher priority.
12
UMASK
R/W
0
Use Acceptance Mask
0: Mask ignored.
1: Use mask (MSK, MXTD, and MDIR bits in the CANIFnMSKn registers)
for acceptance filtering.
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Controller Area Network (CAN) Module
Bit/Field
Name
Type
Reset
11
TXIE
R/W
0
Description
Transmit Interrupt Enable
0: The INTPND bit in the CANIFnMCTL register is unchanged after a
successful transmission of a frame.
1: The INTPND bit in the CANIFnMCTL register is set after a successful
transmission of a frame.
10
RXIE
R/W
0
Receive Interrupt Enable
0: The INTPND bit in the CANIFnMCTL register is unchanged after a
successful reception of a frame.
1: The INTPND bit in the CANIFnMCTL register is set after a successful
reception of a frame.
9
RMTEN
R/W
0
Remote Enable
0: At the reception of a remote frame, the TXRQST bit in the
CANIFnMCTL register is left unchanged.
1: At the reception of a remote frame, the TXRQST bit in the
CANIFnMCTL register is set.
8
TXRQST
R/W
0
Transmit Request
0: This message object is not waiting for transmission.
1: The transmission of this message object is requested and is not yet
done.
7
EOB
R/W
0
End of Buffer
0: Message object belongs to a FIFO Buffer and is not the last message
object of that FIFO Buffer.
1: Single message object or last message object of a FIFO Buffer.
This bit is used to concatenate two or more message objects (up to 32)
to build a FIFO buffer. For a single message object (thus not belonging
to a FIFO buffer), this bit must be set.
6:4
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:0
DLC
R/W
0x0
Data Length Code
Value
Description
0x0-0x8
Specifies the number of bytes in the data frame.
0x9-0xF
Defaults to a data frame with 8 bytes.
The DLC field in the CANIFnMCTL register of a message object must
be defined the same as in all the corresponding objects with the same
identifier at other nodes. When the message handler stores a data frame,
it writes DLC to the value given by the received message.
406
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C
Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040
Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044
Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048
Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C
Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0
Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4
Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8
These registers contain the data to be sent or that has been received. In a CAN data frame, data
byte 0 is the first byte to be transmitted or received and data byte 7 is the last byte to be transmitted
or received. In CAN's serial bit stream, the MSB of each byte is transmitted first.
CAN IF1 Data A1 (CANIF1DA1)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
CAN2 base: 0x4004.2000
Offset 0x03C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
DATA
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
DATA
R/W
0x0000
Data
The CANIFnDA1 registers contain data bytes 1 and 0; CANIFnDA2
data bytes 3 and 2; CANIFnDB1 data bytes 5 and 4; and CANIFnDB2
data bytes 7 and 6.
June 22, 2010
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Controller Area Network (CAN) Module
Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100
Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104
The CANTXRQ1 and CANTXRQ2 registers hold the TXRQST bits of the 32 message objects. By
reading out these bits, the CPU can check which message object has a transmission request pending.
The TXRQST bit of a specific message object can be changed by three sources: (1) the CPU via the
CANIFnMCTL register, (2) the message handler state machine after the reception of a remote
frame, or (3) the message handler state machine after a successful transmission.
The CANTXRQ1 register contains the TXRQST bits of the first 16 message objects in the message
RAM; the CANTXRQ2 register contains the TXRQST bits of the second 16 message objects.
CAN Transmission Request 1 (CANTXRQ1)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
CAN2 base: 0x4004.2000
Offset 0x100
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
TXRQST
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
TXRQST
RO
0x0000
Transmission Request Bits
0: The corresponding message object is not waiting for transmission.
1: The transmission of the corresponding message object is requested
and is not yet done.
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June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Register 32: CAN New Data 1 (CANNWDA1), offset 0x120
Register 33: CAN New Data 2 (CANNWDA2), offset 0x124
The CANNWDA1 and CANNWDA2 registers hold the NEWDAT bits of the 32 message objects. By
reading these bits, the CPU can check which message object has its data portion updated. The
NEWDAT bit of a specific message object can be changed by three sources: (1) the CPU via the
CANIFnMCTL register, (2) the message handler state machine after the reception of a data frame,
or (3) the message handler state machine after a successful transmission.
The CANNWDA1 register contains the NEWDAT bits of the first 16 message objects in the message
RAM; the CANNWDA2 register contains the NEWDAT bits of the second 16 message objects.
CAN New Data 1 (CANNWDA1)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
CAN2 base: 0x4004.2000
Offset 0x120
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
NEWDAT
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
NEWDAT
RO
0x0000
New Data Bits
0: No new data has been written into the data portion of the
corresponding message object by the message handler since the last
time this flag was cleared by the CPU.
1: The message handler or the CPU has written new data into the data
portion of the corresponding message object.
June 22, 2010
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Controller Area Network (CAN) Module
Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140
Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144
The CANMSG1INT and CANMSG2INT registers hold the INTPND bits of the 32 message objects.
By reading these bits, the CPU can check which message object has an interrupt pending. The
INTPND bit of a specific message object can be changed through two sources: (1) the CPU via the
CANIFnMCTL register, or (2) the message handler state machine after the reception or transmission
of a frame.
This field is also encoded in the CANINT register.
The CANMSG1INT register contains the INTPND bits of the first 16 message objects in the message
RAM; the CANMSG2INT register contains the INTPND bits of the second 16 message objects.
CAN Message 1 Interrupt Pending (CANMSG1INT)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
CAN2 base: 0x4004.2000
Offset 0x140
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
INTPND
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
INTPND
RO
0x0000
Interrupt Pending Bits
0: The corresponding message object is not the source of an interrupt.
1: The corresponding message object is the source of an interrupt.
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Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160
Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164
The CANMSG1VAL and CANMSG2VAL registers hold the MSGVAL bits of the 32 message objects.
By reading these bits, the CPU can check which message object is valid. The message value of a
specific message object can be changed with the CANIFnMCTL register.
The CANMSG1VAL register contains the MSGVAL bits of the first 16 message objects in the message
RAM; the CANMSG2VAL register contains the MSGVAL bits of the second 16 message objects in
the message RAM.
CAN Message 1 Valid (CANMSG1VAL)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
CAN2 base: 0x4004.2000
Offset 0x160
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
MSGVAL
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
MSGVAL
RO
0x0000
Message Valid Bits
0: The corresponding message object is not configured and is ignored
by the message handler.
1: The corresponding message object is configured and should be
considered by the message handler.
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15
Ethernet Controller
®
The Stellaris Ethernet Controller consists of a fully integrated media access controller (MAC) and
network physical (PHY) interface. The Ethernet Controller conforms to IEEE 802.3 specifications
and fully supports 10BASE-T and 100BASE-TX standards.
®
The Stellaris Ethernet Controller module has the following features:
■ Conforms to the IEEE 802.3-2002 specification
– 10BASE-T/100BASE-TX IEEE-802.3 compliant. Requires only a dual 1:1 isolation transformer
interface to the line
– 10BASE-T/100BASE-TX ENDEC, 100BASE-TX scrambler/descrambler
– Full-featured auto-negotiation
■ Multiple operational modes
– Full- and half-duplex 100 Mbps
– Full- and half-duplex 10 Mbps
– Power-saving and power-down modes
■ Highly configurable
– Programmable MAC address
– LED activity selection
– Promiscuous mode support
– CRC error-rejection control
– User-configurable interrupts
■ Physical media manipulation
– Automatic MDI/MDI-X cross-over correction
– Register-programmable transmit amplitude
– Automatic polarity correction and 10BASE-T signal reception
15.1
Block Diagram
As shown in Figure 15-1 on page 413, the Ethernet Controller is functionally divided into two layers:
the Media Access Controller (MAC) layer and the Network Physical (PHY) layer. These layers
correspond to the OSI model layers 2 and 1. The CPU accesses the Ethernet Controller via the
MAC layer. The MAC layer provides transmit and receive processing for Ethernet frames. The MAC
layer also provides the interface to the PHY layer via an internal Media Independent Interface (MII).
The PHY layer communicates with the Ethernet bus.
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Figure 15-1. Ethernet Controller
ARM Cortex M3
Ethernet
Media Controller
Physical
Access
Layer Entity
Controller
MAC
(Layer 2)
Magnetics
RJ45
PHY
(Layer 1)
Figure 15-2 on page 413 shows more detail of the internal structure of the Ethernet Controller and
how the register set relates to various functions.
Figure 15-2. Ethernet Controller Block Diagram
Interrupt
Interrupt
Control
Receive
Control
MACRIS
MACIACK
MACIM
MACRCTL
MACNP
TXOP
Transmit
FIFO
Data
Access
Transmit
Encoding
Pulse
Shaping
Collision
Detect
Carrier
Sense
Receive
Decoding
Clock
Recovery
TXON
MDIX
MACDDATA
RXIP
Transmit
Control
MACTCTL
MACTHR
MACTR
Receive
FIFO
MII
Control
Individual
Address
MACIA0
MACIA1
Media Independent Interface
Management Register Set
MACMCTL
MACMDV
MACMTXD
MACMRXD
MR0
MR1
MR2
MR3
MR4
MR5
MR6
MR16
MR17
MR18
MR19
MR23
MR24
RXIN
Auto
Negotiation
XTALPPHY
Clock
Reference
XTALNPHY
LED0
LED1
15.2
Functional Description
Note:
A 12.4-kΩ resistor should be connected between the ERBIAS and ground. The 12.4-kΩ
resistor should have a 1% tolerance and should be located in close proximity to the ERBIAS
pin. Power dissipation in the resistor is low, so a chip resistor of any geometry may be used.
The functional description of the Ethernet Controller is discussed in the following sections.
15.2.1
MAC Operation
The following sections decribe the operation of the MAC unit, including an overview of the Ethernet
frame format, the MAC layer FIFOs, Ethernet transmission and reception options, and LED indicators.
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15.2.1.1
Ethernet Frame Format
Ethernet data is carried by Ethernet frames. The basic frame format is shown in Figure
15-3 on page 414.
Figure 15-3. Ethernet Frame
Preamble
7
Bytes
SFD Destination Address
1
Byte
6
Bytes
Source Address
Length/
Type
Data
FCS
6
Bytes
2
Bytes
46 - 1500
Bytes
4
Bytes
The seven fields of the frame are transmitted from left to right. The bits within the frame are
transmitted from least to most significant bit.
■ Preamble
The Preamble field is used to synchronize with the received frame’s timing. The preamble is 7
octets long.
■ Start Frame Delimiter (SFD)
The SFD field follows the preamble pattern and indicates the start of the frame. Its value is
1010.1011.
■ Destination Address (DA)
This field specifies destination addresses for which the frame is intended. The LSB (bit 16 of DA
oct 1 in the frame, see Table 15-1 on page 415) of the DA determines whether the address is an
individual (0), or group/multicast (1) address.
■ Source Address (SA)
The source address field identifies the station from which the frame was initiated.
■ Length/Type Field
The meaning of this field depends on its numeric value. This field can be interpreted as length
or type code. The maximum length of the data field is 1500 octets. If the value of the Length/Type
field is less than or equal to 1500 decimal, it indicates the number of MAC client data octets. If
the value of this field is greater than or equal to 1536 decimal, then it is type interpretation. The
meaning of the Length/Type field when the value is between 1500 and 1536 decimal is unspecified
by the IEEE 802.3 standard. However, the Ethernet Controller assumes type interpretation if the
value of the Length/Type field is greater than 1500 decimal. The definition of the Type field is
specified in the IEEE 802.3 standard. The first of the two octets in this field is most significant.
■ Data
The data field is a sequence of octets that is at least 46 in length, up to 1500 in length. Full data
transparency is provided so any values can appear in this field. A minimum frame size of 46
octets is required to meet the IEEE standard. If the frame size is too small, the Ethernet Controller
automatically appends extra bits (a pad), thus the pad can have a size of 0 to 46 octets. Data
padding can be disabled by clearing the PADEN bit in the Ethernet MAC Transmit Control
(MACTCTL) register.
For the Ethernet Controller, data sent/received can be larger than 1500 bytes without causing
a Frame Too Long error. Instead, a FIFO overrun error is reported using the FOV bit in the
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Ethernet MAC Raw Interrupt Status(MACRIS) register when the frame received is too large
to fit into the Ethernet Controller’s 2K RAM.
■ Frame Check Sequence (FCS)
The frame check sequence carries the cyclic redundancy check (CRC) value. The CRC is
computed over the destination address, source address, length/type, and data (including pad)
fields using the CRC-32 algorithm. The Ethernet Controller computes the FCS value one nibble
at a time. For transmitted frames, this field is automatically inserted by the MAC layer, unless
disabled by clearing the CRC bit in the MACTCTL register. For received frames, this field is
automatically checked. If the FCS does not pass, the frame is not placed in the RX FIFO, unless
the FCS check is disabled by clearing the BADCRC bit in the MACRCTL register.
15.2.1.2
MAC Layer FIFOs
The Ethernet Controller is capable of simultaneous transmission and reception. This feature is
enabled by setting the DUPLEX bit in the MACTCTL register.
For Ethernet frame transmission, a 2 KB transmit FIFO is provided that can be used to store a single
frame. While the IEEE 802.3 specification limits the size of an Ethernet frame's payload section to
1500 Bytes, the Ethernet Controller places no such limit. The full buffer can be used, for a payload
of up to 2032 bytes (as the first 16 bytes in the FIFO are reserved for destination address, source
address and length/type information).
For Ethernet frame reception, a 2-KB receive FIFO is provided that can be used to store multiple
frames, up to a maximum of 31 frames. If a frame is received, and there is insufficient space in the
RX FIFO, an overflow error is indicated using the FOV bit in the MACRIS register.
For details regarding the TX and RX FIFO layout, refer to Table 15-1 on page 415. Please note the
following difference between TX and RX FIFO layout. For the TX FIFO, the Data Length field in the
first FIFO word refers to the Ethernet frame data payload, as shown in the 5th to nth FIFO positions.
For the RX FIFO, the Frame Length field is the total length of the received Ethernet frame, including
the Length/Type bytes and the FCS bits.
If FCS generation is disabled by clearing the CRC bit in the MACTCTL register, the last word in the
TX FIFO must contain the FCS bytes for the frame that has been written to the FIFO.
Also note that if the length of the data payload section is not a multiple of 4, the FCS field is not be
aligned on a word boundary in the FIFO. However, for the RX FIFO the beginning of the next frame
is always on a word boundary.
Table 15-1. TX & RX FIFO Organization
FIFO Word Read/Write
Sequence
Word Bit Fields
TX FIFO (Write)
1st
7:0
Data Length Least Significant Frame Length Least
Byte
Significant Byte
15:8
Data Length Most Significant Frame Length Most Significant
Byte
Byte
23:16
DA oct 1
31:24
DA oct 2
7:0
DA oct 3
15:8
DA oct 4
23:16
DA oct 5
31:24
DA oct 6
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Table 15-1. TX & RX FIFO Organization (continued)
FIFO Word Read/Write
Sequence
Word Bit Fields
3rd
7:0
SA oct 1
15:8
SA oct 2
23:16
SA oct 3
31:24
SA oct 4
7:0
SA oct 5
15:8
SA oct 6
4th
5th to nth
last
Note:
15.2.1.3
TX FIFO (Write)
RX FIFO (Read)
23:16
Len/Type Most Significant Byte
31:24
Len/Type Least Significant Byte
7:0
data oct n
15:8
data oct n+1
23:16
data oct n+2
31:24
data oct n+3
7:0
FCS 1
15:8
FCS 2
23:16
FCS 3
31:24
FCS 4
If the CRC bit in the MACTCTL register is clear, the FCS bytes must be written with the
correct CRC. If the CRC bit is set, the Ethernet Controller automatically writes the FCS bytes.
Ethernet Transmission Options
At the MAC layer, the transmitter can be configured for both full-duplex and half-duplex operation
by using the DUPLEX bit in the MACTCTL register.
The Ethernet Controller automatically generates and inserts the Frame Check Sequence (FCS) at
the end of the transmit frame when the CRC bit in the MACTCTL register is set. However, for test
purposes, this feature can be disabled in order to generate a frame with an invalid CRC by clearing
the CRC bit.
The IEEE 802.3 specification requires that the Ethernet frame payload section be a minimum of 46
bytes. The Ethernet Controller automatically pads the data section if the payload data section loaded
into the FIFO is less than the minimum 46 bytes when the PADEN bit in the MACTCTL register is
set. This feature can be disabled by clearing the PADEN bit.
The transmitter must be enabled by setting the TXEN bit in the TCTL register.
15.2.1.4
Ethernet Reception Options
The Ethernet Controller RX FIFO should be cleared during software initialization. The receiver should
first be disabled by clearing the RXEN bit in the Ethernet MAC Receive Control (MACRCTL)
register, then the FIFO can be cleared by setting the RSTFIFO bit in the MACRCTL register.
The receiver automatically rejects frames that contain bad CRC values in the FCS field. In this case,
a Receive Error interrupt is generated and the receive data is lost. To accept all frames, clear the
BADCRC bit in the MACRCTL register.
In normal operating mode, the receiver accepts only those frames that have a destination address
that matches the address programmed into the Ethernet MAC Individual Address 0 (MACIA0)
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and Ethernet MAC Individual Address 1 (MACIA1) registers. However, the Ethernet receiver can
also be configured for Promiscuous and Multicast modes by setting the PRMS and AMUL bits in the
MACRCTL register.
15.2.2
Internal MII Operation
For the MII management interface to function properly, the MDIO signal must be connected through
a 10k Ω pull-up resistor to the +3.3 V supply. Failure to connect this pull-up resistor prevents
management transactions on this internal MII to function. Note that it is possible for data transmission
across the MII to still function since the PHY layer auto-negotiates the link parameters by default.
For the MII management interface to function properly, the internal clock must be divided down from
the system clock to a frequency no greater than 2.5 MHz. The Ethernet MAC Management Divider
(MACMDV) register contains the divider used for scaling down the system clock. See page 436 for
more details about the use of this register.
15.2.3
PHY Operation
The Physical Layer (PHY) in the Ethernet Controller includes integrated ENDECs,
scrambler/descrambler, dual-speed clock recovery, and full-featured auto-negotiation functions.
The transmitter includes an on-chip pulse shaper and a low-power line driver. The receiver has an
adaptive equalizer and a baseline restoration circuit required for accurate clock and data recovery.
The transceiver interfaces to Category-5 unshielded twisted pair (Cat-5 UTP) cabling for 100BASE-TX
applications, and Category-3 unshielded twisted pair (Cat-3 UTP) for 10BASE-T applications. The
Ethernet Controller is connected to the line media via dual 1:1 isolation transformers. No external
filter is required.
15.2.3.1
Clock Selection
The Ethernet Controller has an on-chip crystal oscillator which can also be driven by an external
oscillator. In this mode of operation, a 25-MHz crystal should be connected between the XTALPPHY
and XTALNPHY pins. Alternatively, an external 25-MHz clock input can be connected to the XTALPPHY
pin. In this mode of operation, a crystal is not required and the XTALNPHY pin must be tied to ground.
15.2.3.2
Auto-Negotiation
The Ethernet Controller supports the auto-negotiation functions of Clause 28 of the IEEE 802.3
standard for 10/100 Mbps operation over copper wiring. This function is controlled via register
settings. The auto-negotiation function is turned on by default, and the ANEGEN bit in the Ethernet
PHY Management Register 0 - Control (MR0) is set after reset. Software can disable the
auto-negotiation function by clearing the ANEGEN bit. The contents of the Ethernet PHY Management
Register - Auto-Negotiation Advertisement (MR4) are reflected to the Ethernet Controller’s link
partner during auto-negotiation via fast-link pulse coding.
Once auto-negotiation is complete, the DPLX and RATE bits in the Ethernet PHY Management
Register 18 - Diagnostic (MR18) register reflect the actual speed and duplex condition. If
auto-negotiation fails to establish a link for any reason, the ANEGF bit in the MR18 register reflects
this and auto-negotiation restarts from the beginning. Setting the RANEG bit in the MR0 register also
causes auto-negotiation to restart.
15.2.3.3
Polarity Correction
The Ethernet Controller is capable of either automatic or manual polarity reversal for 10BASE-T
and auto-negotiation functions. Bits 4 and 5 (RVSPOL and APOL) in the Ethernet PHY Management
Register 16 - Vendor-Specific (MR16) control this feature. The default is automatic mode, where
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APOL is clear and RVSPOL indicates if the detection circuitry has inverted the input signal. To enter
manual mode, APOL should be set. In manual mode RVSPOL controls the signal polarity.
15.2.3.4
MDI/MDI-X Configuration
The Ethernet Controller supports the MDI/MDI-X configuration as defined in IEEE 802.3-2002
specification. The MDI/MDI-X configuration eliminates the need for cross-over cables when connecting
to another device, such as a hub. The algorithm is controlled via settings in the Ethernet PHY
Management Register 24 - MDI/MIDIX Control (MR24). Refer to page 458 for additional details
about these settings.
15.2.3.5
Power Management
The PHY has two power-saving modes:
■ Power-Down
■ Receive Power Management
Power-down mode is activated by setting the PWRDN bit in the MR0 register. When the PHY is in
power-down mode, it consumes minimum power. While in the power-down state, the Ethernet
Controller still responds to management transactions.
Receive power management (RXCC mode) is activated by setting the RXCC bit in the MR16 register.
In this mode of operation, the adaptive equalizer, the clock recovery phase lock loop (PLL), and all
other receive circuitry are powered down. As soon as a valid signal is detected, all circuits are
automatically powered up to resume normal operation. Note that the RXCC mode is not supported
during 10BASE-T operation.
15.2.3.6
LED Indicators
The Ethernet Controller supports two LED signals that can be used to indicate various states of
operation. These signals are mapped to the LED0 and LED1 pins. By default, these pins are
configured as GPIO signals (PF3 and PF2). For the PHY layer to drive these signals, they must be
reconfigured to their alternate function. See “General-Purpose Input/Outputs (GPIOs)” on page 149
for additional details. The function of these pins is programmable via the PHY layer Ethernet PHY
Management Register 23 - LED Configuration (MR23). Refer to page 457 for additional details on
how to program these LED functions.
15.2.4
Interrupts
The Ethernet Controller can generate an interrupt for one or more of the following conditions:
■ A frame has been received into an empty RX FIFO
■ A frame transmission error has occurred
■ A frame has been transmitted successfully
■ A frame has been received with inadequate room in the RX FIFO (overrun)
■ A frame has been received with one or more error conditions (for example, FCS failed)
■ An MII management transaction between the MAC and PHY layers has completed
■ One or more of the following PHY layer conditions occurs:
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– Auto-Negotiate Complete
– Remote Fault
– Link Status Change
– Link Partner Acknowledge
– Parallel Detect Fault
– Page Received
– Receive Error
– Jabber Event Detected
15.3
Initialization and Configuration
The following sections describe the hardware and software configuration required to set up the
Ethernet Controller.
15.3.1
Hardware Configuration
Figure 15-4 on page 419 shows the proper method for interfacing the Ethernet Controller to a
10/100BASE-T Ethernet jack.
Figure 15-4. Interface to an Ethernet Jack
Stellaris
Microcontroller
PF2/LED1
PF3/LED0
MDIO
TXOP
60
59
PF2/LED1
PF3/LED0
+3.3V
10/100BASE-T Ethernet Jack
P2
58
R3
+3.3V
+3.3V
R4
49.9
10K
R5
49.9
C2
10pF
C3
10pF
43
12
11
R6
330
C4
3
G+
G-
1CT: 1
+3.3V
TX+ 1
TX- 2
5
TXON
RXIP
0.1UF
46
RX+ 3
4
4
7
40
C5
5
RX- 6
1CT: 1
+3.3V
7
6
8
RXIN
0.1UF
37
+3.3V
R8
49.9
R9
49.9
C6
10pF
C7
10pF
R7
8
+3.3V
2
1
Y-
9
10
NC
330
Y+
GND
J3011G21DNL
GL
GR
C13
0.01UF
The following isolation transformers have been tested and are known to successfully interface to
the Ethernet PHY layer.
■ Isolation Transformers
– TDK TLA-6T103
– Bel-Fuse S558-5999-46
– Halo TG22-3506ND
– Pulse PE-68515
– Valor ST6118
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– YCL 20PMT04
■ Isolation transformers in low profile packages (0.100 in/2.5 mm or less)
– TDK TLA-6T118
– Halo TG110-S050
– PCA EPF8023G
■ Isolation transformers with integrated RJ45 connector
– TDK TLA-6T704
– Delta RJS-1A08T089A
■ Isolation transformers with integrated RJ45 connector, LEDs and termination resistors
– Pulse J0011D21B/E
– Pulse J3011G21DNL
15.3.2
Software Configuration
To use the Ethernet Controller, it must be enabled by setting the EPHY0 and EMAC0 bits in the
RCGC2 register (see page 113). The following steps can then be used to configure the Ethernet
Controller for basic operation.
1. Program the MACDIV register to obtain a 2.5 MHz clock (or less) on the internal MII. Assuming
a 20-MHz system clock, the MACDIV value should be 0x03 or greater.
2. Program the MACIA0 and MACIA1 register for address filtering.
3. Program the MACTCTL register for Auto CRC generation, padding, and full-duplex operation
using a value of 0x16.
4. Program the MACRCTL register to flush the receive FIFO and reject frames with bad FCS using
a value of 0x18.
5. Enable both the Transmitter and Receive by setting the LSB in both the MACTCTL and
MACRCTL registers.
6. To transmit a frame, write the frame into the TX FIFO using the Ethernet MAC Data (MACDATA)
register. Then set the NEWTX bit in the Ethernet Mac Transmission Request (MACTR) register
to initiate the transmit process. When the NEWTX bit has been cleared, the TX FIFO is available
for the next transmit frame.
7. To receive a frame, wait for the NPR field in the Ethernet MAC Number of Packets (MACNP)
register to be non-zero. Then begin reading the frame from the RX FIFO by using the MACDATA
register. To ensure that the entire packet is received, either use the DriverLib EthernetPacketGet()
API or compare the number of bytes received to the Length field from the frame to determine
when the packet has been completely read.
15.4
Ethernet Register Map
Table 15-2 on page 421 lists the Ethernet MAC registers. All addresses given are relative to the
Ethernet MAC base address of 0x4004.8000.
The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY
layer. The registers are collectively known as the MII Management registers and are detailed in
Section 22.2.4 of the IEEE 802.3 specification. Table 15-2 on page 421 also lists these MII
Management registers. All addresses given are absolute and are written directly to the REGADR field
of the Ethernet MAC Management Control (MACMCTL) register. The format of registers 0 to 15
are defined by the IEEE specification and are common to all PHY layer implementations. The only
variance allowed is for features that may or may not be supported by a specific PHY implementation.
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Registers 16 to 31 are vendor-specific registers, used to support features that are specific to a
vendor's PHY implementation. Vendor-specific registers not listed are reserved.
Table 15-2. Ethernet Register Map
Offset
Name
Description
See
page
Type
Reset
R/W1C
0x0000.0000
Ethernet MAC Raw Interrupt Status/Acknowledge
423
Ethernet MAC
0x000
MACRIS/MACIACK
0x004
MACIM
R/W
0x0000.007F
Ethernet MAC Interrupt Mask
426
0x008
MACRCTL
R/W
0x0000.0008
Ethernet MAC Receive Control
427
0x00C
MACTCTL
R/W
0x0000.0000
Ethernet MAC Transmit Control
428
0x010
MACDATA
R/W
0x0000.0000
Ethernet MAC Data
429
0x014
MACIA0
R/W
0x0000.0000
Ethernet MAC Individual Address 0
431
0x018
MACIA1
R/W
0x0000.0000
Ethernet MAC Individual Address 1
432
0x01C
MACTHR
R/W
0x0000.003F
Ethernet MAC Threshold
433
0x020
MACMCTL
R/W
0x0000.0000
Ethernet MAC Management Control
435
0x024
MACMDV
R/W
0x0000.0080
Ethernet MAC Management Divider
436
0x02C
MACMTXD
R/W
0x0000.0000
Ethernet MAC Management Transmit Data
437
0x030
MACMRXD
R/W
0x0000.0000
Ethernet MAC Management Receive Data
438
0x034
MACNP
RO
0x0000.0000
Ethernet MAC Number of Packets
439
0x038
MACTR
R/W
0x0000.0000
Ethernet MAC Transmission Request
440
MII Management
-
MR0
R/W
0x3100
Ethernet PHY Management Register 0 – Control
441
-
MR1
RO
0x7849
Ethernet PHY Management Register 1 – Status
443
-
MR2
RO
0x000E
Ethernet PHY Management Register 2 – PHY Identifier
1
445
-
MR3
RO
0x7237
Ethernet PHY Management Register 3 – PHY Identifier
2
446
-
MR4
R/W
0x01E1
Ethernet PHY Management Register 4 – Auto-Negotiation
Advertisement
447
-
MR5
RO
0x0000
Ethernet PHY Management Register 5 – Auto-Negotiation
Link Partner Base Page Ability
449
-
MR6
RO
0x0000
Ethernet PHY Management Register 6 – Auto-Negotiation
Expansion
450
-
MR16
R/W
0x0140
Ethernet PHY Management Register 16 –
Vendor-Specific
451
-
MR17
R/W
0x0000
Ethernet PHY Management Register 17 – Interrupt
Control/Status
453
-
MR18
RO
0x0000
Ethernet PHY Management Register 18 – Diagnostic
455
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Table 15-2. Ethernet Register Map (continued)
See
page
Offset
Name
Type
Reset
Description
-
MR19
R/W
0x4000
Ethernet PHY Management Register 19 – Transceiver
Control
456
-
MR23
R/W
0x0010
Ethernet PHY Management Register 23 – LED
Configuration
457
-
MR24
R/W
0x00C0
Ethernet PHY Management Register 24 –MDI/MDIX
Control
458
15.5
Ethernet MAC Register Descriptions
The remainder of this section lists and describes the Ethernet MAC registers, in numerical order by
address offset. Also see “MII Management Register Descriptions” on page 440.
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Register 1: Ethernet MAC Raw Interrupt Status/Acknowledge
(MACRIS/MACIACK), offset 0x000
The MACRIS/MACIACK register is the interrupt status and acknowledge register. On a read, this
register gives the current status value of the corresponding interrupt prior to masking. On a write,
setting any bit clears the corresponding interrupt status bit.
Reads
Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK)
Base 0x4004.8000
Offset 0x000
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
PHYINT
MDINT
RXER
FOV
TXEMP
TXER
RXINT
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:7
reserved
RO
0x0000.00
6
PHYINT
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PHY Interrupt
When set, indicates that an enabled interrupt in the PHY layer has
occurred. MR17 in the PHY must be read to determine the specific PHY
event that triggered this interrupt.
5
MDINT
RO
0
MII Transaction Complete
When set, indicates that a transaction (read or write) on the MII interface
has completed successfully.
4
RXER
RO
0
Receive Error
This bit indicates that an error was encountered on the receiver. The
possible errors that can cause this interrupt bit to be set are:
3
FOV
RO
0
■
A receive error occurs during the reception of a frame (100 Mb/s
only).
■
The frame is not an integer number of bytes (dribble bits) due to an
alignment error.
■
The CRC of the frame does not pass the FCS check.
■
The length/type field is inconsistent with the frame data size when
interpreted as a length field.
FIFO Overrun
When set, indicates that an overrun was encountered on the receive
FIFO.
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Bit/Field
Name
Type
Reset
2
TXEMP
RO
0
Description
Transmit FIFO Empty
When set, indicates that the packet was transmitted and that the TX
FIFO is empty.
1
TXER
RO
0
Transmit Error
When set, indicates that an error was encountered on the transmitter.
The possible errors that can cause this interrupt bit to be set are:
0
RXINT
RO
0
■
The data length field stored in the TX FIFO exceeds 2032 decimal
(buffer length - 16 bytes of header data). The frame is not sent when
this error occurs.
■
The retransmission attempts during the backoff process have
exceeded the maximum limit of 16 decimal.
Packet Received
When set, indicates that at least one packet has been received and is
stored in the receiver FIFO.
Writes
Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK)
Base 0x4004.8000
Offset 0x000
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
15
14
13
12
RO
0
RO
0
RO
0
RO
0
RO
0
11
10
9
8
7
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:7
reserved
RO
0x0000.00
6
PHYINT
W1C
0
RO
0
RO
0
6
5
4
3
2
1
0
PHYINT
MDINT
RXER
FOV
TXEMP
TXER
RXINT
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Clear PHY Interrupt
Setting this bit clears the PHYINT interrupt in the MACRIS register.
5
MDINT
W1C
0
Clear MII Transaction Complete
Setting this bit clears the MDINT interrupt in the MACRIS register.
4
RXER
W1C
0
Clear Receive Error
Setting this bit clears the RXER interrupt in the MACRIS register.
3
FOV
W1C
0
Clear FIFO Overrun
Setting this bit clears the FOV interrupt in the MACRIS register.
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Bit/Field
Name
Type
Reset
2
TXEMP
W1C
0
Description
Clear Transmit FIFO Empty
Setting this bit clears the TXEMP interrupt in the MACRIS register.
1
TXER
W1C
0
Clear Transmit Error
Setting this bit clears the TXER interrupt in the MACRIS register and
resets the TX FIFO write pointer.
0
RXINT
W1C
0
Clear Packet Received
Setting this bit clears the RXINT interrupt in the MACRIS register.
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Register 2: Ethernet MAC Interrupt Mask (MACIM), offset 0x004
This register allows software to enable/disable Ethernet MAC interrupts. Clearing a bit disables the
interrupt, while setting the bit enables it.
Ethernet MAC Interrupt Mask (MACIM)
Base 0x4004.8000
Offset 0x004
Type R/W, reset 0x0000.007F
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RXERM
FOVM
TXEMPM
TXERM
RXINTM
RO
0
RO
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
reserved
Type
Reset
reserved
Type
Reset
PHYINTM MDINTM
RO
0
Bit/Field
Name
Type
Reset
31:7
reserved
RO
0x0000.00
6
PHYINTM
R/W
1
R/W
1
R/W
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Mask PHY Interrupt
Clearing this bit masks the PHYINT bit in the MACRIS register from
being set.
5
MDINTM
R/W
1
Mask MII Transaction Complete
Clearing this bit masks the MDINT bit in the MACRIS register from being
set.
4
RXERM
R/W
1
Mask Receive Error
Clearing this bit masks the RXER bit in the MACRIS register from being
set.
3
FOVM
R/W
1
Mask FIFO Overrun
Clearing this bit masks the FOV bit in the MACRIS register from being
set.
2
TXEMPM
R/W
1
Mask Transmit FIFO Empty
Clearing this bit masks the TXEMP bit in the MACRIS register from being
set.
1
TXERM
R/W
1
Mask Transmit Error
Clearing this bit masks the TXER bit in the MACRIS register from being
set.
0
RXINTM
R/W
1
Mask Packet Received
Clearing this bit masks the RXINT bit in the MACRIS register from being
set.
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Register 3: Ethernet MAC Receive Control (MACRCTL), offset 0x008
This register configures the receiver and controls the types of frames that are received.
It is important to note that when the receiver is enabled, all valid frames with a broadcast address
of FF-FF-FF-FF-FF-FF in the Destination Address field are received and stored in the RX FIFO,
even if the AMUL bit is not set.
Ethernet MAC Receive Control (MACRCTL)
Base 0x4004.8000
Offset 0x008
Type R/W, reset 0x0000.0008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
4
3
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
10
9
8
7
6
5
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RSTFIFO BADCRC
RO
0
Bit/Field
Name
Type
Reset
31:5
reserved
RO
0x0000.000
4
RSTFIFO
R/W
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
1
2
1
0
PRMS
AMUL
RXEN
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Clear Receive FIFO
When set, this bit clears the receive FIFO. This should be done when
software initialization is performed.
It is recommended that the receiver be disabled (RXEN = 0), before a
reset is initiated (RSTFIFO = 1). This sequence flushes and resets the
RX FIFO.
This bit is automatically cleared when read.
3
BADCRC
R/W
1
Enable Reject Bad CRC
When set, the BADCRC bit enables the rejection of frames with an
incorrectly calculated CRC. If a bad CRC is encountered, the RXER bit
in the MACRIS register is set and the receiver FIFO is reset.
2
PRMS
R/W
0
Enable Promiscuous Mode
When set, the PRMS bit enables Promiscuous mode, which accepts all
valid frames, regardless of the specified Destination Address.
1
AMUL
R/W
0
Enable Multicast Frames
When set, the AMUL bit enables the reception of multicast frames.
0
RXEN
R/W
0
Enable Receiver
When set the RXEN bit enables the Ethernet receiver. When this bit is
clear, the receiver is disabled and all frames are ignored.
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Register 4: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C
This register configures the transmitter and controls the frames that are transmitted.
Ethernet MAC Transmit Control (MACTCTL)
Base 0x4004.8000
Offset 0x00C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
DUPLEX
reserved
CRC
PADEN
TXEN
RO
0
RO
0
RO
0
RO
0
R/W
0
RO
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:5
reserved
RO
0x0000.000
4
DUPLEX
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Enable Duplex Mode
When set, this bit enables Duplex mode, allowing simultaneous
transmission and reception.
3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
CRC
R/W
0
Enable CRC Generation
When set this bit enables the automatic generation of the CRC and its
placement at the end of the packet. If this bit is clear, the frames placed
in the TX FIFO are sent exactly as they are written into the FIFO.
Note that this bit should generally be set.
1
PADEN
R/W
0
Enable Packet Padding
When set, this bit enables the automatic padding of packets that do not
meet the minimum frame size.
Note that this bit should generally be set.
0
TXEN
R/W
0
Enable Transmitter
When set, this bit enables the transmitter. When this bit is clear, the
transmitter is disabled.
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Register 5: Ethernet MAC Data (MACDATA), offset 0x010
Important: Use caution when reading this register. Performing a read may change bit status.
This register enables software to access the TX and RX FIFOs.
Reads from this register return the data stored in the RX FIFO from the location indicated by the
read pointer. The read pointer is then auto incremented to the next RX FIFO location. Reading from
the RX FIFO when a frame has not been received or is in the process of being received will return
indeterminate data and not increment the read pointer.
Writes to this register store the data in the TX FIFO at the location indicated by the write pointer.
The write pointer is the auto incremented to the next TX FIFO location. Writing more data into the
TX FIFO than indicated in the length field will result in the data being lost. Writing less data into the
TX FIFO than indicated in the length field will result in indeterminate data being appended to the
end of the frame to achieve the indicated length. Attempting to write the next frame into the TX FIFO
before transmission of the first has completed will result in the data being lost.
There is no mechanism for randomly accessing bytes in either the RX or TX FIFOs. Data must be
read from the RX FIFO sequentially and stored in a buffer for further processing. Once a read has
been performed, the data in the FIFO cannot be re-read. Data must be written to the TX FIFO
sequentially. If an error is made in placing the frame into the TX FIFO, the write pointer can be reset
to the start of the TX FIFO by writing the TXER bit of the MACIACK register and then the data
re-written.
Reads
Ethernet MAC Data (MACDATA)
Base 0x4004.8000
Offset 0x010
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RXDATA
Type
Reset
RXDATA
Type
Reset
Bit/Field
Name
Type
31:0
RXDATA
RO
Reset
Description
0x0000.0000 Receive FIFO Data
The RXDATA bits represent the next word of data stored in the RX FIFO.
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Writes
Ethernet MAC Data (MACDATA)
Base 0x4004.8000
Offset 0x010
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
15
14
13
12
11
10
9
8
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
23
22
21
20
19
18
17
16
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
7
6
5
4
3
2
1
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
TXDATA
Type
Reset
TXDATA
Type
Reset
Bit/Field
Name
Type
31:0
TXDATA
WO
Reset
Description
0x0000.0000 Transmit FIFO Data
The TXDATA bits represent the next word of data to place in the TX
FIFO for transmission.
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Register 6: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014
This register enables software to program the first four bytes of the hardware MAC address of the
Network Interface Card (NIC). (The last two bytes are in MACIA1). The 6-byte Individual Address
is compared against the incoming Destination Address fields to determine whether the frame should
be received.
Ethernet MAC Individual Address 0 (MACIA0)
Base 0x4004.8000
Offset 0x014
Type R/W, reset 0x0000.0000
31
30
29
28
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
R/W
0
R/W
0
R/W
0
R/W
0
27
26
25
24
23
22
21
20
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
11
10
9
8
7
6
5
4
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
MACOCT4
Type
Reset
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
MACOCT3
MACOCT2
Type
Reset
19
MACOCT1
R/W
0
Bit/Field
Name
Type
Reset
Description
31:24
MACOCT4
R/W
0x00
MAC Address Octet 4
R/W
0
The MACOCT4 bits represent the fourth octet of the MAC address used
to uniquely identify the Ethernet Controller.
23:16
MACOCT3
R/W
0x00
MAC Address Octet 3
The MACOCT3 bits represent the third octet of the MAC address used
to uniquely identify the Ethernet Controller.
15:8
MACOCT2
R/W
0x00
MAC Address Octet 2
The MACOCT2 bits represent the second octet of the MAC address used
to uniquely identify the Ethernet Controller.
7:0
MACOCT1
R/W
0x00
MAC Address Octet 1
The MACOCT1 bits represent the first octet of the MAC address used to
uniquely identify the Ethernet Controller.
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Register 7: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018
This register enables software to program the last two bytes of the hardware MAC address of the
Network Interface Card (NIC). (The first four bytes are in MACIA0). The 6-byte IAR is compared
against the incoming Destination Address fields to determine whether the frame should be received.
Ethernet MAC Individual Address 1 (MACIA1)
Base 0x4004.8000
Offset 0x018
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
MACOCT6
Type
Reset
MACOCT5
R/W
0
Bit/Field
Name
Type
Reset
31:16
reserved
RO
0x0000
15:8
MACOCT6
R/W
0x00
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
MAC Address Octet 6
The MACOCT6 bits represent the sixth octet of the MAC address used
to uniquely identify each Ethernet Controller.
7:0
MACOCT5
R/W
0x00
MAC Address Octet 5
The MACOCT5 bits represent the fifth octet of the MAC address used to
uniquely identify the Ethernet Controller.
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Register 8: Ethernet MAC Threshold (MACTHR), offset 0x01C
In order to increase the transmission rate, it is possible to program the Ethernet Controller to begin
transmission of the next frame prior to the completion of the transmission of the current frame. Note:
Extreme care must be used when implementing this function. Software must be able to guarantee
that the complete frame is able to be stored in the transmission FIFO prior to the completion of the
transmission frame.
This register enables software to set the threshold level at which the transmission of the frame
begins. If the THRESH bits are set to 0x3F, which is the reset value, the early transmission feature
is disabled, and transmission does not start until the NEWTX bit is set in the MACTR register.
Writing the THRESH bits to any value besides 0x3F enables the early transmission feature. Once
the byte count of data in the TX FIFO reaches the value derived from the THRESH bits as shown
below, transmission of the frame begins. When THRESH is set to all 0s, transmission of the frame
begins after 4 bytes (a single write) are stored in the TX FIFO. Each increment of the THRESH bit
field waits for an additional 32 bytes of data (eight writes) to be stored in the TX FIFO. Therefore,
a value of 0x01 causes the transmitter to wait for 36 bytes of data to be written while a value of 0x02
makes the wait equal to 68 bytes of written data. In general, early transmission starts when:
Number of Bytes >= 4 (THRESH x 8 + 1)
Reaching the threshold level has the same effect as setting the NEWTX bit in the MACTR register.
Transmission of the frame begins and then the number of bytes indicated by the Data Length field
is transmitted. Because under-run checking is not performed, if any event, such as an interrupt,
delays the filling of the FIFO, the tail pointer may reach and pass the write pointer in the TX FIFO.
In this event, indeterminate values are transmitted rather than the end of the frame. Therefore,
sufficient bus bandwidth for writing to the TX FIFO must be guaranteed by the software.
If a frame smaller than the threshold level must be sent, the NEWTX bit in the MACTR register must
be set with an explicit write. This initiates the transmission of the frame even though the threshold
limit has not been reached.
If the threshold level is set too small, it is possible for the transmitter to underrun. If this occurs, the
transmit frame is aborted, and a transmit error occurs. Note that in this case, the TXER bit in the
MACRIS is not set meaning that the CPU receives no indication that a transmit error happened.
Ethernet MAC Threshold (MACTHR)
Base 0x4004.8000
Offset 0x01C
Type R/W, reset 0x0000.003F
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
THRESH
RO
0
Bit/Field
Name
Type
Reset
31:6
reserved
RO
0x0000.00
RO
0
RO
0
RO
0
R/W
1
R/W
1
R/W
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
Description
5:0
THRESH
R/W
0x3F
Threshold Value
The THRESH bits represent the early transmit threshold. Once the amount
of data in the TX FIFO exceeds the value represented by the above
equation, transmission of the packet begins.
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Stellaris® LM3S8530 Microcontroller
Register 9: Ethernet MAC Management Control (MACMCTL), offset 0x020
This register enables software to control the transfer of data to and from the MII Management
registers in the Ethernet PHY layer. The address, name, type, reset configuration, and functional
description of each of these registers can be found in Table 15-2 on page 421 and in “MII Management
Register Descriptions” on page 440.
In order to initiate a read transaction from the MII Management registers, the WRITE bit must be
cleared during the same cycle that the START bit is set.
In order to initiate a write transaction to the MII Management registers, the WRITE bit must be set
during the same cycle that the START bit is set.
Ethernet MAC Management Control (MACMCTL)
Base 0x4004.8000
Offset 0x020
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
reserved
WRITE
START
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
RO
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
REGADR
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:3
REGADR
R/W
0x0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
MII Register Address
The REGADR bit field represents the MII Management register address
for the next MII management interface transaction. Refer to
Table 15-2 on page 421 for the PHY register offsets.
Note that any address that is not valid in the register map should not be
written to and any data read should be ignored.
2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
WRITE
R/W
0
MII Register Transaction Type
The WRITE bit represents the operation of the next MII management
interface transaction. If WRITE is set, the next operation is a write; if
WRITE is clear, the next transaction is a read.
0
START
R/W
0
MII Register Transaction Enable
The START bit represents the initiation of the next MII management
interface transaction. When this bit is set, the MII register located at
REGADR is read (WRITE=0) or written (WRITE=1).
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Ethernet Controller
Register 10: Ethernet MAC Management Divider (MACMDV), offset 0x024
This register enables software to set the clock divider for the Management Data Clock (MDC). This
clock is used to synchronize read and write transactions between the system and the MII Management
registers. The frequency of the MDC clock can be calculated from the following formula:
The clock divider must be written with a value that ensures that the MDC clock does not exceed a
frequency of 2.5 MHz.
Ethernet MAC Management Divider (MACMDV)
Base 0x4004.8000
Offset 0x024
Type R/W, reset 0x0000.0080
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
DIV
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
DIV
R/W
0x80
RO
0
R/W
1
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Clock Divider
The DIV bits are used to set the clock divider for the MDC clock used
to transmit data between the MAC and PHY layers over the serial MII
interface.
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Stellaris® LM3S8530 Microcontroller
Register 11: Ethernet MAC Management Transmit Data (MACMTXD), offset
0x02C
This register holds the next value to be written to the MII Management registers.
Ethernet MAC Management Transmit Data (MACMTXD)
Base 0x4004.8000
Offset 0x02C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
MDTX
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
MDTX
R/W
0x0000
MII Register Transmit Data
The MDTX bits represent the data that will be written in the next MII
management transaction.
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Ethernet Controller
Register 12: Ethernet MAC Management Receive Data (MACMRXD), offset
0x030
This register holds the last value read from the MII Management registers.
Ethernet MAC Management Receive Data (MACMRXD)
Base 0x4004.8000
Offset 0x030
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
MDRX
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:0
MDRX
R/W
0x0000
MII Register Receive Data
The MDRX bits represent the data that was read in the previous MII
management transaction.
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Stellaris® LM3S8530 Microcontroller
Register 13: Ethernet MAC Number of Packets (MACNP), offset 0x034
This register holds the number of frames that are currently in the RX FIFO. When NPR is 0, there
are no frames in the RX FIFO, and the RXINT bit is clear. When NPR is any other value, at least
one frame is in the RX FIFO, and the RXINT bit in the MACRIS register is set.
Note:
The FCS bytes are not included in the NPR value. As a result, the NPR value could be zero
before the FCS bytes are read from the FIFO. In addition, a new packet could be received
before the NPR value reaches zero. To ensure that the entire packet is received, either use
the DriverLib EthernetPacketGet() API or compare the number of bytes received to the
Length field from the frame to determine when the packet has been completely read.
Ethernet MAC Number of Packets (MACNP)
Base 0x4004.8000
Offset 0x034
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
2
1
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
NPR
RO
0
Bit/Field
Name
Type
Reset
31:6
reserved
RO
0x0000.00
5:0
NPR
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Number of Packets in Receive FIFO
The NPR bits represent the number of packets stored in the RX FIFO.
While the NPR field is greater than 0, the RXINT interrupt in the MACRIS
register is set.
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Ethernet Controller
Register 14: Ethernet MAC Transmission Request (MACTR), offset 0x038
This register enables software to initiate the transmission of the frame currently located in the TX
FIFO. Once the frame has been transmitted from the TX FIFO or a transmission error has been
encountered, the NEWTX bit is automatically cleared.
Ethernet MAC Transmission Request (MACTR)
Base 0x4004.8000
Offset 0x038
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
NEWTX
R/W
0
RO
0
NEWTX
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
New Transmission
When set, the NEWTX bit initiates an Ethernet transmission once the
packet has been placed in the TX FIFO. This bit is cleared once the
transmission has been completed. If early transmission is being used
(see the MACTHR register), this bit does not need to be set.
15.6
MII Management Register Descriptions
The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY
layer. The registers are collectively known as the MII Management registers. All addresses given
are absolute. Addresses not listed are reserved; these addresses should not be written to and any
data read should be ignored. Also see “Ethernet MAC Register Descriptions” on page 422.
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Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Register 15: Ethernet PHY Management Register 0 – Control (MR0), address
0x00
This register enables software to configure the operation of the PHY layer. The default settings of
these registers are designed to initialize the Ethernet Controller to a normal operational mode without
configuration.
Ethernet PHY Management Register 0 – Control (MR0)
Base 0x4004.8000
Address 0x00
Type R/W, reset 0x3100
15
RESET
Type
Reset
R/W
0
14
13
12
11
LOOPBK SPEEDSL ANEGEN PWRDN
R/W
0
R/W
1
R/W
1
R/W
0
10
9
8
7
ISO
RANEG
DUPLEX
COLT
R/W
0
R/W
0
R/W
1
R/W
0
Bit/Field
Name
Type
Reset
15
RESET
R/W
0
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
reserved
R/W
0
R/W
0
R/W
0
R/W
0
Description
Reset Registers
When set, this bit resets the PHY layer registers to their default state
and reinitializes internal state machines. Once the reset operation has
completed, this bit is cleared by hardware.
14
LOOPBK
R/W
0
Loopback Mode
When set, this bit enables the Loopback mode of operation. The receiver
ignores external inputs and receives the data that is transmitted by the
transmitter.
13
SPEEDSL
R/W
1
Speed Select
Value Description
12
ANEGEN
R/W
1
1
Enables the 100 Mb/s mode of operation (100BASE-TX).
0
Enables the 10 Mb/s mode of operation (10BASE-T).
Auto-Negotiation Enable
When set, this bit enables the auto-negotiation process.
11
PWRDN
R/W
0
Power Down
When set, this bit places the PHY layer into a low-power consuming
state. All data on the data inputs is ignored.
10
ISO
R/W
0
Isolate
When set, this bit isolates the transmit and receive data paths and
ignores all data being transmitted and received.
9
RANEG
R/W
0
Restart Auto-Negotiation
When set, this bit restarts the auto-negotiation process. Once the restart
has initiated, this bit is cleared by hardware.
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Ethernet Controller
Bit/Field
Name
Type
Reset
8
DUPLEX
R/W
1
Description
Set Duplex Mode
Value Description
7
COLT
R/W
0
1
Enables the Full-Duplex mode of operation. This bit can be
set by software in a manual configuration process or by the
auto-negotiation process.
0
Enables the Half-Duplex mode of operation.
Collision Test
When set, this bit enables the Collision Test mode of operation. The
COLT bit is set after the initiation of a transmission and is cleared once
the transmission is halted.
6:0
reserved
R/W
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
These bits should always be written as zero.
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Stellaris® LM3S8530 Microcontroller
Register 16: Ethernet PHY Management Register 1 – Status (MR1), address
0x01
This register enables software to determine the capabilities of the PHY layer and perform its
initialization and operation appropriately.
Ethernet PHY Management Register 1 – Status (MR1)
Base 0x4004.8000
Address 0x01
Type RO, reset 0x7849
Type
Reset
15
14
13
12
11
reserved
100X_F
100X_H
10T_F
10T_H
10
RO
0
RO
1
RO
1
RO
1
RO
1
9
8
7
reserved
RO
0
RO
0
RO
0
RO
0
6
5
4
3
2
1
0
MFPS
ANEGC
RFAULT
ANEGA
LINK
JAB
EXTD
RO
1
RO
0
RC
0
RO
1
RO
0
RC
0
RO
1
Bit/Field
Name
Type
Reset
Description
15
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14
100X_F
RO
1
100BASE-TX Full-Duplex Mode
When set, this bit indicates that the Ethernet Controller is capable of
supporting 100BASE-TX Full-Duplex mode.
13
100X_H
RO
1
100BASE-TX Half-Duplex Mode
When set, this bit indicates that the Ethernet Controller is capable of
supporting 100BASE-TX Half-Duplex mode.
12
10T_F
RO
1
10BASE-T Full-Duplex Mode
When set, this bit indicates that the Ethernet Controller is capable of
10BASE-T Full-Duplex mode.
11
10T_H
RO
1
10BASE-T Half-Duplex Mode
When set, this bit indicates that the Ethernet Controller is capable of
supporting 10BASE-T Half-Duplex mode.
10:7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
MFPS
RO
1
Management Frames with Preamble Suppressed
When set, this bit indicates that the Management Interface is capable
of receiving management frames with the preamble suppressed.
5
ANEGC
RO
0
Auto-Negotiation Complete
When set, this bit indicates that the auto-negotiation process has been
completed and that the extended registers defined by the
auto-negotiation protocol are valid.
4
RFAULT
RC
0
Remote Fault
When set, this bit indicates that a remote fault condition has been
detected. This bit remains set until it is read, even if the condition no
longer exists.
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Ethernet Controller
Bit/Field
Name
Type
Reset
3
ANEGA
RO
1
Description
Auto-Negotiation
When set, this bit indicates that the Ethernet Controller has the ability
to perform auto-negotiation.
2
LINK
RO
0
Link Made
When set, this bit indicates that a valid link has been established by the
Ethernet Controller.
1
JAB
RC
0
Jabber Condition
When set, this bit indicates that a jabber condition has been detected
by the Ethernet Controller. This bit remains set until it is read, even if
the jabber condition no longer exists.
0
EXTD
RO
1
Extended Capabilities
When set, this bit indicates that the Ethernet Controller provides an
extended set of capabilities that can be accessed through the extended
register set.
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Stellaris® LM3S8530 Microcontroller
Register 17: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2),
address 0x02
This register, along with MR3, provides a 32-bit value indicating the manufacturer, model, and
revision information.
Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2)
Base 0x4004.8000
Address 0x02
Type RO, reset 0x000E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
1
RO
0
OUI[21:6]
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
15:0
OUI[21:6]
RO
0x000E
RO
0
Description
Organizationally Unique Identifier[21:6]
This field, along with the OUI[5:0] field in MR3, makes up the
Organizationally Unique Identifier indicating the PHY manufacturer.
June 22, 2010
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Ethernet Controller
Register 18: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3),
address 0x03
This register, along with MR2, provides a 32-bit value indicating the manufacturer, model, and
revision information.
Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3)
Base 0x4004.8000
Address 0x03
Type RO, reset 0x7237
15
14
13
12
11
10
9
8
7
OUI[5:0]
Type
Reset
RO
0
RO
1
RO
1
RO
1
6
5
4
3
2
MN
RO
0
RO
0
RO
1
RO
0
RO
0
1
0
RO
1
RO
1
RN
RO
0
RO
1
RO
1
Bit/Field
Name
Type
Reset
Description
15:10
OUI[5:0]
RO
0x1C
Organizationally Unique Identifier[5:0]
RO
0
RO
1
This field, along with the OUI[21:6] field in MR2, makes up the
Organizationally Unique Identifier indicating the PHY manufacturer.
9:4
MN
RO
0x23
Model Number
The MN field represents the Model Number of the PHY.
3:0
RN
RO
0x7
Revision Number
The RN field represents the Revision Number of the PHY implementation.
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Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Register 19: Ethernet PHY Management Register 4 – Auto-Negotiation
Advertisement (MR4), address 0x04
This register provides the advertised abilities of the Ethernet Controller used during auto-negotiation.
Bits 8:5 represent the Technology Ability Field bits. This field can be overwritten by software to
auto-negotiate to an alternate common technology. Writing to this register has no effect until
auto-negotiation is re-initiated by setting the RANEG bit in the MR0 register.
Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4)
Base 0x4004.8000
Address 0x04
Type R/W, reset 0x01E1
Type
Reset
15
14
13
NP
reserved
RF
12
RO
0
RO
0
R/W
0
11
10
9
reserved
RO
0
RO
0
RO
0
RO
0
8
7
6
5
A3
A2
A1
A0
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
Description
15
NP
RO
0
Next Page
4
3
2
1
0
RO
0
RO
1
S
RO
0
RO
0
RO
0
When set, this bit indicates the Ethernet Controller is capable of Next
Page exchanges to provide more detailed information on the PHY layer’s
capabilities.
14
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13
RF
R/W
0
Remote Fault
When set, this bit indicates to the link partner that a Remote Fault
condition has been encountered.
12:9
reserved
RO
0x0
8
A3
R/W
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Technology Ability Field[3]
When set, this bit indicates that the Ethernet Controller supports the
100Base-TX full-duplex signaling protocol. If software wants to ensure
that this mode is not used, this bit can be cleared and auto-negotiation
re-initiated with the RANEG bit in the MR0 register.
7
A2
R/W
1
Technology Ability Field[2]
When set, this bit indicates that the Ethernet Controller supports the
100Base-TX half-duplex signaling protocol. If software wants to ensure
that this mode is not used, this bit can be cleared and auto-negotiation
re-initiated with the RANEG bit in the MR0 register.
6
A1
R/W
1
Technology Ability Field[1]
When set, this bit indicates that the Ethernet Controller supports the
10BASE-T full-duplex signaling protocol. If software wants to ensure
that this mode is not used, this bit can be cleared and auto-negotiation
re-initiated with the RANEG bit in the MR0 register..
June 22, 2010
447
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Ethernet Controller
Bit/Field
Name
Type
Reset
5
A0
R/W
1
Description
Technology Ability Field[0]
When set, this bit indicates that the Ethernet Controller supports the
10BASE-T half-duplex signaling protocol. If software wants to ensure
that this mode is not used, this bit can be cleared and auto-negotiation
re-initiated with the RANEG bit in the MR0 register..
4:0
S
RO
0x1
Selector Field
The S field encodes 32 possible messages for communicating between
Ethernet Controllers. This field is hard-coded to 0x01, indicating that
®
the Stellaris Ethernet Controller is IEEE 802.3 compliant.
448
June 22, 2010
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Stellaris® LM3S8530 Microcontroller
Register 20: Ethernet PHY Management Register 5 – Auto-Negotiation Link
Partner Base Page Ability (MR5), address 0x05
This register provides the advertised abilities of the link partner’s Ethernet Controller that are received
and stored during auto-negotiation.
Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability (MR5)
Base 0x4004.8000
Address 0x05
Type RO, reset 0x0000
Type
Reset
15
14
13
NP
ACK
RF
RO
0
RO
0
RO
0
12
11
10
9
8
7
6
5
4
3
A[7:0]
RO
0
RO
0
RO
0
RO
0
2
1
0
RO
0
RO
0
S
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
15
NP
RO
0
Next Page
RO
0
RO
0
RO
0
RO
0
RO
0
When set, this bit indicates that the link partner’s Ethernet Controller is
capable of Next page exchanges to provide more detailed information
on the Ethernet Controller’s capabilities.
14
ACK
RO
0
Acknowledge
When set, this bit indicates that the Ethernet Controller has successfully
received the link partner’s advertised abilities during auto-negotiation.
13
RF
RO
0
Remote Fault
Used as a standard transport mechanism for transmitting simple fault
information from the link partner.
12:5
A[7:0]
RO
0x00
Technology Ability Field
The A[7:0] field encodes individual technologies that are supported
by the Ethernet Controller. See the MR4 register for definitions. Note
that bits 12:9 describe functions that are not implemented on the
®
Stellaris Ethernet Controller. Refer to the IEEE 802.3 standard for
definitions.
4:0
S
RO
0x00
Selector Field
The S field encodes possible messages for communicating between
Ethernet Controllers.
Value
Description
0x00
Reserved
0x01
IEEE Std 802.3
0x02
IEEE Std 802.9 ISLAN-16T
0x03
IEEE Std 802.5
0x04
IEEE Std 1394
0x05–0x1F
Reserved
June 22, 2010
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Ethernet Controller
Register 21: Ethernet PHY Management Register 6 – Auto-Negotiation
Expansion (MR6), address 0x06
This register enables software to determine the auto-negotiation and next page capabilities of the
Ethernet Controller and the link partner after auto-negotiation.
Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6)
Base 0x4004.8000
Address 0x06
Type RO, reset 0x0000
15
14
13
12
11
10
9
8
7
6
5
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
4
3
2
1
0
PDF
LPNPA
reserved
PRX
LPANEGA
RC
0
RO
0
RO
0
RC
0
RO
0
Bit/Field
Name
Type
Reset
Description
15:5
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
PDF
RC
0
Parallel Detection Fault
When set, this bit indicates that more than one technology has been
detected at link up. This bit is cleared when read.
3
LPNPA
RO
0
Link Partner is Next Page Able
When set, this bit indicates that the link partner is enabled to support
next page.
2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
PRX
RC
0
New Page Received
When set, this bit indicates that a new page has been received from the
link partner and stored. This bit remains set until the register is read.
0
LPANEGA
RO
0
Link Partner is Auto-Negotiation Able
When set, this bit indicates that the link partner is enabled to support
auto-negotiation.
450
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Stellaris® LM3S8530 Microcontroller
Register 22: Ethernet PHY Management Register 16 – Vendor-Specific (MR16),
address 0x10
This register enables software to configure the operation of vendor-specific modes of the Ethernet
Controller.
Ethernet PHY Management Register 16 – Vendor-Specific (MR16)
Base 0x4004.8000
Address 0x10
Type R/W, reset 0x0140
Type
Reset
15
14
13
12
11
10
RPTR
INPOL
reserved
TXHIM
SQEI
NL10
R/W
0
R/W0
0
RO
0
R/W
0
R/W
0
R/W
0
9
8
7
6
reserved
RO
0
Bit/Field
Name
Type
Reset
15
RPTR
R/W
0
RO
1
RO
0
RO
1
5
4
APOL
RVSPOL
R/W
0
R/W
0
3
2
reserved
RO
0
RO
0
1
0
PCSBP
RXCC
R/W
0
R/W
0
Description
Repeater Mode
When set, this bit enables the repeater mode of operation. In this mode,
full-duplex is not allowed and the Carrier Sense signal only responds
to receive activity.
14
INPOL
R/W0
0
Interrupt Polarity
Value Description
1
Sets the polarity of the PHY interrupt to be active High.
0
Sets the polarity of the PHY interrupt to active Low.
Important:
Because the Media Access Controller expects active
Low interrupts from the PHY, this bit must always be
written with a 0 to ensure proper operation.
13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
TXHIM
R/W
0
Transmit High Impedance Mode
When set, this bit enables the transmitter High Impedance mode. In this
mode, the TXOP and TXON transmitter pins are put into a high impedance
state. The RXIP and RXIN pins remain fully functional.
11
SQEI
R/W
0
SQE Inhibit Testing
When set, this bit prohibits 10BASE-T SQE testing.
When clear, the SQE testing is performed by generating a collision pulse
following the completion of the transmission of a frame.
10
NL10
R/W
0
Natural Loopback Mode
When set, this bit enables the 10BASE-T Natural Loopback mode. In
this mode, the transmission data received by the Ethernet Controller is
looped back onto the receive data path when 10BASE-T mode is
enabled.
9:6
reserved
RO
0x5
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Ethernet Controller
Bit/Field
Name
Type
Reset
5
APOL
R/W
0
Description
Auto-Polarity Disable
When set, this bit disables the Ethernet Controller’s auto-polarity function.
If this bit is clear, the Ethernet Controller automatically inverts the
received signal due to a wrong polarity connection during
auto-negotiation when in 10BASE-T mode.
4
RVSPOL
R/W
0
Receive Data Polarity
This bit indicates whether the receive data pulses are being inverted.
If the APOL bit is 0, then the RVSPOL bit is read-only and indicates
whether the auto-polarity circuitry is reversing the polarity. In this case,
if RVSPOL is set, it indicates that the receive data is inverted; if RVSPOL
is clear, it indicates that the receive data is not inverted.
If the APOL bit is 1, then the RVSPOL bit is writable and software can
force the receive data to be inverted. Setting RVSPOL to 1 forces the
receive data to be inverted; clearing RVSPOL does not invert the receive
data.
3:2
reserved
RO
0x0
1
PCSBP
R/W
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PCS Bypass
When set, this bit enables the bypass of the PCS and
scrambling/descrambling functions in 100BASE-TX mode. This mode
is only valid when auto-negotiation is disabled and 100BASE-TX mode
is enabled.
0
RXCC
R/W
0
Receive Clock Control
When set, this bit enables the Receive Clock Control power saving mode
if the Ethernet Controller is configured in 100BASE-TX mode. This mode
shuts down the receive clock when no data is being received to save
power. This mode should not be used when PCSBP is enabled and is
automatically disabled when the LOOPBK bit in the MR0 register is set.
452
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Stellaris® LM3S8530 Microcontroller
Register 23: Ethernet PHY Management Register 17 – Interrupt Control/Status
(MR17), address 0x11
This register provides the means for controlling and observing the events which trigger a PHY layer
interrupt in the MACRIS register. This register can also be used in a polling mode via the Media
Independent Interface as a means to observe key events within the PHY layer via one register
address. Bits 0 through 7 are status bits which are each set based on an event. These bits are
cleared after the register is read. Bits 8 through 15 of this register, when set, enable the corresponding
bit in the lower byte to signal a PHY layer interrupt in the MACRIS register.
Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17)
Base 0x4004.8000
Address 0x11
Type R/W, reset 0x0000
15
JABBER_IE
Type
Reset
R/W
0
14
13
RXER_IE PRX_IE
R/W
0
12
11
PDF_IE
LPACK_IE
R/W
0
R/W
0
R/W
0
10
9
8
7
6
LSCHG_IE RFAULT_IE ANEGCOMP_IE JABBER_INT RXER_INT
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
15
JABBER_IE
R/W
0
R/W
0
RC
0
5
4
3
2
PRX_INT PDF_INT LPACK_INT LSCHG_INT
RC
0
RC
0
RC
0
RC
0
RC
0
1
0
RFAULT_INT ANEGCOMP_INT
RC
0
RC
0
Description
Jabber Interrupt Enable
When set, this bit enables system interrupts when a Jabber condition
is detected by the Ethernet Controller.
14
RXER_IE
R/W
0
Receive Error Interrupt Enable
When set, this bit enables system interrupts when a receive error is
detected by the Ethernet Controller.
13
PRX_IE
R/W
0
Page Received Interrupt Enable
When set, this bit enables system interrupts when a new page is received
by the Ethernet Controller.
12
PDF_IE
R/W
0
Parallel Detection Fault Interrupt Enable
When set, this bit enables system interrupts when a Parallel Detection
Fault is detected by the Ethernet Controller.
11
LPACK_IE
R/W
0
LP Acknowledge Interrupt Enable
When set, this bit enables system interrupts when FLP bursts are
received with the ACK bit in the MR5 register during auto-negotiation.
10
LSCHG_IE
R/W
0
Link Status Change Interrupt Enable
When set, this bit enables system interrupts when the link status changes
from OK to FAIL.
9
RFAULT_IE
R/W
0
Remote Fault Interrupt Enable
When set, this bit enables system interrupts when a remote fault
condition is signaled by the link partner.
8
ANEGCOMP_IE
R/W
0
Auto-Negotiation Complete Interrupt Enable
When set, this bit enables system interrupts when the auto-negotiation
sequence has completed successfully.
June 22, 2010
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Ethernet Controller
Bit/Field
Name
Type
Reset
7
JABBER_INT
RC
0
Description
Jabber Event Interrupt
When set, this bit indicates that a Jabber event has been detected by
the 10BASE-T circuitry.
6
RXER_INT
RC
0
Receive Error Interrupt
When set, this bit indicates that a receive error has been detected by
the Ethernet Controller.
5
PRX_INT
RC
0
Page Receive Interrupt
When set, this bit indicates that a new page has been received from the
link partner during auto-negotiation.
4
PDF_INT
RC
0
Parallel Detection Fault Interrupt
When set, this bit indicates that a parallel detection fault has been
detected by the Ethernet Controller during the auto-negotiation process.
3
LPACK_INT
RC
0
LP Acknowledge Interrupt
When set, this bit indicates that an FLP burst has been received with
the ACK bit set in the MR5 register during auto-negotiation.
2
LSCHG_INT
RC
0
Link Status Change Interrupt
When set, this bit indicates that the link status has changed from OK to
FAIL.
1
RFAULT_INT
RC
0
Remote Fault Interrupt
When set, this bit indicates that a remote fault condition has been
signaled by the link partner.
0
ANEGCOMP_INT
RC
0
Auto-Negotiation Complete Interrupt
When set, this bit indicates that the auto-negotiation sequence has
completed successfully.
454
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Stellaris® LM3S8530 Microcontroller
Register 24: Ethernet PHY Management Register 18 – Diagnostic (MR18),
address 0x12
This register enables software to diagnose the results of the previous auto-negotiation.
Ethernet PHY Management Register 18 – Diagnostic (MR18)
Base 0x4004.8000
Address 0x12
Type RO, reset 0x0000
15
14
13
reserved
Type
Reset
RO
0
RO
0
12
11
10
9
8
ANEGF
DPLX
RATE
RXSD
RX_LOCK
RC
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
15:13
reserved
RO
0x0
12
ANEGF
RC
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Auto-Negotiation Failure
When set, this bit indicates that no common technology was found during
auto-negotiation and auto-negotiation has failed. This bit remains set
until read.
11
DPLX
RO
0
Duplex Mode
When set, this bit indicates that Full-Duplex was the highest common
denominator found during the auto-negotiation process. Otherwise,
Half-Duplex was the highest common denominator found.
10
RATE
RO
0
Rate
When set, this bit indicates that 100BASE-TX was the highest common
denominator found during the auto-negotiation process. Otherwise,
10BASE-T was the highest common denominator found.
9
RXSD
RO
0
Receive Detection
When set, this bit indicates that receive signal detection has occurred
(in 100BASE-TX mode) or that Manchester-encoded data has been
detected (in 10BASE-T mode).
8
RX_LOCK
RO
0
Receive PLL Lock
When set, this bit indicates that the Receive PLL has locked onto the
receive signal for the selected speed of operation (10BASE-T or
100BASE-TX).
7:0
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 22, 2010
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Ethernet Controller
Register 25: Ethernet PHY Management Register 19 – Transceiver Control
(MR19), address 0x13
This register enables software to set the gain of the transmit output to compensate for transformer
loss.
Ethernet PHY Management Register 19 – Transceiver Control (MR19)
Base 0x4004.8000
Address 0x13
Type R/W, reset 0x4000
15
14
13
12
11
10
9
8
7
TXO
Type
Reset
R/W
0
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
R/W
1
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
15:14
TXO
R/W
0x1
RO
0
RO
0
Description
Transmit Amplitude Selection
The TXO field sets the transmit output amplitude to account for transmit
transformer insertion loss.
Value Description
13:0
reserved
RO
0x000
0x0
Gain set for 0.0dB of insertion loss
0x1
Gain set for 0.4dB of insertion loss
0x2
Gain set for 0.8dB of insertion loss
0x3
Gain set for 1.2dB of insertion loss
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
456
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Register 26: Ethernet PHY Management Register 23 – LED Configuration
(MR23), address 0x17
This register enables software to select the source that causes the LED1 and LED0 signals to toggle.
Ethernet PHY Management Register 23 – LED Configuration (MR23)
Base 0x4004.8000
Address 0x17
Type R/W, reset 0x0010
15
14
13
12
11
10
9
8
7
6
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
5
4
3
LED1[3:0]
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
2
1
0
LED0[3:0]
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
15:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4
LED1[3:0]
R/W
0x1
LED1 Source
The LED1 field selects the source that toggles the LED1 signal.
Value Description
3:0
LED0[3:0]
R/W
0x0
0x0
Link OK
0x1
RX or TX Activity (Default LED1)
0x2
Reserved
0x3
Reserved
0x4
Reserved
0x5
100BASE-TX mode
0x6
10BASE-T mode
0x7
Full-Duplex
0x8
Link OK & Blink=RX or TX Activity
LED0 Source
The LED0 field selects the source that toggles the LED0 signal.
Value Description
0x0
Link OK (Default LED0)
0x1
RX or TX Activity
0x2
Reserved
0x3
Reserved
0x4
Reserved
0x5
100BASE-TX mode
0x6
10BASE-T mode
0x7
Full-Duplex
0x8
Link OK & Blink=RX or TX Activity
June 22, 2010
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Ethernet Controller
Register 27: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24),
address 0x18
This register enables software to control the behavior of the MDI/MDIX mux and its switching
capabilities.
Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24)
Base 0x4004.8000
Address 0x18
Type R/W, reset 0x00C0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
7
6
PD_MODE AUTO_SW
RO
0
RO
0
RO
0
RO
0
R/W
1
R/W
1
5
4
MDIX
MDIX_CM
R/W
0
RO
0
3
2
1
0
MDIX_SD
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
15:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
PD_MODE
R/W
1
Parallel Detection Mode
When set, enables the Parallel Detection mode and allows auto-switching
to work when auto-negotiation is not enabled.
6
AUTO_SW
R/W
1
Auto-Switching Enable
When set, enables Auto-Switching of the MDI/MDIX mux.
5
MDIX
R/W
0
Auto-Switching Configuration
When set, indicates that the MDI/MDIX mux is in the crossover (MDIX)
configuration.
When 0, it indicates that the mux is in the pass-through (MDI)
configuration.
When the AUTO_SW bit is 1, the MDIX bit is read-only. When the
AUTO_SW bit is 0, the MDIX bit is read/write and can be configured
manually.
4
MDIX_CM
RO
0
Auto-Switching Complete
When set, indicates that the auto-switching sequence has completed.
If 0, it indicates that the sequence has not completed or that
auto-switching is disabled.
3:0
MDIX_SD
R/W
0x0
Auto-Switching Seed
This field provides the initial seed for the switching algorithm. This seed
directly affects the number of attempts [5,4] respectively to write bits
[3:0].
A 0 sets the seed to 0x5.
458
June 22, 2010
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Stellaris® LM3S8530 Microcontroller
16
Pin Diagram
The LM3S8530 microcontroller pin diagrams are shown below.
Figure 16-1. 100-Pin LQFP Package Pin Diagram
June 22, 2010
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Texas Instruments-Production Data
Pin Diagram
Figure 16-2. 108-Ball BGA Package Pin Diagram (Top View)
460
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
17
Signal Tables
The following tables list the signals available for each pin. Functionality is enabled by software with
the GPIOAFSEL register.
Important: All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins (PB7
and PC[3:0]) which default to the JTAG functionality.
Table 17-1 on page 461 shows the pin-to-signal-name mapping, including functional characteristics
of the signals. Table 17-2 on page 465 lists the signals in alphabetical order by signal name.
Table 17-3 on page 468 groups the signals by functionality, except for GPIOs. Table 17-4 on page 470
lists the GPIO pins and their alternate functionality.
17.1
100-Pin LQFP Package Pin Tables
Table 17-1. Signals by Pin Number
a
Pin Number
Pin Name
Pin Type
Buffer Type
1
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
2
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
3
VDDA
-
Power
The positive supply (3.3 V) for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be connected to 3.3 V, regardless of
system implementation.
4
GNDA
-
Power
The ground reference for the analog circuits ( etc.). These are
separated from GND to minimize the electrical noise contained on
VDD from affecting the analog functions.
5
6
Description
PE5
I/O
TTL
GPIO port E bit 5.
CAN2Tx
O
TTL
CAN module 2 transmit.
PE4
I/O
TTL
GPIO port E bit 4.
CAN2Rx
I
TTL
CAN module 2 receive.
7
LDO
-
Power
Low drop-out regulator output voltage. This pin requires an external
capacitor between the pin and GND of 1 µF or greater. When the
on-chip LDO is used to provide power to the logic, the LDO pin
must also be connected to the VDD25 pins at the board level in
addition to the decoupling capacitor(s).
8
VDD
-
Power
Positive supply for I/O and some logic.
9
GND
-
Power
Ground reference for logic and I/O pins.
10
PD0
I/O
TTL
GPIO port D bit 0.
CAN0Rx
I
TTL
CAN module 0 receive.
PD1
I/O
TTL
GPIO port D bit 1.
11
CAN0Tx
O
TTL
CAN module 0 transmit.
12
PD2
I/O
TTL
GPIO port D bit 2.
13
PD3
I/O
TTL
GPIO port D bit 3.
14
VDD25
-
Power
Positive supply for most of the logic function, including the
processor core and most peripherals.
15
GND
-
Power
Ground reference for logic and I/O pins.
June 22, 2010
461
Texas Instruments-Production Data
Signal Tables
Table 17-1. Signals by Pin Number (continued)
a
Pin Number
Pin Name
Pin Type
Buffer Type
Description
16
XTALPPHY
I
TTL
Ethernet PHY XTALP 25-MHz oscillator crystal input or external
clock reference input.
17
XTALNPHY
O
TTL
Ethernet PHY XTALN 25-MHz oscillator crystal output. Leave
unconnected when using a single-ended 25-MHz clock input
connected to the XTALPPHY pin.
18
PG1
I/O
TTL
GPIO port G bit 1.
19
PG0
I/O
TTL
GPIO port G bit 0.
20
VDD
-
Power
Positive supply for I/O and some logic.
21
GND
-
Power
Ground reference for logic and I/O pins.
22
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
23
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
24
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
No connect. Leave the pin electrically unconnected/isolated.
25
NC
-
-
26
PA0
I/O
TTL
GPIO port A bit 0.
U0Rx
I
TTL
UART module 0 receive. When in IrDA mode, this signal has IrDA
modulation.
27
28
29
30
31
PA1
I/O
TTL
GPIO port A bit 1.
U0Tx
O
TTL
UART module 0 transmit. When in IrDA mode, this signal has IrDA
modulation.
PA2
I/O
TTL
GPIO port A bit 2.
SSI0Clk
I/O
TTL
SSI module 0 clock.
PA3
I/O
TTL
GPIO port A bit 3.
SSI0Fss
I/O
TTL
SSI module 0 frame.
PA4
I/O
TTL
GPIO port A bit 4.
SSI0Rx
I
TTL
SSI module 0 receive.
PA5
I/O
TTL
GPIO port A bit 5.
SSI module 0 transmit.
SSI0Tx
O
TTL
32
VDD
-
Power
Positive supply for I/O and some logic.
33
GND
-
Power
Ground reference for logic and I/O pins.
34
PA6
I/O
TTL
GPIO port A bit 6.
CCP1
I/O
TTL
Capture/Compare/PWM 1.
35
NC
-
-
36
VCCPHY
-
Power
VCC of the Ethernet PHY.
37
RXIN
I
Analog
RXIN of the Ethernet PHY.
38
VDD25
-
Power
Positive supply for most of the logic function, including the
processor core and most peripherals.
39
GND
-
Power
Ground reference for logic and I/O pins.
40
RXIP
I
Analog
RXIP of the Ethernet PHY.
41
ERBIAS
I
Analog
12.4-kΩ resistor (1% precision) used internally for Ethernet PHY.
42
GNDPHY
-
Power
GND of the Ethernet PHY.
43
TXOP
O
Analog
TXOP of the Ethernet PHY.
44
VDD
-
Power
Positive supply for I/O and some logic.
45
GND
-
Power
Ground reference for logic and I/O pins.
No connect. Leave the pin electrically unconnected/isolated.
462
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Table 17-1. Signals by Pin Number (continued)
Pin Number
Pin Name
46
47
a
Pin Type
Buffer Type
Description
TXON
O
Analog
PF0
I/O
TTL
GPIO port F bit 0.
CAN1Rx
I
TTL
CAN module 1 receive.
TXON of the Ethernet PHY.
48
OSC0
I
Analog
Main oscillator crystal input or an external clock reference input.
49
OSC1
O
Analog
Main oscillator crystal output. Leave unconnected when using a
single-ended clock source.
50
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
51
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
52
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
53
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
54
GND
-
Power
Ground reference for logic and I/O pins.
55
VDD
-
Power
Positive supply for I/O and some logic.
56
VDD
-
Power
Positive supply for I/O and some logic.
57
GND
-
Power
Ground reference for logic and I/O pins.
58
MDIO
I/O
TTL
MDIO of the Ethernet PHY.
59
60
61
PF3
I/O
TTL
GPIO port F bit 3.
LED0
O
TTL
Ethernet LED 0.
PF2
I/O
TTL
GPIO port F bit 2.
LED1
O
TTL
Ethernet LED 1.
PF1
I/O
TTL
GPIO port F bit 1.
CAN module 1 transmit.
CAN1Tx
O
TTL
62
VDD25
-
Power
Positive supply for most of the logic function, including the
processor core and most peripherals.
63
GND
-
Power
Ground reference for logic and I/O pins.
64
RST
I
TTL
System reset input.
65
CMOD0
I
TTL
CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
66
PB0
I/O
TTL
GPIO port B bit 0.
CCP0
I/O
TTL
Capture/Compare/PWM 0.
67
PB1
I/O
TTL
GPIO port B bit 1.
68
VDD
-
Power
Positive supply for I/O and some logic.
69
GND
-
Power
Ground reference for logic and I/O pins.
70
71
72
73
74
PB2
I/O
TTL
GPIO port B bit 2.
I2C0SCL
I/O
OD
I2C module 0 clock.
PB3
I/O
TTL
GPIO port B bit 3.
I2C0SDA
I/O
OD
I2C module 0 data.
PE0
I/O
TTL
GPIO port E bit 0.
SSI1Clk
I/O
TTL
SSI module 1 clock.
PE1
I/O
TTL
GPIO port E bit 1.
SSI1Fss
I/O
TTL
SSI module 1 frame.
PE2
I/O
TTL
GPIO port E bit 2.
SSI1Rx
I
TTL
SSI module 1 receive.
June 22, 2010
463
Texas Instruments-Production Data
Signal Tables
Table 17-1. Signals by Pin Number (continued)
Pin Number
75
a
Pin Name
Pin Type
Buffer Type
Description
PE3
I/O
TTL
GPIO port E bit 3.
SSI1Tx
O
TTL
SSI module 1 transmit.
76
CMOD1
I
TTL
CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
77
PC3
I/O
TTL
GPIO port C bit 3.
SWO
O
TTL
JTAG TDO and SWO.
TDO
O
TTL
JTAG TDO and SWO.
PC2
I/O
TTL
GPIO port C bit 2.
TDI
I
TTL
JTAG TDI.
PC1
I/O
TTL
GPIO port C bit 1.
SWDIO
I/O
TTL
JTAG TMS and SWDIO.
TMS
I/O
TTL
JTAG TMS and SWDIO.
PC0
I/O
TTL
GPIO port C bit 0.
SWCLK
I
TTL
JTAG/SWD CLK.
TCK
I
TTL
JTAG/SWD CLK.
81
VDD
-
Power
Positive supply for I/O and some logic.
82
GND
-
Power
Ground reference for logic and I/O pins.
83
VCCPHY
-
Power
VCC of the Ethernet PHY.
84
VCCPHY
-
Power
VCC of the Ethernet PHY.
85
GNDPHY
-
Power
GND of the Ethernet PHY.
78
79
80
86
GNDPHY
-
Power
GND of the Ethernet PHY.
87
GND
-
Power
Ground reference for logic and I/O pins.
88
VDD25
-
Power
Positive supply for most of the logic function, including the
processor core and most peripherals.
89
PB7
I/O
TTL
GPIO port B bit 7.
TRST
I
TTL
JTAG TRST.
90
PB6
I/O
TTL
GPIO port B bit 6.
91
PB5
I/O
TTL
GPIO port B bit 5.
92
PB4
I/O
TTL
GPIO port B bit 4.
93
VDD
-
Power
Positive supply for I/O and some logic.
94
GND
-
Power
Ground reference for logic and I/O pins.
95
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
96
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
97
GNDA
-
Power
The ground reference for the analog circuits ( etc.). These are
separated from GND to minimize the electrical noise contained on
VDD from affecting the analog functions.
98
VDDA
-
Power
The positive supply (3.3 V) for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be connected to 3.3 V, regardless of
system implementation.
99
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
100
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
464
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Table 17-2. Signals by Signal Name
Pin Name
Pin Number
a
Pin Type
Buffer Type
Description
CAN0Rx
10
I
TTL
CAN module 0 receive.
CAN0Tx
11
O
TTL
CAN module 0 transmit.
CAN1Rx
47
I
TTL
CAN module 1 receive.
CAN1Tx
61
O
TTL
CAN module 1 transmit.
CAN2Rx
6
I
TTL
CAN module 2 receive.
CAN2Tx
5
O
TTL
CAN module 2 transmit.
CCP0
66
I/O
TTL
Capture/Compare/PWM 0.
CCP1
34
I/O
TTL
Capture/Compare/PWM 1.
CMOD0
65
I
TTL
CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
CMOD1
76
I
TTL
CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
ERBIAS
41
I
Analog
12.4-kΩ resistor (1% precision) used internally for Ethernet
PHY.
GND
9
15
21
33
39
45
54
57
63
69
82
87
94
-
Power
Ground reference for logic and I/O pins.
GNDA
4
97
-
Power
The ground reference for the analog circuits ( etc.). These
are separated from GND to minimize the electrical noise
contained on VDD from affecting the analog functions.
GNDPHY
42
85
86
-
Power
GND of the Ethernet PHY.
I2C0SCL
70
I/O
OD
I2C module 0 clock.
I2C0SDA
71
I/O
OD
I2C module 0 data.
LDO
7
-
Power
LED0
59
O
TTL
Ethernet LED 0.
LED1
60
O
TTL
Ethernet LED 1.
MDIO
58
I/O
TTL
MDIO of the Ethernet PHY.
Low drop-out regulator output voltage. This pin requires an
external capacitor between the pin and GND of 1 µF or
greater. When the on-chip LDO is used to provide power to
the logic, the LDO pin must also be connected to the VDD25
pins at the board level in addition to the decoupling
capacitor(s).
June 22, 2010
465
Texas Instruments-Production Data
Signal Tables
Table 17-2. Signals by Signal Name (continued)
a
Pin Name
Pin Number
Pin Type
Buffer Type
Description
NC
1
2
22
23
24
25
35
50
51
52
53
95
96
99
100
-
-
OSC0
48
I
Analog
Main oscillator crystal input or an external clock reference
input.
OSC1
49
O
Analog
Main oscillator crystal output. Leave unconnected when using
a single-ended clock source.
PA0
26
I/O
TTL
GPIO port A bit 0.
PA1
27
I/O
TTL
GPIO port A bit 1.
PA2
28
I/O
TTL
GPIO port A bit 2.
PA3
29
I/O
TTL
GPIO port A bit 3.
PA4
30
I/O
TTL
GPIO port A bit 4.
PA5
31
I/O
TTL
GPIO port A bit 5.
PA6
34
I/O
TTL
GPIO port A bit 6.
PB0
66
I/O
TTL
GPIO port B bit 0.
PB1
67
I/O
TTL
GPIO port B bit 1.
PB2
70
I/O
TTL
GPIO port B bit 2.
PB3
71
I/O
TTL
GPIO port B bit 3.
PB4
92
I/O
TTL
GPIO port B bit 4.
PB5
91
I/O
TTL
GPIO port B bit 5.
PB6
90
I/O
TTL
GPIO port B bit 6.
PB7
89
I/O
TTL
GPIO port B bit 7.
PC0
80
I/O
TTL
GPIO port C bit 0.
PC1
79
I/O
TTL
GPIO port C bit 1.
PC2
78
I/O
TTL
GPIO port C bit 2.
PC3
77
I/O
TTL
GPIO port C bit 3.
PD0
10
I/O
TTL
GPIO port D bit 0.
PD1
11
I/O
TTL
GPIO port D bit 1.
PD2
12
I/O
TTL
GPIO port D bit 2.
PD3
13
I/O
TTL
GPIO port D bit 3.
PE0
72
I/O
TTL
GPIO port E bit 0.
PE1
73
I/O
TTL
GPIO port E bit 1.
PE2
74
I/O
TTL
GPIO port E bit 2.
PE3
75
I/O
TTL
GPIO port E bit 3.
No connect. Leave the pin electrically unconnected/isolated.
466
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Table 17-2. Signals by Signal Name (continued)
a
Pin Name
Pin Number
Pin Type
Buffer Type
Description
PE4
6
I/O
TTL
GPIO port E bit 4.
PE5
5
I/O
TTL
GPIO port E bit 5.
PF0
47
I/O
TTL
GPIO port F bit 0.
PF1
61
I/O
TTL
GPIO port F bit 1.
PF2
60
I/O
TTL
GPIO port F bit 2.
PF3
59
I/O
TTL
GPIO port F bit 3.
PG0
19
I/O
TTL
GPIO port G bit 0.
PG1
18
I/O
TTL
GPIO port G bit 1.
RST
64
I
TTL
RXIN
37
I
Analog
RXIN of the Ethernet PHY.
System reset input.
RXIP of the Ethernet PHY.
RXIP
40
I
Analog
SSI0Clk
28
I/O
TTL
SSI module 0 clock.
SSI0Fss
29
I/O
TTL
SSI module 0 frame.
SSI0Rx
30
I
TTL
SSI module 0 receive.
SSI0Tx
31
O
TTL
SSI module 0 transmit.
SSI1Clk
72
I/O
TTL
SSI module 1 clock.
SSI1Fss
73
I/O
TTL
SSI module 1 frame.
SSI1Rx
74
I
TTL
SSI module 1 receive.
SSI1Tx
75
O
TTL
SSI module 1 transmit.
SWCLK
80
I
TTL
JTAG/SWD CLK.
SWDIO
79
I/O
TTL
JTAG TMS and SWDIO.
SWO
77
O
TTL
JTAG TDO and SWO.
TCK
80
I
TTL
JTAG/SWD CLK.
TDI
78
I
TTL
JTAG TDI.
TDO
77
O
TTL
JTAG TDO and SWO.
TMS
79
I/O
TTL
JTAG TMS and SWDIO.
TRST
89
I
TTL
TXON
46
O
Analog
TXON of the Ethernet PHY.
TXOP
43
O
Analog
TXOP of the Ethernet PHY.
U0Rx
26
I
TTL
UART module 0 receive. When in IrDA mode, this signal has
IrDA modulation.
U0Tx
27
O
TTL
UART module 0 transmit. When in IrDA mode, this signal has
IrDA modulation.
VCCPHY
36
83
84
-
Power
VCC of the Ethernet PHY.
VDD
8
20
32
44
55
56
68
81
93
-
Power
Positive supply for I/O and some logic.
JTAG TRST.
June 22, 2010
467
Texas Instruments-Production Data
Signal Tables
Table 17-2. Signals by Signal Name (continued)
a
Pin Name
Pin Number
Pin Type
Buffer Type
Description
VDD25
14
38
62
88
-
Power
Positive supply for most of the logic function, including the
processor core and most peripherals.
VDDA
3
98
-
Power
The positive supply (3.3 V) for the analog circuits (ADC,
Analog Comparators, etc.). These are separated from VDD
to minimize the electrical noise contained on VDD from
affecting the analog functions. VDDA pins must be connected
to 3.3 V, regardless of system implementation.
XTALNPHY
17
O
TTL
Ethernet PHY XTALN 25-MHz oscillator crystal output. Leave
unconnected when using a single-ended 25-MHz clock input
connected to the XTALPPHY pin.
XTALPPHY
16
I
TTL
Ethernet PHY XTALP 25-MHz oscillator crystal input or
external clock reference input.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 17-3. Signals by Function, Except for GPIO
Function
Controller Area
Network
Ethernet
General-Purpose
Timers
Pin Name
a
Pin Number
Pin Type
Buffer Type
10
I
TTL
CAN module 0 receive.
CAN0Tx
11
O
TTL
CAN module 0 transmit.
CAN1Rx
47
I
TTL
CAN module 1 receive.
CAN1Tx
61
O
TTL
CAN module 1 transmit.
CAN2Rx
6
I
TTL
CAN module 2 receive.
CAN2Tx
5
O
TTL
CAN module 2 transmit.
ERBIAS
41
I
Analog
12.4-kΩ resistor (1% precision) used internally for
Ethernet PHY.
GNDPHY
42
85
86
-
Power
GND of the Ethernet PHY.
LED0
59
O
TTL
Ethernet LED 0.
LED1
60
O
TTL
Ethernet LED 1.
MDIO
58
I/O
TTL
MDIO of the Ethernet PHY.
RXIN
37
I
Analog
RXIN of the Ethernet PHY.
RXIP
40
I
Analog
RXIP of the Ethernet PHY.
TXON
46
O
Analog
TXON of the Ethernet PHY.
TXOP
43
O
Analog
TXOP of the Ethernet PHY.
VCCPHY
36
83
84
-
Power
VCC of the Ethernet PHY.
XTALNPHY
17
O
TTL
Ethernet PHY XTALN 25-MHz oscillator crystal
output. Leave unconnected when using a
single-ended 25-MHz clock input connected to the
XTALPPHY pin.
XTALPPHY
16
I
TTL
Ethernet PHY XTALP 25-MHz oscillator crystal
input or external clock reference input.
CCP0
66
I/O
TTL
Capture/Compare/PWM 0.
CCP1
34
I/O
TTL
Capture/Compare/PWM 1.
CAN0Rx
Description
468
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Table 17-3. Signals by Function, Except for GPIO (continued)
Function
I2C
JTAG/SWD/SWO
Power
Pin Name
Pin Number
Pin Type
a
Buffer Type
Description
I2C0SCL
70
I/O
OD
I2C
I2C0SDA
71
I/O
OD
I2C module 0 data.
SWCLK
80
I
TTL
JTAG/SWD CLK.
SWDIO
79
I/O
TTL
JTAG TMS and SWDIO.
SWO
77
O
TTL
JTAG TDO and SWO.
TCK
80
I
TTL
JTAG/SWD CLK.
TDI
78
I
TTL
JTAG TDI.
TDO
77
O
TTL
JTAG TDO and SWO.
TMS
79
I/O
TTL
JTAG TMS and SWDIO.
TRST
89
I
TTL
JTAG TRST.
GND
9
15
21
33
39
45
54
57
63
69
82
87
94
-
Power
Ground reference for logic and I/O pins.
GNDA
4
97
-
Power
The ground reference for the analog circuits ( etc.).
These are separated from GND to minimize the
electrical noise contained on VDD from affecting the
analog functions.
LDO
7
-
Power
Low drop-out regulator output voltage. This pin
requires an external capacitor between the pin and
GND of 1 µF or greater. When the on-chip LDO is
used to provide power to the logic, the LDO pin must
also be connected to the VDD25 pins at the board
level in addition to the decoupling capacitor(s).
VDD
8
20
32
44
55
56
68
81
93
-
Power
Positive supply for I/O and some logic.
VDD25
14
38
62
88
-
Power
Positive supply for most of the logic function,
including the processor core and most peripherals.
VDDA
3
98
-
Power
The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions. VDDA pins must be connected to 3.3 V,
regardless of system implementation.
June 22, 2010
module 0 clock.
469
Texas Instruments-Production Data
Signal Tables
Table 17-3. Signals by Function, Except for GPIO (continued)
Function
SSI
System Control &
Clocks
UART
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
SSI0Clk
28
I/O
TTL
SSI module 0 clock.
SSI0Fss
29
I/O
TTL
SSI module 0 frame.
SSI0Rx
30
I
TTL
SSI module 0 receive.
SSI0Tx
31
O
TTL
SSI module 0 transmit.
SSI1Clk
72
I/O
TTL
SSI module 1 clock.
SSI1Fss
73
I/O
TTL
SSI module 1 frame.
SSI1Rx
74
I
TTL
SSI module 1 receive.
SSI1Tx
75
O
TTL
SSI module 1 transmit.
CMOD0
65
I
TTL
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
CMOD1
76
I
TTL
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
OSC0
48
I
Analog
Main oscillator crystal input or an external clock
reference input.
OSC1
49
O
Analog
Main oscillator crystal output. Leave unconnected
when using a single-ended clock source.
RST
64
I
TTL
System reset input.
U0Rx
26
I
TTL
UART module 0 receive. When in IrDA mode, this
signal has IrDA modulation.
U0Tx
27
O
TTL
UART module 0 transmit. When in IrDA mode, this
signal has IrDA modulation.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 17-4. GPIO Pins and Alternate Functions
IO
Pin Number
Multiplexed Function
PA0
26
U0Rx
PA1
27
U0Tx
PA2
28
SSI0Clk
PA3
29
SSI0Fss
PA4
30
SSI0Rx
PA5
31
SSI0Tx
PA6
34
CCP1
PB0
66
CCP0
PB1
67
PB2
70
I2C0SCL
PB3
71
I2C0SDA
PB4
92
PB5
91
PB6
90
PB7
89
TRST
PC0
80
TCK
SWCLK
PC1
79
TMS
SWDIO
PC2
78
TDI
470
Multiplexed Function
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Table 17-4. GPIO Pins and Alternate Functions (continued)
17.2
IO
Pin Number
Multiplexed Function
Multiplexed Function
PC3
PD0
77
TDO
SWO
10
CAN0Rx
PD1
11
CAN0Tx
PD2
12
PD3
13
PE0
72
SSI1Clk
PE1
73
SSI1Fss
PE2
74
SSI1Rx
PE3
75
SSI1Tx
PE4
6
CAN2Rx
PE5
5
CAN2Tx
PF0
47
CAN1Rx
PF1
61
CAN1Tx
PF2
60
LED1
PF3
59
LED0
PG0
19
PG1
18
108-Pin BGA Package Pin Tables
Table 17-5. Signals by Pin Number
a
Pin Number
Pin Name
Pin Type
Buffer Type
A1
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
A2
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
A3
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
A4
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
A5
GNDA
-
Power
A6
PB4
I/O
TTL
GPIO port B bit 4.
A7
PB6
I/O
TTL
GPIO port B bit 6.
A8
A9
A10
A11
Description
The ground reference for the analog circuits ( etc.). These are
separated from GND to minimize the electrical noise contained on
VDD from affecting the analog functions.
PB7
I/O
TTL
GPIO port B bit 7.
TRST
I
TTL
JTAG TRST.
PC0
I/O
TTL
GPIO port C bit 0.
SWCLK
I
TTL
JTAG/SWD CLK.
TCK
I
TTL
JTAG/SWD CLK.
PC3
I/O
TTL
GPIO port C bit 3.
SWO
O
TTL
JTAG TDO and SWO.
TDO
O
TTL
JTAG TDO and SWO.
PE0
I/O
TTL
GPIO port E bit 0.
SSI1Clk
I/O
TTL
SSI module 1 clock.
June 22, 2010
471
Texas Instruments-Production Data
Signal Tables
Table 17-5. Signals by Pin Number (continued)
Pin Number
A12
a
Pin Name
Pin Type
Buffer Type
Description
PE3
I/O
TTL
GPIO port E bit 3.
SSI1Tx
O
TTL
SSI module 1 transmit.
B1
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
B2
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
B3
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
B4
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
B5
GNDA
-
Power
The ground reference for the analog circuits ( etc.). These are
separated from GND to minimize the electrical noise contained on
VDD from affecting the analog functions.
B6
GND
-
Power
Ground reference for logic and I/O pins.
B7
PB5
I/O
TTL
GPIO port B bit 5.
B8
PC2
I/O
TTL
GPIO port C bit 2.
TDI
I
TTL
JTAG TDI.
PC1
I/O
TTL
GPIO port C bit 1.
SWDIO
I/O
TTL
JTAG TMS and SWDIO.
TMS
I/O
TTL
JTAG TMS and SWDIO.
B10
CMOD1
I
TTL
CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
B11
PE2
I/O
TTL
GPIO port E bit 2.
SSI1Rx
I
TTL
SSI module 1 receive.
PE1
I/O
TTL
GPIO port E bit 1.
SSI1Fss
I/O
TTL
SSI module 1 frame.
C1
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
C2
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
C3
VDD25
-
Power
Positive supply for most of the logic function, including the
processor core and most peripherals.
C4
GND
-
Power
Ground reference for logic and I/O pins.
C5
GND
-
Power
Ground reference for logic and I/O pins.
C6
VDDA
-
Power
The positive supply (3.3 V) for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be connected to 3.3 V, regardless of
system implementation.
C7
VDDA
-
Power
The positive supply (3.3 V) for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be connected to 3.3 V, regardless of
system implementation.
C8
GNDPHY
-
Power
GND of the Ethernet PHY.
B9
B12
C9
GNDPHY
-
Power
GND of the Ethernet PHY.
C10
VCCPHY
-
Power
VCC of the Ethernet PHY.
C11
PB2
I/O
TTL
GPIO port B bit 2.
I2C0SCL
I/O
OD
I2C module 0 clock.
PB3
I/O
TTL
GPIO port B bit 3.
I2C0SDA
I/O
OD
I2C module 0 data.
C12
472
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Table 17-5. Signals by Pin Number (continued)
Pin Number
D1
D2
a
Pin Name
Pin Type
Buffer Type
Description
PE4
I/O
TTL
GPIO port E bit 4.
CAN2Rx
I
TTL
CAN module 2 receive.
PE5
I/O
TTL
GPIO port E bit 5.
CAN module 2 transmit.
CAN2Tx
O
TTL
D3
VDD25
-
Power
Positive supply for most of the logic function, including the
processor core and most peripherals.
D10
VCCPHY
-
Power
VCC of the Ethernet PHY.
VCC of the Ethernet PHY.
D11
VCCPHY
-
Power
D12
PB1
I/O
TTL
E1
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
No connect. Leave the pin electrically unconnected/isolated.
GPIO port B bit 1.
E2
NC
-
-
E3
LDO
-
Power
Low drop-out regulator output voltage. This pin requires an external
capacitor between the pin and GND of 1 µF or greater. When the
on-chip LDO is used to provide power to the logic, the LDO pin
must also be connected to the VDD25 pins at the board level in
addition to the decoupling capacitor(s).
E10
VDD33
-
Power
Positive supply for I/O and some logic.
E11
CMOD0
I
TTL
CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
E12
PB0
I/O
TTL
GPIO port B bit 0.
CCP0
I/O
TTL
Capture/Compare/PWM 0.
F1
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
F2
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
F3
VDD25
-
Power
Positive supply for most of the logic function, including the
processor core and most peripherals.
F10
GND
-
Power
Ground reference for logic and I/O pins.
F11
GND
-
Power
Ground reference for logic and I/O pins.
F12
GND
-
Power
Ground reference for logic and I/O pins.
G1
G2
PD0
I/O
TTL
GPIO port D bit 0.
CAN0Rx
I
TTL
CAN module 0 receive.
PD1
I/O
TTL
GPIO port D bit 1.
CAN module 0 transmit.
CAN0Tx
O
TTL
G3
VDD25
-
Power
Positive supply for most of the logic function, including the
processor core and most peripherals.
G10
VDD33
-
Power
Positive supply for I/O and some logic.
G11
VDD33
-
Power
Positive supply for I/O and some logic.
G12
VDD33
-
Power
Positive supply for I/O and some logic.
H1
PD3
I/O
TTL
GPIO port D bit 3.
H2
PD2
I/O
TTL
GPIO port D bit 2.
H3
GND
-
Power
Ground reference for logic and I/O pins.
H10
VDD33
-
Power
Positive supply for I/O and some logic.
H11
RST
I
TTL
System reset input.
H12
PF1
I/O
TTL
GPIO port F bit 1.
CAN1Tx
O
TTL
CAN module 1 transmit.
June 22, 2010
473
Texas Instruments-Production Data
Signal Tables
Table 17-5. Signals by Pin Number (continued)
a
Pin Number
Pin Name
Pin Type
Buffer Type
J1
XTALNPHY
O
TTL
Ethernet PHY XTALN 25-MHz oscillator crystal output. Leave
unconnected when using a single-ended 25-MHz clock input
connected to the XTALPPHY pin.
J2
XTALPPHY
I
TTL
Ethernet PHY XTALP 25-MHz oscillator crystal input or external
clock reference input.
J3
GND
-
Power
Ground reference for logic and I/O pins.
J10
GND
-
Power
Ground reference for logic and I/O pins.
J11
J12
Description
PF2
I/O
TTL
GPIO port F bit 2.
LED1
O
TTL
Ethernet LED 1.
PF3
I/O
TTL
GPIO port F bit 3.
LED0
O
TTL
Ethernet LED 0.
PG0
I/O
TTL
GPIO port G bit 0.
K2
PG1
I/O
TTL
GPIO port G bit 1.
K3
ERBIAS
I
Analog
12.4-kΩ resistor (1% precision) used internally for Ethernet PHY.
K4
GNDPHY
-
Power
GND of the Ethernet PHY.
K5
GND
-
Power
Ground reference for logic and I/O pins.
K6
GND
-
Power
Ground reference for logic and I/O pins.
K7
VDD33
-
Power
Positive supply for I/O and some logic.
K8
VDD33
-
Power
Positive supply for I/O and some logic.
K9
VDD33
-
Power
Positive supply for I/O and some logic.
K10
GND
-
Power
Ground reference for logic and I/O pins.
K11
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
K12
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
L1
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
No connect. Leave the pin electrically unconnected/isolated.
K1
L2
NC
-
-
L3
PA0
I/O
TTL
GPIO port A bit 0.
U0Rx
I
TTL
UART module 0 receive. When in IrDA mode, this signal has IrDA
modulation.
PA3
I/O
TTL
GPIO port A bit 3.
SSI0Fss
I/O
TTL
SSI module 0 frame.
PA4
I/O
TTL
GPIO port A bit 4.
SSI0Rx
I
TTL
SSI module 0 receive.
PA6
I/O
TTL
GPIO port A bit 6.
CCP1
I/O
TTL
Capture/Compare/PWM 1.
L4
L5
L6
L7
RXIN
I
Analog
RXIN of the Ethernet PHY.
L8
TXON
O
Analog
TXON of the Ethernet PHY.
L9
MDIO
I/O
TTL
MDIO of the Ethernet PHY.
L10
GND
-
Power
Ground reference for logic and I/O pins.
L11
OSC0
I
Analog
Main oscillator crystal input or an external clock reference input.
L12
VDD
-
Power
Positive supply for I/O and some logic.
M1
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
M2
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
474
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Table 17-5. Signals by Pin Number (continued)
Pin Number
M3
M4
M5
a
Pin Name
Pin Type
Buffer Type
Description
PA1
I/O
TTL
GPIO port A bit 1.
U0Tx
O
TTL
UART module 0 transmit. When in IrDA mode, this signal has IrDA
modulation.
PA2
I/O
TTL
GPIO port A bit 2.
SSI0Clk
I/O
TTL
SSI module 0 clock.
PA5
I/O
TTL
GPIO port A bit 5.
SSI0Tx
O
TTL
SSI module 0 transmit.
M6
NC
-
-
M7
RXIP
I
Analog
RXIP of the Ethernet PHY.
M8
TXOP
O
Analog
TXOP of the Ethernet PHY.
PF0
I/O
TTL
GPIO port F bit 0.
CAN1Rx
I
TTL
CAN module 1 receive.
M9
No connect. Leave the pin electrically unconnected/isolated.
M10
NC
-
-
M11
OSC1
O
Analog
No connect. Leave the pin electrically unconnected/isolated.
M12
NC
-
-
Main oscillator crystal output. Leave unconnected when using a
single-ended clock source.
No connect. Leave the pin electrically unconnected/isolated.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 17-6. Signals by Signal Name
a
Pin Name
Pin Number
Pin Type
Buffer Type
Description
CAN0Rx
G1
I
TTL
CAN module 0 receive.
CAN0Tx
G2
O
TTL
CAN module 0 transmit.
CAN1Rx
M9
I
TTL
CAN module 1 receive.
CAN1Tx
H12
O
TTL
CAN module 1 transmit.
CAN2Rx
D1
I
TTL
CAN module 2 receive.
CAN2Tx
D2
O
TTL
CAN module 2 transmit.
CCP0
E12
I/O
TTL
Capture/Compare/PWM 0.
CCP1
L6
I/O
TTL
Capture/Compare/PWM 1.
CMOD0
E11
I
TTL
CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
CMOD1
B10
I
TTL
CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
ERBIAS
K3
I
Analog
12.4-kΩ resistor (1% precision) used internally for Ethernet
PHY.
GND
B6
C4
C5
F10
F11
F12
H3
J3
J10
K5
K6
K10
L10
-
Power
Ground reference for logic and I/O pins.
June 22, 2010
475
Texas Instruments-Production Data
Signal Tables
Table 17-6. Signals by Signal Name (continued)
a
Pin Name
Pin Number
Pin Type
Buffer Type
Description
GNDA
A5
B5
-
Power
The ground reference for the analog circuits ( etc.). These
are separated from GND to minimize the electrical noise
contained on VDD from affecting the analog functions.
GNDPHY
C8
C9
K4
-
Power
GND of the Ethernet PHY.
I2C0SCL
C11
I/O
OD
I2C module 0 clock.
I2C0SDA
C12
I/O
OD
I2C module 0 data.
LDO
E3
-
Power
LED0
J12
O
TTL
Ethernet LED 0.
LED1
J11
O
TTL
Ethernet LED 1.
MDIO
L9
I/O
TTL
MDIO of the Ethernet PHY.
NC
A1
A2
A3
A4
B1
B2
B3
B4
C1
C2
E1
E2
F1
F2
K11
K12
L1
L2
M1
M2
M6
M10
M12
-
-
OSC0
L11
I
Analog
Main oscillator crystal input or an external clock reference
input.
OSC1
M11
O
Analog
Main oscillator crystal output. Leave unconnected when using
a single-ended clock source.
PA0
L3
I/O
TTL
GPIO port A bit 0.
PA1
M3
I/O
TTL
GPIO port A bit 1.
PA2
M4
I/O
TTL
GPIO port A bit 2.
PA3
L4
I/O
TTL
GPIO port A bit 3.
PA4
L5
I/O
TTL
GPIO port A bit 4.
PA5
M5
I/O
TTL
GPIO port A bit 5.
PA6
L6
I/O
TTL
GPIO port A bit 6.
Low drop-out regulator output voltage. This pin requires an
external capacitor between the pin and GND of 1 µF or
greater. When the on-chip LDO is used to provide power to
the logic, the LDO pin must also be connected to the VDD25
pins at the board level in addition to the decoupling
capacitor(s).
No connect. Leave the pin electrically unconnected/isolated.
476
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Table 17-6. Signals by Signal Name (continued)
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
PB0
E12
I/O
TTL
GPIO port B bit 0.
PB1
D12
I/O
TTL
GPIO port B bit 1.
PB2
C11
I/O
TTL
GPIO port B bit 2.
PB3
C12
I/O
TTL
GPIO port B bit 3.
PB4
A6
I/O
TTL
GPIO port B bit 4.
PB5
B7
I/O
TTL
GPIO port B bit 5.
PB6
A7
I/O
TTL
GPIO port B bit 6.
PB7
A8
I/O
TTL
GPIO port B bit 7.
PC0
A9
I/O
TTL
GPIO port C bit 0.
PC1
B9
I/O
TTL
GPIO port C bit 1.
PC2
B8
I/O
TTL
GPIO port C bit 2.
PC3
A10
I/O
TTL
GPIO port C bit 3.
PD0
G1
I/O
TTL
GPIO port D bit 0.
PD1
G2
I/O
TTL
GPIO port D bit 1.
PD2
H2
I/O
TTL
GPIO port D bit 2.
PD3
H1
I/O
TTL
GPIO port D bit 3.
PE0
A11
I/O
TTL
GPIO port E bit 0.
PE1
B12
I/O
TTL
GPIO port E bit 1.
PE2
B11
I/O
TTL
GPIO port E bit 2.
PE3
A12
I/O
TTL
GPIO port E bit 3.
PE4
D1
I/O
TTL
GPIO port E bit 4.
PE5
D2
I/O
TTL
GPIO port E bit 5.
PF0
M9
I/O
TTL
GPIO port F bit 0.
PF1
H12
I/O
TTL
GPIO port F bit 1.
PF2
J11
I/O
TTL
GPIO port F bit 2.
PF3
J12
I/O
TTL
GPIO port F bit 3.
PG0
K1
I/O
TTL
GPIO port G bit 0.
PG1
K2
I/O
TTL
GPIO port G bit 1.
RST
H11
I
TTL
RXIN
L7
I
Analog
RXIN of the Ethernet PHY.
System reset input.
RXIP
M7
I
Analog
RXIP of the Ethernet PHY.
SSI0Clk
M4
I/O
TTL
SSI module 0 clock.
SSI0Fss
L4
I/O
TTL
SSI module 0 frame.
SSI0Rx
L5
I
TTL
SSI module 0 receive.
SSI0Tx
M5
O
TTL
SSI module 0 transmit.
SSI1Clk
A11
I/O
TTL
SSI module 1 clock.
SSI1Fss
B12
I/O
TTL
SSI module 1 frame.
SSI1Rx
B11
I
TTL
SSI module 1 receive.
SSI1Tx
A12
O
TTL
SSI module 1 transmit.
SWCLK
A9
I
TTL
JTAG/SWD CLK.
SWDIO
B9
I/O
TTL
JTAG TMS and SWDIO.
June 22, 2010
477
Texas Instruments-Production Data
Signal Tables
Table 17-6. Signals by Signal Name (continued)
a
Pin Name
Pin Number
Pin Type
Buffer Type
Description
SWO
A10
O
TTL
JTAG TDO and SWO.
TCK
A9
I
TTL
JTAG/SWD CLK.
TDI
B8
I
TTL
JTAG TDI.
TDO
A10
O
TTL
JTAG TDO and SWO.
TMS
B9
I/O
TTL
JTAG TMS and SWDIO.
TRST
A8
I
TTL
TXON
L8
O
Analog
TXON of the Ethernet PHY.
TXOP
M8
O
Analog
TXOP of the Ethernet PHY.
U0Rx
L3
I
TTL
UART module 0 receive. When in IrDA mode, this signal has
IrDA modulation.
U0Tx
M3
O
TTL
UART module 0 transmit. When in IrDA mode, this signal has
IrDA modulation.
VCCPHY
C10
D10
D11
-
Power
VCC of the Ethernet PHY.
VDD
L12
-
Power
Positive supply for I/O and some logic.
VDD25
C3
D3
F3
G3
-
Power
Positive supply for most of the logic function, including the
processor core and most peripherals.
VDD33
E10
G10
G11
G12
H10
K7
K8
K9
-
Power
Positive supply for I/O and some logic.
VDDA
C6
C7
-
Power
The positive supply (3.3 V) for the analog circuits (ADC,
Analog Comparators, etc.). These are separated from VDD
to minimize the electrical noise contained on VDD from
affecting the analog functions. VDDA pins must be connected
to 3.3 V, regardless of system implementation.
XTALNPHY
J1
O
TTL
Ethernet PHY XTALN 25-MHz oscillator crystal output. Leave
unconnected when using a single-ended 25-MHz clock input
connected to the XTALPPHY pin.
XTALPPHY
J2
I
TTL
Ethernet PHY XTALP 25-MHz oscillator crystal input or
external clock reference input.
JTAG TRST.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 17-7. Signals by Function, Except for GPIO
Function
Controller Area
Network
Pin Name
a
Pin Number
Pin Type
Buffer Type
CAN0Rx
G1
I
TTL
CAN module 0 receive.
Description
CAN0Tx
G2
O
TTL
CAN module 0 transmit.
CAN1Rx
M9
I
TTL
CAN module 1 receive.
CAN1Tx
H12
O
TTL
CAN module 1 transmit.
CAN2Rx
D1
I
TTL
CAN module 2 receive.
CAN2Tx
D2
O
TTL
CAN module 2 transmit.
478
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Table 17-7. Signals by Function, Except for GPIO (continued)
Function
Ethernet
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
ERBIAS
K3
I
Analog
12.4-kΩ resistor (1% precision) used internally for
Ethernet PHY.
GNDPHY
C8
C9
K4
-
Power
GND of the Ethernet PHY.
LED0
J12
O
TTL
Ethernet LED 0.
LED1
J11
O
TTL
Ethernet LED 1.
MDIO
L9
I/O
TTL
MDIO of the Ethernet PHY.
RXIN
L7
I
Analog
RXIN of the Ethernet PHY.
RXIP
M7
I
Analog
RXIP of the Ethernet PHY.
TXON
L8
O
Analog
TXON of the Ethernet PHY.
TXOP
M8
O
Analog
TXOP of the Ethernet PHY.
VCCPHY
C10
D10
D11
-
Power
VCC of the Ethernet PHY.
XTALNPHY
J1
O
TTL
Ethernet PHY XTALN 25-MHz oscillator crystal
output. Leave unconnected when using a
single-ended 25-MHz clock input connected to the
XTALPPHY pin.
XTALPPHY
J2
I
TTL
Ethernet PHY XTALP 25-MHz oscillator crystal
input or external clock reference input.
General-Purpose
Timers
CCP0
E12
I/O
TTL
Capture/Compare/PWM 0.
CCP1
L6
I/O
TTL
Capture/Compare/PWM 1.
I2C
I2C0SCL
C11
I/O
OD
I2C module 0 clock.
I2C0SDA
C12
I/O
OD
I2C module 0 data.
A9
I
TTL
JTAG/SWD CLK.
SWDIO
B9
I/O
TTL
JTAG TMS and SWDIO.
SWO
A10
O
TTL
JTAG TDO and SWO.
TCK
A9
I
TTL
JTAG/SWD CLK.
TDI
B8
I
TTL
JTAG TDI.
TDO
A10
O
TTL
JTAG TDO and SWO.
TMS
B9
I/O
TTL
JTAG TMS and SWDIO.
TRST
A8
I
TTL
JTAG TRST.
JTAG/SWD/SWO
SWCLK
June 22, 2010
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Texas Instruments-Production Data
Signal Tables
Table 17-7. Signals by Function, Except for GPIO (continued)
Function
Power
SSI
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
GND
B6
C4
C5
F10
F11
F12
H3
J3
J10
K5
K6
K10
L10
-
Power
Ground reference for logic and I/O pins.
GNDA
A5
B5
-
Power
The ground reference for the analog circuits ( etc.).
These are separated from GND to minimize the
electrical noise contained on VDD from affecting the
analog functions.
LDO
E3
-
Power
Low drop-out regulator output voltage. This pin
requires an external capacitor between the pin and
GND of 1 µF or greater. When the on-chip LDO is
used to provide power to the logic, the LDO pin must
also be connected to the VDD25 pins at the board
level in addition to the decoupling capacitor(s).
VDD
L12
-
Power
Positive supply for I/O and some logic.
VDD25
C3
D3
F3
G3
-
Power
Positive supply for most of the logic function,
including the processor core and most peripherals.
VDD33
E10
G10
G11
G12
H10
K7
K8
K9
-
Power
Positive supply for I/O and some logic.
VDDA
C6
C7
-
Power
The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions. VDDA pins must be connected to 3.3 V,
regardless of system implementation.
SSI0Clk
M4
I/O
TTL
SSI module 0 clock.
SSI0Fss
L4
I/O
TTL
SSI module 0 frame.
SSI0Rx
L5
I
TTL
SSI module 0 receive.
SSI0Tx
M5
O
TTL
SSI module 0 transmit.
SSI1Clk
A11
I/O
TTL
SSI module 1 clock.
SSI1Fss
B12
I/O
TTL
SSI module 1 frame.
SSI1Rx
B11
I
TTL
SSI module 1 receive.
SSI1Tx
A12
O
TTL
SSI module 1 transmit.
480
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Table 17-7. Signals by Function, Except for GPIO (continued)
Function
System Control &
Clocks
UART
Pin Name
a
Pin Number
Pin Type
Buffer Type
Description
CMOD0
E11
I
TTL
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
CMOD1
B10
I
TTL
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
OSC0
L11
I
Analog
Main oscillator crystal input or an external clock
reference input.
OSC1
M11
O
Analog
Main oscillator crystal output. Leave unconnected
when using a single-ended clock source.
RST
H11
I
TTL
System reset input.
U0Rx
L3
I
TTL
UART module 0 receive. When in IrDA mode, this
signal has IrDA modulation.
U0Tx
M3
O
TTL
UART module 0 transmit. When in IrDA mode, this
signal has IrDA modulation.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 17-8. GPIO Pins and Alternate Functions
IO
Pin Number
Multiplexed Function
PA0
L3
U0Rx
PA1
M3
U0Tx
PA2
M4
SSI0Clk
PA3
L4
SSI0Fss
PA4
L5
SSI0Rx
PA5
M5
SSI0Tx
PA6
L6
CCP1
PB0
E12
CCP0
PB1
D12
PB2
C11
I2C0SCL
I2C0SDA
Multiplexed Function
PB3
C12
PB4
A6
PB5
B7
PB6
A7
PB7
A8
TRST
PC0
A9
TCK
SWCLK
PC1
B9
TMS
SWDIO
PC2
B8
TDI
PC3
A10
TDO
PD0
G1
CAN0Rx
PD1
G2
CAN0Tx
PD2
H2
PD3
H1
PE0
A11
SSI1Clk
PE1
B12
SSI1Fss
PE2
B11
SSI1Rx
June 22, 2010
SWO
481
Texas Instruments-Production Data
Signal Tables
Table 17-8. GPIO Pins and Alternate Functions (continued)
17.3
IO
Pin Number
Multiplexed Function
PE3
A12
SSI1Tx
PE4
D1
CAN2Rx
PE5
D2
CAN2Tx
PF0
M9
CAN1Rx
PF1
H12
CAN1Tx
PF2
J11
LED1
PF3
J12
LED0
PG0
K1
PG1
K2
Multiplexed Function
Connections for Unused Signals
Table 17-9 on page 482 show how to handle signals for functions that are not used in a particular
system implementation for devices that are in a 100-pin LQFP package. Two options are shown in
the table: an acceptable practice and a preferred practice for reduced power consumption and
improved EMC characteristics. If a module is not used in a system, and its inputs are grounded, it
is important that the clock to the module is never enabled by setting the corresponding bit in the
RCGCx register.
Table 17-9. Connections for Unused Signals (100-pin LQFP)
Function
Signal Name
Pin Number
Acceptable Practice
Preferred Practice
Ethernet
ERBIAS
41
Connect to GND through
12.4-kΩ resistor.
Connect to GND through 12.4-kΩ
resistor.
MDIO
58
NC
NC
RXIN
37
NC
GND
RXIP
40
NC
GND
TXON
46
NC
GND
GPIO
No Connects
System
Control
TXOP
43
NC
GND
XTALNPHY
17
NC
NC
XTALPPHY
16
NC
GND
All unused GPIOs
-
NC
GND
NC
-
NC
NC
OSC0
48
NC
GND
OSC1
49
NC
NC
RST
48
Pull up as shown in Figure
6-1 on page 64
Connect through a capacitor to
GND as close to pin as possible
Table 17-10 on page 483 show how to handle signals for functions that are not used in a particular
system implementation for devices that are in a 108-pin BGA package. Two options are shown in
the table: an acceptable practice and a preferred practice for reduced power consumption and
improved EMC characteristics. If a module is not used in a system, and its inputs are grounded, it
is important that the clock to the module is never enabled by setting the corresponding bit in the
RCGCx register.
482
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Table 17-10. Connections for Unused Signals, 108-pin BGA
Function
Signal Name
Pin Number
Acceptable Practice
Preferred Practice
Ethernet
ERBIAS
K3
Connect to GND through
12.4-kΩ resistor.
Connect to GND through 12.4-kΩ
resistor.
MDIO
L9
NC
NC
RXIN
L7
NC
GND
RXIP
M7
NC
GND
TXON
L8
NC
GND
TXOP
M8
NC
GND
XTALNPHY
J1
NC
NC
XTALPPHY
J2
NC
GND
All unused GPIOs
-
NC
GND
GPIO
No Connects
System
Control
NC
-
NC
NC
OSC0
L11
NC
GND
OSC1
M11
NC
NC
RST
H11
Pull up as shown in Figure
6-1 on page 64
Connect through a capacitor to
GND as close to pin as possible
June 22, 2010
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Texas Instruments-Production Data
Operating Characteristics
18
Operating Characteristics
Table 18-1. Temperature Characteristics
Characteristic
Symbol
Value
Industrial operating temperature range
TA
-40 to +85
Unit
°C
Extended operating temperature range
TA
-40 to +105
°C
Unpowered storage temperature range
TS
-65 to +150
°C
Table 18-2. Thermal Characteristics
Characteristic
a
Thermal resistance (junction to ambient)
b
Average junction temperature
Symbol
Value
ΘJA
32
Unit
TJ
TA + (PAVG • ΘJA)
°C/W
°C
a. Junction to ambient thermal resistance θJA numbers are determined by a package simulator.
b. Power dissipation is a function of temperature.
a
Table 18-3. ESD Absolute Maximum Ratings
Parameter Name
Min
Nom
Max
Unit
VESDHBM
-
-
2.0
kV
VESDCDM
-
-
1.0
kV
VESDMM
-
-
100
V
a. All Stellaris parts are ESD tested following the JEDEC standard.
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Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
19
Electrical Characteristics
19.1
DC Characteristics
19.1.1
Maximum Ratings
The maximum ratings are the limits to which the device can be subjected without permanently
damaging the device.
Note:
The device is not guaranteed to operate properly at the maximum ratings.
Table 19-1. Maximum Ratings
Characteristic
Symbol
a
Value
Unit
Min
Max
VDD
0
4
V
Core supply voltage (VDD25)
VDD25
0
3
V
Analog supply voltage (VDDA)
VDDA
0
4
V
VCCPHY
0
4
V
VIN
-0.3
5.5
V
I
-
25
mA
I/O supply voltage (VDD)
Ethernet PHY supply voltage (VCCPHY)
Input voltage
Maximum current per output pins
a. Voltages are measured with respect to GND.
Important: This device contains circuitry to protect the inputs against damage due to high-static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are
connected to an appropriate logic voltage level (for example, either GND or VDD).
19.1.2
Recommended DC Operating Conditions
For special high-current applications, the GPIO output buffers may be used with the following
restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may
be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is
specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only
a maximum of two per side of the physical package or BGA pin group with the total number of
high-current GPIO outputs not exceeding four for the entire package.
Table 19-2. Recommended DC Operating Conditions
Parameter
Parameter Name
Min
Nom
Max
Unit
VDD
I/O supply voltage
3.0
3.3
3.6
V
VDD25
Core supply voltage
2.25
2.5
2.75
V
VDDA
Analog supply voltage
3.0
3.3
3.6
V
Ethernet PHY supply voltage
3.0
3.3
3.6
V
VCCPHY
VIH
High-level input voltage
2.0
-
5.0
V
VIL
Low-level input voltage
-0.3
-
1.3
V
a
VOH
High-level output voltage
2.4
-
-
V
VOLa
Low-level output voltage
-
-
0.4
V
June 22, 2010
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Texas Instruments-Production Data
Electrical Characteristics
Table 19-2. Recommended DC Operating Conditions (continued)
Parameter
IOH
IOL
Parameter Name
Min
Nom
Max
Unit
2-mA Drive
2.0
-
-
mA
4-mA Drive
4.0
-
-
mA
8-mA Drive
8.0
-
-
mA
2-mA Drive
2.0
-
-
mA
4-mA Drive
4.0
-
-
mA
8-mA Drive
8.0
-
-
mA
High-level source current, VOH=2.4 V
Low-level sink current, VOL=0.4 V
a. VOL and VOH shift to 1.2 V when using high-current GPIOs.
19.1.3
On-Chip Low Drop-Out (LDO) Regulator Characteristics
Table 19-3. LDO Regulator Characteristics
Parameter
Parameter Name
Min
Nom
Max
Unit
Programmable internal (logic) power supply
output value
2.25
2.5
2.75
V
Output voltage accuracy
-
2%
-
%
tPON
Power-on time
-
-
100
µs
tON
Time on
-
-
200
µs
tOFF
Time off
-
-
100
µs
VSTEP
Step programming incremental voltage
-
50
-
mV
CLDO
External filter capacitor size for internal power
supply
1.0
-
3.0
µF
Min
Nom
Max
Unit
VLDOOUT
19.1.4
GPIO Module Characteristics
Table 19-4. GPIO Module DC Characteristics
Parameter
19.1.5
Parameter Name
RGPIOPU
GPIO internal pull-up resistor
50
-
110
kΩ
RGPIOPD
GPIO internal pull-down resistor
55
-
180
kΩ
Power Specifications
The power measurements specified in the tables that follow are run on the core processor using
SRAM with the following specifications (except as noted):
■ VDD = 3.3 V
■ VDD25 = 2.50 V
■ VDDA = 3.3 V
■ VDDPHY = 3.3 V
■ Temperature = 25°C
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Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
■ Clock Source (MOSC) =3.579545 MHz Crystal Oscillator
■ Main oscillator (MOSC) = enabled
■ Internal oscillator (IOSC) = disabled
Table 19-5. Detailed Power Specifications
Parameter
Parameter Name Conditions
3.3 V VDD, VDDA,
VDDPHY
Nom
IDD_RUN
Run mode 1
(Flash loop)
VDD25 = 2.50 V
Max
a
2.5 V VDD25
Nom
Max
Unit
48
pending
108
pendinga
mA
5
pendinga
52
pendinga
mA
48
pendinga
100
pendinga
mA
5
pendinga
45
pendinga
mA
5
pendinga
16
pendinga
mA
4.6
pendinga
0.21
pendinga
mA
Code= while(1){} executed in Flash
Peripherals = All ON
System Clock = 50 MHz (with PLL)
Run mode 2
(Flash loop)
VDD25 = 2.50 V
Code= while(1){} executed in Flash
Peripherals = All OFF
System Clock = 50 MHz (with PLL)
Run mode 1
(SRAM loop)
VDD25 = 2.50 V
Code= while(1){} executed in SRAM
Peripherals = All ON
System Clock = 50 MHz (with PLL)
Run mode 2
(SRAM loop)
VDD25 = 2.50 V
Code= while(1){} executed in SRAM
Peripherals = All OFF
System Clock = 50 MHz (with PLL)
IDD_SLEEP
Sleep mode
VDD25 = 2.50 V
Peripherals = All OFF
System Clock = 50 MHz (with PLL)
IDD_DEEPSLEEP Deep-Sleep mode LDO = 2.25 V
Peripherals = All OFF
System Clock = IOSC30KHZ/64
a. Pending characterization completion.
19.1.6
Flash Memory Characteristics
Table 19-6. Flash Memory Characteristics
Parameter
Min
Nom
Max
Unit
10,000
100,000
-
cycles
Data retention at average operating temperature
of 85˚C (industrial) or 105˚C (extended)
10
-
-
years
TPROG
Word program time
20
-
-
µs
TERASE
Page erase time
20
-
-
ms
PECYC
TRET
Parameter Name
Number of guaranteed program/erase cycles
a
before failure
June 22, 2010
487
Texas Instruments-Production Data
Electrical Characteristics
Table 19-6. Flash Memory Characteristics (continued)
Parameter
Parameter Name
Min
Nom
Max
Unit
TME
Mass erase time
-
-
250
ms
a. A program/erase cycle is defined as switching the bits from 1-> 0 -> 1.
19.2
AC Characteristics
19.2.1
Load Conditions
Unless otherwise specified, the following conditions are true for all timing measurements. Timing
measurements are for 4-mA drive strength.
Figure 19-1. Load Conditions
CL = 50 pF
pin
GND
19.2.2
Clocks
Table 19-7. Phase Locked Loop (PLL) Characteristics
Parameter
Parameter Name
a
fref_crystal
Crystal reference
referencea
Min
Nom
Max
Unit
3.579545
-
8.192
MHz
fref_ext
External clock
3.579545
-
8.192
MHz
fpll
PLL frequency
-
400
-
MHz
TREADY
PLL lock time
-
-
0.5
ms
b
a. The exact value is determined by the crystal value programmed into the XTAL field of the Run-Mode Clock Configuration
(RCC) register.
b. PLL frequency is automatically calculated by the hardware based on the XTAL field of the RCC register.
Table 19-8 on page 488 shows the actual frequency of the PLL based on the crystal frequency used
(defined by the XTAL field in the RCC register).
Table 19-8. Actual PLL Frequency
XTAL
Crystal Frequency (MHz)
PLL Frequency (MHz)
Error
0x4
0x5
3.5795
400.904
0.0023%
3.6864
398.1312
0.0047%
0x6
4.0
400
-
0x7
4.096
401.408
0.0035%
0x8
4.9152
398.1312
0.0047%
0x9
5.0
400
-
0xA
5.12
399.36
0.0016%
0xB
6.0
400
-
0xC
6.144
399.36
0.0016%
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June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Table 19-8. Actual PLL Frequency (continued)
XTAL
Crystal Frequency (MHz)
PLL Frequency (MHz)
Error
0xD
7.3728
398.1312
0.0047%
0xE
8.0
400
0.0047%
0xF
8.192
398.6773333
0.0033%
Table 19-9. Clock Characteristics
Parameter Name
Min
Nom
Max
Unit
fIOSC
Parameter
Internal 12 MHz oscillator frequency
8.4
12
15.6
MHz
fIOSC30KHZ
Internal 30 KHz oscillator frequency
15
30
45
KHz
fMOSC
Main oscillator frequency
tMOSC_per
Main oscillator period
fref_crystal_bypass
1
-
8.192
MHz
125
-
1000
ns
Crystal reference using the main oscillator
(PLL in BYPASS mode)
1
-
8.192
MHz
fref_ext_bypass
External clock reference (PLL in BYPASS
mode)
0
-
50
MHz
fsystem_clock
System clock
0
-
50
MHz
Table 19-10. Crystal Characteristics
Parameter Name
Value
Frequency
Frequency tolerance
Aging
Oscillation mode
8
6
4
3.5
MHz
±50
±50
±50
±50
ppm
±5
±5
±5
±5
ppm/yr
Parallel
Parallel
Parallel
Parallel
-
±25
±25
±25
±25
ppm
Temperature stability (-40°C to 85°C)
19.2.3
Units
Temperature stability (-40°C to 105°C)
±25
±25
±25
±25
ppm
Motional capacitance (typ)
27.8
37.0
55.6
63.5
pF
Motional inductance (typ)
14.3
19.1
28.6
32.7
mH
Equivalent series resistance (max)
120
160
200
220
Ω
Shunt capacitance (max)
10
10
10
10
pF
Load capacitance (typ)
16
16
16
16
pF
Drive level (typ)
100
100
100
100
µW
JTAG and Boundary Scan
Table 19-11. JTAG Characteristics
Parameter
No.
J1
Parameter
Parameter Name
Min
Nom
Max
Unit
0
-
10
MHz
fTCK
TCK operational clock frequency
J2
tTCK
TCK operational clock period
100
-
-
ns
J3
tTCK_LOW
TCK clock Low time
-
tTCK
-
ns
J4
tTCK_HIGH
TCK clock High time
-
tTCK
-
ns
J5
tTCK_R
TCK rise time
0
-
10
ns
J6
tTCK_F
TCK fall time
0
-
10
ns
June 22, 2010
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Texas Instruments-Production Data
Electrical Characteristics
Table 19-11. JTAG Characteristics (continued)
Parameter
No.
Parameter
Parameter Name
Min
Nom
Max
Unit
J7
tTMS_SU
TMS setup time to TCK rise
20
-
-
ns
J8
tTMS_HLD
TMS hold time from TCK rise
20
-
-
ns
J9
tTDI_SU
TDI setup time to TCK rise
25
-
-
ns
J10
tTDI_HLD
TDI hold time from TCK rise
25
-
-
ns
J11
TCK fall to Data
Valid from High-Z
-
t TDO_ZDV
23
35
ns
4-mA drive
2-mA drive
15
26
ns
8-mA drive
14
25
ns
18
29
ns
21
35
ns
4-mA drive
14
25
ns
8-mA drive
13
24
ns
18
28
ns
9
11
ns
4-mA drive
7
9
ns
8-mA drive
6
8
ns
8-mA drive with slew rate control
7
9
ns
8-mA drive with slew rate control
J12
t TDO_DV
TCK fall to Data
Valid from Data
Valid
2-mA drive
-
8-mA drive with slew rate control
J13
t TDO_DVZ
TCK fall to High-Z
from Data Valid
J14
tTRST
J15
tTRST_SU
2-mA drive
-
TRST assertion time
100
-
-
ns
TRST setup time to TCK rise
10
-
-
ns
Figure 19-2. JTAG Test Clock Input Timing
J2
J3
J4
TCK
J6
J5
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June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Figure 19-3. JTAG Test Access Port (TAP) Timing
TCK
J7
TMS
TDI
J8
J7
TMS Input Valid
TMS Input Valid
J9
J9
J10
TDI Input Valid
J11
TDO
J8
J10
TDI Input Valid
J12
J13
TDO Output Valid
TDO Output Valid
Figure 19-4. JTAG TRST Timing
TCK
J14
J15
TRST
19.2.4
Reset
Table 19-12. Reset Characteristics
Parameter
No.
Parameter
Parameter Name
R1
VTH
Reset threshold
R2
VBTH
Brown-Out threshold
R3
TPOR
R4
TBOR
Min
Nom
Max
Unit
-
2.0
-
V
2.85
2.9
2.95
V
Power-On Reset timeout
-
10
-
ms
Brown-Out timeout
-
500
-
µs
R5
TIRPOR
Internal reset timeout after POR
6
-
11
ms
R6
TIRBOR
Internal reset timeout after BOR
0
-
1
µs
R7
TIRHWR
Internal reset timeout after hardware reset
(RST pin)
0
-
1
ms
R8
TIRSWR
Internal reset timeout after software-initiated
system reset a
2.5
-
20
µs
R9
TIRWDR
Internal reset timeout after watchdog reseta
2.5
-
20
µs
R10
TVDDRISE
Supply voltage (VDD) rise time (0V-3.3V)
-
-
100
ms
R11
TMIN
Minimum RST pulse width
2
-
-
µs
a
a. 20 * t MOSC_per
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Figure 19-5. External Reset Timing (RST)
RST
R7
R11
/Reset
(Internal)
Figure 19-6. Power-On Reset Timing
R1
VDD
R3
/POR
(Internal)
R5
/Reset
(Internal)
Figure 19-7. Brown-Out Reset Timing
R2
VDD
R4
/BOR
(Internal)
R6
/Reset
(Internal)
Figure 19-8. Software Reset Timing
SW Reset
R8
/Reset
(Internal)
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Figure 19-9. Watchdog Reset Timing
WDOG
Reset
(Internal)
R9
/Reset
(Internal)
19.2.5
Sleep Modes
a
Table 19-13. Sleep Modes AC Characteristics
Parameter No
Parameter
D1
tWAKE_S
D2
tWAKE_PLL_S
Parameter Name
Min
Nom
Max
Unit
Time to wake from interrupt in sleep or
deep-sleep mode, not using the PLL
-
-
7
system clocks
Time to wake from interrupt in sleep or
deep-sleep mode when using the PLL
-
-
TREADY
ms
a. Values in this table assume the IOSC is the clock source during sleep or deep-sleep mode.
19.2.6
General-Purpose I/O (GPIO)
Note:
All GPIOs are 5 V-tolerant.
Table 19-14. GPIO Characteristics
Parameter Parameter Name Condition
tGPIOR
tGPIOF
19.2.7
GPIO Rise Time
(from 20% to 80%
of VDD)
Min
Nom
Max
Unit
-
17
26
ns
9
13
ns
2-mA drive
4-mA drive
8-mA drive
6
9
ns
8-mA drive with slew rate control
10
12
ns
17
25
ns
8
12
ns
8-mA drive
6
10
ns
8-mA drive with slew rate control
11
13
ns
GPIO Fall Time
(from 80% to 20%
of VDD)
2-mA drive
-
4-mA drive
Synchronous Serial Interface (SSI)
Table 19-15. SSI Characteristics
Parameter
No.
Parameter
Parameter Name
Min
Nom
Max
Unit
S1
tclk_per
SSIClk cycle time
2
-
65024
system clocks
S2
tclk_high
SSIClk high time
-
0.5
-
t clk_per
S3
tclk_low
SSIClk low time
-
0.5
-
t clk_per
S4
tclkrf
SSIClk rise/fall time
-
7.4
26
ns
S5
tDMd
Data from master valid delay time
0
-
1
system clocks
S6
tDMs
Data from master setup time
1
-
-
system clocks
S7
tDMh
Data from master hold time
2
-
-
system clocks
S8
tDSs
Data from slave setup time
1
-
-
system clocks
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Table 19-15. SSI Characteristics (continued)
Parameter
No.
Parameter
S9
Parameter Name
tDSh
Min
Nom
Max
Unit
2
-
-
system clocks
Data from slave hold time
Figure 19-10. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement
S1
S4
S2
SSIClk
S3
SSIFss
SSITx
SSIRx
MSB
LSB
4 to 16 bits
Figure 19-11. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer
S2
S1
SSIClk
S3
SSIFss
SSITx
MSB
LSB
8-bit control
SSIRx
0
MSB
LSB
4 to 16 bits output data
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Figure 19-12. SSI Timing for SPI Frame Format (FRF=00), with SPH=1
S1
S2
S4
SSIClk
(SPO=0)
S3
SSIClk
(SPO=1)
S6
SSITx
(master)
S7
MSB
S5
SSIRx
(slave)
S8
LSB
S9
MSB
LSB
SSIFss
19.2.8
Inter-Integrated Circuit (I2C) Interface
Table 19-16. I2C Characteristics
Parameter
No.
Parameter
Parameter Name
Min
Nom
Max
Unit
a
tSCH
Start condition hold time
36
-
-
system clocks
a
tLP
Clock Low period
36
-
-
system clocks
b
tSRT
I2CSCL/I2CSDA rise time (VIL =0.5 V
to V IH =2.4 V)
-
-
(see note
b)
ns
a
tDH
Data hold time
2
-
-
system clocks
c
tSFT
I2CSCL/I2CSDA fall time (VIH =2.4 V
to V IL =0.5 V)
-
9
10
ns
I1
I2
I3
I4
I5
a
tHT
Clock High time
24
-
-
system clocks
a
tDS
Data setup time
18
-
-
system clocks
a
tSCSR
Start condition setup time (for repeated
start condition only)
36
-
-
system clocks
a
tSCS
Stop condition setup time
24
-
-
system clocks
I6
I7
I8
I9
I2C
a. Values depend on the value programmed into the TPR bit in the
Master Timer Period (I2CMTPR) register; a TPR
programmed for the maximum I2CSCL frequency (TPR=0x2) results in a minimum output timing as shown in the table
above. The I 2C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low
period. The actual position is affected by the value programmed into the TPR; however, the numbers given in the above
values are minimum values.
b. Because I2CSCL and I2CSDA are open-drain-type outputs, which the controller can only actively drive Low, the time
I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
c. Specified at a nominal 50 pF load.
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Figure 19-13. I2C Timing
I2
I6
I5
I2CSCL
I1
I4
I7
I8
I3
I9
I2CSDA
19.2.9
Ethernet Controller
a
Table 19-17. 100BASE-TX Transmitter Characteristics
Parameter Name
Min
Nom
Max
Unit
Peak output amplitude
950
-
1050
mVpk
Output amplitude symmetry
98
-
102
%
Output overshoot
-
-
5
%
Rise/Fall time
3
-
5
ns
Rise/Fall time imbalance
-
-
500
ps
Duty cycle distortion
-
-
-
ps
Jitter
-
-
1.4
ns
a. Measured at the line side of the transformer.
a
Table 19-18. 100BASE-TX Transmitter Characteristics (informative)
Parameter Name
Min
Nom
Max
Unit
Return loss
16
-
-
dB
Open-circuit inductance
350
-
-
µH
a. The specifications in this table are included for information only. They are mainly a function of the external transformer
and termination resistors used for measurements.
Table 19-19. 100BASE-TX Receiver Characteristics
Parameter Name
Min
Nom
Max
Unit
Signal detect assertion threshold
600
700
-
mVppd
Signal detect de-assertion threshold
350
425
-
mVppd
-
20
-
kΩ
Differential input resistance
Jitter tolerance (pk-pk)
Baseline wander tracking
4
-
-
ns
-75
-
+75
%
Signal detect assertion time
-
-
1000
µs
Signal detect de-assertion time
-
-
4
µs
Unit
a
Table 19-20. 10BASE-T Transmitter Characteristics
Parameter Name
Min
Nom
Max
Peak differential output signal
2.2
-
2.8
V
Harmonic content
27
-
-
dB
-
100
-
ns
Link pulse width
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Table 19-20. 10BASE-T Transmitter Characteristics (continued)
Parameter Name
Start-of-idle pulse width
Min
Nom
Max
Unit
-
300
-
ns
350
a. The Manchester-encoded data pulses, the link pulse and the start-of-idle pulse are tested against the templates and using
the procedures found in Clause 14 of IEEE 802.3.
a
Table 19-21. 10BASE-T Transmitter Characteristics (informative)
Parameter Name
Output return loss
Min
Nom
Max
Unit
15
-
-
dB
29-17log(f/10)
-
-
dB
Peak common-mode output voltage
-
-
50
mV
Common-mode rejection
-
-
100
mV
Common-mode rejection jitter
-
-
1
ns
Output impedance balance
a. The specifications in this table are included for information only. They are mainly a function of the external transformer
and termination resistors used for measurements.
Table 19-22. 10BASE-T Receiver Characteristics
Parameter Name
DLL phase acquisition time
Min
Nom
Max
Unit
-
10
-
BT
Jitter tolerance (pk-pk)
30
-
-
ns
Input squelched threshold
500
600
700
mVppd
Input unsquelched threshold
275
350
425
mVppd
Differential input resistance
-
20
-
kΩ
-
10-10
-
-
25
-
-
V
Bit error ratio
Common-mode rejection
a
Table 19-23. Isolation Transformers
Name
Value
Condition
1 CT : 1 CT
+/- 5%
Open-circuit inductance
350 uH (min)
@ 10 mV, 10 kHz
Leakage inductance
0.40 uH (max)
@ 1 MHz (min)
Turns ratio
Inter-winding capacitance
25 pF (max)
DC resistance
0.9 Ohm (max)
Insertion loss
0.4 dB (typ)
0-65 MHz
1500
Vrms
HIPOT
a. Two simple 1:1 isolation transformers are required at the line interface. Transformers with integrated common-mode
chokes are recommended for exceeding FCC requirements. This table gives the recommended line transformer
characteristics.
Note:
The 100Base-TX amplitude specifications assume a transformer loss of 0.4 dB. For the
transmit line transformer with higher insertion losses, up to 1.2 dB of insertion loss can be
compensated by selecting the appropriate setting in the Transmit Amplitude Selection (TXO)
bits in the MR19 register.
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a
Table 19-24. Ethernet Reference Crystal
Name
Value
Frequency
Condition
25.00000
MHz
Frequency tolerance
±50
PPM
Aging
±2
PPM/yr
Temperature stability (-40° to 85°)
±5
PPM
Temperature stability (-40° to 105°)
±5
PPM
Oscillation mode
Parallel resonance, fundamental
mode
Parameters at 25° C ±2° C; Drive level = 0.5 mW
Drive level (typ)
50-100
µW
Shunt capacitance (max)
10
pF
Motional capacitance (min)
10
fF
60
Ω
Series resistance (max)
Spurious response (max)
> 5 dB below main within 500 kHz
a. If the internal crystal oscillator is used, select a crystal that meets these specifications.
Figure 19-14. External XTLP Oscillator Characteristics
Tr
Tf
Tclkhi
Tclklo
Tclkper
Table 19-25. External XTLP Oscillator Characteristics
Parameter Name
Symbol
Min
Nom
Max
Unit
XTLN Input Low Voltage
XTLNILV
-
-
0.8
-
XTLPf
-
25.0
-
-
Tclkper
-
40
-
-
XTLPDC
40
-
60
%
a
XTLP Frequency
b
XTLP Period
XTLP Duty Cycle
40
60
Rise/Fall Time
Tr , Tf
-
-
4.0
ns
Absolute Jitter
TJITTER
-
-
0.1
ns
a. IEEE 802.3 frequency tolerance ±50 ppm.
b. IEEE 802.3 frequency tolerance ±50 ppm.
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A
Serial Flash Loader
A.1
Serial Flash Loader
®
The Stellaris serial flash loader is a preprogrammed flash-resident utility used to download code
to the flash memory of a device without the use of a debug interface. The serial flash loader uses
a simple packet interface to provide synchronous communication with the device. The flash loader
runs off the crystal and does not enable the PLL, so its speed is determined by the crystal used.
The two serial interfaces that can be used are the UART0 and SSI0 interfaces. For simplicity, both
the data format and communication protocol are identical for both serial interfaces.
A.2
Interfaces
Once communication with the flash loader is established via one of the serial interfaces, that interface
is used until the flash loader is reset or new code takes over. For example, once you start
communicating using the SSI port, communications with the flash loader via the UART are disabled
until the device is reset.
A.2.1
UART
The Universal Asynchronous Receivers/Transmitters (UART) communication uses a fixed serial
format of 8 bits of data, no parity, and 1 stop bit. The baud rate used for communication is
automatically detected by the flash loader and can be any valid baud rate supported by the host
and the device. The auto detection sequence requires that the baud rate should be no more than
1/32 the crystal frequency of the board that is running the serial flash loader. This is actually the
®
same as the hardware limitation for the maximum baud rate for any UART on a Stellaris device
which is calculated as follows:
Max Baud Rate = System Clock Frequency / 16
In order to determine the baud rate, the serial flash loader needs to determine the relationship
between its own crystal frequency and the baud rate. This is enough information for the flash loader
to configure its UART to the same baud rate as the host. This automatic baud-rate detection allows
the host to use any valid baud rate that it wants to communicate with the device.
The method used to perform this automatic synchronization relies on the host sending the flash
loader two bytes that are both 0x55. This generates a series of pulses to the flash loader that it can
use to calculate the ratios needed to program the UART to match the host’s baud rate. After the
host sends the pattern, it attempts to read back one byte of data from the UART. The flash loader
returns the value of 0xCC to indicate successful detection of the baud rate. If this byte is not received
after at least twice the time required to transfer the two bytes, the host can resend another pattern
of 0x55, 0x55, and wait for the 0xCC byte again until the flash loader acknowledges that it has
received a synchronization pattern correctly. For example, the time to wait for data back from the
flash loader should be calculated as at least 2*(20(bits/sync)/baud rate (bits/sec)). For a baud rate
of 115200, this time is 2*(20/115200) or 0.35 ms.
A.2.2
SSI
The Synchronous Serial Interface (SSI) port also uses a fixed serial format for communications,
with the framing defined as Motorola format with SPH set to 1 and SPO set to 1. See “Frame
Formats” on page 293 in the SSI chapter for more information on formats for this transfer protocol.
Like the UART, this interface has hardware requirements that limit the maximum speed that the SSI
clock can run. This allows the SSI clock to be at most 1/12 the crystal frequency of the board running
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the flash loader. Since the host device is the master, the SSI on the flash loader device does not
need to determine the clock as it is provided directly by the host.
A.3
Packet Handling
All communications, with the exception of the UART auto-baud, are done via defined packets that
are acknowledged (ACK) or not acknowledged (NAK) by the devices. The packets use the same
format for receiving and sending packets, including the method used to acknowledge successful or
unsuccessful reception of a packet.
A.3.1
Packet Format
All packets sent and received from the device use the following byte-packed format.
struct
{
unsigned char ucSize;
unsigned char ucCheckSum;
unsigned char Data[];
};
A.3.2
ucSize
The first byte received holds the total size of the transfer including
the size and checksum bytes.
ucChecksum
This holds a simple checksum of the bytes in the data buffer only.
The algorithm is Data[0]+Data[1]+…+ Data[ucSize-3].
Data
This is the raw data intended for the device, which is formatted in
some form of command interface. There should be ucSize–2
bytes of data provided in this buffer to or from the device.
Sending Packets
The actual bytes of the packet can be sent individually or all at once; the only limitation is that
commands that cause flash memory access should limit the download sizes to prevent losing bytes
during flash programming. This limitation is discussed further in the section that describes the serial
flash loader command, COMMAND_SEND_DATA (see “COMMAND_SEND_DATA
(0x24)” on page 502).
Once the packet has been formatted correctly by the host, it should be sent out over the UART or
SSI interface. Then the host should poll the UART or SSI interface for the first non-zero data returned
from the device. The first non-zero byte will either be an ACK (0xCC) or a NAK (0x33) byte from
the device indicating the packet was received successfully (ACK) or unsuccessfully (NAK). This
does not indicate that the actual contents of the command issued in the data portion of the packet
were valid, just that the packet was received correctly.
A.3.3
Receiving Packets
The flash loader sends a packet of data in the same format that it receives a packet. The flash loader
may transfer leading zero data before the first actual byte of data is sent out. The first non-zero byte
is the size of the packet followed by a checksum byte, and finally followed by the data itself. There
is no break in the data after the first non-zero byte is sent from the flash loader. Once the device
communicating with the flash loader receives all the bytes, it must either ACK or NAK the packet to
indicate that the transmission was successful. The appropriate response after sending a NAK to
the flash loader is to resend the command that failed and request the data again. If needed, the
host may send leading zeros before sending down the ACK/NAK signal to the flash loader, as the
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flash loader only accepts the first non-zero data as a valid response. This zero padding is needed
by the SSI interface in order to receive data to or from the flash loader.
A.4
Commands
The next section defines the list of commands that can be sent to the flash loader. The first byte of
the data should always be one of the defined commands, followed by data or parameters as
determined by the command that is sent.
A.4.1
COMMAND_PING (0X20)
This command simply accepts the command and sets the global status to success. The format of
the packet is as follows:
Byte[0] = 0x03;
Byte[1] = checksum(Byte[2]);
Byte[2] = COMMAND_PING;
The ping command has 3 bytes and the value for COMMAND_PING is 0x20 and the checksum of one
byte is that same byte, making Byte[1] also 0x20. Since the ping command has no real return status,
the receipt of an ACK can be interpreted as a successful ping to the flash loader.
A.4.2
COMMAND_GET_STATUS (0x23)
This command returns the status of the last command that was issued. Typically, this command
should be sent after every command to ensure that the previous command was successful or to
properly respond to a failure. The command requires one byte in the data of the packet and should
be followed by reading a packet with one byte of data that contains a status code. The last step is
to ACK or NAK the received data so the flash loader knows that the data has been read.
Byte[0] = 0x03
Byte[1] = checksum(Byte[2])
Byte[2] = COMMAND_GET_STATUS
A.4.3
COMMAND_DOWNLOAD (0x21)
This command is sent to the flash loader to indicate where to store data and how many bytes will
be sent by the COMMAND_SEND_DATA commands that follow. The command consists of two 32-bit
values that are both transferred MSB first. The first 32-bit value is the address to start programming
data into, while the second is the 32-bit size of the data that will be sent. This command also triggers
an erase of the full area to be programmed so this command takes longer than other commands.
This results in a longer time to receive the ACK/NAK back from the board. This command should
be followed by a COMMAND_GET_STATUS to ensure that the Program Address and Program size
are valid for the device running the flash loader.
The format of the packet to send this command is a follows:
Byte[0]
Byte[1]
Byte[2]
Byte[3]
Byte[4]
Byte[5]
Byte[6]
Byte[7]
=
=
=
=
=
=
=
=
11
checksum(Bytes[2:10])
COMMAND_DOWNLOAD
Program Address [31:24]
Program Address [23:16]
Program Address [15:8]
Program Address [7:0]
Program Size [31:24]
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Byte[8] = Program Size [23:16]
Byte[9] = Program Size [15:8]
Byte[10] = Program Size [7:0]
A.4.4
COMMAND_SEND_DATA (0x24)
This command should only follow a COMMAND_DOWNLOAD command or another
COMMAND_SEND_DATA command if more data is needed. Consecutive send data commands
automatically increment address and continue programming from the previous location. The caller
should limit transfers of data to a maximum 8 bytes of packet data to allow the flash to program
successfully and not overflow input buffers of the serial interfaces. The command terminates
programming once the number of bytes indicated by the COMMAND_DOWNLOAD command has been
received. Each time this function is called it should be followed by a COMMAND_GET_STATUS to
ensure that the data was successfully programmed into the flash. If the flash loader sends a NAK
to this command, the flash loader does not increment the current address to allow retransmission
of the previous data.
Byte[0] = 11
Byte[1] = checksum(Bytes[2:10])
Byte[2] = COMMAND_SEND_DATA
Byte[3] = Data[0]
Byte[4] = Data[1]
Byte[5] = Data[2]
Byte[6] = Data[3]
Byte[7] = Data[4]
Byte[8] = Data[5]
Byte[9] = Data[6]
Byte[10] = Data[7]
A.4.5
COMMAND_RUN (0x22)
This command is used to tell the flash loader to execute from the address passed as the parameter
in this command. This command consists of a single 32-bit value that is interpreted as the address
to execute. The 32-bit value is transmitted MSB first and the flash loader responds with an ACK
signal back to the host device before actually executing the code at the given address. This allows
the host to know that the command was received successfully and the code is now running.
Byte[0]
Byte[1]
Byte[2]
Byte[3]
Byte[4]
Byte[5]
Byte[6]
A.4.6
=
=
=
=
=
=
=
7
checksum(Bytes[2:6])
COMMAND_RUN
Execute Address[31:24]
Execute Address[23:16]
Execute Address[15:8]
Execute Address[7:0]
COMMAND_RESET (0x25)
This command is used to tell the flash loader device to reset. This is useful when downloading a
new image that overwrote the flash loader and wants to start from a full reset. Unlike the
COMMAND_RUN command, this allows the initial stack pointer to be read by the hardware and set
up for the new code. It can also be used to reset the flash loader if a critical error occurs and the
host device wants to restart communication with the flash loader.
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Byte[0] = 3
Byte[1] = checksum(Byte[2])
Byte[2] = COMMAND_RESET
The flash loader responds with an ACK signal back to the host device before actually executing the
software reset to the device running the flash loader. This allows the host to know that the command
was received successfully and the part will be reset.
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Register Quick Reference
B
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
System Control
Base 0x400F.E000
DID0, type RO, offset 0x000, reset VER
CLASS
MAJOR
MINOR
PBORCTL, type R/W, offset 0x030, reset 0x0000.7FFD
BORIOR
LDOPCTL, type R/W, offset 0x034, reset 0x0000.0000
VADJ
RIS, type RO, offset 0x050, reset 0x0000.0000
PLLLRIS
BORRIS
PLLLIM
BORIM
PLLLMIS
BORMIS
IMC, type R/W, offset 0x054, reset 0x0000.0000
MISC, type R/W1C, offset 0x058, reset 0x0000.0000
RESC, type R/W, offset 0x05C, reset -
SW
WDT
BOR
POR
EXT
RCC, type R/W, offset 0x060, reset 0x0780.3AD1
ACG
PWRDN
SYSDIV
USESYSDIV
BYPASS
XTAL
OSCSRC
IOSCDIS MOSCDIS
PLLCFG, type RO, offset 0x064, reset -
F
R
RCC2, type R/W, offset 0x070, reset 0x0780.2810
USERCC2
SYSDIV2
PWRDN2
BYPASS2
OSCSRC2
DSLPCLKCFG, type R/W, offset 0x144, reset 0x0780.0000
DSDIVORIDE
DSOSCSRC
DID1, type RO, offset 0x004, reset VER
FAM
PARTNO
PINCOUNT
TEMP
PKG
ROHS
QUAL
DC0, type RO, offset 0x008, reset 0x00FF.002F
SRAMSZ
FLASHSZ
DC1, type RO, offset 0x010, reset 0x0700.309F
CAN2
CAN1
CAN0
MINSYSDIV
MPU
PLL
WDT
SWO
SWD
JTAG
TIMER3
TIMER2
TIMER1
TIMER0
DC2, type RO, offset 0x014, reset 0x000F.1031
I2C0
SSI1
SSI0
UART0
DC3, type RO, offset 0x018, reset 0x8300.0000
32KHZ
CCP1
CCP0
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31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
TIMER2
TIMER1
TIMER0
DC4, type RO, offset 0x01C, reset 0x5000.007F
EPHY0
EMAC0
RCGC0, type R/W, offset 0x100, reset 0x00000040
CAN2
CAN1
CAN0
WDT
SCGC0, type R/W, offset 0x110, reset 0x00000040
CAN2
CAN1
CAN0
WDT
DCGC0, type R/W, offset 0x120, reset 0x00000040
CAN2
CAN1
CAN0
WDT
RCGC1, type R/W, offset 0x104, reset 0x00000000
TIMER3
I2C0
SSI1
SSI0
UART0
SSI1
SSI0
SSI1
SSI0
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
TIMER2
TIMER1
TIMER0
SCGC1, type R/W, offset 0x114, reset 0x00000000
TIMER3
I2C0
TIMER2
TIMER1
TIMER0
UART0
DCGC1, type R/W, offset 0x124, reset 0x00000000
TIMER3
I2C0
TIMER2
TIMER1
TIMER0
UART0
RCGC2, type R/W, offset 0x108, reset 0x00000000
EPHY0
EMAC0
SCGC2, type R/W, offset 0x118, reset 0x00000000
EPHY0
EMAC0
DCGC2, type R/W, offset 0x128, reset 0x00000000
EPHY0
EMAC0
SRCR0, type R/W, offset 0x040, reset 0x00000000
CAN2
CAN1
CAN0
WDT
SRCR1, type R/W, offset 0x044, reset 0x00000000
TIMER3
I2C0
SSI1
SSI0
GPIOF
GPIOE
UART0
SRCR2, type R/W, offset 0x048, reset 0x00000000
EPHY0
EMAC0
GPIOG
GPIOD
GPIOC
GPIOB
GPIOA
Internal Memory
Flash Memory Control Registers (Flash Control Offset)
Base 0x400F.D000
FMA, type R/W, offset 0x000, reset 0x0000.0000
OFFSET
OFFSET
FMD, type R/W, offset 0x004, reset 0x0000.0000
DATA
DATA
FMC, type R/W, offset 0x008, reset 0x0000.0000
WRKEY
COMT
June 22, 2010
MERASE
ERASE
WRITE
505
Texas Instruments-Production Data
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PRIS
ARIS
PMASK
AMASK
PMISC
AMISC
DBG1
DBG0
FCRIS, type RO, offset 0x00C, reset 0x0000.0000
FCIM, type R/W, offset 0x010, reset 0x0000.0000
FCMISC, type R/W1C, offset 0x014, reset 0x0000.0000
Internal Memory
Flash Memory Protection Registers (System Control Offset)
Base 0x400F.E000
USECRL, type R/W, offset 0x140, reset 0x31
USEC
FMPRE0, type R/W, offset 0x130 and 0x200, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPPE0, type R/W, offset 0x134 and 0x400, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
USER_DBG, type R/W, offset 0x1D0, reset 0xFFFF.FFFE
NW
DATA
DATA
USER_REG0, type R/W, offset 0x1E0, reset 0xFFFF.FFFF
NW
DATA
DATA
USER_REG1, type R/W, offset 0x1E4, reset 0xFFFF.FFFF
NW
DATA
DATA
FMPRE1, type R/W, offset 0x204, reset 0x0000.FFFF
READ_ENABLE
READ_ENABLE
FMPRE2, type R/W, offset 0x208, reset 0x0000.0000
READ_ENABLE
READ_ENABLE
FMPRE3, type R/W, offset 0x20C, reset 0x0000.0000
READ_ENABLE
READ_ENABLE
FMPPE1, type R/W, offset 0x404, reset 0x0000.FFFF
PROG_ENABLE
PROG_ENABLE
FMPPE2, type R/W, offset 0x408, reset 0x0000.0000
PROG_ENABLE
PROG_ENABLE
FMPPE3, type R/W, offset 0x40C, reset 0x0000.0000
PROG_ENABLE
PROG_ENABLE
506
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
General-Purpose Input/Outputs (GPIOs)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIODATA, type R/W, offset 0x000, reset 0x0000.0000
DATA
GPIODIR, type R/W, offset 0x400, reset 0x0000.0000
DIR
GPIOIS, type R/W, offset 0x404, reset 0x0000.0000
IS
GPIOIBE, type R/W, offset 0x408, reset 0x0000.0000
IBE
GPIOIEV, type R/W, offset 0x40C, reset 0x0000.0000
IEV
GPIOIM, type R/W, offset 0x410, reset 0x0000.0000
IME
GPIORIS, type RO, offset 0x414, reset 0x0000.0000
RIS
GPIOMIS, type RO, offset 0x418, reset 0x0000.0000
MIS
GPIOICR, type W1C, offset 0x41C, reset 0x0000.0000
IC
GPIOAFSEL, type R/W, offset 0x420, reset -
AFSEL
GPIODR2R, type R/W, offset 0x500, reset 0x0000.00FF
DRV2
GPIODR4R, type R/W, offset 0x504, reset 0x0000.0000
DRV4
GPIODR8R, type R/W, offset 0x508, reset 0x0000.0000
DRV8
GPIOODR, type R/W, offset 0x50C, reset 0x0000.0000
ODE
GPIOPUR, type R/W, offset 0x510, reset -
PUE
June 22, 2010
507
Texas Instruments-Production Data
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GPIOPDR, type R/W, offset 0x514, reset 0x0000.0000
PDE
GPIOSLR, type R/W, offset 0x518, reset 0x0000.0000
SRL
GPIODEN, type R/W, offset 0x51C, reset -
DEN
GPIOLOCK, type R/W, offset 0x520, reset 0x0000.0001
LOCK
LOCK
GPIOCR, type -, offset 0x524, reset -
CR
GPIOPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000
PID4
GPIOPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000
PID5
GPIOPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000
PID6
GPIOPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000
PID7
GPIOPeriphID0, type RO, offset 0xFE0, reset 0x0000.0061
PID0
GPIOPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000
PID1
GPIOPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
PID2
GPIOPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
PID3
GPIOPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
GPIOPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
GPIOPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
CID2
GPIOPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
508
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
General-Purpose Timers
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
GPTMCFG, type R/W, offset 0x000, reset 0x0000.0000
GPTMCFG
GPTMTAMR, type R/W, offset 0x004, reset 0x0000.0000
TAAMS
TACMR
TAMR
TBAMS
TBCMR
TBMR
GPTMTBMR, type R/W, offset 0x008, reset 0x0000.0000
GPTMCTL, type R/W, offset 0x00C, reset 0x0000.0000
TBPWML
TBEVENT
TBSTALL
TBEN
TAPWML
RTCEN
TAEVENT
TASTALL
TAEN
CBEIM
CBMIM
TBTOIM
RTCIM
CAEIM
CAMIM
TATOIM
CBERIS
CBMRIS TBTORIS
RTCRIS
CAERIS
CAMRIS
TATORIS
CBEMIS
CBMMIS TBTOMIS
RTCMIS
CAEMIS
CAMMIS TATOMIS
GPTMIMR, type R/W, offset 0x018, reset 0x0000.0000
GPTMRIS, type RO, offset 0x01C, reset 0x0000.0000
GPTMMIS, type RO, offset 0x020, reset 0x0000.0000
GPTMICR, type W1C, offset 0x024, reset 0x0000.0000
CBECINT CBMCINT TBTOCINT
RTCCINT CAECINT CAMCINT TATOCINT
GPTMTAILR, type R/W, offset 0x028, reset 0xFFFF.FFFF
TAILRH
TAILRL
GPTMTBILR, type R/W, offset 0x02C, reset 0x0000.FFFF
TBILRL
GPTMTAMATCHR, type R/W, offset 0x030, reset 0xFFFF.FFFF
TAMRH
TAMRL
GPTMTBMATCHR, type R/W, offset 0x034, reset 0x0000.FFFF
TBMRL
GPTMTAPR, type R/W, offset 0x038, reset 0x0000.0000
TAPSR
GPTMTBPR, type R/W, offset 0x03C, reset 0x0000.0000
TBPSR
GPTMTAPMR, type R/W, offset 0x040, reset 0x0000.0000
TAPSMR
GPTMTBPMR, type R/W, offset 0x044, reset 0x0000.0000
TBPSMR
June 22, 2010
509
Texas Instruments-Production Data
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESEN
INTEN
GPTMTAR, type RO, offset 0x048, reset 0xFFFF.FFFF
TARH
TARL
GPTMTBR, type RO, offset 0x04C, reset 0x0000.FFFF
TBRL
Watchdog Timer
Base 0x4000.0000
WDTLOAD, type R/W, offset 0x000, reset 0xFFFF.FFFF
WDTLoad
WDTLoad
WDTVALUE, type RO, offset 0x004, reset 0xFFFF.FFFF
WDTValue
WDTValue
WDTCTL, type R/W, offset 0x008, reset 0x0000.0000
WDTICR, type WO, offset 0x00C, reset WDTIntClr
WDTIntClr
WDTRIS, type RO, offset 0x010, reset 0x0000.0000
WDTRIS
WDTMIS, type RO, offset 0x014, reset 0x0000.0000
WDTMIS
WDTTEST, type R/W, offset 0x418, reset 0x0000.0000
STALL
WDTLOCK, type R/W, offset 0xC00, reset 0x0000.0000
WDTLock
WDTLock
WDTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000
PID4
WDTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000
PID5
WDTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000
PID6
WDTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000
PID7
WDTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0005
PID0
WDTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0018
PID1
WDTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
PID2
510
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OE
BE
PE
FE
EPS
PEN
BRK
SIRLP
SIREN
UARTEN
WDTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
PID3
WDTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
WDTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
WDTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
CID2
WDTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
Universal Asynchronous Receivers/Transmitters (UARTs)
UART0 base: 0x4000.C000
UARTDR, type R/W, offset 0x000, reset 0x0000.0000
OE
BE
PE
FE
DATA
UARTRSR/UARTECR, type RO, offset 0x004, reset 0x0000.0000 (Reads)
UARTRSR/UARTECR, type WO, offset 0x004, reset 0x0000.0000 (Writes)
DATA
UARTFR, type RO, offset 0x018, reset 0x0000.0090
TXFE
RXFF
TXFF
RXFE
BUSY
UARTILPR, type R/W, offset 0x020, reset 0x0000.0000
ILPDVSR
UARTIBRD, type R/W, offset 0x024, reset 0x0000.0000
DIVINT
UARTFBRD, type R/W, offset 0x028, reset 0x0000.0000
DIVFRAC
UARTLCRH, type R/W, offset 0x02C, reset 0x0000.0000
SPS
WLEN
FEN
STP2
UARTCTL, type R/W, offset 0x030, reset 0x0000.0300
RXE
TXE
LBE
UARTIFLS, type R/W, offset 0x034, reset 0x0000.0012
RXIFLSEL
TXIFLSEL
UARTIM, type R/W, offset 0x038, reset 0x0000.0000
OEIM
BEIM
PEIM
FEIM
RTIM
TXIM
RXIM
OERIS
BERIS
PERIS
FERIS
RTRIS
TXRIS
RXRIS
UARTRIS, type RO, offset 0x03C, reset 0x0000.000F
June 22, 2010
511
Texas Instruments-Production Data
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OEMIS
BEMIS
PEMIS
FEMIS
RTMIS
TXMIS
RXMIS
OEIC
BEIC
PEIC
FEIC
RTIC
TXIC
RXIC
SSE
LBM
UARTMIS, type RO, offset 0x040, reset 0x0000.0000
UARTICR, type W1C, offset 0x044, reset 0x0000.0000
UARTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000
PID4
UARTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000
PID5
UARTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000
PID6
UARTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000
PID7
UARTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0011
PID0
UARTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000
PID1
UARTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
PID2
UARTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
PID3
UARTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
UARTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
UARTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
CID2
UARTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
Synchronous Serial Interface (SSI)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSICR0, type R/W, offset 0x000, reset 0x0000.0000
SCR
SPH
SPO
FRF
DSS
SSICR1, type R/W, offset 0x004, reset 0x0000.0000
SOD
512
MS
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BSY
RFF
RNE
TNF
TFE
TXIM
RXIM
RTIM
RORIM
TXRIS
RXRIS
RTRIS
RORRIS
TXMIS
RXMIS
RTMIS
RORMIS
RTIC
RORIC
SSIDR, type R/W, offset 0x008, reset 0x0000.0000
DATA
SSISR, type RO, offset 0x00C, reset 0x0000.0003
SSICPSR, type R/W, offset 0x010, reset 0x0000.0000
CPSDVSR
SSIIM, type R/W, offset 0x014, reset 0x0000.0000
SSIRIS, type RO, offset 0x018, reset 0x0000.0008
SSIMIS, type RO, offset 0x01C, reset 0x0000.0000
SSIICR, type W1C, offset 0x020, reset 0x0000.0000
SSIPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000
PID4
SSIPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000
PID5
SSIPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000
PID6
SSIPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000
PID7
SSIPeriphID0, type RO, offset 0xFE0, reset 0x0000.0022
PID0
SSIPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000
PID1
SSIPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
PID2
SSIPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
PID3
SSIPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
SSIPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
June 22, 2010
513
Texas Instruments-Production Data
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SSIPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
CID2
SSIPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
Inter-Integrated Circuit
(I2C)
Interface
I2C Master
I2C Master 0 base: 0x4002.0000
I2CMSA, type R/W, offset 0x000, reset 0x0000.0000
SA
R/S
I2CMCS, type RO, offset 0x004, reset 0x0000.0000 (Reads)
BUSBSY
IDLE
ARBLST
DATACK
ADRACK
ERROR
BUSY
ACK
STOP
START
RUN
I2CMCS, type WO, offset 0x004, reset 0x0000.0000 (Writes)
I2CMDR, type R/W, offset 0x008, reset 0x0000.0000
DATA
I2CMTPR, type R/W, offset 0x00C, reset 0x0000.0001
TPR
I2CMIMR, type R/W, offset 0x010, reset 0x0000.0000
IM
I2CMRIS, type RO, offset 0x014, reset 0x0000.0000
RIS
I2CMMIS, type RO, offset 0x018, reset 0x0000.0000
MIS
I2CMICR, type WO, offset 0x01C, reset 0x0000.0000
IC
I2CMCR, type R/W, offset 0x020, reset 0x0000.0000
SFE
MFE
LPBK
Inter-Integrated Circuit (I2C) Interface
I2C Slave
I2C Slave 0 base: 0x4002.0800
I2CSOAR, type R/W, offset 0x000, reset 0x0000.0000
OAR
I2CSCSR, type RO, offset 0x004, reset 0x0000.0000 (Reads)
FBR
TREQ
RREQ
I2CSCSR, type WO, offset 0x004, reset 0x0000.0000 (Writes)
DA
514
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I2CSDR, type R/W, offset 0x008, reset 0x0000.0000
DATA
I2CSIMR, type R/W, offset 0x00C, reset 0x0000.0000
DATAIM
I2CSRIS, type RO, offset 0x010, reset 0x0000.0000
DATARIS
I2CSMIS, type RO, offset 0x014, reset 0x0000.0000
DATAMIS
I2CSICR, type WO, offset 0x018, reset 0x0000.0000
DATAIC
Controller Area Network (CAN) Module
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
CAN2 base: 0x4004.2000
CANCTL, type R/W, offset 0x000, reset 0x0000.0001
TEST
CCE
DAR
BOFF
EWARN
EPASS
EIE
SIE
IE
INIT
CANSTS, type R/W, offset 0x004, reset 0x0000.0000
RXOK
TXOK
LEC
CANERR, type RO, offset 0x008, reset 0x0000.0000
RP
REC
TEC
CANBIT, type R/W, offset 0x00C, reset 0x0000.2301
TSEG2
TSEG1
SJW
BRP
CANINT, type RO, offset 0x010, reset 0x0000.0000
INTID
CANTST, type R/W, offset 0x014, reset 0x0000.0000
RX
TX
LBACK
SILENT
BASIC
CANBRPE, type R/W, offset 0x018, reset 0x0000.0000
BRPE
CANIF1CRQ, type R/W, offset 0x020, reset 0x0000.0001
BUSY
MNUM
CANIF2CRQ, type R/W, offset 0x080, reset 0x0000.0001
BUSY
MNUM
CANIF1CMSK, type R/W, offset 0x024, reset 0x0000.0000
WRNRD
MASK
ARB
CONTROL CLRINTPND
WRNRD
MASK
ARB
CONTROL CLRINTPND
NEWDAT /
TXRQST
DATAA
DATAB
DATAA
DATAB
CANIF2CMSK, type R/W, offset 0x084, reset 0x0000.0000
June 22, 2010
NEWDAT /
TXRQST
515
Texas Instruments-Production Data
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CANIF1MSK1, type R/W, offset 0x028, reset 0x0000.FFFF
MSK
CANIF2MSK1, type R/W, offset 0x088, reset 0x0000.FFFF
MSK
CANIF1MSK2, type R/W, offset 0x02C, reset 0x0000.FFFF
MXTD
MDIR
MSK
CANIF2MSK2, type R/W, offset 0x08C, reset 0x0000.FFFF
MXTD
MDIR
MSK
CANIF1ARB1, type R/W, offset 0x030, reset 0x0000.0000
ID
CANIF2ARB1, type R/W, offset 0x090, reset 0x0000.0000
ID
CANIF1ARB2, type R/W, offset 0x034, reset 0x0000.0000
MSGVAL
XTD
DIR
ID
CANIF2ARB2, type R/W, offset 0x094, reset 0x0000.0000
MSGVAL
XTD
DIR
ID
CANIF1MCTL, type R/W, offset 0x038, reset 0x0000.0000
NEWDAT MSGLST
INTPND
UMASK
TXIE
RXIE
RMTEN
TXRQST
EOB
DLC
RMTEN
TXRQST
EOB
DLC
CANIF2MCTL, type R/W, offset 0x098, reset 0x0000.0000
NEWDAT MSGLST
INTPND
UMASK
TXIE
RXIE
CANIF1DA1, type R/W, offset 0x03C, reset 0x0000.0000
DATA
CANIF1DA2, type R/W, offset 0x040, reset 0x0000.0000
DATA
CANIF1DB1, type R/W, offset 0x044, reset 0x0000.0000
DATA
CANIF1DB2, type R/W, offset 0x048, reset 0x0000.0000
DATA
CANIF2DA1, type R/W, offset 0x09C, reset 0x0000.0000
DATA
CANIF2DA2, type R/W, offset 0x0A0, reset 0x0000.0000
DATA
CANIF2DB1, type R/W, offset 0x0A4, reset 0x0000.0000
DATA
516
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Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PHYINT
MDINT
RXER
FOV
TXEMP
TXER
RXINT
PHYINT
MDINT
RXER
FOV
TXEMP
TXER
RXINT
RXERM
FOVM
TXEMPM
TXERM
RXINTM
PRMS
AMUL
RXEN
CRC
PADEN
TXEN
CANIF2DB2, type R/W, offset 0x0A8, reset 0x0000.0000
DATA
CANTXRQ1, type RO, offset 0x100, reset 0x0000.0000
TXRQST
CANTXRQ2, type RO, offset 0x104, reset 0x0000.0000
TXRQST
CANNWDA1, type RO, offset 0x120, reset 0x0000.0000
NEWDAT
CANNWDA2, type RO, offset 0x124, reset 0x0000.0000
NEWDAT
CANMSG1INT, type RO, offset 0x140, reset 0x0000.0000
INTPND
CANMSG2INT, type RO, offset 0x144, reset 0x0000.0000
INTPND
CANMSG1VAL, type RO, offset 0x160, reset 0x0000.0000
MSGVAL
CANMSG2VAL, type RO, offset 0x164, reset 0x0000.0000
MSGVAL
Ethernet Controller
Ethernet MAC
Base 0x4004.8000
MACRIS/MACIACK, type RO, offset 0x000, reset 0x0000.0000 (Reads)
MACRIS/MACIACK, type WO, offset 0x000, reset 0x0000.0000 (Writes)
MACIM, type R/W, offset 0x004, reset 0x0000.007F
PHYINTM MDINTM
MACRCTL, type R/W, offset 0x008, reset 0x0000.0008
RSTFIFO BADCRC
MACTCTL, type R/W, offset 0x00C, reset 0x0000.0000
DUPLEX
MACDATA, type RO, offset 0x010, reset 0x0000.0000 (Reads)
RXDATA
RXDATA
MACDATA, type WO, offset 0x010, reset 0x0000.0000 (Writes)
TXDATA
TXDATA
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Texas Instruments-Production Data
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WRITE
START
MACIA0, type R/W, offset 0x014, reset 0x0000.0000
MACOCT4
MACOCT3
MACOCT2
MACOCT1
MACIA1, type R/W, offset 0x018, reset 0x0000.0000
MACOCT6
MACOCT5
MACTHR, type R/W, offset 0x01C, reset 0x0000.003F
THRESH
MACMCTL, type R/W, offset 0x020, reset 0x0000.0000
REGADR
MACMDV, type R/W, offset 0x024, reset 0x0000.0080
DIV
MACMTXD, type R/W, offset 0x02C, reset 0x0000.0000
MDTX
MACMRXD, type R/W, offset 0x030, reset 0x0000.0000
MDRX
MACNP, type RO, offset 0x034, reset 0x0000.0000
NPR
MACTR, type R/W, offset 0x038, reset 0x0000.0000
NEWTX
Ethernet Controller
MII Management
MR0, type R/W, address 0x00, reset 0x3100
RESET
LOOPBK SPEEDSL ANEGEN
PWRDN
ISO
RANEG
DUPLEX
COLT
MR1, type RO, address 0x01, reset 0x7849
100X_F
100X_H
10T_F
10T_H
MFPS
ANEGC
RFAULT
ANEGA
LINK
JAB
EXTD
PRX
LPANEGA
PCSBP
RXCC
MR2, type RO, address 0x02, reset 0x000E
OUI[21:6]
MR3, type RO, address 0x03, reset 0x7237
OUI[5:0]
MN
RN
MR4, type R/W, address 0x04, reset 0x01E1
NP
RF
A3
A2
A1
A0
S
MR5, type RO, address 0x05, reset 0x0000
NP
ACK
RF
A[7:0]
S
MR6, type RO, address 0x06, reset 0x0000
PDF
LPNPA
MR16, type R/W, address 0x10, reset 0x0140
RPTR
INPOL
TXHIM
SQEI
NL10
APOL
RVSPOL
MR17, type R/W, address 0x11, reset 0x0000
JABBER_IE
RXER_IE
PRX_IE
PDF_IE
LPACK_IE
LSCHG_IE RFAULT_IE ANEGCOMP_IE JABBER_INT RXER_INT
PRX_INT PDF_INT LPACK_INT LSCHG_INT
RFAULT_INT ANEGCOMP_INT
MR18, type RO, address 0x12, reset 0x0000
ANEGF
DPLX
RATE
RXSD
RX_LOCK
MR19, type R/W, address 0x13, reset 0x4000
TXO
518
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Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MR23, type R/W, address 0x17, reset 0x0010
LED1[3:0]
LED0[3:0]
MR24, type R/W, address 0x18, reset 0x00C0
PD_MODE AUTO_SW
MDIX
June 22, 2010
MDIX_CM
MDIX_SD
519
Texas Instruments-Production Data
Ordering and Contact Information
C
Ordering and Contact Information
C.1
Ordering Information
LM3Snnnn–gppss–rrm
Part Number
nnn = Sandstorm-class parts
nnnn = All other Stellaris® parts
Shipping Medium
T = Tape-and-reel
Omitted = Default shipping (tray or tube)
Temperature
E = –40°C to +105°C
I = –40°C to +85°C
Revision
Speed
20 = 20 MHz
25 = 25 MHz
50 = 50 MHz
80 = 80 MHz
Package
BZ = 108-ball BGA
QC = 100-pin LQFP
QN = 48-pin LQFP
QR = 64-pin LQFP
GZ = 48-pin QFN
Table C-1. Part Ordering Information
C.2
Orderable Part Number
Description
LM3S8530-IBZ50-A2
Stellaris LM3S8530 Microcontroller Industrial Temperature 108-ball BGA
LM3S8530-IBZ50-A2T
Stellaris LM3S8530 Microcontroller Industrial Temperature 108-ball BGA
Tape-and-reel
LM3S8530-EQC50-A2
Stellaris LM3S8530 Microcontroller Extended Temperature 100-pin LQFP
LM3S8530-EQC50-A2T
Stellaris LM3S8530 Microcontroller Extended Temperature 100-pin LQFP
Tape-and-reel
LM3S8530-IQC50-A2
Stellaris LM3S8530 Microcontroller Industrial Temperature 100-pin LQFP
LM3S8530-IQC50-A2T
Stellaris LM3S8530 Microcontroller Industrial Temperature 100-pin LQFP
Tape-and-reel
®
®
®
®
®
®
Part Markings
®
The Stellaris microcontrollers are marked with an identifying number. This code contains the
following information:
■ The first line indicates the part number. In the example figure below, this is the LM3S6965.
■ The first seven characters in the second line indicate the temperature, package, speed, and
revision. In the example figure below, this is an Industrial temperature (I), 100-pin LQFP package
(QC), 50-MHz (50), revision A2 (A2) device.
■ The remaining characters contain internal tracking numbers.
520
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
C.3
Kits
®
The Stellaris Family provides the hardware and software tools that engineers need to begin
development quickly.
■ Reference Design Kits accelerate product development by providing ready-to-run hardware and
comprehensive documentation including hardware design files
®
■ Evaluation Kits provide a low-cost and effective means of evaluating Stellaris microcontrollers
before purchase
■ Development Kits provide you with all the tools you need to develop and prototype embedded
applications right out of the box
See the website at www.ti.com/stellaris for the latest tools available, or ask your distributor.
C.4
Support Information
®
For support on Stellaris products, contact the TI Worldwide Product Information Center nearest
you: http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm.
June 22, 2010
521
Texas Instruments-Production Data
Package Information
D
Package Information
Figure D-1. 100-Pin LQFP Package
Note:
The following notes apply to the package drawing.
1. All dimensions shown in mm.
2. Dimensions shown are nominal with tolerances indicated.
3. Foot length 'L' is measured at gage plane 0.25 mm above seating plane.
522
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Body +2.00 mm Footprint, 1.4 mm package thickness
Symbols
Leads
100L
A
Max.
1.60
A1
-
0.05 Min./0.15 Max.
A2
±0.05
1.40
D
±0.20
16.00
D1
±0.05
14.00
E
±0.20
16.00
E1
±0.05
14.00
L
+0.15/-0.10
0.60
e
Basic
0.50
b
+0.05
0.22
θ
-
0˚-7˚
ddd
Max.
0.08
ccc
Max.
0.08
JEDEC Reference Drawing
MS-026
Variation Designator
BED
June 22, 2010
523
Texas Instruments-Production Data
Package Information
Figure D-2. 108-Ball BGA Package
524
June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
Note:
The following notes apply to the package drawing.
Symbols
MIN
NOM
MAX
A
1.22
1.36
1.50
A1
0.29
0.34
0.39
A3
0.65
0.70
0.75
c
0.28
0.32
0.36
D
9.85
10.00
10.15
D1
E
8.80 BSC
9.85
E1
b
10.00
8.80 BSC
0.43
0.48
bbb
0.53
.20
ddd
.12
e
0.80 BSC
f
10.15
-
0.60
M
12
n
108
-
REF: JEDEC MO-219F
June 22, 2010
525
Texas Instruments-Production Data
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