April 2006 LMH0046 HD/SD Multi-Rate Serial Digital Video Data Reclocker General Description Features The LMH0046 HD/SD Multi-Rate Serial Digital Video Data Reclocker is a monolithic integrated circuit that retimes bitserial digital video data conforming to the SMPTE 259M (A & C) and SMPTE 292M standards. The LMH0046 operates at serial data rates of 143 Mbps, 270 Mbps, 1.483 Gbps and 1.485 Gbps. The LMH0046 supports DVB-ASI operation at 270 Mbps. n Supports SMPTE 259M (A & C) and SMPTE 292M serial digital video standards n Supports 143 Mbps, 270 Mbps, 1.483 Gbps, and 1.485 Gbps serial data rate operation n Supports DVB-ASI at 270 Mbps n Single 3.3V supply operation n 330 mW typical power consumption n Two differential, reclocked outputs n Choice of second reclocked output or low-jitter, differential, data-rate clock output n Single 27 MHz external crystal or reference clock input n Manual rate select input n SD/HD operating rate indicator output n Lock Detect indicator output n Output mute function for data and clock n Auto/Manual reclocker bypass n Differential LVPECL compatible serial data inputs and outputs n LVCMOS control inputs and indicator outputs n 20-Pin TSSOP package n Industrial temperature range: -40˚C to +85˚C The LMH0046 automatically detects the incoming data rate and adjusts itself to retime the incoming data to suppress accumulated jitter. The LMH0046 recovers the serial datarate clock and optionally provides it as an output. The LMH0046 has two differential serial data outputs; the second output may be selected as a low-jitter, data-rate clock output. Controls and indicators are: serial clock or second serial data output select, manual rate select input, SD/HD rate indicator output, lock detect output, auto/manual data bypass and output mute. The serial data inputs, outputs, and serial data-rate clock outputs are differential LVPECL compatible. The CML serial data and serial data-rate clock outputs are suitable for driving 100Ω differentially terminated networks. The control logic inputs and outputs are LVCMOS compatible. The LMH0046 is powered from a single 3.3V supply. Power dissipation is typically 330 mW. The device is housed in a 20-pin TSSOP package. Applications n SDTV/HDTV serial digital video interfaces for: — Digital video routers and switchers — Digital video processing and editing equipment — DVB-ASI equipment — Video standards and format converters Typical Application 20182601 © 2006 National Semiconductor Corporation DS201826 www.national.com LMH0046 HD/SD Multi-Rate Serial Digital Video Data Reclocker PRELIMINARY LMH0046 Block Diagram 20182603 Connection Diagram 20182602 The exposed die attach pad is the negative electrical terminal for this device. It must be connected to the negative power supply voltage. 20-Pin TSSOP Order Number LMH0046MT See NS Package Number MXA-20A www.national.com 2 LMH0046 Pin Descriptions TSSOP Pin Name Description 1 LF1 Loop Filter 2 LF2 Loop Filter 3 RATE 0 Data Rate Select Input 4 RATE 1 Data Rate Select Input 5 SDI Data Input True 6 SDI Data Input Complement 7 VCC Positive power supply input 8 BYPASS/AUTO BYPASS Bypass/Auto Bypass mode select 9 OUTPUT MUTE Data and Clock Output Mute Input (active LOW) 10 XTAL IN/EXT CLK Crystal or External Oscillator Input 11 XTAL OUT Crystal Oscillator Output 12 LOCK DETECT PLL Lock Detect Output (active HIGH) 13 SCO/SDO2 Serial Clock or Serial Data Output 2 Complement 14 SCO/SDO2 Serial Clock or Serial Data Output 2 True 15 VCCO Positive power supply input (Output Driver) 16 SDO Data Output Complement 17 SDO Data Output True 18 VCCO Positive power supply input (Output Driver) 19 SD/HD Data Rate Range Output 20 SCO_EN Multiplexer control, Serial Clock or Serial Data 2 Output 3 www.national.com LMH0046 Absolute Maximum Ratings (Note 1) It is anticipated that this device will not be offered in a military qualified version. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC–VEE) Package Thermal Resistance, TSSOP 36˚C/W 6.4˚C/W Storage Temp. Range −65˚C to +150˚C Junction Temperature +150˚C Lead Temperature (Soldering 4 Sec) 4.0V Logic Supply Voltage (Vi) θJA θJC VEE−0.15V to VCC+0.15V +260˚C (Pb-free) ESD Rating (HBM) 2 kV ESD Rating (MM) 250V Logic Input Current (single input): Vi = VEE−0.15V −5 mA Vi = VCC+0.15V +5 mA Logic Output Voltage (Vo) Recommended Operating Conditions VEE−0.15V to VCC+0.15V ± 8 mA Logic Output Source/Sink Current Serial Data Input Voltage (VSDI) VEE to VCC 800 mV ± 10% Differential Serial Input Voltage VCC to VCC−2.0V Serial Data Output Sink Current (ISDO) 3.3V ± 5% Supply Voltage (VCC–VEE) Logic Input Voltage Serial Data or Clock Output Sink Current (ISO) 24 mA Operating Free Air Temperature (TA) 16 mA max. −40˚C to +85˚C DC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 2, 3) Symbol Parameter Conditions VIH Input Voltage High Level VIL Input Voltage Low Level IIH Input Current High Level VIH = VCC IIL Reference Logic level inputs Input Current Low Level VIL = VEE Output Voltage High Level IOH = −2 mA VOL Output Voltage Low Level IOL = +2 mA VSDID Serial Input Voltage, Differential SDI, SDI VCMI Input Common Mode Voltage SDI, SDI VSDOD Serial Output Voltage, Differential 100Ω differential load Output Common Mode Voltage 100Ω differential load ILEAK Typ 2 VEE VOH VCMO Min All logic level outputs SCO, SCO SDO, SDO Leakage Current Units VCC V 0.8 V 1 20 µA −1 −20 µA 2 V VEE + 0.6 V 200 1600 mVP-P VCC−1.6 VCC−0.2 V 880 mVP-P 720 800 SCO, SCO VCC− SDO, SDO VSDOD /2 V TBD µA ICC Power Supply Current, 3.3V supply, Total 270 Mbps, NTSC color bar pattern 100 mA ICC Power Supply Current, 3.3V supply, Total 1485 Mbps, NTSC color bar pattern 100 mA www.national.com LF1, LF2 Max 4 Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Note 3) Symbol Parameter Conditions Reference Min Typ Max Units BRSD Serial Data Rate SMPTE 259M, A SDI, SDO 143 Mbps BRSD Serial Data Rate SMPTE 259M, C SDI, SDO 270 Mbps BRSD Serial Data Rate SMPTE 292M SDI, SDO 1483, 1485 Mbps TOLJIT Serial Input Jitter Tolerance 143 or 270 Mbps, (Notes 7, 8, 9) SDI TOLJIT Serial Input Jitter Tolerance 143 or 270 Mbps, (Notes 7, 8, 10, 13) SDI TOLJIT Serial Input Jitter Tolerance 1483 Mbps or 1485 Mbps, (Notes 7, 8, 9) SDI TOLJIT Serial Input Jitter Tolerance 1483 Mbps or 1485 Mbps, (Notes 7, 8, 10, 13) SDI tJIT Additive Output Jitter 143 Mbps, (Note 8) SDO 0.02 0.08 UIP-P tJIT Additive Output Jitter 270 Mbps, (Note 8) SDO 0.02 0.08 UIP-P tJIT Additive Output Jitter 1483 Mbps, 1485 Mbps, (Note 8) SDO 0.05 0.1 UIP-P λBW Jitter Transfer Function −3 dB Bandwidth (Fractional Loop Bandwidth) All supported data rates, (Note 11) 0.25 0.35 %BRSD Jitter Transfer Function Peaking All supported data rates, (Note 12) 0.05 0.1 dB FCO Serial Clock Output Frequency 143 Mbps data rate SCO, SCO FCO Serial Clock Output Frequency 270 Mbps data rate SCO, SCO FCO Serial Clock Output Frequency 1483 Mbps data rate SCO, SCO FCO Serial Clock Output Frequency 1485 Mbps data rate SCO, SCO tJIT Serial Clock Output Jitter SCO, SCO Serial Clock Output Alignment with respect to Data Interval SDO, SDO, SCO, SCO Serial Clock Output Duty Cycle SCO, SCO δ TACQ Acquisition Time >6 UIP-P > 0.6 UIP-P >6 UIP-P > 0.6 UIP-P 0.1 143 MHz 270 MHz 1483 MHz 1485 MHz 2 3 psRMS 35 65 % 40 60 % Color bar pattern or PRBS 23 sequence. (Note 6) 10 tr, tf Input rise/fall time 10%–90% Logic inputs tr, tf Input rise/fall time 20%–80%, 143 or 270 Mbps SDI tr, tf Input rise/fall time 20%–80%, 1483 or 1485 Mbps SDI tr, tf Output rise/fall time 10%–90%, CL = 5 pF Logic outputs tr, tf Output rise/fall time 20%–80%,1483 or 1485 SDO, SDO, SCO, SCO Mbps, (Note 5) 5 1.5 3 ns 1500 ps 120 170 ps 1.5 3 ns 90 130 ps 400 80 ms www.national.com LMH0046 AC Electrical Characteristics LMH0046 AC Electrical Characteristics (Continued) Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Note 3) Symbol Parameter FREF Reference Clock Frequency FTOL Ref. Clock Freq. Tolerance VRAMP Conditions Reference Min −10˚C to +60˚C Power Supply Ramp Rate VCC, VEE Typ Max Units 27 MHz ± 50 ppm TBD V/µS Note 1: “Absolute Maximum Ratings” are those parameter values beyond which the life and operation of the device cannot be guaranteed. The stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of “Electrical Characteristics” specifies acceptable device operating conditions. Note 2: Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are referenced to VEE (equal to zero volts). Note 3: Typical values are stated for: VCC = +3.3V, TA = +25˚C. Note 4: Spec is guaranteed by design. Note 5: RL = 100Ω differential. Note 6: Measured from first SDI transition until Lock Detect (LD) output goes high (true). Note 7: Peak-to-peak amplitude with sinusoidal modulation per SMPTE RP 184-1996 paragraph 4.1. The test data signal shall be color bars. Note 8: This parameter is guaranteed by characterization over voltage and temperature limits. Note 9: Refer to “A1” in Figure 1 of SMPTE RP 184-1996. Note 10: Refer to “A2” in Figure 1 of SMPTE RP 184-1996. Note 11: Refer to ”fc” in Figure 3 of SMPTE RP 184-1996. Note 12: Refer to ”P” in Figure 3 of SMPTE RP 184-1996. Note 13: The input jitter tolerance at frequencies higher than the B3 frequency indicated in SMPTE 259M or SMPTE 292M shall be ≥0.8 UI when measured using the Gennum stepped-jitter method described in Gupta, A., Tailor, B., and Francis, J., “The Deficiencies in Measuring Input Jitter Tolerance (IJT) using Sine wave modulated Jitter.” www.national.com 6 The LMH0046 HD/SD Mutli-Rate Serial Digital Video Reclocker is used in many types of digital video signal processing equipment. Supported serial digital video standards are SMPTE 259M A & C and SMPTE 292M. Corresponding serial data rates are 143 Mbps, 270 Mbps, 1.483 Gbps and 1.485 Gbps. DVB-ASI data at 270 Mbps may also be retimed. The LMH0046 retimes the serial data stream to suppress accumulated jitter. It provides two low-jitter, differential, serial data outputs. The second output may be selected to output either serial data or a low-jitter serial data-rate clock. Controls and indicators are: serial data-rate clock or second serial data output select, manual rate select input, SD/HD rate output, lock detect output, auto/manual data bypass and output mute. SERIAL DATA CLOCK/SERIAL DATA 2 OUTPUT The Serial Data Clock/Serial Data 2 Output is controlled by the SCO_EN input and provides either a second retimed serial data output or a low jitter differential clock output appropriate to the serial data rate being processed. When operating as a serial clock output, the rising edge of the clock will be positioned within the corresponding serial data bit interval within 15% of the center of the data interval. Differential output SCO/SDO2 functions as the second serial data output when the SCO_EN input is a logic-low level. This output functions as the serial data-rate clock output when the SCO_EN input is a logic-high level. The SCO_EN input has an internal pull-down device and the default state of SCO_EN is low (serial data output 2 enabled). SCO/SDO2 is muted when the MUTE input is a logic low level. When the Bypass mode is activated and this output is functioning as a serial clock output, the output will also be muted. Serial data inputs are CML and LVPECL compatible. Serial data and data-rate clock outputs are differential CML and produce LVPECL compatible levels. The output buffer design can drive AC or DC-coupled, terminated 100Ω differential loads. The differential output level is 800 mVP-P ± 10% into 100Ω AC or DC-coupled differential loads. Logic inputs and outputs are LVCMOS compatible. The device package is a TSSOP20 with an exposed die attach pad. The exposed die attach pad is electrically connected to device ground (VEE) and is the negative electrical terminal for the device. This terminal must be connected to the negative power supply or circuit ground. Control Inputs and Indicator Outputs Serial Data Inputs, Serial Data and Clock Outputs SERIAL DATA RATE SELECTOR The Serial Data Rate Selector (RATE [1:0]) permits the user to fix the operating serial data rate. The pins have internal pull-downs which maintain a logic-low input condition unless externally driven to a logic-high condition. This input also serves to place the device in a test mode. The codes shown in Table 1 select the desired operating serial data rate. The LMH0046 then enters either the Auto-Rate Detect mode, a single operating rate, or the test mode. Selecting the 270 Mbps rate mode may also be used when reclocking DVBASI data. DVB-ASI data is MPEG2 coded data that is transmitted in 8B10B coding. The device should reclock this data without harmonic locking. SERIAL DATA INPUT AND OUTPUTS The differential serial data input, SDI, accepts serial digital video data at the rates specified in Table 1. The serial data input is differential LVPECL compatible. These inputs are intended to be DC interfaced to devices such as the LMH0034 adaptive cable equalizer. These inputs are not internally terminated or biased. The inputs may be ACcoupled if a suitable input bias voltage is provided. The LMH0046 has two, retimed, differential, serial data outputs, SDO and SCO/SDO2. These outputs provide low jitter, differential, retimed data to devices such as the LMH0002 cable driver or the LMH0031 deserializer. Output SCO/ SDO2 is multiplexed and can provide either a second serial data output or a serial data-rate clock output. The SCO_EN input controls the operating mode for the SCO/SDO2 output. When the SCO_EN input is high the SCO/SDO2 output provides a serial data-rate clock. When SCO_EN is low, the SCO/SDO2 output provides retimed serial data. Both differential serial data outputs, SDO and SCO/SDO2, are muted when the MUTE input is a logic low level. SCO/ SDO2 also mutes when the Bypass mode is activated when this output is operating as the serial clock output. When muted, SDO and SDO (or SDO2 and SDO2) will assume opposite differential output levels. The CML serial data outputs are differential LVPECL compatible. These outputs have internal 50Ω pull-ups and are suitable for driving AC or DC-coupled, 100Ω center-tapped, AC grounded or 100Ω un-center-tapped, differentially terminated networks. TABLE 1. Data Rate Select Input Codes Rate [1:0] Code Data Rate or Mode Comments 00 Auto-Rate Detect mode 143 Mbps rate operation supported only in ARD mode 01 270 Mbps May be used to support DVB-ASI operation 10 1483/1485 Mbps LOCK DETECT The Lock Detect (LD) output, when high, indicates that data is being received and the PLL is locked. LD may be connected to the MUTE input to mute the data and clock outputs when no data signal is being received. See Table 2. 7 www.national.com LMH0046 OPERATING SERIAL DATA RATES This device operates at serial data rates of 143 Mbps, 270 Mbps, 1483 Mbps and 1485 Mbps. The device does not lock to harmonics of these rates. The device does not lock and automatically enters the reclocker bypass mode for the following data rates: 177 Mbps, 360 Mbps, and 540 Mbps. Device Description LMH0046 Control Inputs and Indicator Outputs (Continued) BYPASS/AUTO BYPASS The Bypass/Auto Bypass input, when high, forces the device to output the data without reclocking it. When this input is low, the device automatically bypasses the reclocking function when the device is in an unlocked condition or the detected data rate is a rate which the device does not support. See Table 2. MUTE The MUTE input, when low, mutes the serial data and clock outputs. It may be connected to Lock Detect or externally driven to mute or un-mute the outputs. If MUTE is connected to LD, then the data and clock outputs are muted when the PLL is not locked. This function overrides the Bypass function: see Table 2. TABLE 2. Control Functionality LOCK DETECT OUTPUT MUTE BYPASS/AUTO BYPASS 0 1 0 PLL unlocked, reclocker bypassed DEVICE STATUS PLL locked to supported data rate, reclocker not bypassed 1 1 0 X 0 X Outputs muted 0 LOCK DETECT X Outputs muted 1 LOCK DETECT 0 PLL locked to supported data rate, reclocker not bypassed 1 LOCK DETECT 1 PLL locked to supported data rate, reclocker bypassed X 1 1 Outputs not muted, reclocker bypassed SD/HD LVCMOS compatible clock signal may be input to XTAL IN/EXT CLK. Parameters for a suitable crystal are given in Table 3. The SD/HD output indicates whether the LMH0046 is processing SD or HD data rates. It may be used to control another device such as the LMH0002 cable driver. When this output is high it indicates that the data rate is 270 Mbps (or 143 Mbps). When low, the indicated data rate is 1483 or 1485 Mbps. The SD/HD output is only valid when the PLL is locked and the Lock Detect output is high. When the PLL is not locked (the Lock Detect output is low), the SD/HD output will toggle between SD and HD. TABLE 3. Crystal Parameters Parameter SCO_EN Input SCO_EN enables the SCO/SDO2 differential output to function either as a serial data-rate clock or second serial data output. SCO/SDO2 functions as a serial data-rate clock when SCO_EN is high. This pin has an internal pull-down device. The default state (low) enables the SCO/SDO2 output as a second serial data output. CRYSTAL OR EXTERNAL CLOCK REFERENCE The LMH0046 uses a 27 MHz crystal or external clock signal as a timing reference input. A 27 MHz parallel resonant crystal and load network may be connected to the XTAL IN/EXT CLK and XTAL OUT pins. Alternatively, a 27 MHz www.national.com 8 Value Frequency 27 MHz Frequency Stability ± 100 ppm @ recommended drive level Operating Mode Fundamental mode, Parallel Resonant Load Capacitance 20 pF Shunt Capacitance 7 pF Series Resistance 40Ω max. Recommended Drive Level 100 µW Maximum Drive Level 500 µW Operating Temperature Range −10˚C to +60˚C LMH0046 Application Information Figure 1 shows an application circuit for the LMH0046 along with the LMH0034 SMPTE 292M / 259M Adaptive Cable Equalizer and LMH0002 SMPTE 292M / 259M Cable Driver. 20182604 FIGURE 1. Application Circuit 9 www.national.com LMH0046 HD/SD Multi-Rate Serial Digital Video Data Reclocker Physical Dimensions inches (millimeters) unless otherwise noted 20-Pin TSSOP Order Number LMH0046MT NS Package Number MXA-20A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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