LPC1850/30/20/10
32-bit ARM Cortex-M3 MCU; up to 200 kB SRAM; Ethernet,
two High-speed USB, LCD, and external memory controller
Rev. 1 — 3 January 2011
Objective data sheet
1. General description
The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embedded
applications. The ARM Cortex-M3 is a next generation core that offers system
enhancements such as low power consumption, enhanced debug features, and a high
level of support block integration.
The LPC1850/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARM
Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with
separate local instruction and data buses as well as a third bus for peripherals. The ARM
Cortex-M3 CPU also includes an internal prefetch unit that supports speculative
branching.
The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM, a quad SPI Flash
Interface (SPIFI), a State Configurable Timer (SCT) subsystem, two High-speed USB
controllers, Ethernet, LCD, an external memory controller, and multiple digital and analog
peripherals.
2. Features and benefits
Processor core
ARM Cortex-M3 processor, running at frequencies of up to 150 MHz.
ARM Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions.
ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
Non-maskable Interrupt (NMI) input.
JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points.
ETM and ETB support.
System tick timer.
On-chip memory
136 kB SRAM for code and data use.
Two 32 kB SRAM blocks with separate bus access. Both SRAM blocks can be
powered down individually.
32 kB ROM containing boot code and on-chip software drivers.
32-bit One-Time Programmable (OTP) memory for general-purpose customer use.
Clock generation unit
Crystal oscillator with an operating range of 1 MHz to 25 MHz.
12 MHz internal RC oscillator trimmed to 1 % accuracy.
Ultra-low power RTC crystal oscillator.
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Two PLLs allow CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. Second PLL can be used for USB.
Clock output.
Serial interfaces:
Quad SPI Flash Interface (SPIFI) with four lanes and data rates of up to 40 MB per
second total.
10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high
throughput at low CPU load.
One High-speed USB 2.0 Host/Device/OTG interface with DMA support and
on-chip PHY.
One High-speed USB 2.0 Host/Device interface with DMA support, on-chip
full-speed PHY and ULPI interface to external high-speed PHY.
Four 550 UARTs with DMA support: one UART with full modem interface; one
UART with IrDA interface; three USARTs support synchronous mode and a smart
card interface conforming to ISO7816 specification.
One C_CAN 2.0B controller with one channel.
Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA
support.
One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O
pins conforming to the full I2C-bus specification. Supports data rates of up to
1 Mbit/s.
One standard I2C-bus interface with monitor mode and standard I/O pins.
One I2S interface with DMA support and with one input and one output.
Digital peripherals:
External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,
and SDRAM devices.
LCD controller with DMA support and a programmable display resolution of up to
1024H × 768V. Supports monochrome and color STN panels and TFT color panels;
supports 1/2/4/8 bpp CLUT and 16/24-bit direct pixel mapping.
SD/MMC card interface.
Eight-channel General-Purpose DMA (GPDMA) controller can access all memories
on the AHB and all DMA-capable AHB slaves.
Up to 80 General-Purpose Input/Output (GPIO) pins with configurable
pull-up/pull-down resistors and open-drain modes.
GPIO registers are located on the AHB for fast access. GPIO ports have DMA
support.
State Configurable Timer (SCT) subsystem on AHB.
Four general-purpose timer/counters with capture and match capabilities.
One motor control PWM for three-phase motor control.
One Quadrature Encoder Interface (QEI).
Repetitive Interrupt timer (RI timer).
Windowed watchdog timer.
Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes
of battery powered backup registers.
Alarm timer; can be battery powered.
Analog peripherals:
One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.
LPC1850_30_20_10
Objective data sheet
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Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
2 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s.
Security:
AES decryption engine programmable through an on-chip API.
Two 128-bit secure OTP memories for AES key storage and customer use.
Unique ID for each device.
Power:
Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip internal voltage regulator for
the core supply and the RTC power domain.
RTC power domain can be powered separately by a 3 V battery supply.
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.
Overdrive mode to increase CPU and bus clock frequency.
Processor wake-up from Sleep mode via wake-up interrupts from various
peripherals.
Wake-up from Deep-sleep, Power-down, and Deep power-down modes via
external interrupts and interrupts generated by battery powered blocks in the RTC
power domain.
Brownout detect with four separate thresholds for interrupt and forced reset.
Power-On Reset (POR).
Available as 208-pin and 144-pin LQFP packages and as 100-pin, 180-pin, and
256-pin LBGA packages.
3. Applications
Industrial
Consumer
White goods
RFID readers
e-Metering
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
LPC1850FET256
LBGA256
plastic low profile ball grid array package; 256 balls; body 17 × 17 × 1 mm
sot740-2
LPC1850
LQFP208
<tbd>
<tbd>
LPC1850
BGA180
<tbd>
<tbd>
LPC1830FET256
LBGA256
plastic low profile ball grid array package; 256 balls; body 17 × 17 × 1 mm
sot740-2
LPC1830
LQFP208
<tbd>
<tbd>
LPC1830
BGA180
<tbd>
<tbd>
LPC1820
LQFP144
<tbd>
<tbd>
LPC1820FET100
BGA100
<tbd>
<tbd>
LPC1810
LQFP144
<tbd>
<tbd>
LPC1810FET100
BGA100
<tbd>
<tbd>
LPC1850_30_20_10
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
3 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
4.1 Ordering options
Table 2.
Ordering options
Type number
SRAM
LCD
Ethernet
USB0 (Host,
Device, OTG)
USB1 (Host,
Device)
Package
LPC1850
200 kB
yes
yes
yes
yes
LBGA256
LPC1850
200 kB
yes
yes
yes
yes
LQFP208
LPC1850
200 kB
yes
yes
yes
yes
BGA180
LPC1830
200 kB
no
yes
yes
yes
LBGA256
LPC1830
200 kB
no
yes
yes
yes
BGA180
LPC1830
200 kB
no
yes
yes
yes
LQFP208
LPC1820
168 kB
no
no
yes
no
BGA100
LPC1820
168 kB
no
no
yes
no
LQFP144
LPC1810
136 kB
no
no
no
no
BGA100
LPC1810
136 kB
no
no
no
no
LQFP144
LPC1850_30_20_10
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
4 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
5. Block diagram
SWD/TRACE PORT/JTAG
LPC1850/30/20/10
HIGH-SPEED PHY
TEST/DEBUG
INTERFACE
ETHERNET(1)
10/100
MAC
IEEE 1588
GPDMA
ARM
CORTEX-M3
HIGHSPEED
USB0(1)
HOST/
DEVICE/
OTG
USB1(1)
HOST/
DEVICE
LCD(1)
SD/
MMC(1)
system
bus
D-code
bus
I-code
bus
masters
slaves
AHB MULTILAYER MATRIX
slaves
SPIFI
BRIDGE 0
BRIDGE 1
BRIDGE 2
BRIDGE 3
BRIDGE
BRIDGE
WWDT
RI TIMER
I2C1
CGU
ALARM TIMER
64/96 kB LOCAL SRAM
USART0
MOTOR
CONTROL
PWM
USART2
10-bit DAC
CCU1
BACKUP REGISTERS
40 kB LOCAL SRAM
UART1
I2C0
USART3
C_CAN
CCU2
POWER MODE CONTROL
16/32 kB AHB SRAM
SSP0
I2S0
TIMER2
10-bit ADC0
RGU
CONFIGURATION
REGISTERS
16 kB +
16 kB AHB SRAM(1)
TIMER0
TIMER3
10-bit ADC1
EVENT ROUTER
AES
TIMER1
SSP1
OTP MEMORY
HS GPIO
EMC
32 kB ROM
SCU
QEI
RTC OSC
RTC
SCT
12 MHz IRC
RTC POWER DOMAIN
= connected to GPDMA
002aaf218
(1) Not available on all parts (see Table 2).
Fig 1.
LPC1850/30/20/10 block diagram
LPC1850_30_20_10
Objective data sheet
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Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
5 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
6. Pinning information
6.1 Pinning
LPC1850/30FET256
ball A1
index area
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
002aaf230
Transparent top view
Fig 2.
Pin configuration LBGA256 package
6.2 Pin description
On the LPC1850/30/20/10, digital pins are grouped into 16 ports, named P0 to P9 and PA
to PF, with up to 20 pins used per port. Each digital pin may support up to four different
digital functions, including General Purpose I/O (GPIO), selectable through the SYSCON
registers. Note that the pin name is not indicative of the GPIO port assigned to it.
Analog functions and power pins are pinned out separately and do not share pins with
digital functions.
Pin description
Symbol
LBGA256
Table 3.
Reset
state
Type Description
[1]
Multiplexed digital pins
P0_0[2]
P0_1[2]
LPC1850_30_20_10
Objective data sheet
L3
M2
I; PU
I; PU
I/O
GPIO0[0] — General purpose digital input/output pin.
I/O
SSP1_MISO — Master In Slave Out for SSP1.
I
ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface).
-
n.c.
I/O
GPIO0[1] — General purpose digital input/output pin.
I/O
SSP1_MOSI — Master Out Slave in for SSP1.
I
ENET_COL — Ethernet Collision detect (MII interface).
-
n.c.
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Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
6 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Pin description …continued
Symbol
P1_0[2]
P1_1[2]
P1_2[2]
P1_3[2]
P1_4[2]
P1_5[2]
P1_6[2]
P1_7[2]
P1_8[2]
LPC1850_30_20_10
Objective data sheet
LBGA256
Table 3.
Reset
state
P2
I; PU
R2
R3
P5
T3
R5
T4
T5
R7
Type Description
[1]
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I/O
GPIO0[4] — General purpose digital input/output pin.
I
CTIN_3 — SCT input 3. Capture input 1 of timer 1.
I/O
EXTBUS_A5 — External memory address line 5.
-
n.c.
I/O
GPIO0[8] — General purpose digital input/output pin.
O
CTOUT_7 — SCT output 7. Match output 3 of timer 1.
I/O
EXTBUS_A6 — External memory address line 6. Boot control pin 0 (see
Table 5).
-
n.c.
I/O
GPIO0[9] — General purpose digital input/output pin.
O
CTOUT_6 — SCT output 6. Match output 2 of timer 1.
I/O
EXTBUS_A7 — External memory address line 7. Boot control pin 1 (see
Table 5).
-
n.c.
I/O
GPIO0[10] — General purpose digital input/output pin.
O
CTOUT_8 — SCT output 8. Match output 0 of timer 2.
-
n.c.
O
EXTBUS_OE — LOW active Output Enable signal.
I/O
GPIO0[11] — General purpose digital input/output pin.
O
CTOUT_9 — SCT output 9. Match output 1 of timer 2.
-
n.c.
O
EXTBUS_BLS0 — LOW active Byte Lane select signal 0.
I/O
GPIO1[8] — General purpose digital input/output pin.
O
CTOUT_10 — SCT output 10. Match output 2 of timer 2.
-
n.c.
O
EXTBUS_CS0 — LOW active Chip Select 0 signal.
I/O
GPIO1[9] — General purpose digital input/output pin.
I
CTIN_5 — SCT input 5. Capture input 2 of timer 2.
-
n.c.
O
EXTBUS_WE — LOW active Write Enable signal.
I/O
GPIO1[0] — General purpose digital input/output pin.
I
U1_DSR — Data Set Ready input for UART1.
O
CTOUT_13 — SCT output 13. Match output 1 of timer 3.
I/O
EXTBUS_D0 — External memory data line 0.
I/O
GPIO1[1] — General purpose digital input/output pin.
O
U1_DTR — Data Terminal Ready output for UART1.
O
CTOUT_12 — SCT output 12. Match output 0 of timer 3.
I/O
EXTBUS_D1 — External memory data line 1.
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Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
7 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Pin description …continued
Symbol
P1_9[2]
P1_10[2]
P1_11[2]
P1_12[2]
P1_13[2]
P1_14[2]
P1_15[2]
P1_16[2]
P1_17[2]
LPC1850_30_20_10
Objective data sheet
LBGA256
Table 3.
Reset
state
T7
I; PU
R8
T9
R9
R10
R11
T12
M7
M8
Type Description
[1]
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I/O
GPIO1[2] — General purpose digital input/output pin.
O
U1_RTS — Request to Send output for UART1.
O
CTOUT_11 — SCT output 11. Match output 3 of timer 2.
I/O
EXTBUS_D2 — External memory data line 2.
I/O
GPIO1[3] — General purpose digital input/output pin.
I
U1_RI — Ring Indicator input for UART1.
O
CTOUT_14 — SCT output 14. Match output 2 of timer 3.
I/O
EXTBUS_D3 — External memory data line 3.
I/O
GPIO1[4] — General purpose digital input/output pin.
I
U1_CTS — Clear to Send input for UART1.
O
CTOUT_15 — SCT output 15. Match output 3 of timer 3.
I/O
EXTBUS_D4 — External memory data line 4.
I/O
GPIO1[5] — General purpose digital input/output pin.
I
U1_DCD — Data Carrier Detect input for UART1.
-
n.c.
I/O
EXTBUS_D5 — External memory data line 5.
I/O
GPIO1[6] — General purpose digital input/output pin.
O
U1_TXD — Transmitter output for UART1.
-
n.c.
I/O
EXTBUS_D6 — External memory data line 6.
I/O
GPIO1[7] — General purpose digital input/output pin.
I
U1_RXD — Receiver input for UART1.
-
n.c.
I/O
EXTBUS_D7 — External memory data line 7.
I/O
GPIO0[2] — General purpose digital input/output pin.
O
U2_TXD — Transmitter output for UART2.
-
n.c.
I
ENET_RXD0 — Ethernet receive data 0 (RMII/MII interface).
I/O
GPIO0[3] — General purpose digital input/output pin.
I
U2_RXD — Receiver input for UART2.
-
n.c.
I
ENET_CRS (ENET_CRS_DV) — Ethernet Carrier Sense (MII interface) or
Ethernet Carrier Sense/Data Valid (RMII interface).
I/O
GPIO0[12] — General purpose digital input/output pin.
I/O
U2_UCLK — Serial clock input/output for UART2 in synchronous mode.
-
n.c.
I/O
ENET_MDIO — Ethernet MIIM data input and output.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
8 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Pin description …continued
Symbol
P1_18[2]
P1_19[2]
P1_20[2]
P2_0[2]
P2_1[2]
P2_2[2]
P2_3[2]
P2_4[2]
LPC1850_30_20_10
Objective data sheet
LBGA256
Table 3.
Reset
state
N12
I; PU
M11
[1]
<tbd>
M10 I; PU
T16
N15
<tbd>
<tbd>
M15 <tbd>
J12
K11
Type Description
<tbd>
<tbd>
I/O
GPIO0[13] — General purpose digital input/output pin.
I/O
U2_DIR — RS-485/EIA-485 output enable/direction control for UART2.
-
n.c.
O
ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface).
I
ENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit Clock (MII
interface) or Ethernet Reference Clock (RMII interface).
I/O
SSP1_SCK — Serial clock for SSP1.
-
n.c.
-
n.c.
I/O
GPIO0[15] — General purpose digital input/output pin.
I/O
SSP1_SSEL — Slave Select for SSP1.
-
n.c.
O
ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface).
-
n.c.
O
U0_TXD — Transmitter output for USART0.
I/O
EXTBUS_A13 — External memory address line 13.
O
USB0_PWR_EN — VBUS drive signal (towards external charge pump or
power management unit); indicates that Vbus must be driven (active high).
-
n.c.
I
U0_RXD — Receiver input for USART0.
I/O
EXTBUS_A12 — External memory address line 12.
O
USB0_PWR_FAULT — Port power fault signal indicating overcurrent
condition; this signal monitors over-current on the USB bus (external circuitry
required to detect over-current condition).
-
n.c.
I/O
U0_UCLK — Serial clock input/output for USART0 in synchronous mode.
I/O
EXTBUS_A11 — External memory address line 11.
O
USB0_IND1 — USB0 port indicator LED control output 1.
-
n.c.
I/O
I2C1_SDA — I2C1 data input/output (this pin does not use a specialized I2C
pad).
O
U3_TXD — Transmitter output for USART3.
I
CTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture input 1 of timer 2.
-
n.c.
I/O
I2C1_SCL — I2C1 clock input/output (this pin does not use a specialized I2C
pad).
I
U3_RXD — Receiver input for USART3.
I
CTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3.
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Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
9 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Pin description …continued
Symbol
P2_5[3]
LBGA256
Table 3.
Reset
state
K14
<tbd>
Type Description
[1]
-
n.c.
I
CTIN_2 — SCT input 2. Capture input 2 of timer 0.
I
USB1_VBUS — Monitors the presence of USB1 bus power.
Note: This signal must be HIGH for USB reset to occur.
P2_6[2]
P2_7[2]
P2_8[2]
P2_9[2]
P2_10[2]
P2_11[2]
P2_12[2]
P2_13[2]
LPC1850_30_20_10
Objective data sheet
K16
H14
J16
H16
G16
F16
E15
C16
<tbd>
I; PU
<tbd>
I; PU
I; PU
I; PU
I; PU
I; PU
I
ADCTRIG1 — ADC trigger input 1.
-
n.c.
I/O
U0_DIR — RS-485/EIA-485 output enable/direction control for USART0.
I/O
EXTBUS_A10 — External memory address line 10.
O
USB0_IND0 — USB0 port indicator LED control output 0.
I/O
GPIO0[7] — General purpose digital input/output pin. This pin is sampled at
RESET for ISP entry.
O
CTOUT_1 — SCT output 1. Match output 1 of timer 0.
I/O
U3_UCLK — Serial clock input/output for USART3 in synchronous mode.
I/O
EXTBUS_A9 — External memory address line 9.
-
n.c.
O
CTOUT_0 — SCT output 0. Match output 0 of timer 0.
I/O
U3_DIR — RS-485/EIA-485 output enable/direction control for USART3.
I/O
EXTBUS_A8 — External memory address line 8. Boot control pin 2 (see
Table 5).
I/O
GPIO1[10] — General purpose digital input/output pin.
O
CTOUT_3 — SCT output 3. Match output 3 of timer 0.
I/O
U3_BAUD3 — <tbd>for USART3.
I/O
EXTBUS_A0 — External memory address line 0.
I/O
GPIO0[14] — General purpose digital input/output pin.
O
CTOUT_2 — SCT output 2. Match output 2 of timer 0.
O
U2_TXD — Transmitter output for USART2.
I/O
EXTBUS_A1 — External memory address line 1.
I/O
GPIO1[11] — General purpose digital input/output pin.
O
CTOUT_5 — SCT output 5. Match output 1 of timer 1.
I
U2_RXD — Receiver input for USART2.
I/O
EXTBUS_A2 — External memory address line 2.
I/O
GPIO1[12] — General purpose digital input/output pin.
O
CTOUT_4 — SCT output 4. Match output 0 of timer 1.
-
n.c.
I/O
EXTBUS_A3 — External memory address line 3.
I/O
GPIO1[13] — General purpose digital input/output pin.
I
CTIN_4 — SCT input 4. Capture input 2 of timer 1.
-
n.c.
I/O
EXTBUS_A4 — External memory address line 4.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
10 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Pin description …continued
Symbol
P3_0[2]
P3_1[2]
P3_2[2]
P3_3[2]
P3_4[2]
P3_5[2]
P3_6[2]
P3_7[2]
LPC1850_30_20_10
Objective data sheet
LBGA256
Table 3.
Reset
state
F13
<tbd>
G11
F11
B14
A15
C12
B13
C11
Type Description
[1]
<tbd>
<tbd>
<tbd>
I; PU
I; PU
I; PU
<tbd>
I/O
I2S_RX_SCK — Receive Clock. It is driven by the master and received by the
slave. Corresponds to the signal SCK in the I2S-bus specification.
O
I2S_RX_MCLK — I2S receive master clock.
I/O
I2S_TX_SCK — I2S transmit clock. It is driven by the master and received by
the slave. Corresponds to the signal SCK in the I2S-bus specification.
O
I2S_TX_MCLK — I2S transmit master clock.
I/O
I2S_TX_WS — Transmit Word Select. It is driven by the master and received
by the slave. Corresponds to the signal WS in the I2S-bus specification.
I/O
I2S_RX_WS — Receive Word Select. It is driven by the master and received
by the slave. Corresponds to the signal WS in the I2S-bus specification.
I
CAN1_RD — CAN1 receiver input.
O
USB1_IND1 — USB1 port indicator LED control output 1.
I/O
I2S_TX_SDA — I2S transmit data. It is driven by the transmitter and read by
the receiver. Corresponds to the signal SD in the I2S-bus specification.
I/O
I2S_RX_SDA — I2S Receive data. It is driven by the transmitter and read by
the receiver. Corresponds to the signal SD in the I2S-bus specification.
O
CAN1_TD — CAN1 transmitter output.
O
USB1_IND0 — USB1 port indicator LED control output 0.
-
n.c.
-
n.c.
I/O
SSP0_SCK — Serial clock for SSP0.
O
SPIFI_SCK — Serial clock for SPIFI.
I/O
GPIO1[14] — General purpose digital input/output pin.
-
n.c.
-
n.c.
I/O
SPIFI_SIO3 — I/O lane 3 for SPIFI.
I/O
GPIO1[15] — General purpose digital input/output pin.
-
n.c.
-
n.c.
I/O
SPIFI_SIO2 — I/O lane 2 for SPIFI.
I/O
GPIO0[6] — General purpose digital input/output pin.
-
n.c.
I/O
SSP0_SSEL — Slave Select for SSP0.
I/O
SPIFI_MISO — Input I1 in SPIFI quad mode; SPIFI output IO1.
-
n.c.
-
n.c.
I/O
SSP0_MISO — Master In Slave Out for SSP0.
I/O
SPIFI_MOSI — Input I0 in SPIFI quad mode; SPIFI output IO0.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
11 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Pin description …continued
Symbol
P3_8[2]
P4_0[2]
P4_1[2]
P4_2[2]
P4_3[2]
P4_4[2]
P4_5[2]
P4_6[2]
P4_7[2]
LPC1850_30_20_10
Objective data sheet
LBGA256
Table 3.
Reset
state
C10
<tbd>
D5
A1
D3
C2
B1
D2
C1
H4
Type Description
[1]
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
<tbd>
-
n.c.
-
n.c.
I/O
SSP0_MOSI — Master Out Slave in for SSP0.
I/O
SPIFI_CS — SPIFI serial flash chip select.
I/O
GPIO2[0] — General purpose digital input/output pin.
O
MCOA0 — Motor control PWM channel 0, output A.
I
NMI — External interrupt input to NMI.
-
n.c.
I/O
GPIO2[1] — General purpose digital input/output pin.
O
CTOUT_1 — SCT output 1. Match output 1 of timer 0.
O
LCDVD0 — LCD data.
-
n.c.
I/O
GPIO2[2] — General purpose digital input/output pin.
O
CTOUT_0 — SCT output 0. Match output 0 of timer 0.
O
LCDVD3 — LCD data.
-
n.c.
I/O
GPIO2[3] — General purpose digital input/output pin.
O
CTOUT_3 — SCT output 0. Match output 3 of timer 0.
O
LCDVD2 — LCD data.
-
n.c.
I/O
GPIO2[4] — General purpose digital input/output pin.
O
CTOUT_2 — SCT output 2. Match output 2 of timer 0.
O
LCDVD1 — LCD data.
-
n.c.
I/O
GPIO2[5] — General purpose digital input/output pin.
O
CTOUT_5 — SCT output 5. Match output 1 of timer 1.
O
LCDFP — Frame pulse (STN). Vertical synchronization pulse (TFT).
-
n.c.
I/O
GPIO2[6] — General purpose digital input/output pin.
O
CTOUT_4 — SCT output 4. Match output 0 of timer 1.
O
LCDENAB/LCDM — STN AC bias drive or TFT data enable input.
-
n.c.
O
LCDDCLK — LCD panel clock.
I
GP_CLKIN — General purpose clock input to the CGU.
-
n.c.
-
n.c.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
12 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Pin description …continued
Symbol
P4_8[2]
P4_9[2]
P4_10[2]
P5_0[2]
P5_1[2]
P5_2[2]
P5_3[2]
P5_4[2]
P5_5[2]
LPC1850_30_20_10
Objective data sheet
LBGA256
Table 3.
Reset
state
E2
<tbd>
L2
M3
N3
P3
R4
T8
P9
P10
Type Description
[1]
<tbd>
<tbd>
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
-
n.c.
I
CTIN_5 — SCT input 5. Capture input 2 of timer 2.
O
LCDVD9 — LCD data.
-
n.c.
-
n.c.
I
CTIN_6 — SCT input 6. Capture input 1 of timer 3.
O
LCDVD11 — LCD data.
-
n.c.
-
n.c.
I
CTIN_2 — SCT input 2. Capture input 2 of timer 0.
O
LCDVD10 — LCD data.
-
n.c.
I/O
GPIO2[9] — General purpose digital input/output pin.
O
MCOB2 — Motor control PWM channel 2, output B.
I/O
EXTBUS_D12 — External memory data line 12.
-
n.c.
I/O
GPIO2[10] — General purpose digital input/output pin.
I
MCI2 — Motor control PWM channel 2, input.
I/O
EXTBUS_D13 — External memory data line 13.
-
n.c.
I/O
GPIO2[11] — General purpose digital input/output pin.
I
MCI1 — Motor control PWM channel 1, input.
I/O
EXTBUS_D14 — External memory data line 14.
-
n.c.
I/O
GPIO2[12] — General purpose digital input/output pin.
I
MCI0 — Motor control PWM channel 0, input.
I/O
EXTBUS_D15 — External memory data line 15.
-
n.c.
I/O
GPIO2[13] — General purpose digital input/output pin.
O
MCOB0 — Motor control PWM channel 0, output B.
I/O
EXTBUS_D8 — External memory data line 8.
-
n.c.
I/O
GPIO2[14] — General purpose digital input/output pin.
O
MCOA1 — Motor control PWM channel 1, output A.
I/O
EXTBUS_D9 — External memory data line 9.
-
n.c.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
13 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Pin description …continued
Symbol
P5_6[2]
P5_7[2]
P6_0
P6_1[2]
P6_2[2]
P6_3[2]
P6_4[2]
P6_5[2]
LPC1850_30_20_10
Objective data sheet
LBGA256
Table 3.
Reset
state
T13
I; PU
R12
[1]
I; PU
M12 <tbd>
R15
L13
P15
R16
P16
Type Description
I; PU
I; PU
I; PU
I; PU
I; PU
I/O
GPIO2[15] — General purpose digital input/output pin.
O
MCOB1 — Motor control PWM channel 1, output B.
I/O
EXTBUS_D10 — External memory data line 10.
-
n.c.
I/O
GPIO2[7] — General purpose digital input/output pin.
O
MCOA2 — Motor control PWM channel 2, output A.
I/O
EXTBUS_D11 — External memory data line 11.
-
n.c.
I/O
I2S_RX_SCK — Receive Clock. It is driven by the master and received by the
slave. Corresponds to the signal SCK in the I2S-bus specification.
O
I2S_RX_MCLK — I2S receive master clock.
-
n.c.
-
n.c.
I/O
GPIO3[0] — General purpose digital input/output pin.
O
EXTBUS_DYCS1 — SDRAM chip select 1.
I/O
U0_UCLK — Serial clock input/output for USART0 in synchronous mode.
I/O
I2S_RX_WS — Receive Word Select. It is driven by the master and received
by the slave. Corresponds to the signal WS in the I2S-bus specification.
I/O
GPIO3[1] — General purpose digital input/output pin.
O
EXTBUS_CKEOUT1 — SDRAM clock enable 1.
I/O
U0_DIR — RS-485/EIA-485 output enable/direction control for USART0.
I/O
I2S_RX_SDA — I2S Receive data. It is driven by the transmitter and read by
the receiver. Corresponds to the signal SD in the I2S-bus specification.
I/O
GPIO3[2] — General purpose digital input/output pin.
O
USB0_PWR_EN — VBUS drive signal (towards external charge pump or
power management unit); indicates that Vbus must be driven (active high).
-
n.c.
O
EXTBUS_CS1 — LOW active Chip Select 1 signal.
I/O
GPIO3[3] — General purpose digital input/output pin.
I
CTIN_6 — SCT input 6. Capture input 1 of timer 3.
O
U0_TXD — Transmitter output for USART0.
O
EXTBUS_CAS — LOW active SDRAM Column Address Strobe.
I/O
GPIO3[4] — General purpose digital input/output pin.
O
CTOUT_6 — SCT output 6. Match output 2 of timer 1.
I
U0_RXD — Receiver input for USART0.
O
EXTBUS_RAS — LOW active SDRAM Row Address Strobe.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
14 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Pin description …continued
Symbol
P6_6[2]
P6_7[2]
P6_8[2]
P6_9[2]
P6_10[2]
P6_11[2]
P6_12[2]
P7_0[2]
P7_1[2]
LPC1850_30_20_10
Objective data sheet
LBGA256
Table 3.
Reset
state
L14
I; PU
J13
H13
J15
H15
H12
G15
B16
C14
Type Description
[1]
<tbd>
<tbd>
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I/O
GPIO0[5] — General purpose digital input/output pin.
O
EXTBUS_BLS1 — LOW active Byte Lane select signal 1.
-
n.c.
O
USB0_PWR_FAULT — Port power fault signal indicating overcurrent
condition; this signal monitors over-current on the USB bus (external circuitry
required to detect over-current condition).
-
n.c.
I/O
EXTBUS_A15 — External memory address line 15.
-
n.c.
O
USB0_IND1 — USB0 port indicator LED control output 1.
-
n.c.
I/O
EXTBUS_A14 — External memory address line 14.
-
n.c.
O
USB0_IND0 — USB0 port indicator LED control output 0.
I/O
GPIO3[5] — General purpose digital input/output pin.
-
n.c.
-
n.c.
O
EXTBUS_DYCS0 — SDRAM chip select 0.
I/O
GPIO3[6] — General purpose digital input/output pin.
O
MCABORT — Motor control PWM, LOW-active fast abort.
-
n.c.
O
EXTBUS_DQMOUT1 — Data mask 1 used with SDRAM and static devices.
I/O
GPIO3[7] — General purpose digital input/output pin.
-
n.c.
-
n.c.
O
EXTBUS_CKEOUT0 — SDRAM clock enable 0.
I/O
GPIO2[8] — General purpose digital input/output pin.
O
CTOUT_7 — SCT output 7. Match output 3 of timer 1.
-
n.c.
O
EXTBUS_DQMOUT0 — Data mask 0 used with SDRAM and static devices.
I/O
GPIO3[8] — General purpose digital input/output pin.
O
CTOUT_14 — SCT output 14. Match output 2 of timer 3.
-
n.c.
O
LCDLE — Line end signal.
I/O
GPIO3[9] — General purpose digital input/output pin.
O
CTOUT_15 — SCT output 15. Match output 3 of timer 3.
I/O
I2S_TX_WS — Transmit Word Select. It is driven by the master and received
by the slave. Corresponds to the signal WS in the I2S-bus specification.
O
LCDVD19 — LCD data.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
15 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Pin description …continued
Symbol
P7_2[2]
P7_3[2]
P7_4[2]
P7_5[2]
P7_6[2]
P7_7[2]
P8_0[2]
P8_1[2]
P8_2[2]
LPC1850_30_20_10
Objective data sheet
LBGA256
Table 3.
Reset
state
A16
I; PU
C13
C8
A7
C7
B6
E5
H5
K4
Type Description
[1]
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I/O
GPIO3[10] — General purpose digital input/output pin.
I
CTIN_4 — SCT input 4. Capture input 2 of timer 1.
I/O
I2S_TX_SDA — I2S transmit data. It is driven by the transmitter and read by
the receiver. Corresponds to the signal SD in the I2S-bus specification.
O
LCDVD18 — LCD data.
I/O
GPIO3[11] — General purpose digital input/output pin.
I
CTIN_3 — SCT input 3. Capture input 1 of timer 1.
-
n.c.
O
LCDVD17 — LCD data.
I/O
GPIO3[12] — General purpose digital input/output pin.
O
CTOUT_13 — SCT output 13. Match output 1 of timer 3.
-
n.c.
O
LCDVD16 — LCD data.
I/O
GPIO3[13] — General purpose digital input/output pin.
O
CTOUT_12 — SCT output 12. Match output 0 of timer 3.
-
n.c.
O
LCDVD8 — LCD data.
I/O
GPIO3[14] — General purpose digital input/output pin.
O
CTOUT_11 — SCT output 1. Match output 3 of timer 2.
-
n.c.
O
LCDLP — Line synchronization pulse (STN). Horizontal synchronization
pulse (TFT).
I/O
GPIO3[15] — General purpose digital input/output pin.
O
CTOUT_8 — SCT output 8. Match output 0 of timer 2.
-
n.c.
O
LCDPWR — LCD panel power enable.
I/O
GPIO4[0] — General purpose digital input/output pin.
O
USB0_PWR_FAULT — Port power fault signal indicating overcurrent
condition; this signal monitors over-current on the USB bus (external circuitry
required to detect over-current condition).
-
n.c.
I
MCI2 — Motor control PWM channel 2, input.
I/O
GPIO4[1] — General purpose digital input/output pin.
O
USB0_IND1 — USB0 port indicator LED control output 1.
-
n.c.
I
MCI1 — Motor control PWM channel 1, input.
I/O
GPIO4[2] — General purpose digital input/output pin.
O
USB0_IND0 — USB0 port indicator LED control output 0.
-
n.c.
I
MCI0 — Motor control PWM channel 0, input.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
16 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Pin description …continued
Symbol
P8_3[2]
P8_4[2]
P8_5[2]
P8_6[2]
P8_7[2]
P8_8[2]
P9_0[2]
P9_1[2]
P9_2[2]
LPC1850_30_20_10
Objective data sheet
LBGA256
Table 3.
Reset
state
J3
I; PU
J2
J1
K3
K1
L1
T1
N6
N8
Type Description
[1]
I; PU
I; PU
I; PU
I; PU
<tbd>
I; PU
I; PU
I; PU
I/O
GPIO4[3] — General purpose digital input/output pin.
I/O
USB1_ULPI_D2 — ULPI link bidirectional data line 2.
-
n.c.
O
LCDVD12 — LCD data.
I/O
GPIO4[4] — General purpose digital input/output pin.
I/O
USB1_ULPI_D1 — ULPI link bidirectional data line 1.
-
n.c.
O
LCDVD7 — LCD data.
I/O
GPIO4[5] — General purpose digital input/output pin.
I/O
USB1_ULPI_D0 — ULPI link bidirectional data line 0.
-
n.c.
O
LCDVD6 — LCD data.
I/O
GPIO4[6] — General purpose digital input/output pin.
I
USB1_ULPI_NXT — ULPI link NXT signal. Data flow control signal from the
PHY.
-
n.c.
O
LCDVD5 — LCD data.
I/O
GPIO4[7] — General purpose digital input/output pin.
O
USB1_ULPI_STP — ULPI link STP signal. Asserted to end or interrupt
transfers to the PHY.
-
n.c.
O
LCDVD4 — LCD data.
-
n.c.
I
USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock generated by the
PHY.
-
n.c.
-
n.c.
I/O
GPIO4[12] — General purpose digital input/output pin.
O
MCABORT — Motor control PWM, LOW-active fast abort.
-
n.c.
-
n.c.
I/O
GPIO4[13] — General purpose digital input/output pin.
O
MCOA2 — Motor control PWM channel 2, output A.
-
n.c.
-
n.c.
I/O
GPIO4[14] — General purpose digital input/output pin.
O
MCOB2 — Motor control PWM channel 2, output B.
-
n.c.
-
n.c.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
17 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Pin description …continued
Symbol
P9_3[2]
P9_4[2]
P9_5[2]
P9_6[2]
PA_0[2]
PA_1[2]
PA_2[2]
PA_3[2]
PA_4[2]
LPC1850_30_20_10
Objective data sheet
LBGA256
Table 3.
Reset
state
M6
I; PU
N10
M9
L11
L12
J14
K15
H11
G13
Type Description
[1]
<tbd>
<tbd>
I; PU
<tbd>
I; PU
I; PU
I; PU
<tbd>
I/O
GPIO4[15] — General purpose digital input/output pin.
O
MCOA0 — Motor control PWM channel 0, output A.
O
USB1_IND1 — USB1 Port indicator LED control output 1.
-
n.c.
-
n.c.
O
MCOB0 — Motor control PWM channel 0, output B.
O
USB1_IND0 — USB1 Port indicator LED control output 0.
-
n.c.
-
n.c.
O
MCOA1 — Motor control PWM channel 1, output A.
O
USB1_VBUS_EN — USB1 VBUS power enable.
-
n.c.
I/O
GPIO4[11] — General purpose digital input/output pin.
O
MCOB1 — Motor control PWM channel 1, output B.
O
USB1_PWR_FAULT — USB1 Port power fault signal indicating over-current
condition; this signal monitors over-current on the USB1 bus (external
circuitry required to detect over-current condition).
-
n.c.
-
n.c.
O
SPIFI_SCK — Serial clock for SPIFI.
-
n.c.
-
n.c.
I/O
GPIO4[8] — General purpose digital input/output pin.
I
QEI_IDX — Quadrature Encoder Interface INDEX input.
-
n.c.
-
n.c.
I/O
GPIO4[9] — General purpose digital input/output pin.
I
QEI_PHB — Quadrature Encoder Interface PHB input.
-
n.c.
-
n.c.
I/O
GPIO4[10] — General purpose digital input/output pin.
I
QEI_PHA — Quadrature Encoder Interface PHA input.
-
n.c.
I/O
SPIFI_SIO3 — I/O lane 3 for SPIFI.
-
n.c.
O
CTOUT_9 — SCT output 9. Match output 1 of timer 2.
-
n.c.
I/O
EXTBUS_A23 — External memory address line 23.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
18 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Pin description …continued
Symbol
PB_0[2]
PB_1[2]
PB_2[2]
PB_3[2]
PB_4[2]
PB_5[2]
PB_6[2]
PC_0[2]
PC_1[2]
LPC1850_30_20_10
Objective data sheet
LBGA256
Table 3.
Reset
state
B15
<tbd>
A14
B12
A13
B11
A12
A6
D4
E4
Type Description
[1]
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
-
n.c.
O
CTOUT_10 — SCT output 10. Match output 2 of timer 2.
O
LCDVD23 — LCD data.
-
n.c.
-
n.c.
I
USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP data line
direction.
O
LCDVD22 — LCD data.
-
n.c.
-
n.c.
I/O
USB1_ULPI_D7 — ULPI link bidirectional data line 7.
O
LCDVD21 — LCD data.
-
n.c.
-
n.c.
I/O
USB1_ULPI_D6 — ULPI link bidirectional data line 6.
O
LCDVD20 — LCD data.
-
n.c.
-
n.c.
I/O
USB1_ULPI_D5 — ULPI link bidirectional data line 5.
O
LCDVD15 — LCD data.
-
n.c.
-
n.c.
I/O
USB1_ULPI_D4 — ULPI link bidirectional data line 4.
O
LCDVD14 — LCD data.
-
n.c.
-
n.c.
I/O
USB1_ULPI_D3 — ULPI link bidirectional data line 3.
O
LCDVD13 — LCD data.
-
n.c.
I/O
ENET_RX_CLK (ENET_REF_CLK) — Ethernet Receive Clock (MII
interface) or Ethernet Reference Clock (RMII interface).
I
USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock generated by the
PHY.
-
n.c.
I/O
SDIO_CLK — SD/MMC card clock.
I/O
USB1_ULPI_D7 — ULPI link bidirectional data line 7.
O
SDIO_VOLT0 — SD/MMC bus voltage select output 0.
I
U1_RI — Ring Indicator input for UART 1.
O
ENET_MDC — Ethernet MIIM clock.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
19 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Pin description …continued
Symbol
PC_2[2]
PC_3[2]
PC_4[2]
PC_5[2]
PC_6[2]
PC_7[2]
PC_8[2]
PC_9[2]
PC_10[2]
LPC1850_30_20_10
Objective data sheet
LBGA256
Table 3.
Reset
state
F6
<tbd>
F5
F4
G4
H6
G5
N4
K2
M5
Type Description
[1]
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
I/O
USB1_ULPI_D6 — ULPI link bidirectional data line 6.
O
SDIO_RST — SD/MMC reset signal for MMC4.4 card.
I
U1_CTS — Clear to Send input for UART 1.
O
ENET_TXD2 — Ethernet transmit data 2 (MII interface).
I/O
USB1_ULPI_D5 — ULPI link bidirectional data line 5.
O
SDIO_VOLT1 — SD/MMC bus voltage select output 1.
O
U1_RTS — Request to Send output for UART 1. Can also be configured to be
an RS-485/EIA-485 output enable signal for UART 1.
O
ENET_TXD3 — Ethernet transmit data 3 (MII interface).
I/O
SDIO_D0 — SD/MMC data bus line 0.
I/O
USB1_ULPI_D4 — ULPI link bidirectional data line 4.
I/O
SPIFI_CS — SPIFI serial flash chip select.
O
ENET_TX_EN — Ethernet transmit data enable (RMII/MII interface).
I/O
SDIO_D1 — SD/MMC data bus line 1.
I/O
USB1_ULPI_D3 — ULPI link bidirectional data line 3.
I/O
SPIFI_MISO — Input I1 in SPIFI quad mode; SPIFI output IO1.
O
ENET_TX_ER — Ethernet Transmit Error (MII interface).
I/O
SDIO_D2 — SD/MMC data bus line 2.
I/O
USB1_ULPI_D2 — ULPI link bidirectional data line 2.
-
n.c.
I
ENET_RXD2 — Ethernet receive data 2 (RMII/MII interface).
I/O
SDIO_D3 — SD/MMC data bus line 3.
I/O
USB1_ULPI_D1 — ULPI link bidirectional data line 1.
-
n.c.
I
ENET_RXD3 — Ethernet receive data 3 (RMII/MII interface).
I
SDIO_CD — SD/MMC card detect input.
I/O
USB1_ULPI_D0 — ULPI link bidirectional data line 0.
I/O
SPIFI_SIO2 — I/O lane 2 for SPIFI.
I
ENET_RX_DV — Ethernet Receive Data Valid (MII interface).
O
SDIO_POW — <tbd>.
I
USB1_ULPI_NXT — ULPI link NXT signal. Data flow control signal from the
PHY.
-
n.c.
I
ENET_RX_ER — Ethernet receive error (RMII/MII interface).
I/O
SDIO_CMD — SD/MMC command signal.
O
USB1_ULPI_STP — ULPI link STP signal. Asserted to end or interrupt
transfers to the PHY.
I
U1_DSR — Data Set Ready input for UART 1.
-
n.c.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
20 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Pin description …continued
Symbol
PC_11[2]
PC_12[2]
PC_13[2]
PC_14[2]
PD_0[2]
PD_1[2]
PD_2[2]
PD_3[2]
PD_4[2]
LPC1850_30_20_10
Objective data sheet
LBGA256
Table 3.
Reset
state
L5
<tbd>
L6
M1
N1
N2
P1
R1
P4
T2
Type Description
[1]
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
I/O
SDIO_D4 — SD/MMC data bus line 4.
I
USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP data line
direction.
I
U1_DCD — Data Carrier Detect input for UART 1.
-
n.c.
I/O
SDIO_D5 — SD/MMC data bus line 5.
-
n.c.
O
U1_DTR — Data Terminal Ready output for UART 1. Can also be configured
to be an RS-485/EIA-485 output enable signal for UART 1.
-
n.c.
I/O
SDIO_D6 — SD/MMC data bus line 6.
-
n.c.
O
U1_TXD — Transmitter output for UART 1.
-
n.c.
I/O
SDIO_D7 — SD/MMC data bus line 7.
-
n.c.
I
U1_RXD — Receiver input for UART 1.
-
n.c.
-
n.c.
O
CTOUT_15 — SCT output 15. Match output 3 of timer 3.
O
EXTBUS_DQMOUT2 — Data mask 2 used with SDRAM and static devices.
-
n.c.
-
n.c.
-
n.c.
O
EXTBUS_CKEOUT2 — SDRAM clock enable 2.
-
n.c.
-
n.c.
O
CTOUT_7 — SCT output 7. Match output 3 of timer 1.
I/O
EXTBUS_D16 — External memory data line 16.
-
n.c.
-
n.c.
O
CTOUT_6 — SCT output 7. Match output 2 of timer 1.
I/O
EXTBUS_D17 — External memory data line 17.
-
n.c.
-
n.c.
O
CTOUT_8 — SCT output 8. Match output 0 of timer 2.
I/O
EXTBUS_D18 — External memory data line 18.
-
n.c.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
21 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Pin description …continued
Symbol
PD_5[2]
PD_6[2]
PD_7[2]
PD_8[2]
PD_9[2]
PD_10[2]
PD_11[2]
PD_12[2]
PD_13[2]
LPC1850_30_20_10
Objective data sheet
LBGA256
Table 3.
Reset
state
P6
<tbd>
R6
T6
P8
T11
P11
N9
N11
T14
Type Description
[1]
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
-
n.c.
O
CTOUT_9 — SCT output 9. Match output 1 of timer 2.
I/O
EXTBUS_D19 — External memory data line 19.
-
n.c.
-
n.c.
O
CTOUT_10 — SCT output 10. Match output 2 of timer 2.
I/O
EXTBUS_D20 — External memory data line 20.
-
n.c.
-
n.c.
I
CTIN_5 — SCT input 5. Capture input 2 of timer 2.
I/O
EXTBUS_D21 — External memory data line 21.
-
n.c.
-
n.c.
I
CTIN_6 — SCT input 6. Capture input 1 of timer 3.
I/O
EXTBUS_D22 — External memory data line 22.
-
n.c.
-
n.c.
O
CTOUT_13 — SCT output 13. Match output 1 of timer 3.
I/O
EXTBUS_D23 — External memory data line 23.
-
n.c.
-
n.c.
I
CTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture input 1 of timer 2.
O
EXTBUS_BLS3 — LOW active Byte Lane select signal 3.
-
n.c.
-
n.c.
-
n.c.
O
EXTBUS_CS3 — LOW active Chip Select 3 signal.
-
n.c.
-
n.c.
-
n.c.
O
EXTBUS_CS2 — LOW active Chip Select 2 signal.
-
n.c.
-
n.c.
I
CTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3.
O
EXTBUS_BLS2 — LOW active Byte Lane select signal 2.
-
n.c.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
22 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Pin description …continued
Symbol
PD_14[2]
PD_15[2]
PD_16[2]
PE_0[2]
PE_1[2]
PE_2[2]
PE_3[2]
PE_4[2]
PE_5[2]
LPC1850_30_20_10
Objective data sheet
LBGA256
Table 3.
Reset
state
R13
<tbd>
T15
R14
P14
N14
[1]
<tbd>
<tbd>
<tbd>
<tbd>
M14 <tbd>
K12
K13
N16
Type Description
<tbd>
<tbd>
<tbd>
-
n.c.
-
n.c.
O
EXTBUS_DYCS2 — SDRAM chip select 2.
-
n.c.
-
n.c.
-
n.c.
I/O
EXTBUS_A17 — External memory address line 17.
-
n.c.
-
n.c.
-
n.c.
I/O
EXTBUS_A16 — External memory address line 16.
-
n.c.
-
n.c.
-
n.c.
-
n.c.
I/O
EXTBUS_A18 — External memory address line 18.
-
n.c.
-
n.c.
-
n.c.
I/O
EXTBUS_A19 — External memory address line 19.
I
ADCTRIG0 — ADC trigger input 0.
I
CAN1_RD — CAN1 receiver input.
I/O
SPIFI_MOSI — Input I0 in SPIFI quad mode; SPIFI output IO0.
I/O
EXTBUS_A20 — External memory address line 20.
-
n.c.
O
CAN1_TD — CAN1 transmitter output.
I
ADCTRIG1 — ADC trigger input 1.
I/O
EXTBUS_A21 — External memory address line 21.
-
n.c.
I
NMI — External interrupt input to NMI.
-
n.c.
I/O
EXTBUS_A22 — External memory address line 22.
-
n.c.
O
CTOUT_3 — SCT output 3. Match output 3 of timer 0.
O
U1_RTS — Request to Send output for UART 1. Can also be configured to be
an RS-485/EIA-485 output enable signal for UART 1.
I/O
EXTBUS_D24 — External memory data line 24.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
23 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Pin description …continued
Symbol
PE_6[2]
PE_7[2]
PE_8[2]
PE_9[2]
PE_10[2]
PE_11[2]
PE_12[2]
PE_13[2]
PE_14[2]
LPC1850_30_20_10
Objective data sheet
LBGA256
Table 3.
Reset
state
[1]
M16 <tbd>
F15
F14
E16
E14
D16
D15
G14
C15
Type Description
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
-
n.c.
O
CTOUT_2 — SCT output 2. Match output 2 of timer 0.
I
U1_RI — Ring Indicator input for UART 1.
I/O
EXTBUS_D25 — External memory data line 25.
-
n.c.
O
CTOUT_5 — SCT output 5. Match output 1 of timer 1.
I
U1_CTS — Clear to Send input for UART1.
I/O
EXTBUS_D26 — External memory data line 26.
-
n.c.
O
CTOUT_4 — SCT output 4. Match output 0 of timer 0.
I
U1_DSR — Data Set Ready input for UART 1.
I/O
EXTBUS_D27 — External memory data line 27.
-
n.c.
I
CTIN_4 — SCT input 4. Capture input 2 of timer 1.
I
U1_DCD — Data Carrier Detect input for UART 1.
I/O
EXTBUS_D28 — External memory data line 28.
-
n.c.
I
CTIN_3 — SCT input 3. Capture input 1 of timer 1.
O
U1_DTR — Data Terminal Ready output for UART 1. Can also be configured
to be an RS-485/EIA-485 output enable signal for UART 1.
I/O
EXTBUS_D29 — External memory data line 29.
-
n.c.
O
CTOUT_12 — SCT output 12. Match output 0 of timer 3.
O
U1_TXD — Transmitter output for UART 1.
I/O
EXTBUS_D30 — External memory data line 30.
-
n.c.
O
CTOUT_11 — SCT output 11. Match output 3 of timer 2.
I
U1_RXD — Receiver input for UART 1.
I/O
EXTBUS_D31 — External memory data line 31.
-
n.c.
O
CTOUT_14 — SCT output 14. Match output 2 of timer 3.
I/O
I2C1_SDA — I2C1 data input/output (this pin does not use a specialized I2C
pad).
O
EXTBUS_DQMOUT3 — Data mask 3 used with SDRAM and static devices.
-
n.c.
-
n.c.
-
n.c.
O
EXTBUS_DYCS3 — SDRAM chip select 3.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
24 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Pin description …continued
Symbol
PE_15[2]
PF_0[2]
PF_1[2]
PF_2[2]
PF_3[2]
PF_4[2]
PF_5[2]
PF_6[2]
PF_7[2]
LPC1850_30_20_10
Objective data sheet
LBGA256
Table 3.
Reset
state
E13
<tbd>
D12
E11
D11
E10
D10
E9
E7
B7
Type Description
[1]
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
-
n.c.
O
CTOUT_0 — SCT output 0. Match output 0 of timer 0.
I/O
I2C1_SCL — I2C1 clock input/output (this pin does not use a specialized I2C
pad).
O
EXTBUS_CKEOUT3 — SDRAM clock enable 3.
I/O
SSP0_SCK — Serial clock for SSP0.
-
n.c.
-
n.c.
-
n.c.
-
n.c.
-
n.c.
I/O
SSP0_SSEL — Slave Select for SSP0.
-
n.c.
-
n.c.
O
U3_TXD — Transmitter output for USART3.
I/O
SSP0_MISO — Master In Slave Out for SSP0.
-
n.c.
-
n.c.
I
U3_RXD — Receiver input for USART3.
I/O
SSP0_MOSI — Master Out Slave in for SSP0.
-
n.c.
I/O
SSP1_SCK — Serial clock for SSP1.
I
GP_CLKIN — General purpose clock input to the CGU.
O
TRACECLK — Trace clock.
-
n.c.
-
n.c.
I/O
U3_UCLK — Serial clock input/output for USART3 in synchronous mode.
I/O
SSP1_SSEL — Slave Select for SSP1.
O
TRACEDATA[0] — Trace data, bit 0.
-
n.c.
I/O
U3_DIR — RS-485/EIA-485 output enable/direction control for USART3.
I/O
SSP1_MISO — Master In Slave Out for SSP1.
O
TRACEDATA[1] — Trace data, bit 1.
-
n.c.
I/O
U3_BAUD — <tbd> for USART3.
I/O
SSP1_MOSI — Master Out Slave in for SSP1.
O
TRACEDATA[2] — Trace data, bit 2.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
25 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Pin description …continued
Symbol
PF_8[2]
PF_9[2]
PF_10[2]
PF_11[2]
LBGA256
Table 3.
Reset
state
E6
<tbd>
D6
A3
A2
Type Description
[1]
<tbd>
<tbd>
<tbd>
-
n.c.
I/O
U0_UCLK — Serial clock input/output for USART0 in synchronous mode.
I
CTIN_2 — SCT input 2. Capture input 2 of timer 0.
O
TRACEDATA[3] — Trace data, bit 3.
-
n.c.
I/O
U0_DIR — RS-485/EIA-485 output enable/direction control for USART0.
O
CTOUT_1 — SCT output 1. Match output 1 of timer 0.
-
n.c.
-
n.c.
O
U0_TXD — Transmitter output for USART0.
I
SDIO_WP — SD/MMC card write protect input.
-
n.c.
-
n.c.
I
U0_RXD — Receiver input for USART0.
O
SDIO_VOLT2 — SD/MMC bus voltage select output 2.
-
n.c.
O
EXTBUS_CLK0 — SDRAM clock 0.
O
CLKOUT — Clock output pin.
-
n.c.
-
n.c.
O
EXTBUS_CLK1 — SDRAM clock 1.
O
CLKOUT — Clock output pin.
-
n.c.
-
n.c.
O
EXTBUS_CLK3 — SDRAM clock 3.
O
CLKOUT — Clock output pin.
-
n.c.
-
n.c.
O
EXTBUS_CLK2 — SDRAM clock 2.
O
CLKOUT — Clock output pin.
-
n.c.
-
n.c.
Clock pins
CLK0[4]
CLK1[2]
CLK2[2]
CLK3[2]
N5
T10
D14
P12
<tbd>
<tbd>
<tbd>
<tbd>
Debug pins
-
DBGEN[2]
L4
<tbd>
TCK/SWDCLK[2]
J5
<tbd>
I
Test Clock for JTAG interface (default) or Serial Wire (SW) clock.
TRST[2]
M4
<tbd>
I
Test Reset for JTAG interface.
TMS/SWDIO[2]
K6
<tbd>
I
Test Mode Select for JTAG interface (default) or SW debug data input/output.
TDO/SWO[2]
K5
<tbd>
O
Test Data Out for JTAG interface (default) or SW trace output.
LPC1850_30_20_10
Objective data sheet
I
JTAG interface control signal. Also used for boundary scan.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
26 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Pin description …continued
LBGA256
Table 3.
Symbol
Reset
state
J4
<tbd>
I
Test Data In for JTAG interface.
I2C0_SCL[8]
L15
<tbd>
I/O
I2C clock input/output. Open-drain output (for I2C-bus compliance).
I2C0_SDA[8]
L16
<tbd>
I/O
I2C data input/output. Open-drain output (for I2C-bus compliance).
USB0_DP[5]
F2
<tbd>
I/O
USB0 bidirectional D+ line.
USB0_DM[5]
G2
<tbd>
I/O
USB0 bidirectional D− line.
USB0_VBUS[5]
F1
<tbd>
I/O
VBUS pin (power on USB cable).
USB0_ID[6]
H2
<tbd>
I
Indicates to the transceiver whether connected a A-device (ID LOW) or
B-device (ID HIGH).
USB0_RREF[6]
H1
<tbd>
USB1_DP[7]
F12
<tbd>
I/O
USB1 bidirectional D+ line.
USB1_DM[7]
G12
<tbd>
I/O
USB1 bidirectional D− line.
TDI[2]
I2C-bus
Type Description
[1]
pins
USB0 pins
12.0 kΩ (accuracy 1 %) on-board resistor to ground for current reference.
USB1 pins
Reset and wake-up pins
RESET[9]
D9
<tbd>
I
External reset input: A LOW on this pin resets the device, causing I/O ports
and peripherals to take on their default states, and processor execution to
begin at address 0.
WAKEUP0[9]
A9
<tbd>
I
External wake-up input; can raise an interrupt and can cause wake-up from
any of the low power modes.
WAKEUP1
A10
<tbd>
I
External wake-up input; can raise an interrupt and can cause wake-up from
any of the low power modes.
WAKEUP2
C9
<tbd>
I
External wake-up input; can raise an interrupt and can cause wake-up from
any of the low power modes.
WAKEUP3
D8
<tbd>
I
External wake-up input; can raise an interrupt and can cause wake-up from
any of the low power modes.
ADC0[6]
E3
<tbd>
ADC0/1 input channel 0. Shared between ADC0, ADC1, and DAC.
ADC1[6]
C3
<tbd>
ADC0/1 input channel 1.
ADC2[6]
A4
<tbd>
ADC0/1 input channel 2.
ADC3[6]
B5
<tbd>
ADC0/1 input channel 3.
ADC4[6]
C6
<tbd>
ADC0/1 input channel 4.
ADC5[6]
B3
<tbd>
ADC0/1 input channel 5.
ADC6[6]
A5
<tbd>
ADC0/1 input channel 6.
ADC7[6]
C5
<tbd>
ADC0/1 input channel 7.
RTC_ALARM
A11
-
RTC controlled output.
RTCX1
A8
-
Input to the RTC 32 kHz ultra-low power oscillator circuit.
RTCX2
B8
-
Output from the RTC 32 kHz ultra-low power oscillator circuit.
ADC pins
RTC
Crystal oscillator pins
XTAL1[6]
LPC1850_30_20_10
Objective data sheet
D1
-
I
Input to the oscillator circuit and internal clock generator circuits.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
27 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Pin description …continued
Symbol
XTAL2[6]
LBGA256
Table 3.
Reset
state
E1
-
Type Description
[1]
O
Output from the oscillator amplifier.
Power and ground pins
USB0_VDDA3V3_
DRIVER
F3
<tbd>
Separate analog 3.3 V power supply for driver.
USB0_VDDA3V3
G3
<tbd>
USB 3.3 V separate power supply voltage
USB0_VSSA_TERM
H3
<tbd>
Dedicated analog ground for clean reference for termination resistors.
USB0_VSSA_REF
G1
<tbd>
Dedicated clean analog ground for generation of reference currents and
voltages.
VDDA
B4
-
Analog power supply.
VBAT
B10
-
RTC power supply: 3.3 V on this pin supplies power to the RTC.
VDDREG
F10;
F9;
L8;
L7;
Main regulator power supply
VPP
E8
OTP programming voltage
VDDIO
F7;
J7;
N7;
L10;
E12;
N13;
L9;
H10;
G10;
D7;
J6;
F8;
K7
I/O power supply
VSSA
B2
VSS
H7;
K8;
G9;
J11;
J10
LPC1850_30_20_10
Objective data sheet
-
Ground
Ground
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
28 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Pin description …continued
Symbol
VSSIO
LBGA256
Table 3.
Reset
state
Type Description
[1]
G6;
J8;
J9;
K9;
K10;
P7;
M13;
P13;
D13;
G8;
H8;
G7;
C4;
H9
Ground
Pins not connected
-
B9
-
n.c.
[1]
I = input, O = output, IA = inactive; PU = pull-up enabled; F = floating
[2]
Digital I/O pin. Not 5 V tolerant.
[3]
Digital I/O pin. 5 V tolerant.
[4]
Digital high-speed I/O pin.
[5]
5 V tolerant analog I/O pin.
[6]
3.3 V tolerant analog I/O pin.
[7]
5 V tolerant USB I/O pin.
[8]
I2C-bus 5 V tolerant open-drain pin.
[9]
Reset input pin; <tbd>.
[10] Alarm output pin; <tbd>.
LPC1850_30_20_10
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
29 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
7. Functional description
7.1 Architectural overview
The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and
the D-code bus. The I-code and D-code core buses allow for concurrent code and data
accesses from different slave ports.
The LPC1850/30/20/10 use a multi-layer AHB matrix to connect the ARM Cortex-M3
buses and other bus masters to peripherals in a flexible manner that optimizes
performance by allowing peripherals that are on different slaves ports of the matrix to be
accessed simultaneously by different bus masters.
7.2 ARM Cortex-M3 processor
The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM Cortex-M3 offers many new
features, including a Thumb-2 instruction set, low interrupt latency, hardware divide,
interruptable/continuable multiple load and store instructions, automatic state save and
restore for interrupts, tightly integrated interrupt controller with wake-up interrupt
controller, and multiple core buses capable of simultaneous accesses.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical
Reference Manual.
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7.3 AHB multilayer matrix
TEST/DEBUG
INTERFACE
ARM
CORTEX-M3
System
bus
I-code
bus
ETHERNET(1)
GPDMA
D-code
bus
0
USB0(1)
USB1(1)
LCD(1)
SD/
MMC(1)
masters
1
slaves
32 kB ROM
64/96 kB LOCAL SRAM
40 kB LOCAL SRAM
32 kB AHB SRAM
16 kB AHB SRAM(1)
16 kB AHB SRAM
EXTERNAL
MEMORY
CONTROLLER
AHB REGISTER
INTERFACES,
APB, RTC DOMAIN
PERIPHERALS
AHB MULTILAYER MATRIX
= master-slave connection
002aaf880
(1) Not available on all parts (see Table 2).
Fig 3.
AHB multilayer matrix master and slave connections
7.4 Nested Vectored Interrupt Controller (NVIC)
The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low
interrupt latency and efficient processing of late arriving interrupts.
7.4.1 Features
•
•
•
•
•
•
LPC1850_30_20_10
Objective data sheet
Controls system exceptions and peripheral interrupts.
In the LPC1850/30/20/10, the NVIC supports 32 vectored interrupts.
32 programmable interrupt priority levels, with hardware priority level masking.
Relocatable vector table.
Non-Maskable Interrupt (NMI).
Software interrupt generation.
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7.4.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
7.5 Event router
The event router combines various internal signals, interrupts, and the external interrupt
pins (WAKEUP[3:0]) to create an interrupt in the NVIC if enabled and to create a wake-up
signal to the ARM core and the CCU for waking up from Sleep, Deep-sleep, Power-down,
and Deep power-down modes. Individual events can be configured as edge or level
sensitive and can be enabled or disabled in the event router. The event router can be
battery powered.
The following events if enabled in the event router can create a wake-up signal and/or an
interrupt:
•
•
•
•
•
External pins WAKEUP0/1/2/3 and RESET
Alarm timer, RTC, WWDT, BOD interrupts
C_CAN and QEI interrupts
Ethernet, USB0, USB1 signals
Selected outputs of combined timers (SCT and timer0/1/3)
7.6 System Tick timer (SysTick)
The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a 10 ms interval.
7.7 On-chip static RAM
The LPC1850/30/20/10 support up to 200 kB SRAM with separate bus master access for
higher throughput and individual power control for low power operation.
7.8 Boot ROM
The internal ROM memory is used to store the boot code of the LPC1850/30/20/10. After
a reset, the ARM processor will start its code execution from this memory.
The boot ROM memory includes the following features:
• ROM memory size is 32 kB.
• Supports booting from UART interfaces and external static memory such as NOR
flash, SPI flash, quad SPI flash.
• Includes APIs for power control and OTP programming.
• Includes SPIFI and USB drivers.
AES capable parts also support:
• CMAC authentication on the boot image.
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32-bit ARM Cortex-M3 microcontroller
• Secure booting from an encrypted image. In development mode booting from a plain
text image is possible. Development mode is terminated by programming the AES
key.
• API for AES programming.
Several boot modes are available depending on the values of the OTP bits BOOT_SRC. If
the OTP memory is not programmed or the BOOT_SRC bits are all zero, the boot mode is
determined by the states of the boot pins P2_8, P1_2, and P1_1.
Table 4.
Boot mode
BOOT_SRC BOOT_SRC
bit 2
bit 1
BOOT_SRC Description
bit 0
Boot mode
defined by pin
state at reset
0
0
0
Boot source is defined by the
reset state of P1_1, P1_2, and
P2_8 pins. See Table 5.
UART
0
0
1
Boot from device connected to
USART0 using pins P2_0 and
P2_1.
SPIFI
0
1
0
Boot from Quad SPI flash
connected to the SPIFI interface
using pins P3_3 to P3_8.
EMC 8-bit
0
1
1
Boot from external static memory
(such as NOR flash) using CS0
and an 8-bit data bus.
EMC 16-bit
1
0
0
Boot from external static memory
(such as NOR flash) using CS0
and a 16-bit data bus.
EMC 32-bit
1
0
1
Boot from external static memory
(such as NOR flash) using CS0
and a 32-bit data bus.
Reserved
1
1
0
Do not use this option.
Reserved
1
1
1
Do not use this option.
Table 5.
Objective data sheet
Boot mode when OPT BOOT_SRC bits are zero
Boot mode
P2_8
P1_2
P1_1
Description
UART
LOW
LOW
LOW
Boot from device connected to USART0 using pins
P2_0 and P2_1.
SPIFI
LOW
LOW
HIGH
Boot from Quad SPI flash connected to the SPIFI
interface on P3_3 to P3_8[1].
EMC 8-bit
LOW
HIGH
LOW
Boot from external static memory (such as NOR
flash) using CS0 and an 8-bit data bus.
EMC 16-bit
LOW
HIGH
HIGH
Boot from external static memory (such as NOR
flash) using CS0 and a 16-bit data bus.
EMC 32-bit
HIGH
LOW
LOW
Boot from external static memory (such as NOR
flash) using CS0 and a 32-bit data bus.
Reserved
HIGH
LOW
HIGH
Do not use this option.
Reserved
HIGH
HIGH
LOW
Do not use this option.
SPI
HIGH
HIGH
HIGH
Boot from SPI flash connected to the SSP0
interface on P3_3, P3_6, P3_7 and P3_8[1].
[1]
LPC1850_30_20_10
Boot mode when OTP BOOT_SRC bits are programmed
The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.
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32-bit ARM Cortex-M3 microcontroller
7.9 Memory mapping
LPC1850/30/20/10
4 GB
0xFFFF FFFF
reserved
0xE010 0000
ARM private bus
reserved
SPIFI data
256 MB dynamic external memory DYCS3
256 MB dynamic external memory DYCS2
reserved
peripheral bit band alias region
reserved
0xE000 0000
0x8800 0000
0x8000 0000
0x7000 0000
0x6000 0000
0x4400 0000
0x4200 0000
0x4010 2000
reserved
reserved
reserved
AES
high-speed GPIO
APB peripherals #3
reserved
APB peripherals #2
reserved
0x2000 0000
0x1F00 0000
0x1E00 0000
0x1D00 0000
0x1C00 0000
16 MB static external memory CS3
APB peripherals #1
16 MB static external memory CS2
reserved
16 MB static external memory CS1
APB peripherals #0
16 MB static external memory CS0
reserved
0x4010 1000
0x4010 0000
0x400F 2000
0x400F 1000
0x400F 0000
0x400E 0000
0x400D 0000
0x400C 0000
0x400B 0000
0x400A 0000
0x4009 0000
0x4008 0000
0x4006 0000
clocking/reset peripherals
RTC domain peripherals
0x4005 0000
0x4004 0000
reserved
0x4001 2000
reserved
AHB peripherals
1 GB
256 MB dynamic external memory DYCS1
128 MB dynamic external memory DYCS0
0x1040 8000
0x1040 0000
0x1008 A000
0x1008 0000
0x1001 8000
0x1001 0000
0x4000 0000
0x3000 0000
0x2800 0000
reserved
32 kB ROM
0x2400 0000
reserved
32 MB AHB SRAM bit banding
0x2200 0000
32 kB + 8 kB local SRAM
(LPC1850/30/20/10)
reserved
reserved
16 kB AHB SRAM (LPC1850/30/20)
32 kB local SRAM (LPC1850/30)
16 kB AHB SRAM (LPC1850/30/20/10)
64 kB local SRAM
(LPC1850/30/20/10)
16 kB AHB SRAM (LPC1850/30/20/10)
0x2001 0000
16 kB AHB SRAM (LPC1850/30/20)
0x1000 0000
local SRAM/
external static memory banks
0 GB
256 MB shadow area
0x2000 C000
0x2000 8000
0x2000 4000
0x2000 0000
0x1000 0000
0x0000 0000
002aaf228
Fig 4.
LPC1850/30/20/10 Memory mapping (overview)
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors
LPC1850_30_20_10
Objective data sheet
LPC1850/30/20/10
0x400F 0000
0x400E 5000
reserved
0x400E 4000
ADC1
0x400E 3000
ADC0
0x400E 2000
C_CAN
0x400E 1000
DAC
0x400E 0000
APB3
peripherals
0x6000 0000
I2C1
reserved
0x400D 0000
0x400C 7000
peripheral bit band alias region
reserved
reserved
Rev. 1 — 3 January 2011
0x400C 5000
SSP1
0x400C 4000
timer3
0x400C 3000
timer2
0x400C 2000
USART3
0x400C 1000
USART2
0x400C 0000
RI timer
reserved
APB2
peripherals
0x400A 1000
0x400A 0000
reserved
AES
high-speed GPIO
APB peripherals #3
reserved
APB peripherals #2
0x400B 0000
0x400A 2000
reserved
reserved
I2S0
I2C0
reserved
APB1
peripherals
APB peripherals #1
reserved
motor control PWM
APB peripherals #0
0x4009 0000
0x4008 6000
system control
0x4008 5000
timer1
0x4008 4000
timer0
0x4008 3000
SSP0
0x4008 2000
UART1 w/ modem
0x4008 1000
USART0
0x4008 0000
WWDT
reserved
clocking/reset peripherals
RTC domain peripherals
0x4200 0000
RGU
0x4005 3000
CCU2
0x4005 2000
CCU1
0x4005 1000
CGU
0x4005 0000
0x4010 2000
0x4010 1000
reserved
0x4004 7000
0x4010 0000
RTC
0x4004 6000
0x400F 2000
OTP controller
0x4004 5000
event router
0x4004 4000
CREG
0x4004 3000
power mode control
0x4004 2000
backup registers
0x4004 1000
alarm timer
0x4004 0000
0x400A 0000
ethernet
0x4001 2000
0x4001 0000
0x4009 0000
reserved
0x4000 9000
0x4008 0000
LCD
0x4000 8000
USB1
0x4000 7000
USB0
0x4000 6000
EMC
0x4000 5000
SD/MMC
0x4000 4000
SPIFI
0x4000 3000
DMA
0x4000 2000
reserved
0x4000 1000
SCT
0x4000 0000
0x400F 1000
0x400F 0000
RTC domain
peripherals
0x400E 0000
0x400D 0000
0x400C 0000
0x400B 0000
0x4006 0000
0x4005 0000
0x4004 0000
reserved
APB0
peripherals
0x4006 0000
0x4005 4000
0x4001 2000
AHB peripherals
0x4000 0000
SRAM memories
external memory banks
AHB
peripherals
0x0000 0000
35 of 84
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002aaf229
Fig 5.
LPC1850/30/20/10 Memory mapping (peripherals)
LPC1850/30/20/10
0x4008 7000
reserved
0x4400 0000
clocking and
reset control
peripherals
reserved
32-bit ARM Cortex-M3 microcontroller
All information provided in this document is subject to legal disclaimers.
0x400C 6000
QEI
0x400A 3000
0xFFFF FFFF
external memories and
ARM private bus
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
7.10 Security features
7.10.1 AES decryption engine
The hardware AES engine can decrypt data using the AES algorithm.
7.10.1.1
Features
•
•
•
•
Decryption of external flash data connected to the quad SPI Flash Interface (SPIFI).
Secure storage of decryption keys.
Support for CMAC hash calculation to authenticate encrypted data.
Data is processed in little endian mode. This means that the first byte read from flash
is integrated into the AES codeword as least significant byte. The 16th byte read from
flash is the most significant byte of the first AES codeword.
• AES engine performance of 1 byte/clock cycle.
• DMA transfers supported through the GPDMA.
7.10.2 One-Time Programmable (OTP) memory
The OTP provides two 128-bit non-volatile memories to store AES decryption keys or
other custom data.
7.11 General Purpose I/O (GPIO)
The LPC1850/30/20/10 provides 5 GPIO ports with up to 16 GPIO pins each.
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back as well as the current state of the port pins.
All GPIO pins default to inputs with pull-up resistors enabled on reset.
7.11.1 Features
• Accelerated GPIO functions:
– GPIO registers are located on the AHB so that the fastest possible I/O timing can
be achieved.
– Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
– All GPIO registers are byte and half-word addressable.
– Entire port value can be written in one instruction.
• Bit-level set and clear registers allow a single instruction set or clear of any number of
bits in one port.
• Direction control of individual bits.
• All I/O default to inputs after reset.
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7.12 AHB peripherals
7.12.1 State Configurable Timer (SCT) subsystem
The SCT allows a wide variety of timing, counting, output modulation, and input capture
operations. The inputs and outputs of the SCT are shared with the capture and match
inputs/outputs of the 32-bit general purpose counter/timers.
The SCT can be configured as two 16-bit counters or a unified 32-bit counter. In the
two-counter case, in addition to the counter value the following operational elements are
independent for each half:
• State variable
• Limit, halt, stop, and start conditions
• Values of Match/Capture registers, plus reload or capture control values
In the two-counter case, the following operational elements are global to the SCT, but the
last three can use match conditions from either counter:
•
•
•
•
•
7.12.1.1
Clock selection
Inputs
Events
Outputs
Interrupts
Features
•
•
•
•
•
•
•
•
Two 16-bit counters or one 32-bit counter.
Counter(s) clocked by bus clock or selected input.
Up counter(s) or up-down counter(s).
State variable allows sequencing across multiple counter cycles.
Event combines input or output condition and/or counter match in a specified state.
Events control outputs and interrupts.
Selected event(s) can limit, halt, start, or stop a counter.
Supports:
– up to 8 inputs (one input connected internally)
– up to 16 outputs
– 16 match/capture registers
– 16 events
– 32 states
7.12.2 General Purpose DMA (GPDMA)
The DMA controller allows peripheral-to memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
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example, a bidirectional port requires one stream for transmit and one for receives. The
source and destination areas can each be either a memory region or a peripheral for
master 1, but only memory for master 0.
7.12.2.1
Features
• Eight DMA channels. Each channel can support an unidirectional transfer.
• 16 DMA request lines.
• Single DMA and burst DMA request signals. Each peripheral connected to the DMA
Controller can assert either a burst DMA request or a single DMA request. The DMA
burst size is set by programming the DMA Controller.
• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral transfers are supported.
• Scatter or gather DMA is supported through the use of linked lists. This means that
the source and destination areas do not have to occupy contiguous areas of memory.
• Hardware DMA channel priority.
• AHB slave DMA programming interface. The DMA Controller is programmed by
writing to the DMA control registers over the AHB slave interface.
• Two AHB bus masters for transferring data. These interfaces transfer data when a
DMA request goes active. Master 1 can access memories and peripherals, master 0
can access memories only.
• 32-bit AHB master bus width.
• Incrementing or non-incrementing addressing for source and destination.
• Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data.
• Internal four-word FIFO per channel.
• Supports 8, 16, and 32-bit wide transactions.
• Big-endian and little-endian support. The DMA Controller defaults to little-endian
mode on reset.
• An interrupt to the processor can be generated on a DMA completion or when a DMA
error has occurred.
• Raw interrupt status. The DMA error and DMA count raw interrupt status can be read
prior to masking.
7.12.3 SPI Flash Interface (SPIFI)
The SPI Flash Interface (allows low-cost serial flash memories to be connected to the
ARM Cortex-M3 processor with little performance penalty compared to parallel flash
devices with higher pin count.
After a few commands configure the interface at startup, the entire flash content is
accessible as normal memory using byte, halfword, and word accesses by the processor
and/or DMA channels. Erasure and programming are handled by simple sequences of
commands.
Many serial flash devices use a half-duplex command-driven SPI protocol for device setup
and initialization and then move to a half-duplex, command-driven 4-bit protocol for
normal operation. Different serial flash vendors and devices accept or require different
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commands and command formats. SPIFI provides sufficient flexibility to be compatible
with common flash devices and includes extensions to help insure compatibility with future
devices.
7.12.3.1
Features
•
•
•
•
•
Interfaces to serial flash memory in the main memory map.
Supports classic and 4-bit bidirectional serial protocols.
Half-duplex protocol compatible with various vendors and devices.
Data rates of up to 40 MB per second total.
Supports DMA access.
7.12.4 SD/MMC card interface
The SD/MMC card interface supports the following modes to control:
•
•
•
•
Secure Digital memory (SD version 3.0)
Secure Digital I/O (SDIO version 2.0)
Consumer Electronics Advanced Transport Architecture (CE-ATA version 1.1)
Multimedia Cards (MMC version 4.4)
7.12.5 External Memory Controller (EMC)
The LPC1850/30/20/10 EMC is a Memory Controller peripheral offering support for
asynchronous static memory devices such as RAM, ROM, and NOR flash. In addition, it
can be used as an interface with off-chip memory-mapped devices and peripherals.
7.12.5.1
Features
• Dynamic memory interface support including single data rate SDRAM.
• Asynchronous static memory device support including RAM, ROM, and NOR flash,
with or without asynchronous page mode.
• Low transaction latency.
• Read and write buffers to reduce latency and to improve performance.
• 8/16/32 data and 24 address lines wide static memory support. On parts LPC1820/10
only 8/16 data lines are available.
• 16 bit and 32 bit wide chip select SDRAM memory support.
• Static memory features include:
– Asynchronous page mode read
– Programmable Wait States
– Bus turnaround delay
– Output enable and write enable delays
– Extended wait
• Four chip selects for synchronous memory and four chip selects for static memory
devices.
• Power-saving modes dynamically control CKE and CLKOUT to SDRAMs.
• Dynamic memory self-refresh mode controlled by software.
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• Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row
address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB
parts, with 4, 8, 16, or 32 data bits per device.
• Separate reset domains allow the for auto-refresh through a chip reset if desired.
Note: Synchronous static memory devices (synchronous burst mode) are not supported.
7.12.6 High-speed USB Host/Device/OTG interface (USB0)
Remark: USB0 is not available on the LPC1810 (see Table 2).
The USB OTG module allows the part to connect directly to a USB host such as a PC (in
device mode) or to a USB device in host mode.
7.12.6.1
Features
•
•
•
•
•
•
•
Complies with Universal Serial Bus specification 2.0.
Complies with USB On-The-Go supplement.
Complies with Enhanced Host Controller Interface Specification.
Supports auto USB 2.0 mode discovery.
Supports all high-speed USB-compliant peripherals.
Supports all full-speed USB-compliant peripherals.
Supports software Host Negotiation Protocol (HNP) and Session Request Protocol
(SRP) for OTG peripherals.
• Contains UTMI+ compliant transceiver (PHY).
• Supports interrupts.
• This module has its own, integrated DMA engine.
7.12.7 High-speed USB Host/Device interface with ULPI (USB1)
Remark: USB1 is not available on the LPC1820/10 (see Table 2).
The USB1 interface can operate as a full-speed USB host/device interface or can connect
to an external ULPI PHY for High-speed operation.
7.12.7.1
Features
•
•
•
•
Complies with Universal Serial Bus specification 2.0.
Complies with Enhanced Host Controller Interface Specification.
Supports auto USB 2.0 mode discovery.
Supports all high-speed USB-compliant peripherals if connected to external ULPI
PHY.
• Supports all full-speed USB-compliant peripherals.
• Supports interrupts.
• This module has its own, integrated DMA engine.
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7.12.8 LCD controller
The LCD controller provides all of the necessary control signals to interface directly to a
variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT
panels can be operated. The display resolution is selectable and can be up to 1024 × 768
pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode.
An on-chip 512-byte color palette allows reducing bus utilization (i.e. memory size of the
displayed data) while still supporting a large number of colors.
The LCD interface includes its own DMA controller to allow it to operate independently of
the CPU and other system functions. A built-in FIFO acts as a buffer for display data,
providing flexibility for system timing. Hardware cursor support can further reduce the
amount of CPU time needed to operate the display.
7.12.8.1
Features
•
•
•
•
AHB master interface to access frame buffer.
Setup and control via a separate AHB slave interface.
Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.
Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays
with 4-bit or 8-bit interfaces.
• Supports single and dual-panel color STN displays.
• Supports Thin Film Transistor (TFT) color displays.
• Programmable display resolution including, but not limited to: 320 × 200, 320 × 240,
640 × 200, 640 × 240, 640 × 480, 800 × 600, and 1024 × 768.
•
•
•
•
•
•
•
•
•
•
•
•
Hardware cursor support for single-panel displays.
15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support.
1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.
1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.
16 bpp true-color non-palettized for color STN and TFT.
24 bpp true-color non-palettized for color TFT.
Programmable timing for different display panels.
256 entry, 16-bit palette RAM, arranged as a 128 × 32-bit RAM.
Frame, line, and pixel clock signals.
AC bias signal for STN, data enable signal for TFT panels.
Supports little and big-endian, and Windows CE data formats.
LCD panel clock may be generated from the peripheral clock, or from a clock input
pin.
7.12.9 Ethernet
Remark: Ethernet is not available on the LPC1820/10 (see Table 2).
7.12.9.1
Features
• 10/100 Mbit/s
• TCP/IP hardware checksum
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•
•
•
•
IP checksum
DMA support
Power management remote wake-up frame and magic packet detection
Supports both full-duplex and half-duplex operation
– Supports CSMA/CD Protocol for half-duplex operation.
– Supports IEEE 802.3x flow control for full-duplex operation.
– Optional forwarding of received pause control frames to the user application in
full-duplex operation.
– Back-pressure support for half-duplex operation.
– Automatic transmission of zero-quanta pause frame on deassertion of flow control
input in full-duplex operation.
7.13 Digital serial peripherals
7.13.1 UART1
The LPC1850/30/20/10 contain one UART with standard transmit and receive data lines,
UART1 also provides a full modem control handshake interface and support for
RS-485/9-bit mode allowing both software address detection and automatic address
detection using 9-bit mode.
UART1 includes a fractional baud rate generator. Standard baud rates such as 115200 Bd
can be achieved with any crystal frequency above 2 MHz.
7.13.1.1
Features
•
•
•
•
•
Maximum UART data bit rate of <tbd> MBit/s.
16 B Receive and Transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
• Auto baud capabilities and FIFO control mechanism that enables software flow
control implementation.
• Equipped with standard modem interface signals. This module also provides full
support for hardware flow control (auto-CTS/RTS).
• Support for RS-485/9-bit/EIA-485 mode (UART1).
• DMA support.
7.13.2 USART0/2/3
The LPC1850/30/20/10 contain three USARTs. In addition to standard transmit and
receive data lines, the USARTs support a synchronous mode.
The USARTs include a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
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7.13.2.1
Features
•
•
•
•
•
Maximum UART data bit rate of <tbd> MBit/s.
16 B Receive and Transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
• Auto baud capabilities and FIFO control mechanism that enables software flow
control implementation.
•
•
•
•
•
Support for RS-485/9-bit/EIA-485 mode.
USART3 includes an IrDA mode to support infrared communication.
All USARTs have DMA support.
Support for synchronous mode.
Smart card mode conforming to ISO7816 specification
7.13.3 SSP0/1 serial I/O controllers
The LPC1850/30/20/10 contain two SSP controllers. The SSP controller is capable of
operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and
slaves on the bus. Only a single master and a single slave can communicate on the bus
during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits
to 16 bits of data flowing from the master to the slave and from the slave to the master. In
practice, often only one of these data flows carries meaningful data.
7.13.3.1
Features
• Maximum SSP speed of <tbd> Mbit/s (master) or <tbd> Mbit/s (slave)
• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
•
•
•
•
•
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
DMA transfers supported by GPDMA
7.13.4 I2C0/1-bus interfaces
The LPC1850/30/20/10 each contain two I2C-bus controllers.
The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line
(SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be
controlled by more than one bus master connected to it.
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7.13.4.1
Features
• I2C0 is a standard I2C compliant bus interface with open-drain pins. I2C0 also
supports Fast mode plus with bit rates up to 1 Mbit/s.
•
•
•
•
•
•
I2C1 uses standard I/O pins with bit rates of up to 400 kbit/s (Fast I2C-bus).
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I2C-bus can be used for test and diagnostic purposes.
• All I2C-bus controllers support multiple address recognition and a bus monitor mode.
7.13.5 I2S interface
The I2S-bus provides a standard communication interface for digital audio applications.
The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line,
and one word select signal. The basic I2S-bus connection has one master, which is
always the master, and one slave. The I2S-bus interface provides a separate transmit and
receive channel, each of which can operate as either a master or a slave.
7.13.5.1
Features
• The interface has separate input/output channels each of which can operate in master
or slave mode.
• Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
• Mono and stereo audio data supported.
• The sampling frequency can range from 16 kHz to 96 kHz (16, 22.05, 32, 44.1, 48,
96) kHz.
• Support for an audio master clock.
• Configurable word select period in master mode (separately for I2S-bus input and
output).
• Two 8-word FIFO data buffers are provided, one for transmit and one for receive.
• Generates interrupt requests when buffer levels cross a programmable boundary.
• Two DMA requests, controlled by programmable buffer levels. These are connected
to the GPDMA block.
• Controls include reset, stop and mute options separately for I2S-bus input and I2S-bus
output.
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7.13.6 C_CAN
Controller Area Network (CAN) is the definition of a high performance communication
protocol for serial data communication. The C_CAN controller is designed to provide a full
implementation of the CAN protocol according to the CAN Specification Version 2.0B. The
C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by
supporting distributed real-time control with a very high level of security.
7.13.6.1
Features
•
•
•
•
•
•
•
Conforms to protocol version 2.0 parts A and B.
Supports bit rate of up to 1 Mbit/s.
Supports 32 Message Objects.
Each Message Object has its own identifier mask.
Provides programmable FIFO mode (concatenation of Message Objects).
Provides maskable interrupts.
Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN
applications.
• Provides programmable loop-back mode for self-test operation.
7.14 Counter/timers and motor control
7.14.1 General purpose 32-bit timers/external event counters
The LPC1850/30/20/10 include four 32-bit timer/counters. The timer/counter is designed
to count cycles of the system derived clock or an externally-supplied clock. It can
optionally generate interrupts, generate timed DMA requests, or perform other actions at
specified timer values, based on four match registers. Each timer/counter also includes
two capture inputs to trap the timer value when an input signal transitions, optionally
generating an interrupt.
7.14.1.1
Features
• A 32-bit timer/counter with a programmable 32-bit prescaler.
• Counter or timer operation.
• Two 32-bit capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event may also generate an interrupt.
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
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• Up to two match registers can be used to generate timed DMA requests.
7.14.2 Motor control PWM
The motor control PWM is a specialized PWM supporting 3-phase motors and other
combinations. Feedback inputs are provided to automatically sense rotor position and use
that information to ramp speed up or down. An abort input is also provided that causes the
PWM to immediately release all motor drive outputs. At the same time, the motor control
PWM is highly configurable for other generalized timing, counting, capture, and compare
applications.
7.14.3 Quadrature Encoder Interface (QEI)
A quadrature encoder, also known as a 2-channel incremental encoder, converts angular
displacement into two pulse signals. By monitoring both the number of pulses and the
relative phase of the two signals, the user can track the position, direction of rotation, and
velocity. In addition, a third channel, or index signal, can be used to reset the position
counter. The quadrature encoder interface decodes the digital pulses from a quadrature
encoder wheel to integrate position over time and determine direction of rotation. In
addition, the QEI can capture the velocity of the encoder wheel.
7.14.3.1
Features
•
•
•
•
•
•
•
•
•
•
Tracks encoder position.
Increments/decrements depending on direction.
Programmable for 2× or 4× position counting.
Velocity capture using built-in timer.
Velocity compare function with “less than” interrupt.
Uses 32-bit registers for position and velocity.
Three position compare registers with interrupts.
Index counter for revolution counting.
Index compare register with interrupts.
Can combine index and position interrupts to produce an interrupt for whole and
partial revolution displacement.
• Digital filter with programmable delays for encoder input signals.
• Can accept decoded signal inputs (clk and direction).
7.14.4 Repetitive Interrupt (RI) timer
The repetitive interrupt timer provides a free-running 32-bit counter which is compared to
a selectable value, generating an interrupt when a match occurs. Any bits of the
timer/compare can be masked such that they do not contribute to the match detection.
The repetitive interrupt timer can be used to create an interrupt that repeats at
predetermined intervals.
7.14.4.1
Features
• 32-bit counter. Counter can be free-running or be reset by a generated interrupt.
• 32-bit compare value.
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• 32-bit compare mask. An interrupt is generated when the counter value equals the
compare value, after masking. This allows for combinations not possible with a simple
compare.
7.14.5 Windowed WatchDog Timer (WWDT)
The purpose of the watchdog is to reset the controller if software fails to periodically
service it within a programmable time window.
7.14.5.1
Features
• Internally resets chip if not periodically reloaded during the programmable time-out
period.
• Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
• Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
•
•
•
•
Incorrect feed sequence causes reset or interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 24-bit timer with internal prescaler.
Selectable time period from (Tcy(WDCLK) × 256 × 4) to (Tcy(WDCLK) × 224 × 4) in
multiples of Tcy(WDCLK) × 4.
• The Watchdog Clock (WDCLK) uses the IRC as the clock source.
7.15 Analog peripherals
7.15.1 Analog-to-Digital Converter (ADC0/1)
7.15.1.1
Features
•
•
•
•
•
•
•
10-bit successive approximation analog to digital converter.
Input multiplexing among 8 pins.
Power-down mode.
Measurement range 0 to 3 V.
Sampling frequency up to 400 kSamples/s.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition on ADCTRIG0 or ADCTRIG1 pins, combined timer
outputs 8 or 15, or the PWM output MCOA2.
• Individual result registers for each A/D channel to reduce interrupt overhead.
• DMA support.
7.15.2 Digital-to-Analog Converter (DAC)
7.15.2.1
Features
• 10-bit resolution
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•
•
•
•
•
Integral Non-Linearity
Differential Non-Linearity
Monotonic by design (resistor string architecture)
Controllable conversion speed
Low power consumption
7.16 Peripherals in the RTC power domain
7.16.1 RTC
The Real Time Clock (RTC) is a set of counters for measuring time when system power is
on, and optionally when it is off. It uses very little power when its registers are not being
accessed by the CPU, especially reduced power modes. The RTC is clocked by a
separate 32 kHz oscillator that produces a 1 Hz internal time reference and is powered by
its own power supply pin, VBAT.
7.16.1.1
Features
• Measures the passage of time to maintain a calendar and clock. Provides seconds,
minutes, hours, day of month, month, year, day of week, and day of year.
• Ultra-low power design to support battery powered systems. Less than <tbd> required
for battery operation. Uses power from the CPU power supply when it is present.
•
•
•
•
•
Dedicated battery power supply pin.
RTC power supply is isolated from the rest of the chip.
Calibration counter allows adjustment to better than ±1 sec/day with 1 sec resolution.
Periodic interrupts can be generated from increments of any field of the time registers.
Alarm interrupt can be generated for a specific date/time.
7.16.2 Alarm timer
The alarm timer is a 16-bit timer and counts down at 1 kHz from a preset value generating
alarms in intervals of up to 1 min. The counter triggers a status bit when it reaches 0x00
and asserts an interrupt if enabled.
The alarm timer is part of the RTC power domain and can be battery powered.
7.17 System control
7.17.1 Configuration registers (CREG)
The following settings are controlled in the configuration register block:
•
•
•
•
•
•
•
LPC1850_30_20_10
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BOD trip settings
Oscillator output
DMA-to-peripheral muxing
Ethernet mode
Memory mapping
Timer/USART inputs
Enabling the USB controllers
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In addition, the CREG block contains the part identification and part configuration
information.
7.17.2 System Control Unit (SCU)
The system control unit determines the function and electrical mode of the digital pins. By
default function 0 is selected for all pins with pull-up enabled.
Analog I/Os for the ADCs and the DAC as well as most USB pins are on separate pads
and are not controlled through the SCU.
7.17.3 Clock Generation Unit (CGU)
The Clock Generator Unit (CGU) generates several base clocks. The base clocks may be
unrelated in frequency and phase and can have different clock sources within the CGU.
One CGU base clock is routed to the CLKOUT pins.
Derived from each base clock may be multiple branch clocks. The branch clocks offer
very flexible control for power-management purposes. All branch clocks are outputs of
one of two Clock Control Units (CCUs) and can be controlled independently. Branch
clocks derived from the same base clock are synchronous in frequency and phase.
7.17.4 Internal RC oscillator (IRC)
The IRC is used as the clock source for the WWDT and/or as the clock that drives the
PLLs and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is
trimmed to 1 % accuracy over the entire voltage and temperature range.
Upon power-up or any chip reset, the LPC1850/30/20/10 use the IRC as the clock source.
Software may later switch to one of the other available clock sources.
7.17.5 PLL0 (for USB0)
PLL0 is a dedicated PLL for the USB0 High-speed controller.
PLL0 accepts an input clock frequency from an external oscillator in the range of 14 kHz
to 25 MHz. The input frequency is multiplied up to a high frequency with a Current
Controlled Oscillator (CCO). The CCO operates in the range of 4.3 MHz to 550 MHz.
7.17.6 System PLL1
The PLL1 accepts an input clock frequency from an external oscillator in the range of
10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current
Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO
operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop
to keep the CCO within its frequency range while the PLL is providing the desired output
frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output
clock. Since the minimum output divider value is 2, it is insured that the PLL output has a
50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be
enabled by software. The program must configure and activate the PLL, wait for the PLL
to lock, and then connect to the PLL as a clock source. The PLL settling time is 100 μs.
7.17.7 Reset Generation Unit (RGU)
The RGU allows generation of independent reset signals for individual blocks and
peripherals.
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7.17.8 Power control
The LPC1850/30/20/10 support four reduced power modes: Sleep, Deep-sleep,
Power-down, and Deep power-down.
The LPC1850/30/20/10 can wake up from Deep-sleep, Power-down, and Deep
power-down modes via the WAKEUP[3:0] pins and interrupts generated by battery
powered blocks in the RTC power domain.
7.18 Emulation and debugging
Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and
trace functions are supported in addition to a standard JTAG debug and parallel trace
functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four
watch points.
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8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
Parameter
Conditions
Min
Max
Unit
3.6
V
VDD(REG)(3V3)
regulator supply voltage (3.3 V)
on pin VDD_REG
2.2[2]
VDD(IO)
I/O supply voltage
on pin VDDIO
2.2
3.6
V
VDDA(3V3)
analog supply voltage (3.3 V)
on pin VDDA
2.0
3.6
V
VBAT
battery supply voltage
for the RTC
2.2
3.6
V
Vprog(pf)
polyfuse programming
on pin VPP
2.7
3.6
V
voltage
analog input voltage
VIA
on ADC pins
0
VDDA(3V3)
V
2.0
3.6
V
VI
input voltage
only valid when the
VDD(IO) supply
voltage is present
[3]
IDD
supply current
per supply pin
[4]
-
<tbd>
mA
[4]
-
<tbd>
mA
-
<tbd>
mA
ISS
ground current
per ground pin
Ilatch
I/O latch-up current
−(0.5VDD(IO)) < VI <
(1.5VDD(IO));
Tj < 125 °C
[5]
Tstg
storage temperature
Ptot(pack)
total power dissipation (per package)
based on package
heat transfer, not
device power
consumption
VESD
electrostatic discharge voltage
human body
model; all pins
[1]
[6]
<tbd>
<tbd>
°C
-
<tbd>
W
<tbd>
<tbd>
V
The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
[2]
2.0 V if VBAT ≥ 2.2 V.
[3]
Including voltage on outputs in 3-state mode; at 2.0 V the speed will be reduced.
[4]
The peak current is limited to 25 times the corresponding maximum current.
[5]
Dependent on package type.
[6]
Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
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9. Thermal characteristics
The average chip junction temperature, Tj (°C), can be calculated using the following
equation:
T j = T amb + ( P D × R th ( j – a ) )
(1)
• Tamb = ambient temperature (°C),
• Rth(j-a) = the package junction-to-ambient thermal resistance (°C/W)
• PD = sum of internal and I/O power dissipation
The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of
the I/O pins is often small and many times can be negligible. However it can be significant
in some applications.
Table 7.
Thermal characteristics
VDD = 2.2 V to 3.6 V; Tamb = −40 °C to +85 °C unless otherwise specified;
Symbol
Parameter
Tj(max)
maximum junction
temperature
LPC1850_30_20_10
Objective data sheet
Conditions
Min
Typ
Max
Unit
-
-
<tbd>
°C
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10. Static characteristics
Table 8.
Static characteristics
Tamb = −40 °C to +85 °C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
Supply pins
VDD(IO)
I/O supply voltage
2.2
-
3.6
V
VDD(REG)(3V3)
regulator supply voltage
(3.3 V)
2.2
-
3.6
V
VDDA(3V3)
analog supply voltage
(3.3 V)
2.0
-
3.6
V
VBAT
battery supply voltage
[2]
2.2
-
3.6
V
IDD(REG)(3V3)
regulator supply current active mode; code
(3.3 V)
while(1){}
CCLK = 12 MHz; PLL
disabled
[3]
-
<tbd>
-
mA
CCLK = 100 MHz; PLL
enabled
[3]
-
<tbd>
-
mA
CCLK = 150 MHz; PLL
enabled
[3]
-
<tbd>
-
mA
executed from <tbd>; all
peripherals disabled
[3]
-
<tbd>
-
mA
deep sleep mode
[3][4]
-
<tbd>
-
μA
power-down mode
[3][4]
-
<tbd>
-
μA
[3]
-
<tbd>
-
nA
VDD(REG)(3V3) present
[5]
-
<tbd>
-
nA
VDD(REG)(3V3) not
present
[6]
<tbd>
-
nA
sleep mode
deep power-down mode;
RTC not running
IBAT
IDD(IO)
IDD(ADC)
battery supply current
I/O supply current
ADC supply current
LPC1850_30_20_10
Objective data sheet
deep power-down mode;
RTC running
deep sleep mode
[7]
-
<tbd>
-
nA
power-down mode
[7]
-
<tbd>
-
nA
deep power-down mode
[7]
-
<tbd>
-
nA
deep sleep mode
[8]
-
<tbd>
-
nA
power-down mode
[8]
-
<tbd>
-
nA
deep power-down mode
[8]
-
<tbd>
-
nA
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Table 8.
Static characteristics …continued
Tamb = −40 °C to +85 °C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
Digital pins
IIL
LOW-level input current VI = 0 V; on-chip pull-up
resistor disabled
-
-
<tbd>
μA
IIH
HIGH-level input
current
VI = VDD(IO); on-chip
pull-down resistor
disabled
-
-
<tbd>
μA
IOZ
OFF-state output
current
VO = 0 V; VO = VDD(IO);
on-chip pull-up/down
resistors disabled
-
-
<tbd>
μA
VI
input voltage
pin configured to provide
a digital function
<tbd>
-
<tbd>
V
<tbd>
-
VDD(IO)
V
[9][10]
[11]
VO
output voltage
VIH
HIGH-level input
voltage
<tbd>
-
-
V
output active
VIL
LOW-level input voltage
-
-
<tbd>
V
Vhys
hysteresis voltage
<tbd>
-
-
V
VOH
HIGH-level output
voltage
IOH = −4 mA
VDD(IO) −
0.4
-
-
V
VOL
LOW-level output
voltage
IOL = 4 mA
-
-
<tbd>
V
IOH
HIGH-level output
current
VOH = VDD(IO) − 0.4 V
<tbd>
-
-
mA
IOL
LOW-level output
current
VOL = 0.4 V
<tbd>
-
-
mA
IOHS
HIGH-level short-circuit VOH = 0 V
output current
[12]
-
-
<tbd>
mA
IOLS
LOW-level short-circuit
output current
VOL = VDD(IO)
[12]
-
-
<tbd>
mA
Ipd
pull-down current
VI = 3.6 V
<tbd>
<tbd>
<tbd>
μA
Ipu
pull-up current
VI = 0 V
<tbd>
<tbd>
<tbd>
μA
VDD(IO) < VI < 3.6 V
<tbd>
<tbd>
<tbd>
μA
<tbd>
-
-
V
Open-drain I2C0-bus pins
VIH
HIGH-level input
voltage
VIL
LOW-level input voltage
-
-
<tbd>
V
Vhys
hysteresis voltage
-
<tbd>
-
V
VOL
LOW-level output
voltage
IOLS = <tbd> mA
-
-
<tbd>
V
ILI
input leakage current
VI = VDD(IO)
VI = 5 V
LPC1850_30_20_10
Objective data sheet
[13]
-
<tbd>
<tbd>
μA
-
<tbd>
<tbd>
μA
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Table 8.
Static characteristics …continued
Tamb = −40 °C to +85 °C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
Oscillator pins
Vi(XTAL1)
input voltage on pin
XTAL1
−0.5
-
1.2
V
Vo(XTAL2)
output voltage on pin
XTAL2
−0.5
-
1.2
V
high-speed mode
<tbd>
<tbd>
<tbd>
mV
full-speed/low-speed
mode
<tbd>
-
<tbd>
mV
chirp mode
<tbd>
-
<tbd>
mV
<tbd>
<tbd>
<tbd>
mV
USB pins
common-mode input
voltage
VIC
Vi(dif)
differential input voltage
[1]
Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.
[2]
The RTC typically fails when VVBAT drops below 1.6 V.
[3]
VDD(REG)(3V3) = 3.3 V; Tamb = 25 °C for all power consumption measurements.
[4]
Conditions <tbd>.
[5]
On pin VBAT; IDD(REG)(3V3) = <tbd> nA; VDD(REG)(3V3) = 3.3 V; VBAT < VDD(REG)(3V3); Tamb = 25 °C.
[6]
On pin VBAT; VBAT = 3.3 V; Tamb = 25 °C.
[7]
All internal pull-ups disabled. All pins configured as output and driven LOW. VDD(3V3) = 3.3 V; Tamb = 25 °C.
[8]
VDDA(3V3) = 3.3 V; Tamb = 25 °C.
[9]
Including voltage on outputs in 3-state mode.
[10] VDD(3V3) supply voltages must be present.
[11] 3-state outputs go into 3-state mode in Deep power-down mode.
[12] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[13] To VSS.
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10.1 Electrical pin characteristics
001aab173
X
X
(X)
001aab173
X
X
(X)
X
X
X
X
<tbd>
X
<tbd>
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X (X)
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; standard
port pins.
Fig 6.
Typical HIGH-level output voltage VOH versus
HIGH-level output source current IOH
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; standard
port pins.
Fig 7.
001aab173
X
X
(X)
Typical LOW-level output current IOL versus
LOW-level output voltage VOL
001aab173
X
X
(X)
X
X
X
X
<tbd>
X
<tbd>
X
X
X
X
X
X
X
X
X
X
X
X
X
X (X)
Typical pull-up current Ipu versus input voltage
VI
LPC1850_30_20_10
Objective data sheet
X
X
X
X
X (X)
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; standard
port pins.
Fig 8.
X
X (X)
Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; standard
port pins.
Fig 9.
Typical pull-down current Ipd versus input
voltage VI
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10.2 Power consumption
001aab173
X
X
(X)
001aab173
X
X
(X)
X
X
X
X
<tbd>
X
<tbd>
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X (X)
Conditions: Tamb = 25 °C; VDD(REEG)(3V3) = 3.3 V; <tbd>
Fig 10. Typical supply current versus regulator supply
voltage VDD(REEG)(3V3) in active mode
Conditions: Tamb = 25 °C; VDD(REEG)(3V3) = 3.3 V; <tbd>.
Fig 11. Typical supply current versus temperature in
active mode
001aab173
X
X
X (X)
X
(X)
001aab173
X
X
(X)
X
X
X
X
<tbd>
X
<tbd>
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X (X)
Conditions: Tamb = 25 °C; <tbd>.
Conditions: Tamb = 25 °C; V; <tbd>.
Fig 12. Typical supply current versus temperature in
Sleep mode
LPC1850_30_20_10
Objective data sheet
X
X (X)
Fig 13. Typical supply current versus temperature in
Deep-sleep mode
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001aab173
X
X
(X)
001aab173
X
X
(X)
X
X
X
X
<tbd>
X
<tbd>
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X (X)
Conditions: Tamb = 25 °C; <tbd>.
Conditions: Tamb = 25 °C; V; <tbd>.
Fig 14. Typical supply current versus temperature in
Power-down mode
LPC1850_30_20_10
Objective data sheet
X
X (X)
Fig 15. Typical supply current versus temperature in
Deep power-down mode
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Table 9.
Power consumption for individual peripherals
Tamb = 25 °C; VDD(REEG)(3V3) = 3.3 V.
Peripheral
Conditions
Typical IDD[1]
IRC
ADC
DAC
I2C0
I2C1
I2S
SSP0
SSP1
USART0
UART1
USART2
USART3
USB0
USB1
Ethernet
<tbd>
[1]
LPC1850_30_20_10
Objective data sheet
Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply
voltages.
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11. Dynamic characteristics
11.1 External clock
Table 10. Dynamic characteristic: external clock
Tamb = −40 °C to +85 °C; VDD(IO) over specified ranges.[1]
Symbol Parameter
Conditions
Typ[2]
Min
Max
Unit
fosc
oscillator frequency
1
-
25
MHz
Tcy(clk)
clock cycle time
40
-
1000
ns
tCHCX
clock HIGH time
Tcy(clk) × <tbd>
-
-
ns
tCLCX
clock LOW time
Tcy(clk) × <tbd>
-
-
ns
tCLCH
clock rise time
-
-
<tbd>
ns
tCHCL
clock fall time
-
-
<tbd>
ns
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply
voltages.
tCHCL
tCHCX
tCLCH
tCLCX
Tcy(clk)
002aaa907
Fig 16. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
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11.2 IRC and RTC oscillators
Table 11. Dynamic characteristic: IRC and RTC oscillators
Tamb = −40 °C to +85 °C; <tbd> ≤ VDD(IO) ≤ <tbd>.[1]
Symbol
Parameter
Conditions
Min
Typ[2]
Max
Unit
fosc(RC)
internal RC oscillator
frequency
-
<tbd>
12.00
<tbd>
MHz
fi(RTC)
RTC input frequency
-
-
32.768
-
kHz
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply
voltages.
001aab173
X
X
(X)
X
X
<tbd>
X
X
X
X
X
X
X
X
X
X (X)
Conditions: Frequency values are typical values. 12 MHz ± 1 % accuracy is guaranteed for
2.7 V ≤ VDD(IO) ≤ 3.6 V and Tamb = −40 °C to +85 °C. Variations between parts may cause the IRC
to fall outside the 12 MHz ± 1 % accuracy specification for voltages below 2.7 V.
Fig 17. Internal RC oscillator frequency versus temperature
11.3 I2C-bus
Table 12. Dynamic characteristic: I2C-bus pins
Tamb = −40 °C to +85 °C.[1]
Symbol
Parameter
Conditions
Min
Max
Unit
fSCL
SCL clock frequency
Standard-mode
0
100
kHz
Fast-mode
0
400
kHz
Fast-mode Plus
0
1
MHz
of both SDA and
SCL signals
-
300
ns
Fast-mode
20 + 0.1 × Cb
300
ns
Fast-mode Plus
-
120
ns
tf
fall time
[3][4][5][6]
Standard-mode
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Table 12. Dynamic characteristic: I2C-bus pins
Tamb = −40 °C to +85 °C.[1]
Symbol
Parameter
Conditions
Min
Max
Unit
tLOW
LOW period of the SCL clock
Standard-mode
4.7
-
μs
Fast-mode
1.3
-
μs
tHIGH
tHD;DAT
tSU;DAT
[1]
HIGH period of the SCL clock
[2][3][7]
data hold time
[8][9]
data set-up time
Fast-mode Plus
0.5
-
μs
Standard-mode
4.0
-
μs
Fast-mode
0.6
-
μs
Fast-mode Plus
0.26
-
μs
Standard-mode
0
-
μs
Fast-mode
0
-
μs
Fast-mode Plus
0
-
μs
Standard-mode
250
-
ns
Fast-mode
100
-
ns
Fast-mode Plus
50
-
ns
Parameters are valid over operating temperature range unless otherwise specified.
[2]
tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.
[3]
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
[4]
Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.
[5]
The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified tf.
[6]
In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should
allow for this when considering bus timing.
[7]
The maximum tHD;DAT could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or
tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If
the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
[8]
tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the
acknowledge.
[9]
A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the
Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
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tf
SDA
tSU;DAT
70 %
30 %
70 %
30 %
tHD;DAT
tf
70 %
30 %
SCL
tVD;DAT
tHIGH
70 %
30 %
70 %
30 %
70 %
30 %
tLOW
S
1 / fSCL
002aaf425
Fig 18. I2C-bus pins clock timing
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11.4 SSP interface
Table 13.
Dynamic characteristics: SSP pins in SPI mode
Symbol
Parameter
Tcy(PCLK)
PCLK cycle time
Tcy(clk)
Conditions
Min
Max
Unit
<tbd>
-
ns
[1]
<tbd>
-
ns
in SPI mode
[2]
<tbd>
Tcy(clk)
ns
in SPI mode
[2]
-
<tbd>
ns
in SPI mode
[2]
-
<tbd>
ns
data output hold time
in SPI mode
[2]
-
<tbd>
ns
data set-up time
in SPI mode
[3][4]
<tbd>
-
ns
<tbd> × Tcy(PCLK) +
<tbd>
-
ns
clock cycle time
SSP master
data set-up time
tDS
data hold time
tDH
data output valid time
tv(Q)
th(Q)
SSP slave
tDS
tDH
data hold time
in SPI mode
[3][4]
tv(Q)
data output valid time
in SPI mode
[3][4]
-
<tbd> × Tcy(PCLK) +
<tbd>
ns
th(Q)
data output hold time
in SPI mode
[3][4]
-
<tbd> × Tcy(PCLK) +
<tbd>
ns
[1]
Tcy(clk) = (SSPCLKDIV × (1 + SCR) × CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the
main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0
register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).
[2]
Tamb = −40 °C to 85 °C; VDD(REG)(3V3) = 2.0 V to 3.6 V; VDD(IO) = 2.0 V to 3.6 V.
[3]
Tcy(clk) = 12 × Tcy(PCLK).
[4]
Tamb = 25 °C; VDD(REG)(3V3) = 3.3 V; VDD(IO) = 3.3 V.
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Tcy(clk)
tclk(H)
tclk(L)
SCK (CPOL = 0)
SCK (CPOL = 1)
tv(Q)
th(Q)
DATA VALID
MOSI
DATA VALID
tDS
DATA VALID
MISO
tDH
DATA VALID
th(Q)
tv(Q)
MOSI
DATA VALID
DATA VALID
tDH
tDS
MISO
CPHA = 1
DATA VALID
CPHA = 0
DATA VALID
002aae829
Fig 19. SSP master timing in SPI mode
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Tcy(clk)
tclk(H)
tclk(L)
tDS
tDH
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI
DATA VALID
DATA VALID
tv(Q)
MISO
th(Q)
DATA VALID
tDS
MOSI
DATA VALID
tDH
DATA VALID
tv(Q)
MISO
DATA VALID
CPHA = 1
DATA VALID
th(Q)
CPHA = 0
DATA VALID
002aae830
Fig 20. SSP slave timing in SPI mode
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11.5 USB interface
Table 14. Dynamic characteristics: USB pins (full-speed)
CL = 50 pF; Rpu = 1.5 kΩ on D+ to VDD(IO), unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tr
rise time
10 % to 90 %
<tbd>
-
<tbd>
ns
tf
fall time
10 % to 90 %
<tbd>
-
<tbd>
ns
tFRFM
differential rise and fall time
matching
tr / tf
<tbd>
-
<tbd>
%
VCRS
output signal crossover voltage
<tbd>
-
<tbd>
V
tFEOPT
source SE0 interval of EOP
see Figure 21
<tbd>
-
<tbd>
ns
tFDEOP
source jitter for differential transition
to SE0 transition
see Figure 21
<tbd>
-
<tbd>
ns
tJR1
receiver jitter to next transition
<tbd>
-
<tbd>
ns
tJR2
receiver jitter for paired transitions
10 % to 90 %
<tbd>
-
<tbd>
ns
tEOPR1
EOP width at receiver
must reject as
EOP; see
Figure 21
[1]
<tbd>
-
-
ns
tEOPR2
EOP width at receiver
must accept as
EOP; see
Figure 21
[1]
<tbd>
-
-
ns
[1]
Characterized but not implemented as production test. Guaranteed by design.
TPERIOD
crossover point
extended
crossover point
differential
data lines
source EOP width: tFEOPT
differential data to
SE0/EOP skew
n × TPERIOD + tFDEOP
receiver EOP width: tEOPR1, tEOPR2
002aab561
Fig 21. Differential data-to-EOP transition skew and EOP width
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11.6 Dynamic external memory interface
Table 15. Dynamic characteristics: Dynamic external memory interface
CL = 30 pF; Tamb = −40 °C to 85 °C; VDD(REG)(3V3) and VDD(IO) over specified ranges <tbd>; AHB clock = 1 MHz.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Common
td(SV)
chip select valid delay time
-
<tbd>
<tbd>
ns
th(S)
chip select hold time
<tbd>
<tbd>
-
ns
td(RASV)
row address strobe valid delay time
-
<tbd>
<tbd>
ns
th(RAS)
row address strobe hold time
<tbd>
<tbd>
-
ns
td(CASV)
column address strobe valid delay time
-
<tbd>
<tbd>
ns
th(CAS)
column address strobe hold time
<tbd>
<tbd>
-
ns
td(WV)
write valid delay time
-
<tbd>
<tbd>
ns
th(W)
write hold time
<tbd>
<tbd>
-
ns
td(GV)
output enable valid delay time
-
<tbd>
<tbd>
ns
th(G)
output enable hold time
<tbd>
<tbd>
-
ns
td(AV)
address valid delay time
-
<tbd>
<tbd>
ns
th(A)
address hold time
<tbd>
<tbd>
-
ns
Read cycle parameters
tsu(D)
data input set-up time
<tbd>
<tbd>
-
ns
th(D)
data input hold time
<tbd>
<tbd>
-
ns
Write cycle parameters
td(QV)
data output valid delay time
-
<tbd>
<tbd>
ns
th(Q)
data output hold time
<tbd>
<tbd>
-
ns
LPC1850_30_20_10
Objective data sheet
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NXP Semiconductors
LPC1850_30_20_10
Objective data sheet
11.7 Static external memory interface
Table 16. Dynamic characteristics: Static external memory interface
CL = 30 pF; Tamb = −40 °C to 85 °C; VDD(REG)(3V3) and VDD(IO) over specified ranges <tbd>; AHB clock = 1 MHz
Symbol
Parameter
Common to read and write
tCSLAV
Conditions
Min
Typ
Max
Unit
<tbd>
<tbd>
<tbd>
ns
cycles[1]
CS LOW to address valid
time
Read cycle parameters[1][2]
Rev. 1 — 3 January 2011
OE LOW to address valid
time
<tbd>
<tbd>
<tbd>
ns
tCSLOEL
CS LOW to OE LOW time
<tbd> + Tcy(CCLK) ×
WAITOEN
0 + Tcy(CCLK) × WAITOEN
<tbd> + Tcy(CCLK) ×
WAITOEN
ns
tam
memory access time
th(D)
data input hold time
<tbd>
<tbd>
<tbd>
ns
tCSHOEH
CS HIGH to OE HIGH time
<tbd>
<tbd>
<tbd>
ns
tOEHANV
OE HIGH to address invalid
time
<tbd>
<tbd>
<tbd>
ns
tOELOEH
OE LOW to OE HIGH time
<tbd> + (WAITRD −
WAITOEN + 1) × Tcy(CCLK)
0 + (WAITRD − WAITOEN +
1) × Tcy(CCLK)
<tbd> + (WAITRD −
WAITOEN + 1) × Tcy(CCLK)
tBLSLAV
BLS LOW to address valid
time
<tbd>
<tbd>
<tbd>
ns
tCSHBLSH
CS HIGH to BLS HIGH time
<tbd>
<tbd>
<tbd>
ns
<tbd> + Tcy(CCLK) × (1 +
WAITWEN)
<tbd> + Tcy(CCLK) × (1 +
WAITWEN)
<tbd> + Tcy(CCLK) × (1 +
WAITWEN)
ns
[3][4]
[5]
(WAITRD − WAITOEN + 1) × (WAITRD − WAITOEN + 1) × (WAITRD − WAITOEN + 1) × ns
Tcy(CCLK) − <tbd>
Tcy(CCLK) − <tbd>
Tcy(CCLK) − <tbd>
tCSLWEL
CS LOW to WE LOW time
tCSLBLSL
CS LOW to BLS LOW time
−0.88
0.49
0.98
ns
tWELDV
WE LOW to data valid time
0.68
2.54
5.86
ns
tCSLDV
CS LOW to data valid time
69 of 84
© NXP B.V. 2011. All rights reserved.
tWELWEH
WE LOW to WE HIGH time
tBLSLBLSH BLS LOW to BLS HIGH
time
tWEHANV
WE HIGH to address invalid
time
0
2.64
4.79
ns
[3]
<tbd> + Tcy(CCLK) ×
(WAITWR − WAITWEN + 1)
0 + Tcy(CCLK) × (WAITWR −
WAITWEN + 1)
<tbd> + Tcy(CCLK) ×
(WAITWR − WAITWEN + 1)
ns
[3]
<tbd> + Tcy(CCLK) ×
(WAITWR − WAITWEN + 3)
0 + Tcy(CCLK) × (WAITWR −
WAITWEN + 3)
<tbd> + Tcy(CCLK) ×
(WAITWR − WAITWEN + 3)
ns
[3]
<tbd> + Tcy(CCLK)
<tbd> + Tcy(CCLK)
<tbd> + Tcy(CCLK)
ns
LPC1850/30/20/10
Write cycle parameters[1][6]
32-bit ARM Cortex-M3 microcontroller
All information provided in this document is subject to legal disclaimers.
tOELAV
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Symbol
Parameter
Conditions
Min
Typ
Max
Unit
<tbd>
<tbd>
<tbd>
ns
tWEHDNV
WE HIGH to data invalid
time
[3]
tBLSHANV
BLS HIGH to address
invalid time
[3]
<tbd>
<tbd>
<tbd>
ns
tBLSHDNV
BLS HIGH to data invalid
time
[3]
<tbd>
<tbd>
<tbd>
ns
[1]
VOH = 2.5 V, VOL = 0.2 V.
[2]
VIH = 2.5 V, VIL = 0.5 V.
Rev. 1 — 3 January 2011
Tcy(CCLK) = 1/CCLK.
[4]
Latest of address valid, CS LOW, OE LOW to data valid.
[5]
Earliest of CS HIGH, OE HIGH, address change to data invalid.
[6]
Byte lane state bit (PB) = 1.
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[3]
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LPC1850_30_20_10
Objective data sheet
Table 16. Dynamic characteristics: Static external memory interface …continued
CL = 30 pF; Tamb = −40 °C to 85 °C; VDD(REG)(3V3) and VDD(IO) over specified ranges <tbd>; AHB clock = 1 MHz
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
tCSLAV
tCSHOEH
CS
addr
tam
th(D)
data
tCSLOEL
tOELAV
tOEHANV
tOELOEH
OE
tCSHBLSH
tBLSLAV
BLS
002aad955
Fig 22. Static external memory controller read access
CS
tCSLAV
tCSLWEL
tWELWEH
tBLSLBLSH
BLS/WE
tWEHANV
tCSLBLSL
tWELDV
tBLSHANV
addr
tCSLDV
tWEHDNV
tBLSHDNV
data
OE
002aad956
Fig 23. Static external memory controller write access
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12. ADC/DAC electrical characteristics
Table 17. ADC characteristics
VDDA(3V3) over specified ranges; Tamb = −40 °C to +85 °C; ADC frequency 4.5 MHz; unless otherwise specified.
Symbol
Parameter
VIA
Cia
ED
differential linearity error
Min
Typ
Max
analog input voltage
0
-
VDDA(3V3)
V
analog input capacitance
-
-
<tbd>
pF
[1][2][3]
-
-
<tbd>
LSB
integral non-linearity
[1][4]
-
-
<tbd>
LSB
EO
offset error
[1][5]
-
−
<tbd>
LSB
EG
gain error
[1][6]
-
-
<tbd>
%
ET
absolute error
[1][7]
-
-
<tbd>
LSB
Rvsi
voltage source interface
resistance
-
-
<tbd>
kΩ
Ri
input resistance
-
-
<tbd>
MΩ
fclk(ADC)
ADC clock frequency
-
-
<tbd>
MHz
fc(ADC)
ADC conversion frequency
-
-
<tbd>
kSamples/s
EL(adj)
[1]
Conditions
[8][9]
Unit
Conditions: VSSA = 0 V, VDDA(3V3) = 3.3 V.
[2]
The ADC is monotonic, there are no missing codes.
[3]
The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 24.
[4]
The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 24.
[5]
The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 24.
[6]
The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 24.
[7]
The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve. See Figure 24.
[8]
Tamb = 25 °C; maximum sampling frequency fs = 4.5 MHz and analog input capacitance Cia = 1 pF.
[9]
Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs × Cia).
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32-bit ARM Cortex-M3 microcontroller
offset
error
EO
gain
error
EG
1023
1022
1021
1020
1019
1018
(2)
7
code
out
(1)
6
5
(5)
4
(4)
3
(3)
2
1 LSB
(ideal)
1
0
1
2
3
4
5
6
7
1018
1019
1020
1021
1022
1023
1024
VIA (LSBideal)
offset error
EO
1 LSB =
VDDA(3V3) − VSSA
1024
002aaf959
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.
Fig 24. 10-bit ADC characteristics
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32-bit ARM Cortex-M3 microcontroller
Table 18. DAC electrical characteristics
VDDA(3V3) over specified ranges; Tamb = −40 °C to +85 °C; unless otherwise specified
Symbol
Parameter
ED
Min
Typ
Max
Unit
differential linearity error
-
<tbd>
-
LSB
EL(adj)
integral non-linearity
-
<tbd>
-
LSB
EO
offset error
-
<tbd>
-
%
EG
gain error
-
<tbd>
-
%
CL
load capacitance
-
<tbd>
-
pF
RL
load resistance
<tbd>
-
-
kΩ
LPC1850_30_20_10
Objective data sheet
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13. Application information
13.1 LCD panel signal usage
Table 19.
LCD panel connections for STN single panel mode
External pin
4-bit mono STN single panel
8-bit mono STN single panel
Color STN single panel
LPC18xx pin
used
LCD function
LPC18xx pin
used
LCD function
LPC18xx pin
used
LCD function
LCDVD[23:8]
-
-
-
-
-
-
LCDVD7
-
-
P8_4
UD[7]
P8_4
UD[7]
LCDVD6
-
-
P8_5
UD[6]
P8_5
UD[6]
LCDVD5
-
-
P8_6
UD[5]
P8_6
UD[5]
LCDVD4
-
-
P8_7
UD[4]
P8_7
UD[4]
LCDVD3
P4_2
UD[3]
P4_2
UD[3]
P4_2
UD[3]
LCDVD2
P4_3
UD[2]
P4_3
UD[2]
P4_3
UD[2]
LCDVD1
P4_4
UD[1]
P4_4
UD[1]
P4_4
UD[1]
LCDVD0
P4_1
UD[0]
P4_1
UD[0]
P4_1
UD[0]
LCDLP
P7_6
LCDLP
P7_6
LCDLP
P7_6
LCDLP
LCDENAB/
LCDM
P4_6
LCDENAB/
LCDM
P4_6
LCDENAB/
LCDM
P4_6
LCDENAB/
LCDM
LCDFP
P4_5
LCDFP
P4_5
LCDFP
P4_5
LCDFP
LCDDCLK
P4_7
LCDDCLK
P4_7
LCDDCLK
P4_7
LCDDCLK
LCDLE
P7_0
LCDLE
P7_0
LCDLE
P7_0
LCDLE
LCDPWR
P7_7
CDPWR
P7_7
LCDPWR
P7_7
LCDPWR
GP_CLKIN
PF_4
LCDCLKIN
PF_4
LCDCLKIN
PF_4
LCDCLKIN
Table 20.
LCD panel connections for STN dual panel mode
External pin
4-bit mono STN dual panel
8-bit mono STN dual panel
Color STN dual panel
LPC18xx pin
used
LCD function
LPC18xx pin
used
LCD function
LPC18xx pin
used
LCD function
LCDVD[23:16]
-
-
-
-
-
-
LCDVD15
-
-
PB_4
LD[7]
PB_4
LD[7]
LCDVD14
-
-
PB_5
LD[6]
PB_5
LD[6]
LCDVD13
-
-
PB_6
LD[5]
PB_6
LD[5]
LCDVD12
-
-
P8_3
LD[4]
P8_3
LD[4]
LCDVD11
P4_9
LD[3]
P4_9
LD[3]
P4_9
LD[3]
LCDVD10
P4_10
LD[2]
P4_10
LD[2]
P4_10
LD[2]
LCDVD9
P4_8
LD[1]
P4_8
LD[1]
P4_8
LD[1]
LCDVD8
P7_5
LD[0]
P7_5
LD[0]
P7_5
LD[0]
LCDVD7
-
-
UD[7]
P8_4
UD[7]
LCDVD6
-
-
P8_5
UD[6]
P8_5
UD[6]
LCDVD5
-
-
P8_6
UD[5]
P8_6
UD[5]
LCDVD4
-
-
P8_7
UD[4]
P8_7
UD[4]
LCDVD3
P4_2
UD[3]
P4_2
UD[3]
P4_2
UD[3]
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32-bit ARM Cortex-M3 microcontroller
Table 20.
LCD panel connections for STN dual panel mode
External pin
4-bit mono STN dual panel
8-bit mono STN dual panel
Color STN dual panel
LPC18xx pin
used
LCD function
LPC18xx pin
used
LCD function
LPC18xx pin
used
LCD function
LCDVD2
P4_3
UD[2]
P4_3
UD[2]
P4_3
UD[2]
LCDVD1
P4_4
UD[1]
P4_4
UD[1]
P4_4
UD[1]
LCDVD0
P4_1
UD[0]
P4_1
UD[0]
P4_1
UD[0]
LCDLP
P7_6
LCDLP
P7_6
LCDLP
P7_6
LCDLP
LCDENAB/
LCDM
P4_6
LCDENAB/
LCDM
P4_6
LCDENAB/
LCDM
P4_6
LCDENAB/
LCDM
LCDFP
P4_5
LCDFP
P4_5
LCDFP
P4_5
LCDFP
LCDDCLK
P4_7
LCDDCLK
P4_7
LCDDCLK
P4_7
LCDDCLK
LCDLE
P7_0
LCDLE
P7_0
LCDLE
P7_0
LCDLE
LCDPWR
P7_7
LCDPWR
P7_7
LCDPWR
P7_7
LCDPWR
GP_CLKIN
PF_4
LCDCLKIN
PF_4
LCDCLKIN
PF_4
LCDCLKIN
Table 21.
External
pin
LCD panel connections for TFT panels
TFT 12 bit (4:4:4 mode) TFT 16 bit (5:6:5 mode)
TFT 16 bit (1:5:5:5 mode) TFT 24 bit
LPC18xx
pin used
LCD
function
LPC18xx
pin used
LCD
function
LPC18xx pin LCD
used
function
LCDVD23
PB_0
BLUE3
PB_0
BLUE4
PB_0
BLUE4
BLUE7
LCDVD22
PB_1
BLUE2
PB_1
BLUE3
PB_1
BLUE3
BLUE6
LCDVD21
PB_2
BLUE1
PB_2
BLUE2
PB_2
BLUE2
BLUE5
LCDVD20
PB_3
BLUE0
PB_3
BLUE1
PB_3
BLUE1
BLUE4
LCDVD19
-
-
P7_1
BLUE0
P7_1
BLUE0
BLUE3
LPC18xx
pin used
LCD
function
LCDVD18
-
-
-
-
P7_2
intensity
LCDVD17
-
-
-
-
-
-
P7_3
BLUE2
BLUE1
LCDVD16
-
-
-
-
-
-
P7_4
BLUE0
LCDVD15
PB_4
GREEN3
PB_4
GREEN5
PB_4
GREEN4
PB_4
GREEN7
LCDVD14
PB_5
GREEN2
PB_5
GREEN4
PB_5
GREEN3
PB_5
GREEN6
LCDVD13
PB_6
GREEN1
PB_6
GREEN3
PB_6
GREEN2
PB_6
GREEN5
LCDVD12
P8_3
GREEN0
P8_3
GREEN2
P8_3
GREEN1
P8_3
GREEN4
LCDVD11
-
-
P4_9
GREEN1
P4_9
GREEN0
P4_9
GREEN3
LCDVD10
-
-
P4_10
GREEN0
P4_10
intensity
P4_10
GREEN2
LCDVD9
-
-
-
-
-
-
P4_8
GREEN1
LCDVD8
-
-
-
-
-
-
P7_5
GREEN0
LCDVD7
P8_4
RED3
P8_4
RED4
P8_4
RED4
P8_4
RED7
LCDVD6
P8_5
RED2
P8_5
RED3
P8_5
RED3
P8_5
RED6
LCDVD5
P8_6
RED1
P8_6
RED2
P8_6
RED2
P8_6
RED5
LCDVD4
P8_7
RED0
P8_7
RED1
P8_7
RED1
P8_7
RED4
LCDVD3
-
-
P4_2
RED0
P4_2
RED0
P4_2
RED3
LCDVD2
-
-
-
-
P4_3
intensity
P4_3
RED2
LCDVD1
-
-
-
-
-
-
P4_4
RED1
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Table 21.
External
pin
LCD panel connections for TFT panels
TFT 12 bit (4:4:4 mode) TFT 16 bit (5:6:5 mode)
TFT 16 bit (1:5:5:5 mode) TFT 24 bit
LPC18xx
pin used
LCD
function
LPC18xx pin LCD
used
function
LCDVD0
-
-
-
-
-
-
P4_1
RED0
LCDLP
P7_6
LCDLP
P7_6
LCDLP
P7_6
LCDLP
P7_6
LCDLP
LCDENAB/
LCDM
P4_6
LCDENAB/ P4_6
LCDM
LPC18xx
pin used
LCD
function
LPC18xx
pin used
LCD
function
LCDENAB/ P4_6
LCDM
LCDENAB/ P4_6
LCDM
LCDFP
P4_5
LCDFP
P4_5
LCDFP
P4_5
LCDFP
P4_5
LCDFP
LCDDCLK
P4_7
LCDDCLK
P4_7
LCDDCLK
P4_7
LCDDCLK
P4_7
LCDDCLK
LCDLE
P7_0
LCDLE
P7_0
LCDLE
P7_0
LCDLE
P7_0
LCDLE
LCDPWR
P7_7
LCDPWR
P7_7
LCDPWR
P7_7
LCDPWR
P7_7
LCDPWR
LCDCLKIN
PF_4
LCDCLKIN PF_4
GP_CLKIN PF_4
LCDCLKIN PF_4
LCDENAB/
LCDM
LCDCLKIN
13.2 XTAL1 input
The input voltage to the on-chip oscillators is limited to 1.2 V. If the oscillator is driven by a
clock in slave mode, it is recommended that the input be coupled through a capacitor with
Ci = 100 pF. To limit the input voltage to the specified range, choose an additional
capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave
mode, a minimum of 200 mV (RMS) is needed. For more details see <tbd>.
LPC1xxx
XTAL1
Ci
100 pF
Cg
002aae835
Fig 25. Slave mode operation of the on-chip oscillator
13.3 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines
The crystal should be connected on the PCB as close as possible to the oscillator input
and output pins of the chip. Take care that the load capacitors Cx1, Cx2, and Cx3 in case of
third overtone crystal usage have a common ground plane. The external components
must also be connected to the ground plain. Loops must be made as small as possible in
order to keep the noise coupled in via the PCB as small as possible. Also parasitics
should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller
accordingly to the increase in parasitics of the PCB layout.
LPC1850_30_20_10
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14. Package outline
LBGA256: plastic low profile ball grid array package; 256 balls; body 17 x 17 x 1 mm
A
B
D
SOT740-2
ball A1
index area
A2
A
E
A1
detail X
C
e1
e
y
y1 C
∅v M C A B
b
1/2 e
∅w M C
T
R
e
P
N
M
L
K
J
e2
H
G
1/2 e
F
E
D
C
B
A
ball A1
index area
1
3
2
5
4
7
6
9
8
11
10
13
12
15
14
16
X
5
0
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
A2
b
D
E
e
e1
e2
v
w
y
y1
mm
1.55
0.45
0.35
1.1
0.9
0.55
0.45
17.2
16.8
17.2
16.8
1
15
15
0.25
0.1
0.12
0.35
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT740-2
---
MO-192
---
EUROPEAN
PROJECTION
ISSUE DATE
05-06-16
05-08-04
Fig 26. Package outline LBGA256 package sot740_2
LPC1850_30_20_10
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
78 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
15. Abbreviations
Table 22.
LPC1850_30_20_10
Objective data sheet
Abbreviations
Acronym
Description
ADC
Analog-to-Digital Converter
AES
Advanced Encryption Standard
AHB
Advanced High-performance Bus
APB
Advanced Peripheral Bus
API
Application Programming Interface
BOD
BrownOut Detection
CAN
Controller Area Network
CMAC
Cipher-based Message Authentication Code
CSMA/CD
Carrier Sense Multiple Access with Collision Detection
DAC
Digital-to-Analog Converter
DMA
Direct Memory Access
ETB
Embedded Trace Buffer
ETM
Embedded Trace Macrocell
GPIO
General Purpose Input/Output
IRC
Internal RC
IrDA
Infrared Data Association
JTAG
Joint Test Action Group
LCD
Liquid Crystal Display
LSB
Least Significant Bit
MAC
Media Access Control
MCU
MicroController Unit
MIIM
Media Independent Interface Management
n.c.
not connected
OTG
On-The-Go
PHY
PHYsical layer
PLL
Phase-Locked Loop
PWM
Pulse Width Modulator
RMII
Reduced Media Independent Interface
SDRAM
Synchronous Dynamic Random Access Memory
SPI
Serial Peripheral Interface
SSI
Serial Synchronous Interface
SSP
Synchronous Serial Port
TCP/IP
Transmission Control Protocol/Internet Protocol
UART
Universal Asynchronous Receiver/Transmitter
ULPI
UTMI+ Low Pin Interface
USART
Universal Synchronous Asynchronous Receiver/Transmitter
USB
Universal Serial Bus
UTMI
USB 2.0 Transceiver Macrocell Interface
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
79 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
16. Revision history
Table 23.
Revision history
Document ID
Release date Data sheet status
Change notice Supersedes
LPC1850_30_20_10 v.1
20110103
-
LPC1850_30_20_10
Objective data sheet
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
-
© NXP B.V. 2011. All rights reserved.
80 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
LPC1850_30_20_10
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
81 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
LPC1850_30_20_10
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
82 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
19. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
4.1
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4
5
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6
Pinning information . . . . . . . . . . . . . . . . . . . . . . 6
6.1
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
7
Functional description . . . . . . . . . . . . . . . . . . 30
7.1
Architectural overview . . . . . . . . . . . . . . . . . . 30
7.2
ARM Cortex-M3 processor . . . . . . . . . . . . . . . 30
7.3
AHB multilayer matrix . . . . . . . . . . . . . . . . . . . 31
7.4
Nested Vectored Interrupt Controller (NVIC) . 31
7.4.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.4.2
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 32
7.5
Event router . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.6
System Tick timer (SysTick) . . . . . . . . . . . . . . 32
7.7
On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 32
7.8
Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.9
Memory mapping . . . . . . . . . . . . . . . . . . . . . . 34
7.10
Security features. . . . . . . . . . . . . . . . . . . . . . . 36
7.10.1
AES decryption engine . . . . . . . . . . . . . . . . . . 36
7.10.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.10.2
One-Time Programmable (OTP) memory . . . 36
7.11
General Purpose I/O (GPIO) . . . . . . . . . . . . . 36
7.11.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.12
AHB peripherals . . . . . . . . . . . . . . . . . . . . . . . 37
7.12.1
State Configurable Timer (SCT) subsystem . . 37
7.12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.12.2
General Purpose DMA (GPDMA) . . . . . . . . . . 37
7.12.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.12.3
SPI Flash Interface (SPIFI). . . . . . . . . . . . . . . 38
7.12.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.12.4
SD/MMC card interface . . . . . . . . . . . . . . . . . 39
7.12.5
External Memory Controller (EMC). . . . . . . . . 39
7.12.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.12.6
High-speed USB Host/Device/OTG interface
(USB0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.12.6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.12.7
High-speed USB Host/Device interface with
ULPI (USB1) . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.12.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.12.8
LCD controller. . . . . . . . . . . . . . . . . . . . . . . . . 41
7.12.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.12.9
Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.12.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.13
7.13.1
7.13.1.1
7.13.2
7.13.2.1
7.13.3
7.13.3.1
7.13.4
7.13.4.1
7.13.5
7.13.5.1
7.13.6
7.13.6.1
7.14
7.14.1
Digital serial peripherals. . . . . . . . . . . . . . . . .
UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USART0/2/3 . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSP0/1 serial I/O controllers . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C0/1-bus interfaces . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2S interface . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C_CAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Counter/timers and motor control . . . . . . . . .
General purpose 32-bit timers/external
event counters . . . . . . . . . . . . . . . . . . . . . . . .
7.14.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.14.2
Motor control PWM . . . . . . . . . . . . . . . . . . . .
7.14.3
Quadrature Encoder Interface (QEI) . . . . . . .
7.14.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.14.4
Repetitive Interrupt (RI) timer. . . . . . . . . . . . .
7.14.4.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.14.5
Windowed WatchDog Timer (WWDT) . . . . . .
7.14.5.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.15
Analog peripherals . . . . . . . . . . . . . . . . . . . . .
7.15.1
Analog-to-Digital Converter (ADC0/1) . . . . . .
7.15.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.15.2
Digital-to-Analog Converter (DAC). . . . . . . . .
7.15.2.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.16
Peripherals in the RTC power domain . . . . . .
7.16.1
RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.16.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.16.2
Alarm timer. . . . . . . . . . . . . . . . . . . . . . . . . . .
7.17
System control . . . . . . . . . . . . . . . . . . . . . . . .
7.17.1
Configuration registers (CREG) . . . . . . . . . . .
7.17.2
System Control Unit (SCU) . . . . . . . . . . . . . .
7.17.3
Clock Generation Unit (CGU) . . . . . . . . . . . .
7.17.4
Internal RC oscillator (IRC) . . . . . . . . . . . . . .
7.17.5
PLL0 (for USB0). . . . . . . . . . . . . . . . . . . . . . .
7.17.6
System PLL1 . . . . . . . . . . . . . . . . . . . . . . . . .
7.17.7
Reset Generation Unit (RGU) . . . . . . . . . . . .
7.17.8
Power control . . . . . . . . . . . . . . . . . . . . . . . . .
7.18
Emulation and debugging . . . . . . . . . . . . . . .
8
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
9
Thermal characteristics . . . . . . . . . . . . . . . . .
10
Static characteristics . . . . . . . . . . . . . . . . . . .
10.1
Electrical pin characteristics. . . . . . . . . . . . . .
42
42
42
42
43
43
43
43
44
44
44
45
45
45
45
45
46
46
46
46
46
47
47
47
47
47
47
47
48
48
48
48
48
48
49
49
49
49
49
49
50
50
51
52
53
56
continued >>
LPC1850_30_20_10
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
83 of 84
LPC1850/30/20/10
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
10.2
11
11.1
11.2
11.3
11.4
11.5
11.6
11.7
12
13
13.1
13.2
13.3
14
15
16
17
17.1
17.2
17.3
17.4
18
19
Power consumption . . . . . . . . . . . . . . . . . . . .
Dynamic characteristics . . . . . . . . . . . . . . . . .
External clock . . . . . . . . . . . . . . . . . . . . . . . . .
IRC and RTC oscillators . . . . . . . . . . . . . . . . .
I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSP interface . . . . . . . . . . . . . . . . . . . . . . . . .
USB interface . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic external memory interface . . . . . . . .
Static external memory interface . . . . . . . . . .
ADC/DAC electrical characteristics . . . . . . . .
Application information. . . . . . . . . . . . . . . . . .
LCD panel signal usage . . . . . . . . . . . . . . . . .
XTAL1 input . . . . . . . . . . . . . . . . . . . . . . . . . .
XTAL and RTCX Printed Circuit Board (PCB)
layout guidelines . . . . . . . . . . . . . . . . . . . . . . .
Package outline . . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . . .
Legal information. . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information. . . . . . . . . . . . . . . . . . . . .
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
60
60
61
61
64
67
68
69
72
75
75
77
77
78
79
80
81
81
81
81
82
82
83
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 3 January 2011
Document identifier: LPC1850_30_20_10