SMSC LPC47N217-JV 64 - pin supur i/o with lpc interface Datasheet

LPC47N217
64-Pin Super I/O with LPC
Interface
Data Brief
Product Features
3.3 Volt Operation (5V tolerant)
Multi-Mode Parallel Port with ChiProtect
Programmable Wakeup Event Interface
(IO_PME# Pin)
− Standard Mode IBM PC/XT, PC/AT, and PS/2
Compatible Bidirectional Parallel Port
− Enhanced Parallel Port (EPP) Compatible - EPP 1.7
and EPP 1.9 (IEEE 1284 Compliant)
− IEEE 1284 Compliant Enhanced Capabilities Port
(ECP)
− ChiProtect Circuitry for Protection Against Damage
Due to Printer Power-On
− 192 Base I/O Address, 15 IRQ and 3 DMA Options
SMI Support (IO_SMI# Pin)
GPIOs (14)
Two IRQ Input Pins
XNOR Chain
PC99a, PC2001
ACPI 2.0 Compliant
LPC Bus Host Interface
64-pin STQFP Package
−
−
−
−
−
Intelligent Auto Power Management
Serial Ports
− One Full Function Serial Port
− High Speed 16C550A Compatible UART with
Send/Receive 16-Byte FIFO
− Supports 230k and 460k Baud
− Programmable Baud Rate Generator
− Modem Control Circuitry
−
−
Multiplexed Command, Address and Data Bus
8-Bit I/O Transfers
8-Bit DMA Transfers
16-Bit Address Qualification
Serial IRQ Interface Compatible with Serialized
IRQ Support for PCI Systems
PCI CLKRUN# Support
Power Management Event (IO_PME#) Interface
Pin
Infrared Communications Controller
− IrDA v1.2 (4Mbps), HPSIR, ASKIR, Consumer IR
Support
− 1 IR Port
− 96 Base I/O Address, 15 IRQ Options and 3 DMA
Options
ORDERING INFORMATION
Order Number(s):
LPC47N217-JN for 64 pin STQFP package
LPC47N217-JV for 64 pin lead-free STQFP package
SMSC LPC47N217
Page 1
PRODUCT PREVIEW
Revision 06-10-03
80 Arkay Drive
Hauppauge, NY 11788
(631) 435-6000
FAX (631) 273-3123
Copyright © SMSC 2004. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information
does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of
SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's
standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or
errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon
request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure
could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC
and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms
of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Revision 06-10-03
Page 2
PRODUCT PREVIEW
SMSC LPC47N217
General Description
The SMSC LPC47N217 is a 3.3V PC 99, PC2001, and ACPI 2.0 compliant Super I/O Controller. The
LPC47N217 implements the LPC interface, a pin reduced ISA interface which provides the same or better
performance as the ISA/X-bus with a substantial savings in pins used. The part also includes 14 GPIO
pins.
The LPC47N217 incorporates a 16C550A compatible UART and one Multi-Mode parallel port with
ChiProtect circuitry plus EPP and ECP support. This device also offers a full 16-bit internally decoded
address bus, a Serial IRQ interface with PCI CLKRUN# support, relocatable configuration ports, and three
DMA channel options.
The on-chip UART is compatible with the 16C550A. There is a dedicated Serial Infrared interface UART,
which complies with IrDA v1.2 (Fast IR), HPSIR, and ASKIR formats (used by Sharp and other PDAs), as
well as Consumer IR.
The parallel port is compatible with IBM PC/AT architectures, as well as IEEE 1284 EPP and ECP. The
parallel port ChiProtect circuitry prevents damage caused by an attached powered printer when the
LPC47N217 is not powered.
The LPC47N217 features Software Configurable Logic (SCL) for ease of use. SCL allows programmable
system configuration of key functions such as the parallel port and UART.
The LPC47N217 supports the ISA Plug-and-Play Standard register set (Version 1.0a) and provides the
recommended functionality to support Windows operating systems, PC99, and PC2001. The I/O Address,
DMA Channel, and Hardware IRQ of each device in the LPC47N217 may be reprogrammed through the
internal configuration registers. There are multiple I/O address location options, a Serialized IRQ interface,
and three DMA channels.
IBM, PC/XT and PC/AT are registered trademarks and PS/2 is a trademark of International Business Machines Corporation. SMSC is a
registered trademark and ChiProtect, SuperCell, and Multi-Mode are trademarks of Standard Microsystems Corporation.
SMSC LPC47N217
Page 3
PRODUCT PREVIEW
Revision 06-10-03
Block Diagram
PD[0:7],
IO_SMI#*
IO_PME#
MULTI-MODE
PARALLEL
PORT
SMI PME WDT
CONTROL, ADDRESS, DATA
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ#
PCI_RESET#
SERIAL
IRQ
IRQIN1*, IRQIN2*
ACPI
BLOCK
CONFIGURATION
REGISTERS
nSLCTIN, nALF
nINIT, nSTROBE
GP10, GP11,
GP12*, GP13*,
GP14*,
GP23*,
GP4[0:7]
GENERAL
PURPOSE
I/O
SER_IRQ
PCI_CLK
BUSY, SLCT,
PE, nERROR, nACK
TXD1, nRTS1, nDTR1
16C550
COMPATIBLE
SERIAL
PORT 1
LPC BUS
INTERFACE
nCTS1, RXD1,
nDSR1, nDCD1, nRI1
LPCPD#
CLKRUN#
IRTX2, IRMODE*
INFRARED
INTERFACE
IRRX2, IRRX3*
CLOCK
GEN
V TR Vcc Vss
CLOCKI
* Denotes Multifunction Pins
Figure 1 - LPC47N217 Block Diagram
Revision 06-10-03
Page 4
PRODUCT PREVIEW
SMSC LPC47N217
Package Outline
Figure 2 - 64 Pin STQFP Package Outline, 7x7x1.4 Body, 2 MM Footprint
Table 1 - 64 Pin STQFP Package Parameters
A
A1
A2
D
D1
E
E1
H
L
L1
e
θ
W
ccc
MIN
~
0.05
1.35
8.80
6.80
8.80
6.80
0.09
0.45
~
o
0
0.13
~
NOMINAL
~
~
1.40
9.00
7.00
9.00
7.00
~
0.60
1.00 REF.
0.40 Basic
~
0.18
~
MAX
1.60
0.15
1.45
9.20
7.20
9.20
7.20
0.20
0.75
~
REMARKS
Overall Package Height
Standoff
Body Thickness
X Span
X body Size
Y Span
Y body Size
Lead Frame Thickness
Lead Foot Length
Lead Length
Lead Pitch
Lead Foot Angle
Lead Width
Coplanarity
7o
0.23
0.08
Notes:
1. Controlling Unit: millimeter.
2. Tolerance on the true position of the leads is ± 0.035 mm maximum.
3. Package body dimensions D1 and E1 do not include the mold protrusion.
Maximum mold protrusion is 0.25 mm per side. D1 and E1 dimensions determined at datum plane H.
4. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane.
5. Details of pin 1 identifier are optional but must be located within the zone indicated.
SMSC LPC47N217
Page 5
PRODUCT PREVIEW
Revision 06-10-03
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