Linear LS4118 Ultra-high input impedance n-channel jfet Datasheet

LS4117, 4118, 4119
ULTRA-HIGH INPUT IMPEDANCE
N-CHANNEL JFET
Linear Integrated Systems
FEATURES
LOW POWER
IDSS<90 µA (2N4117)
MINIMUM CIRCUIT LOADING
IGSS<1 pA (2N4117A Series)
ABSOLUTE MAXIMUM RATINGS (NOTE 1)
@ 25°C (unless otherwise noted)
Gate-Source or Gate-Drain Voltage (NOTE 1)
Gate-Current
Total Device Dissipation
(Derate 2mW/°C to 175°C)
Storage Temperature Range
Lead Temperature
(1/16" from case for 10 seconds)
G
-40V
50mA
SD
BVGSS
VGS(off)
Gate-Source Cutoff Voltage
IDSS
Saturation Drain Current
0.03
(NOTE 2)
FN4117/A 0.015
Common-Source Forward
70
Transconductance
(NOTE 2)
Common-Source Output
-Conductance
Common-Source Input
-Capacitance
Common-Source Reverse
-Transfer Capacitance
Ciss
Crss
3
1
4
SC
TO-72
Bottom View
255°C
"A" Series only
Gate-Source Breakdown Voltage
gos
2
300mW
-65°C to +175°C
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
2N4117/A
2N4118
FN4117/A
2N4118A
SYMBOL
CHARACTERISTICS
MIN MAX MIN
MAX
Gate Reverse Current
--10
--10
IGSS
Standard only
--25
--25
IGSS
Gate Reverse Current
--1
--1
gfs
Case
G
D
--40
-0.6
-2.5
--
--40
-2.5
--
2N4119
2N4119A
MIN MAX
--10
--25
--1
--40
-2.5
--
-1.8
-1
-3
-2
-6
0.09
0.08
0.24
0.20
0.60
210
80
250
100
330
3
--
5
--
10
3
--
3
--
3
1.5
--
1.5
--
1.5
UNITS
pA
nA
pA
CONDITIONS
VGS= -20V VDS= 0
150°C
VGS=-20V VDS= 0
150°C
nA
V
mA
IG=-1µA
VDS= 0
VDS=10V
ID= 1nA
VDS=10V
VGS= 0
µmho
f=1kHz
VDS= 10V
pF
VGS= 0
f=1MHz
NOTES:
1. Due to symmetrical geometry, these units may be operated with source and drain leads interchanged.
2. This parameter is measured during a 2 ms interval 100 ms after power is applied. (Not a JEDEC condition.)
Linear Integrated Systems
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