LINER LT1460-2.5

LT1460-2.5
Micropower Precision
Series Reference
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DESCRIPTIO
FEATURES
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Trimmed to High Accuracy: 0.075% Max
Low Drift: 10ppm/°C Max
Industrial Temperature Range SO Package
Temperature Coefficient Guaranteed to 125°C
Low Supply Current: 130µA Max
Minimum Output Current: 20mA
No Output Capacitor Required
Reverse Battery Protection
Minimum Input/Output Differential: 0.9V
Available in Small MSOP Package
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APPLICATIO S
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Handheld Instruments
Precision Regulators
A/D and D/A Converters
Power Supplies
Hard Disk Drives
, LTC and LT are registered trademarks of Linear Technology Corporation.
The LT ®1460-2.5 is a micropower bandgap reference that
combines very high accuracy and low drift with low power
dissipation and small package size. This series reference
uses curvature compensation to obtain low temperature
coefficient and trimmed precision thin-film resistors to
achieve high output accuracy. The reference will supply up to
20mA, making it ideal for precision regulator applications, yet
it is almost totally immune to input voltage variations.
This series reference provides supply current and power
dissipation advantages over shunt references that must idle
the entire load current to operate. Additionally, the LT14602.5 does not require an output compensation capacitor, but
it is stable with capacitive loads. This feature is important in
critical applications where PC board space is a premium or
fast settling is demanded. Reverse battery protection keeps
the reference from conducting current and being damaged.
The LT1460-2.5 is available in the 8-lead MSOP, SO, PDIP
and the 3-lead TO-92 packages. It is also available in the
SOT-23 package (see separate data sheet LT1460S3-2.5).
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TYPICAL APPLICATIO
Typical Distribution of Output Voltage
S8 Package
Basic Connection
20
18
LT1460-2.5
IN
C1
0.1µF
OUT
2.5V
1400 PARTS
FROM 2 RUNS
16
14
GND
1460-2.5 TA01
UNITS (%)
3.4V
TO 20V
12
10
8
6
4
2
0
–0.10
–0.06 –0.02 0 0.02
0.06
OUTPUT VOLTAGE ERROR (%)
0.10
1460-2.5 TA02
1
LT1460-2.5
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ABSOLUTE MAXIMUM RATINGS
(Note 1)
Input Voltage ........................................................... 30V
Reverse Voltage .................................................... – 15V
Output Short-Circuit Duration, TA = 25°C
VIN > 10V ........................................................... 5 sec
VIN ≤ 10V ................................................... Indefinite
Specified Temperature Range
Commercial ............................................ 0°C to 70°C
Industrial ........................................... – 40°C to 85°C
Storage Temperature Range (Note 2) ... – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
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PACKAGE/ORDER INFORMATION
TOP VIEW
DNC*
VIN
DNC*
GND
8
7
6
5
1
2
3
4
BOTTOM VIEW
TOP VIEW
DNC*
DNC*
VOUT
DNC*
DNC* 1
*CONNECTED INTERNALLY.
DO NOT CONNECT EXTERNAL
CIRCUITRY TO THESE PINS
DNC*
7
DNC*
DNC* 3
6
VOUT
GND 4
5
DNC*
VIN 2
MS8 PACKAGE
8-LEAD PLASTIC MSOP
8
N8 PACKAGE
8-LEAD PDIP
*CONNECTED INTERNALLY.
DO NOT CONNECT
EXTERNAL CIRCUITRY
TO THESE PINS
3
2
1
VIN
VOUT
GND
Z PACKAGE
3-LEAD TO-92 PLASTIC
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 250°C/ W
TJMAX = 125°C, θJA = 130°C/ W (N8)
TJMAX = 125°C, θJA = 190°C/ W (S8)
TJMAX = 125°C, θJA = 160°C/ W
ORDER PART NUMBER
ORDER PART NUMBER
ORDER PART NUMBER
LT1460ACS8-2.5
LT1460BIS8-2.5
LT1460DCS8-2.5
LT1460EIS8-2.5
LT1460GCZ-2.5
LT1460GIZ-2.5
LT1460ACN8-2.5
LT1460BIN8-2.5
LT1460DCN8-2.5
LT1460EIN8-2.5
LT1460CCMS8-2.5
LT1460FCMS8-2.5
MS8 PART MARKING
LTAA
LTAB
LT1460LHS8-2.5
LT1460MHS8-2.5
S8 PART MARKING
1460A2
460BI2
1460D2
460EI2
460LH2
460MH2
Consult factory for Military grade parts.
Available Options
ACCURACY
(%)
TEMPERATURE
COEFFICIENT
(ppm/°C)
N8
S8
0°C to 70°C
0.075
10
LT1460ACN8-2.5
LT1460ACS8-2.5
– 40°C to 85°C
0.10
10
LT1460BIN8-2.5
LT1460BIS8-2.5
0°C to 70°C
0.10
15
0°C to 70°C
0.10
20
LT1460DCN8-2.5
LT1460DCS8-2.5
– 40°C to 85°C
0.125
20
LT1460EIN8-2.5
LT1460EIS8-2.5
0°C to 70°C
0.15
25
0°C to 70°C
0.25
25
– 40°C to 85°C
0.25
25
– 40°C to 85°C/125°C
0.20
20/50
LT1460LHS8-2.5
– 40°C to 125°C
0.20
50
LT1460MHS8-2.5
TEMPERATURE
2
PACKAGE TYPE
MS8
Z
LT1460CCMS8-2.5
LT1460FCMS8-2.5
LT1460GCZ-2.5
LT1460GIZ-2.5
LT1460-2.5
ELECTRICAL CHARACTERISTICS
VIN = 5V, IOUT = 0, TA = 25°C unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
Output Voltage (Note 3)
LT1460ACN8, ACS8
2.49813
– 0.075
2.500
2.50188
0.075
V
%
LT1460BIN8, BIS8, CCMS8, DCN8, DCS8
2.4975
– 0.10
2.500
2.5025
0.10
V
%
LT1460EIN8, EIS8
2.49688
– 0.125
2.500
2.50313
0.125
V
%
LT1460FCMS8
2.49625
– 0.15
2.500
2.50375
0.15
V
%
LT1460GCZ, GIZ
2.49375
– 0.25
2.500
2.50625
0.25
V
%
2.495
– 0.20
2.500
2.505
0.20
V
%
5
7
10
12
10
25
25
10
15
20
25
20
50
50
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
30
60
80
ppm/V
ppm/V
10
25
35
ppm/V
ppm/V
1500
2800
3500
ppm/mA
ppm/mA
80
135
180
ppm/mA
ppm/mA
70
100
140
ppm/mA
ppm/mA
0.5
LT1460LHS8, MHS8
Output Voltage Temperature Coefficient (Note 4)
Line Regulation
TMIN ≤ TJ ≤ TMAX
LT1460ACN8, ACS8, BIN8, BIS8
LT1460CCMS8
LT1460DCN8, DCS8, EIN8, EIS8
LT1460FCMS8, GCZ, GIZ
LT1460LHS8
– 40°C to 85°C
– 40°C to 125°C
LT1460MHS8
– 40°C to 125°C
●
●
●
●
●
●
●
3.4V ≤ VIN ≤ 5V
●
5V ≤ VIN ≤ 20V
●
Load Regulation Sourcing (Note 5)
IOUT = 100µA
●
IOUT = 10mA
●
IOUT = 20mA
0°C to 70°C
Thermal Regulation (Note 6)
∆P = 200mW
Dropout Voltage (Note 7)
VIN – VOUT, ∆VOUT ≤ 0.1%, IOUT = 0
●
2.5
ppm/mW
●
0.9
V
●
1.3
1.4
V
V
VIN – VOUT, ∆VOUT ≤ 0.1%, IOUT = 10mA
Output Current
Short VOUT to GND
Reverse Leakage
VIN = – 15V
40
●
Supply Current
10
µA
100
130
165
µA
µA
0.1Hz ≤ f ≤ 10Hz
10Hz ≤ f ≤ 1kHz
10
10
µVP-P
µVRMS
40
ppm/√kHr
∆T = – 40°C to 85°C
∆T = 0°C to 70°C
160
25
ppm
ppm
Long-Term Stability of Output Voltage, S8 Pkg (Note 9)
Hysteresis (Note 10)
mA
0.5
●
Output Voltage Noise (Note 8)
UNITS
3
LT1460-2.5
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the specified temperature
range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: If the part is stored outside of the specified temperature range, the
output may shift due to hysteresis.
Note 3: ESD (Electrostatic Discharge) sensitive device. Extensive use of
ESD protection devices are used internal to the LT1460, however, high
electrostatic discharge can damage or degrade the device. Use proper ESD
handling precautions.
Note 4: Temperature coefficient is measured by dividing the change in
output voltage by the specified temperature range. Incremental slope is
also measured at 25°C.
Note 5: Load regulation is measured on a pulse basis from no load to the
specified load current. Output changes due to die temperature change
must be taken into account separately.
Note 6: Thermal regulation is caused by die temperature gradients created
by load current or input voltage changes. This effect must be added to
normal line or load regulation. This parameter is not 100% tested.
Note 7: Excludes load regulation errors.
Note 8: Peak-to-peak noise is measured with a single highpass filter at
0.1Hz and 2-pole lowpass filter at 10Hz. The unit is enclosed in a still-air
environment to eliminate thermocouple effects on the leads. The test time
is 10 sec. RMS noise is measured with a single highpass filter at 10Hz and
a 2-pole lowpass filter at 1kHz. The resulting output is full wave rectified
and then integrated for a fixed period, making the final reading an average
as opposed to RMS. A correction factor of 1.1 is used to convert from
average to RMS and a second correction of 0.88 is used to correct for the
nonideal bandpass of the filters.
Note 9: Long-term stability typically has a logarithmic characteristic and
therefore, changes after 1000 hours tend to be much smaller than before
that time. Total drift in the second thousand hours is normally less than
one third that of the first thousand hours with a continuing trend toward
reduced drift with time. Significant improvement in long-term drift can be
realized by preconditioning the IC with a 100 hour to 200 hour, 125°C
burn-in. Long-term stability will also be affected by differential stresses
between the IC and the board material created during board assembly. See
PC Board Layout in the Applications Information section.
Note 10: Hysteresis in output voltage is created by package stress that
differs depending on whether the IC was previously at a higher or lower
temperature. Output voltage is always measured at 25°C, but the IC is
cycled to 85°C or – 40°C before successive measurements. Hysteresis is
roughly proportional to the square of the temperature change. Hysteresis
is not normally a problem for operational temperature excursions where
the instrument might be stored at high or low temperature.
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TYPICAL PERFORMANCE CHARACTERISTICS
Minimum Input-Output Voltage
Differential
Load Regulation, Sourcing
10
–55°C
125°C
1
25°C
80
5
OUTPUT VOLTAGE CHANGE (mV)
OUTPUT VOLTAGE CHANGE (mV)
OUTPUT CURRENT (mA)
Load Regulation, Sinking
6
100
125°C
4
3
25°C
2
–55°C
1
70
125°C
60
50
25°C
40
30
20
–55°C
10
0.1
0
0
0.5
1.0
1.5
2.0
INPUT-OUTPUT VOLTAGE (V)
2.5
1460-2.5 G01
4
0.1
1
10
OUTPUT CURRENT (mA)
100
1460-2.5 G02
0
0
1.0
0.5
OUTPUT CURRENT (mA)
1.5
1460-2.5 G03
LT1460-2.5
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TYPICAL PERFORMANCE CHARACTERISTICS
Output Voltage Temperature Drift
Supply Current vs Input Voltage
2.503
Line Regulation
2.5014
175
3 TYPICAL PARTS
125°C
150
2.500
OUTPUT VOLTAGE (V)
SUPPLY CURRENT (µA)
OUTPUT VOLTAGE (V)
2.501
125
25°C
100
–55°C
75
50
2.499
0
0
25
50
TEMPERATURE (°C)
–25
75
100
5
0
10
25°C
2.5002
2.4998
–55°C
2.4990
20
15
0
2
4
INPUT VOLTAGE (V)
1460-2.5 G04
6 8 10 12 14 16 18 20
INPUT VOLTAGE (V)
1460-2.5 G06
1460-2.5 G05
Power Supply Rejection Ratio
vs Frequency
Transient Responses
Output Impedance vs Frequency
90
1k
70
60
50
40
30
20
LOAD CAPACITANCE (µF)
CL= 0.1µF
80
OUTPUT IMPEDANCE (Ω)
POWER SUPPLY REJECTION RATIO (dB)
2.5006
2.4994
25
2.498
–50
125°C
2.5010
2.502
CL = 0
100
10
10
1
0.1
0
10
IOUT = 10mA
1460 G09
CL= 1µF
0
–10
100
1
1k
10k
100k
FREQUENCY (Hz)
1M
100
10
1k
10k
FREQUENCY (Hz)
100k
1M
1460-2.5 G08
1460-2.5 G07
Output Voltage Noise Spectrum
Long-Term Drift
Three Typical Parts (S8 Package)
Output Noise 0.1Hz to 10Hz
1000
2.5000
OUTPUT VOLTAGE (V)
NOISE VOLTAGE (nV/√Hz)
OUTPUT NOISE (10µV/DIV)
2.4998
100
1k
10k
FREQUENCY (Hz)
100k
1460-2.5 G10
2.4994
2.4992
100
10
2.4996
0
1
2
3
4 5 6
TIME (SEC)
7
8
9
10
1460-2.5 G11
2.4990
0
200
600
400
TIME (HOURS)
800
1000
1460-2.5 G12
5
LT1460-2.5
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APPLICATIONS INFORMATION
Longer Battery Life
Series references have a large advantage over older shunt
style references. Shunt references require a resistor from
the power supply to operate. This resistor must be chosen
to supply the maximum current that can ever be demanded by the circuit being regulated. When the circuit
being controlled is not operating at this maximum current,
the shunt reference must always sink this current, resulting in high dissipation and short battery life.
The LT1460-2.5 series reference does not require a current setting resistor and can operate with any supply
voltage from VOUT + 0.9V to 20V. When the circuitry being
regulated does not demand current, the LT1460-2.5 reduces its dissipation and battery life is extended. If the
reference is not delivering load current it dissipates only
500µW on a 5V supply, yet the same configuration can
deliver 20mA of load current when demanded.
response of the LT1460-2.5 with a RS = 2Ω and CL = 1µF.
RS should not be made arbitrarily large because it will limit
the load regulation.
2.5V
VGEN
1.5V
VOUT
RL = 10k
VOUT
RL = 1k
1µs/DIV
1460 F02
Figure 2. CL = 0
2.5V
VGEN
1.5V
Capacitive Loads
VOUT
The LT1460-2.5 is designed to be stable with capacitive
loads. With no capacitive load, the reference is ideal for
fast settling or applications where PC board space is a
premium. The test circuit shown in Figure 1 is used to
measure the response time for various load currents and
load capacitors. The 1V step from 2.5V to 1.5V produces
a current step of 1mA or 100µA for RL = 1k or RL = 10k.
Figure 2 shows the response of the reference with no load
capacitance.
The reference settles to 2.5mV (0.1%) in less than 1µs for
a 100µA pulse and to 0.1% in 1.5µs with a 1mA step. When
load capacitance is greater than 0.01µF, the reference
begins to ring due to the pole formed with the output
impedance. Figure 3 shows the response of the reference
to a 1mA and 100µA load with a 0.01µF load capacitor. The
ringing can be greatly reduced with a DC load as small as
200µA. With large output capacitors, ≥ 1µF, the ringing
can be reduced with a small resistor in series with the
reference output as shown in Figure 4. Figure 5 shows the
VIN = 5V
CIN
0.1µF
LT1460-2.5
RL
VOUT
VGEN
CL
6
RL = 1k
VOUT
20µs/DIV
1460 F03
Figure 3. CL = 0.01µF
RS
VIN = 5V
VOUT
RL
LT1460-2.5
VGEN
CIN
0.1µF
2.5V
1.5V
CL
1460-2.5 F04
Figure 4. Isolation Resistor Test Circuit
2.5V
VGEN
1.5V
VOUT
RL = 1k,
RS = 0
VOUT
RL = 1k,
RS = 2Ω
2.5V
1.5V
1460-2.5 F01
Figure 1. Response Time Test Circuit
RL = 10k
0.1ms/DIV
1460 F05
Figure 5. Effect of RS for CL = 1µF
LT1460-2.5
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APPLICATIONS INFORMATION
Fast Turn-On
It is recommended to add a 0.1µF or larger input capacitor
to the input pin of the LT1460-2.5. This helps stability with
large load currents and speeds up turn-on. The LT14602.5 can start in 2µs, but it is important to limit the dv/dt of
the input. Under light load conditions and with a very fast
input, internal nodes overslew and this requires finite
recovery time. Figure 6 shows the result of no bypass
capacitance on the input and no output load. In this case
the supply dv/dt is 5V in 30ns which causes internal
overslew, and the output does not bias to 2.5V until 500µs.
Figure 7 shows the effect of a 0.1µF bypass capacitor
which limits the input dv/dt to approximately 5V in 2µs and
the output settles quickly.
Output Accuracy
Like all references, either series or shunt, the error budget
of the LT1460-2.5 is made up of primarily three components: initial accuracy, temperature coefficient and load
regulation. Line regulation is neglected because it typically
contributes only 30ppm/V, or 75µV for a 1V input change.
The LT1460-2.5 typically shifts less than 0.01% when
soldered into a PCB, so this is also neglected (see PC
Board Layout section). The output errors are calculated as
follows for a 100µA load and 0°C to 70°C temperature
range:
LT1460AC
VIN
VOUT
5V
Initial accuracy = 0.075%
0V
For IO = 100µA,
 3500ppm
∆VOUT = 
 0.1mA 2.5V = 875µV
 mA 
(
0V
0.2ms/DIV
)( )
which is 0.035%.
1460 F06
For temperature 0°C to 70°C the maximum ∆T = 70°C,
Figure 6. CIN = 0
 10ppm
∆VOUT = 
 70°C 2.5V = 1.75mV
 °C 
( )( )
which is 0.07%.
5V
VIN
Total worst-case output error is:
0.075% + 0.035% + 0.070% = 0.180%.
0V
VOUT
Table 1 gives worst-case accuracy for the LT1460AC, CC,
DC, FC, GC from 0°C to 70°C and the LT1460BI, EI, GI
from – 40°C to 85°C.
2µs/DIV
1460 F07
Figure 7. CIN = 0.1µF
Table 1. Worst-Case Output Accuracy Over Temperature
IOUT
LT1460AC
LT1460BI
LT1460CC
LT1460DC
LT1460EI
LT1460FC
LT1460GC
LT1460GI
0
0.145%
0.225%
0.205%
0.240%
0.375%
0.325%
0.425%
0.562%
100µA
0.180%
0.260%
0.240%
0.275%
0.410%
0.360%
0.460%
0.597%
10mA
0.325%
0.405%
0.385%
0.420%
0.555%
0.505%
0.605%
0.742%
20mA
0.425%
N/A
0.485%
0.520%
N/A
0.605%
0.705%
N/A
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LT1460-2.5
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APPLICATIONS INFORMATION
PC Board Layout
In 13- to 16-bit systems where initial accuracy and temperature coefficient calibrations have been done, the mechanical and thermal stress on a PC board (in a cardcage
for instance) can shift the output voltage and mask the true
temperature coefficient of a reference. In addition, the
mechanical stress of being soldered into a PC board can
cause the output voltage to shift from its ideal value.
Surface mount voltage references (MS8 and S8) are the
most susceptible to PC board stress because of the small
amount of plastic used to hold the lead frame.
reference and the leads can exit on the fourth side. This
“tongue” of PC board material can be oriented in the long
direction of the board to further reduce stress transferred
to the reference.
The results of slotting the PC boards of Figures 9a and
9b are shown in Figures 10a and 10b. In this example the
slots can improve the output shift from about 100ppm to
nearly zero.
1
A simple way to improve the stress-related shifts is to
mount the reference near the short edge of the PC board,
or in a corner. The board edge acts as a stress boundary,
or a region where the flexure of the board is minimum. The
package should always be mounted so that the leads
absorb the stress and not the package. The package is
generally aligned with the leads parallel to the long side of
the PC board as shown in Figure 9a.
The most effective technique to improve PC board stress
is to cut slots in the board around the reference to serve as
a strain relief. These slots can be cut on three sides of the
3
4
1460-2.5 F08
Figure 8. Flexure Numbers
OUTPUT DEVIATION (mV)
2
1
LONG DIMENSION
0
–1
0
10
20
40
30
FLEXURE NUMBER
1460-2.5 F09a
Figure 9a. Two Typical LT1460S8-2.5s, Vertical
Orientation Without Slots
2
OUTPUT DEVIATION (mV)
A qualitative technique to evaluate the effect of stress on
voltage references is to solder the part into a PC board and
deform the board a fixed amount as shown in Figure 8. The
flexure #1 represents no displacement, flexure #2 is
concave movement, flexure #3 is relaxation to no displacement and finally, flexure #4 is a convex movement.
This motion is repeated for a number of cycles and the
relative output deviation is noted. The result shown in
Figure 9a is for two LT1460S8-2.5s mounted vertically
and Figure 9b is for two LT1460S8-2.5s mounted horizontally. The parts oriented in Figure 9a impart less stress into
the package because stress is absorbed in the leads.
Figures 9a and 9b show the deviation to be between 125µV
and 250µV and implies a 50ppm and 100ppm change
respectively. This corresponds to a 13- to 14-bit system
and is not a problem for most 10- to 12-bit systems unless
the system has a calibration. In this case, as with temperature hysteresis, this low level can be important and even
more careful techniques are required.
2
1
LONG DIMENSION
0
–1
0
10
20
FLEXURE NUMBER
40
30
1460-2.5 F09b
Figure 9b. Two Typical LT1460S8-2.5s, Horizontal
Orientation Without Slots
8
LT1460-2.5
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APPLICATIONS INFORMATION
2
OUTPUT DEVIATION (mV)
OUTPUT DEVIATION (mV)
2
1
0
SLOT
–1
1
0
SLOT
–1
0
10
20
FLEXURE NUMBER
40
30
1460-2.5 F10a
Figure 10a. Same Two LT1460S8-2.5s in Figure 9a,
but With Slots
0
10
20
FLEXURE NUMBER
40
30
1460-2.5 F10b
Figure 10b. Same Two LT1460S8-2.5s in Figure 9b,
but With Slots
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SI PLIFIED SCHE ATIC
VCC
VOUT
51k
48k
GND
1460-2.5 SS
9
LT1460-2.5
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PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.118 ± 0.004*
(3.00 ± 0.102)
0.040 ± 0.006
(1.02 ± 0.15)
0.007
(0.18)
0.034 ± 0.004
(0.86 ± 0.102)
8
7 6
5
0° – 6° TYP
SEATING
PLANE 0.012
(0.30)
0.0256
REF
(0.65)
TYP
0.021 ± 0.006
(0.53 ± 0.015)
0.006 ± 0.004
(0.15 ± 0.102)
0.118 ± 0.004**
(3.00 ± 0.102)
0.192 ± 0.004
(4.88 ± 0.10)
MSOP (MS8) 1197
1
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
2 3
4
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.300 – 0.325
(7.620 – 8.255)
0.009 – 0.015
(0.229 – 0.381)
(
+0.035
0.325 –0.015
8.255
+0.889
–0.381
)
0.045 – 0.065
(1.143 – 1.651)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
10
0.130 ± 0.005
(3.302 ± 0.127)
0.065
(1.651)
TYP
0.100 ± 0.010
(2.540 ± 0.254)
0.400*
(10.160)
MAX
8
7
6
5
1
2
3
4
0.255 ± 0.015*
(6.477 ± 0.381)
0.125
(3.175) 0.020
MIN (0.508)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
N8 1197
LT1460-2.5
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
7
8
6
5
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
SO8 0996
1
2
3
4
Z Package
3-Lead Plastic TO-92 (Similar to TO-226)
(LTC DWG # 05-08-1410)
0.060 ± 0.005
(1.524± 0.127)
DIA
0.180 ± 0.005
(4.572 ± 0.127)
0.500
(12.70)
MIN
0.180 ± 0.005
(4.572 ± 0.127)
0.060 ± 0.010
(1.524 ± 0.254)
0.90
(2.286)
NOM
0.050 UNCONTROLLED
(1.270) LEAD DIMENSION
MAX
0.140 ± 0.010
(3.556 ± 0.127)
5°
NOM
10° NOM
0.015 ± 0.002
(0.381 ± 0.051)
0.050 ± 0.005
(1.270 ± 0.127)
Z3 (TO-92) 0695
0.016 ± 0.003
(0.406 ± 0.076)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LT1460-2.5
U
TYPICAL APPLICATIONS
Boosted Output Current with No Current Limit
Boosted Output Current with Current Limit
V+ ≥ VOUT + 2.8V
V + ≥ (VOUT + 1.8V)
+
R1
220Ω
D1*
LED
47µF
+
R1
220Ω
8.2Ω
2N2905
2N2905
IN
IN
2.5V
100mA
LT1460-2.5 OUT
GND
47µF
+
2.5V
100mA
LT1460-2.5 OUT
2µF
SOLID
TANT
+
GND
2µF
SOLID
TANT
* GLOWS IN CURRENT LIMIT,
DO NOT OMIT
1460-2.5 TA04
1460-2.5 TA03
Handling Higher Load Currents
5V
40mA
+
47µF
IN
10mA
R1*
63Ω
VOUT
2.5V
LT1460-2.5 OUT
GND
RL
TYPICAL LOAD
CURRENT = 50mA
*SELECT R1 TO DELIVER 80% OF TYPICAL LOAD CURRENT.
LT1460 WILL THEN SOURCE AS NECESSARY TO MAINTAIN
PROPER OUTPUT. DO NOT REMOVE LOAD AS OUTPUT WILL
BE DRIVEN UNREGULATED HIGH. LINE REGULATION IS
DEGRADED IN THIS APPLICATION
1460-2.5 TA05
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1236
Precision Low Noise Reference
0.05% Max, 5ppm/°C Max, SO Package
LT1019
Precision Bandgap Reference
0.05% Max, 5ppm/°C Max
LT1027
Precision 5V Reference
0.02%, 2ppm/°C Max
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
1460fa LT/TP 1298 2K REV A • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 1996