LINER LTC1250C Very low noise zero-drift bridge amplifier Datasheet

LTC1250
Very Low Noise
Zero-Drift Bridge Amplifier
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DESCRIPTIO
FEATURES
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The LTC®1250 is a high performance, very low noise zerodrift operational amplifier. The LTC1250’s combination of
low front-end noise and DC precision makes it ideal for use
with low impedance bridge transducers. The LTC1250
features typical input noise of 0.75µVP-P from 0.1Hz to
10Hz, and 0.2µVP-P from 0.1Hz to 1Hz. The LTC1250 has
DC to 1Hz noise of 0.35µVP-P, surpassing that of low noise
bipolar parts including the OP-07, OP-77, and LT1012.
The LTC1250 uses the industry-standard single op amp
pinout, and requires no external components or nulling
signals, allowing it to be a plug-in replacement for bipolar
op amps.
Very Low Noise: 0.75µVP-P Typ, 0.1Hz to 10Hz
DC to 1Hz Noise Lower Than OP-07
Full Output Swing into 1k Load
Offset Voltage: 10µV Max
Offset Voltage Drift: 50nV/°C Max
Common-Mode Rejection Ratio: 110dB Min
Power Supply Rejection Ratio: 115dB Min
No External Components Required
Pin-Compatible with Standard 8-Pin Op Amps
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APPLICATI
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Electronic Scales
Strain Gauge Amplifiers
Thermocouple Amplifiers
High Resolution Data Acquisition
Low Noise Transducers
Instrumentation Amplifiers
The LTC1250 incorporates an improved output stage
capable of driving 4.3V into a 1k load with a single 5V
supply; it will swing ±4.9V into 5k with ±5V supplies. The
input common mode range includes ground with single
power supply voltages above 12V. Supply current is 3mA
with a ±5V supply, and overload recovery times from
positive and negative saturation are 0.5ms and 1.5ms,
respectively. The internal nulling clock is set at 5kHz for
optimum low frequency noise and offset drift; no external
connections are necessary.
and LTC are registered trademarks and LT is a trademark of Linear Technology Corporation.
The LTC1250 is available in standard 8-pin ceramic and
plastic DIPs, as well as an 8-pin SOIC package.
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TYPICAL APPLICATI
Differential Bridge Amplifier
Input Referred Noise 0.1Hz to 10Hz
2
5V
5V
50Ω
GAIN
TRIM
VS = ±5V
AV = 10k
1000pF
0.1µF
1
µV
18.2k
350Ω
STRAIN
GAUGE
2
LTC1250
3
1000pF
–5V
–
+
0
7
6
AV = 100
–1
4
–2
18.2k
–5V
1250 TA01
0
2
6
4
TIME (s)
8
10
LT1250 TA02
1
LTC1250
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PACKAGE/ORDER I FOR ATIO
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Total Supply Voltage (V + to V –) ............................. 18V
Input Voltage ........................ (V + + 0.3V) to (V – – 0.3V)
Output Short Circuit Duration ......................... Indefinite
Operating Temperature Range
LTC1250M..................................... – 55°C to 125°C
LTC1250C .......................................... 0°C TO 70°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................ 300°C
ORDER PART
NUMBER
TOP VIEW
NC 1
8
NC
–IN 2
7
V+
+IN 3
6
OUT
V– 4
5
NC
N8 PACKAGE
J8 PACKAGE
8-LEAD CERAMIC DIP 8-LEAD PLASTIC DIP
S8 PACKAGE
8-LEAD PLASTIC SOIC
TJMAX = 150°C, θJA = 100°CW (J8)
TJMAX = 110°C, θJA = 130°CW (N8)
TJMAX = 110°C, θJA = 200°CW (S8)
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER
VOS
Input Offset Voltage
∆VOS
Average Input Offset Drift
Long Term Offset Drift
en
Input Noise Voltage (Note 2)
CONDITIONS
TA = 25°C (Note 1)
(Note 1)
in
IB
Input Noise Current
Input Bias Current
IOS
Input Offset Current
TA = 25°C (Note 3)
CMRR
PSRR
AVOL
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large-Signal Voltage Gain
Maximum Output Voltage Swing
VCM = – 4V to 3V
VS = ±2.375V to ±8V
RL = 10k, VOUT = ±4V
RL = 1k
RL = 100k
RL = 10k, CL = 50pF
●
●
fS
Internal Sampling Frequency
LTC1250M
TYP
MAX
±5
±10
±0.01 ±0.05
50
0.75
1.0
0.2
4.0
±50
±150
±950
±100 ±300
±500
110
130
115
130
125
170
±4.0 4.3/–4.7
±4.92
10
1.5
3.0
4.0
7.0
4.75
MIN
●
Slew Rate
Gain-Bandwidth Product
Supply Current
LTC1250MJ8
LTC1250CJ8
LTC1250CN8
LTC1250CS8
S8 PART MARKING
1250
VIN = ±5V, TA = Operating Temperature Range, unless otherwise noted.
TA = 25°C, 0.1Hz to 10Hz
TA = 25°C, 0.1Hz to 1Hz
f = 10Hz
TA = 25°C (Note 3)
SR
GBW
IS
W
AXI U
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ABSOLUTE
●
●
●
●
No Load, TA = 25°C
●
TA = 25°C
MIN
110
115
125
±4.0
LTC1250C
TYP
MAX
±5
±10
±0.01 ±0.05
50
0.75
1.0
0.2
4.0
±50
±200
±450
±100 ±400
±500
130
130
170
4.3 /–4.7
±4.95
10
1.5
3.0
4.0
5.0
4.75
UNITS
µV
µV/°C
nV/√Mo
µVP-P
µVP-P
fA/√Hz
pA
pA
pA
pA
dB
dB
dB
V
V
V/µs
MHz
mA
mA
kHz
LTC1250C
TYP
MAX
±2
±5
±0.01 ±0.05
1.0
0.3
±20
±100
±40
±200
UNITS
µV
µV/°C
µVP-P
µVP-P
pA
pA
VIN = 5V, TA = Operating Temperature Range, unless otherwise noted.
SYMBOL
VOS
∆VOS
en
PARAMETER
Input Offset Voltage
Average Input Offset Drift
Input Noise Voltage (Note 2)
IB
IOS
Input Bias Current
Input Offset Current
2
CONDITIONS
TA = 25°C (Note 1)
(Note 1)
TA = 25°C, 0.1Hz to 10Hz
TA = 25°C, 0.1Hz to 1Hz
TA = 25°C (Note 3)
TA = 25°C (Note 3)
MIN
●
LTC1250M
TYP
MAX
±2
±5
±0.01 ±0.05
1.0
0.3
±20
±100
±40
±200
MIN
LTC1250
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER
Maximum Output Voltage Swing
IS
fS
VIN = 5V, TA = Operating Temperature Range, unless otherwise noted.
CONDITIONS
RL = 1k
RL = 100k
TA = 25°C
TA = 25°C
Supply Current
Sampling Frequency
MIN
4.0
The ● denotes specifications which apply over the full operating
temperature range.
Note 1: These parametes are guaranteed by design. Thermocouple effects
preclude measurement of these voltage levels during automated testing.
Note 2: 0.1Hz to 10Hz noise is specified DC coupled in a 10s window;
0.1Hz to 1Hz noise is specified in a 100s window with an RC high-pass
LTC1250M
TYP
MAX
4.3
4.95
1.8
2.5
3
MIN
4.0
LTC1250C
TYP
MAX
4.3
4.95
1.8
2.5
3
UNITS
V
V
mA
kHz
filter at 0.1Hz. The LTC1250 is sample tested for noise; for 100% tested
parts contact LTC Marketing Dept.
Note 3: At T ≤ 0°C these parameters are guaranteed by design and not
tested.
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TYPICAL PERFOR A CE CHARACTERISTICS
Input Noise vs Supply Voltage
6
4.0
1.6
1.2
3.0
1.0
0.1Hz TO 10Hz
0.6
0.4
SAMPLING FREQUENCY (kHz)
3.5
SUPPLY CURRENT (mA)
1.4
0.8
TA = 25°C
TA = 25°C
TA = 25°C
INPUT NOISE (µVP-P)
Sampling Frequency vs Supply
Voltage
Supply Current vs Supply Voltage
2.5
2.0
1.5
1.0
0.1Hz TO 1Hz
4
3
0.5
0.2
2
0
0
4
10
6
8
12
14
TOTAL SUPPLY VOLTAGE, V + TO V – (V)
4
16
10
6
8
12
14
TOTAL SUPPLY VOLTAGE, V + TO V – (V)
4
16
Input Noise vs Temperature
16
LTC1250 G03
Sampling Frequency vs
Temperature
Supply Current vs Temperature
4.5
1.2
8
VS = ±5V
VS = ±5V
VS = ±5V
7
1.0
0.1Hz TO 10Hz
0.6
0.4
0.1Hz TO 1Hz
SAMPLING FREQUENCY (kHz)
SUPPLY CURRENT (mA)
4.0
0.8
3.5
3.0
2.5
0.2
0
–50 –25
10
6
8
12
14
TOTAL SUPPLY VOLTAGE, V + TO V – (V)
LTC1250 G02
LTC1250 G01
INPUT NOISE (µVP-P)
5
6
5
4
3
2
1
50
25
75
0
TEMPERATURE (°C)
100
125
LTC1250 G04
2.0
–50 –25
50
25
0
75
TEMPERATURE (°C)
100
125
LTC1250 G05
0
–50 –25
75
50
25
TEMPERATURE (°C)
0
100
150
LTC1250 G06
3
LTC1250
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TYPICAL PERFOR A CE CHARACTERISTICS
Voltage Noise vs Frequency
80
100
80
80
60
GAIN (dB)
50
40
30
GAIN
40
40
PHASE:
RL = 1k
20
VS = ±5V OR
SINGLE 5V
TA = 25°C
CL = 100pF
20
0
10
0
100
1k
FREQUENCY (Hz)
10k
10k
1k
20
–20
10M
100k
1M
FREQUENCY (Hz)
LTC1250 G11
10
–50
Common-Mode Rejection Ratio
vs Frequency
Common-Mode Input Range
vs Supply Voltage
140
–5
500µs/DIV
AV = 100, RL = 100k, CL = 50pF, VS = ±5V
6
120
4
100
2
CMRR (dB)
INPUT COMMON MODE RANGE (V)
INPUT (V)
OUTPUT (V)
VS = ±5V
VCM = 1VRMS
TA = 25°C
0
0
–2
80
60
40
–4
20
–6
0
–8
5
4
6
SUPPLY VOLTAGE (±V)
3
2
8
7
1
10
100
1k
FREQUENCY (Hz)
10k
Output Swing vs Load
Resistance, Dual Supplies
Output Voltage Swing vs Load
Resistance, Single Supply
18
10
RL TO GND
9
OUTPUT SWING (V)
OUTPUT SWING (±V)
2V/DIV
14
7
6
VS = ±5V
5
4
VS = ±2.5V
3
2
0
NEGATIVE SWING
POSITIVE SWING
VS = 10V
10
8
6
VS = 5V
V – = GND
RL TO GND
2
0
0
1
2
3 4 5 6 7 8
LOAD RESISTANCE (kΩ)
9
10
LTC1250 G08
4
12
4
1
AV = 1, RL = 100k, CL = 50pF, VS = ±5V
VS = 16V
16
VS = ±8V
8
1µs/DIV
100k
LTC1250 G12
LTC1250 G07
Transient Response
125
100
LTC1250 G14
8
0
50
75
0
25
TEMPERATURE (°C)
–25
LTC1250 G10
Overload Recovery
0.2
100
0
–20
10
60
PHASE:
RL = 100k
BIAS CURRENT (|pA|)
60
1
1000
VS = ±5V
PHASE MARGIN (DEG)
VOLTAGE NOISE (nV/√Hz)
100
VS = ±5V
RS = 10Ω
70
Bias Current (Magnitude) vs
Temperature
Gain/Phase vs Frequency
0
1
2
3 4 5 6 7 8
LOAD RESISTANCE (kΩ)
9
10
LTC1250 G09
LTC1250
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TYPICAL PERFOR A CE CHARACTERISTICS
Output Swing vs Output Current,
±5V Supply
Output Swing vs Output Current,
Single 5V Supply
6
5
40
VS = SINGLE 5V
VS = ±5V
4
OUTPUT VOLTAGE (V)
2
1
0
–1
–2
–3
SHORT-CIRCUIT CURRENT (mA)
5
3
OUTPUT VOLTAGE (V)
Short-Circuit Current
vs Temperature
4
3
2
1
0.1
1
OUTPUT CURRENT (mA)
0
0.01
10
VOUT = V –
20
10
0
–10
–20
VOUT = V +
–30
–4
–5
0.01
VS = ±15V
30
0.1
1
OUTPUT CURRENT (mA)
–40
–50 –25
10
0
50
25
75
TEMPERATURE (°C)
LTC1250 G17
LTC1250 G16
100
125
LTC1250 G18
TEST CIRCUITS
DC to 10Hz Noise Test Circuit
(for DC to 1Hz Multiply All Capacitor Values by 10)
Offset Test Circuit
100pF
100pF
100k
100k
2
5V
7
–
6
LTC1250
+
OUTPUT
3
4
7
2
+
–5V
6
800k
4
0.02µF
–5V
3
–
8
0.04µF
6
800k
5
–
1/2
LT1057
1
1/2
LT1057
800k
+4
7
OUTPUT
+
0.01µF
–5V
1250 TC01
1250 TC02
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APPLICATI
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3
–
LTC1250
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10Ω
10Ω
U
2
5V
5V
S I FOR ATIO
80
Input Noise
OP-27
VOLTAGE NOISE (nV/√Hz)
The LTC1250, like all CMOS amplifiers, exhibits two types
of low frequency noise: thermal noise and 1/f noise. The
LTC1250 uses several design modifications to minimize
these noise sources. Thermal noise is minimized by raising the gM of the front-end transistors by running them at
high bias levels and using large transistor geometries. 1/f
noise is combated by optimizing the zero-drift nulling loop
to run at twice the 1/f corner frequency, allowing it to
reduce the inherently high CMOS 1/f noise to near thermal
levels at low frequencies. The resultant noise spectrum is
quite low at frequencies below the internal 5kHz clock
70
OP-07
VS = ±5V
RS = 10Ω
60
50
40
LTC1250
30
20
10
0
0.01
0.1
FREQUENCY (Hz)
1
LTC1250 F01
Figure 1. Voltage Noise vs Frequency
5
LTC1250
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APPLICATI
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frequency, approaching the best bipolar op amps at 10Hz
and surpassing them below 1Hz (Figure 1). All this is
accomplished in an industry-standard pinout; the LTC1250
requires no external capacitors, no nulling or clock signals, and conforms to industry-standard 8-pin DIP and 8pin SOIC packages.
Input Capacitance and Compensation
The large input transistors create a parasitic 55pF capacitance from each input to V +. This input capacitance will
react with the external feedback resistors to form a pole
which can affect amplifier stability. In low gain, high
impedance configurations, the pole can land below the
unity-gain frequency of the feedback network and degrade
phase margin, causing ringing, oscillation, and other
unpleasantness. This is true of any op amp, however, the
55pF capacitance at the LTC1250’s inputs can affect
stability with a feedback network impedance as low as
1.9k. This effect can be eliminated by adding a capacitor
across the feedback resistor, adding a zero which cancels
the input pole (Figure 2). The value of this capacitor should
be:
55pF
CF ≥
AV
where AV = closed-loop gain. Note that CF is not dependent
on the value of RF. Circuits with higher gain (AV > 50) or
low loop impedance should not require CF for stability.
CF
RF
RIN
CP
–
fully cancel the 1/f noise spectrum and the low frequency
noise of the part will rise. If the loop is underdamped (large
RF, no CF) it will ring for more than 150µs and the noise
and offset will suffer.
The solution is to add CF as above but beware! Too large
a value of CF will overdamp the loop, again preventing it
from reaching a final value by the 150µs deadline. This
condition doesn’t affect the LTC1250’s offset or output
stability, but 1/f noise begins to rise. As a rule of thumb,
the RFCF feedback pole should be ≥ 7kHz (1/150µs, the
frequency at which the loop settles) for best 1/f performance; values between 100pF and 500pF work well with
feedback resistors below 100k. This ensures adequate
gain at 7kHz for the LTC1250 to properly null. High value
feedback resistors (above 1M) may require experimentation to find the correct value because parasitics, both in
the LTC1250 and on the PC board, play an increasing role.
Low value resistors (below 5k) may not require a capacitor at all.
Input Bias Current
The inputs of the LTC1250, like all zero-drift op amps,
draw only small switching spikes of AC bias current; DC
leakage current is negligible except at very high temperatures. The large front-end transistors cause switching
spikes 3 to 4 times greater than standard zero-drift op
amps: the ±50pA bias current spec is still many times
better than most bipolar parts. The spikes don’t match
from one input pin to the other, and are sometimes (but
not always) of opposite polarity. As a result, matching the
impedances at the inputs (Figure 3) will not cancel the bias
current, and may cause additional errors. Don’t do it.
LTC1250
+
RF
1250 F02
RIN
Figure 2. CF Cancels Phase Shift Due to Parasitic CP
Larger values of CF, commonly used in band-limited DC
circuits, may actually increase low frequency noise. The
nulling circuitry in the LTC1250 closes a loop that includes
the external feedback network during part of its cycle. This
loop must settle to its final value within 150µs or it will not
6
–
LTC1250
+
1250 F03
Figure 3. Extra Resistor Will Not Cancel Bias Current Errors
LTC1250
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APPLICATI
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Output Drive
The LTC1250 includes an enhanced output stage which
provides nearly symmetrical output source/sink currents.
This output is capable of swinging a minimum of ±4V into a
1k load with ±5V supplies, and can sink or source >20mA
into low impedance loads. Lightly loaded (RL ≥100k), the
LTC1250 will swing to within millivolts of either rail. In single
supply applications, it will typically swing 4.3V into a 1k load
with a 5V supply.
the previous page). Applications which require spike-free
output in addition to minimum noise will need a low-pass
filter after the LTC1250; a simple RC will usually do the job
(Figure 4). The LTC1051/LTC1053 data sheet includes more
information about zero-drift amplifier sampling behavior.
CF
RF
–
47k
Minimizing External Errors
LTC1250
+
The input noise, offset voltage, and bias current specs for the
LTC1250 are all well below the levels of circuit board
parasitics. Thermocouples between the copper pins of the
LTC1250 and the tin/lead solder used to connect them can
overwhelm the offset voltage of the LTC1250, especially if a
soldering iron has been around recently. Note also that when
the LTC1250’s output is heavily loaded, the chip may
dissipate substantial power, raising the temperature of the
package and aggravating thermocouples at the inputs.
Although the LTC1250 will maintain its specified accuracy
under these conditions, care must be taken in the layout to
prevent or compensate circuit errors. Be especially careful
of air currents when measuring low frequency noise; nearby
moving objects (like people) can create very large noise
peaks with an unshielded circuit board. For more detailed
explanations and advice on how to avoid these errors, see
the LTC1051/LTC1053 data sheet.
Sampling Behavior
The LTC1250’s zero-drift nulling loop samples the input at
≈ 5kHz, allowing it to process signals below 2kHz with no
aliasing. Signals above this frequency may show aliasing
behavior, although wideband internal circuitry generally
keeps errors to a minimum. The output of the LTC1250 will
have small spikes at the clock frequency and its harmonics;
these will vary in amplitude with different feedback configurations. Low frequency or band-limited systems should not
be affected, but systems with higher bandwidth
(oversampling A/Ds, for example) may need to filter out
these clock artifacts. Output spikes can be minimized with a
large feedback capacitor, but this will adversely affect noise
performance (see Input Capacitance and Compensation on
0.01
1250 F04
Figure 4. RC Output Pole Limits Bandwidth to 330Hz
Single Supply Operation
The LTC1250 will operate with single supply voltages as low
as 4.5V, and the output swings to within millivolts of either
supply when lightly loaded. The input stage will common
mode to within 250mV of ground with a single 5V supply,
and will common mode to ground with single supplies
above 11V. Most bridge transducers bias their inputs above
ground when powered from single supplies, allowing them
to interface directly to the LTC1250 in single supply applications. Single-ended, ground-referenced signals will need to
be level shifted slightly to interface to the LTC1250’s inputs.
Fault Conditions
The LTC1250 is designed to withstand most external fault
conditions without latch-up or damage. However, unusually
severe fault conditions can destroy the part. All pins are
protected against faults of ±25mA or 5V beyond either
supply, whichever comes first. If the external circuitry can
exceed these limits, series resistors or voltage clamp diodes
should be included to prevent damage.
The LTC1250 includes internal protection against ESD damage. All data sheet parameters are maintained to 1kV ESD on
any pin; beyond 1kV, the input bias and offset currents will
increase, but the remaining specs are unaffected and the
part remains functional to 5kV at the input pins and 8kV at the
output pin. Extreme ESD conditions should be guarded
against by using standard anti-static precautions.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
7
LTC1250
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TYPICAL APPLICATI
S
Differential Thermocouple Ampliifer
Reference Buffer
15V
3
3
1
7
+
–
R1
10k
0.1%
6
LTC1250
2
LM399
5V
2
4
7
–
6
LTC1250
3
4
R3
1M
0.1%
C1
100pF
7.5k
2
+
–
–5V
R4
1M
0.1%
VCM
R6
7.5k
1%
4
R2
10k
0.1%
TYPE K †
±10ppm ERROR AT ±15mA
1µVP-P OUTPUT NOISE
2.5µV/°C DRIFT (DUE TO LM399)
+
VOUT
100mV/°C
R7
500Ω
FULL-SCALE TRIM
C2
100pF
1250 TA03
5V
R8
5k
1%
R5
3k
VIN
10mV/°C
VOUT
LT1025
R9
33k
GND
†
FOR BEST ACCURACY, THERMOCOUPLE
RESISTANCE SHOULD BE LESS THAN 100Ω
–5V
1250 TA04
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PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
J8 Package 8-Lead Ceramic DIP
CORNER LEADS OPTION
(4 PLCS)
0.005
(0.127)
MIN
0.023 – 0.045
(0.584 – 1.143)
HALF LEAD
OPTION
0.045 – 0.068
(1.143 – 1.727)
FULL LEAD
OPTION
N8 Package 8-Lead Plastic DIP
0.400*
(10.160)
MAX
0.405
(10.287)
MAX
8
7
6
5
0.025
(0.635)
RAD TYP
2
3
4
0.200
(5.080)
MAX
0.300 – 0.325
(7.620 – 8.255)
0° – 15°
0.385 ± 0.025
(9.779 ± 0.635)
(
0.125
3.175
0.100 ± 0.010 MIN
(2.540 ± 0.254)
0.014 – 0.026
(0.360 – 0.660)
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS.
+0.025
0.325 –0.015
+0.635
8.255
–0.381
0.008 – 0.010
(0.203 – 0.254)
0.053 – 0.069
(1.346 – 1.752)
0.014 – 0.019
(0.355 – 0.483)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm).
)
3
4
0.130 ± 0.005
(3.302 ± 0.127)
0.125
(3.175)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
0.015
(0.380)
MIN
N8 0694
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTURSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm).
0.189 – 0.197*
(4.801 – 5.004)
8
Linear Technology Corporation
7
6
5
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
BSC
0.150 – 0.157*
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
8
2
J8 0694
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
1
0.045 ± 0.015
(1.143 ± 0.381)
S8 Package 8-Lead Plastic SOIC
0.010 – 0.020
× 45°
(0.254 – 0.508)
5
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
0.045 – 0.068
(1.143 – 1.727)
6
0.045 – 0.065
(1.143 – 1.651)
0.015 – 0.060
(0.381 – 1.524)
0.008 – 0.018
(0.203 – 0.457)
7
0.255 ± 0.015*
(6.477 ± 0.381)
0.220 – 0.310
(5.588 – 7.874)
1
0.300 BSC
(0.762 BSC)
8
2
3
4
SO8 0294
LT/GP 0894 2K REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977
 LINEAR TECHNOLOGY CORPORATION 1994