LINER LTC1293DCN Single chip 12-bit data acquisition system Datasheet

LTC1293/LTC1294/LTC1296
Single Chip 12-Bit
Data Acquisition System
U
DESCRIPTIO
FEATURES
■
■
■
■
■
■
Software Programmable Features
Unipolar/Bipolar Conversion
Differential/Single Ended Inputs
MSB-First or MSB/LSB Data Sequence
Power Shutdown
Built-In Sample and Hold
Single Supply 5V or ±5V Operation
Direct 4-Wire Interface to Most MPU Serial
Ports and All MPU Parallel Ports
46.5kHz Maximum Throughput Rate
System Shutdown Output (LTC1296)
The LTC1293/4/6 is a family of data acquisition systems
which contain a serial I/O successive approximation A/D
converter. It uses LTCMOSTM switched capacitor technology to perform either 12-bit unipolar, or 11-bit plus sign
bipolar A/D conversions. The input multiplexer can be
configured for either single ended or differential inputs (or
combinations thereof). An on-chip sample and hold is
included for all single ended input channels. When the
LTC1293/4/6 is idle it can be powered down in applications where low power consumption is desired. The
LTC1296 includes a System Shutdown Output pin which
can be used to power down external circuitry, such as
signal conditioning circuitry prior to the input mux.
U
KEY SPECIFICATIO S
■
■
■
The serial I/O is designed to communicate without external
hardware to most MPU serial ports and all MPU parallel
I/O ports allowing up to eight channels of data to be
transmitted over as few as three wires.
Resolution: 12 Bits
Fast Conversion Time: 12µs Max Over Temp
Low Supply Current: 6.0mA
LTCMOSTM is a trademark of Linear Technology Corporation
UO
TYPICAL APPLICATI
12-Bit Data Acquisition System with Power Shutdown
RB
5.1k
2N3906
R2
1.2M
+
R1
10k
350Ω STRAIN
GAUGE BRIDGE
CH0
VCC
1/4 LT1014
CH1
SSO
–
CH2
CLK
CH3
CS
R2
1.2M
CH4
DOUT
C2
1µF
CH6
REF+
CH7
REF –
COM
AGND
THREE ADDITIONAL STRAIN GAUGE INPUTS
CAN BE ACCOMMODATED USING THE OTHER
AMPLIFIERS IN THE LT1014
CH5
DGND
74HC04
+5V
47µF
MPU
LTC1296
1N4148
DIN
V–
LTC1293 TA01
129346fs
1
LTC1293/LTC1294/LTC1296
W W
W
AXI U
U
ABSOLUTE
RATI GS (Notes 1 and 2)
Supply Voltage (VCC) to GND or V – ......................... 12V
Negative Supply Voltage (V –) ..................... –6V to GND
Voltage
Analog and Reference
Inputs ............................ (V –) –0.3V to VCC + 0.3V
Digital Inputs ......................................... –0.3V to 12V
Digital Outputs .......................... –0.3V to VCC + 0.3V
U
W
U
PACKAGE/ORDER I FOR ATIO
CH0
1
16 VCC
CH1
2
15 CLK
CH2
3
14 CS
CH3
4
13 DOUT
CH4
5
12 DIN
ORDER PART
NUMBER
LTC1293BCSW
LTC1293CCSW
LTC1293DCSW
Power Dissipation ............................................. 500mW
Operating Temperature Range
LTC1293/4/6BC, LTC1293/4/6CC,
LTC1293/4/6DC ....................................... 0°C to 70°C
LTC1296BI, LTC1296CI, LTC1296DI ... –40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................ 300°C
(Top Views) Consult factory for Industrial and Military grades.
CH0
1
16 VCC
CH1
2
15 CLK
CH2
3
14 CS
CH3
4
13 DOUT
CH4
5
12 DIN
CH5
6
11 VREF
CH5
6
11 VREF
COM
7
10 AGND
COM
7
10 AGND
DGND
8
9
V–
DGND
8
9
SW PACKAGE, 16-LEAD PLASTIC SO WIDE
TJMAX = 110°C, θJA = 150°C/ W
CH0
1
20 DVCC
CH1
2
19 AVCC
CH2
3
18 CLK
CH3
4
17 CS
CH4
5
16 DOUT
CH5
6
15 DIN
CH6
7
14 REF +
CH7
8
13 REF –
COM
9
12 AGND
DGND 10
LTC1294BCSW
LTC1294CCSW
LTC1294DCSW
V–
CH0
1
20 DVCC
CH1
2
19 AVCC
CH2
3
18 CLK
CH3
4
17 CS
CH4
5
16 DOUT
CH5
6
15 DIN
CH6
7
14 REF+
CH7
8
13 REF –
COM
9
12 AGND
DGND 10
11 V –
J PACKAGE, 20-LEAD CERDIP
TJMAX = 150°C, θJA = 80°C/ W (J)
OBSOLETE PACKAGE
Consider the N Package for Alternate Source
20 VCC
CH1
2
19 SSO
CH2
3
18 CLK
CH3
4
17 CS
CH4
5
16 DOUT
CH5
6
15 DIN
CH6
7
14 REF +
CH7
8
13 REF –
COM
9
12 AGND
DGND 10
11 V –
SW PACKAGE, 20-LEAD PLASTIC SO WIDE
TJMAX = 110°C, θJA = 150°C/ W
LTC1294BCN
LTC1294CCN
LTC1294DCN
N PACKAGE, 20-LEAD PDIP
TJMAX = 110°C, θJA = 100°C/ W (N)
SW PACKAGE, 20-LEAD PLASTIC SO WIDE
TJMAX = 110°C, θJA = 150°C/ W
1
LTC1293BCN
LTC1293CCN
LTC1293DCN
N PACKAGE, 16-LEAD PDIP
TJMAX = 110°C, θJA = 100°C/ W (N)
11 V –
CH0
ORDER PART
NUMBER
LTC1296BCSW
LTC1296CCSW
LTC1296DCSW
LTC1296BISW
LTC1296CISW
LTC1296DISW
CH0
1
20 VCC
CH1
2
19 SSO
CH2
3
18 CLK
CH3
4
17 CS
CH4
5
16 DOUT
CH5
6
15 DIN
CH6
7
14 REF +
CH7
8
13 REF –
COM
9
12 AGND
DGND 10
LTC1294BCJ
LTC1294CCJ
LTC1294DCJ
LTC1296BIN
LTC1296CIN
LTC1296DIN
LTC1296BCN
LTC1296CCN
LTC1296DCN
11 V –
N PACKAGE, 20-LEAD PDIP
TJMAX = 110°C, θJA = 100°C/ W (N)
J PACKAGE, 20-LEAD CERDIP
TJMAX = 150°C, θJA = 80°C/ W (J)
OBSOLETE PACKAGE
Consider the N Package for Alternate Source
LTC1296BCJ
LTC1296CCJ
LTC1296DCJ
129346fs
2
LTC1293/LTC1294/LTC1296
W U
U
CO VERTER A D
ULTIPLEXER CHARACTERISTICS
PARAMETER
CONDITIONS
TYP MAX
UNITS
Offset Error
(Note 4)
●
±3.0
±3.0
±3.0
LSB
Linearity Error (INL)
(Notes 4, 5)
●
±0.5
±0.5
±0.75
LSB
Gain Error
(Note 4)
●
±0.5
±1.0
±4.0
LSB
●
12
12
12
Bits
LTC1293/4/6B
Minimum Resolution for which No
Missing Codes are Guaranteed
MIN
TYP MAX
(Note 3)
LTC1293/4/6C
MIN
TYP MAX
LTC1293/4/6D
MIN
(V –)–0.05V to VCC + 0.05V
Analog and REF Input Range
(Note 7)
On Channel Leakage Current (Note 8)
On Channel = 5V
Off Channel = 0V
●
±1
±1
±1
µA
On Channel = 0V
Off Channel = 5V
●
±1
±1
±1
µA
On Channel = 5V
Off Channel = 0V
●
±1
±1
±1
µA
On Channel = 0V
Off Channel = 5V
●
±1
±1
±1
µA
Off Channel Lekage Current (Note 8)
V
AC CHARACTERISTICS (Note 3)
SYMBOL
PARAMETER
CONDITIONS
LTC1293/4/6B
LTC1293/4/6C
LTC1293/4/6D
MIN
TYP
MAX
fCLK
Clock Frequency
VCC = 5V (Note 6)
0.1
tSMPL
Analog Input Sample Time
See Operating Sequence
2.5
CLK Cycles
tCONV
Conversion Time
See Operating Sequence
12
CLK Cycles
tCYC
Total Cycle Time
See Operating Sequence (Note 6)
tdDO
Delay Time, CLK↓ to DOUT Data Valid
See Test Circuits
●
160
300
ns
tdis
Delay Time, CS↑ to DOUT Hi-Z
See Test Circuits
●
80
150
ns
ten
Delay Time, CLK↓ to DOUT Enabled
See Test Circuits
●
80
200
ns
thDI
Hold Time, DIN after CLK↑
VCC = 5V (Note 6)
thDO
Time Output Data Remains Valid After CLK↓
tf
DOUT Fall Time
tr
tWHCLK
1.0
21 CLK
+500ns
UNITS
MHz
Cycles
50
ns
130
ns
See Test Circuits
●
DOUT Rise Time
See Test Circuits
●
CLK High Time
VCC = 5V (Note 6)
300
ns
tWLCLK
CLK Low Time
VCC = 5V (Note 6)
400
ns
tsuDI
Set-up Time, DIN Stable Before CLK↑
VCC = 5V (Note 6)
50
ns
tsuCS
Set-up Time, CS↓ before CLK↑
VCC = 5V (Note 6)
50
ns
twHCS
CS High Time During Conversion
VCC = 5V (Note 6)
500
ns
twLCS
CS Low Time During Data Transfer
VCC = 5V (Note 6)
21
CLK Cycles
tenSSO
Delay Time, CLK↓ to SSO↓
See Test Circuits
●
tdisSSO
Delay Time, CS↓ to SSO↑
See Test Circuits
●
CIN
Input Capacitance
Analog Inputs On Channel
Analog Inputs Off Channel
Digital Inputs
65
130
25
50
750
1500
250
500
100
5
5
ns
ns
ns
ns
pF
129346fs
3
LTC1293/LTC1294/LTC1296
U
DIGITAL A D DC ELECTRICAL CHARACTERISTICS (Note 3)
LTC1293/4/6B
LTC1293/4/6C
LTC1293/4/6D
MIN
TYP
MAX
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage
VCC = 5.25V
●
VIL
Low Level Input Voltage
VCC = 4.75V
●
0.8
V
IIH
High Level Input Current
VIN = VCC
●
2.5
µA
IIL
Low Level Input Current
VIN = 0V
●
–2.5
µA
VOH
High Level Output Voltage
VCC = 4.75V, IO = –10mA
IO = 360µA
●
2.0
2.4
UNITS
V
4.7
4.0
V
VOL
Low Level Output Voltage
VCC = 4.75V, IO = 1.6mA
●
0.4
V
IOZ
High Z Output Leakage
VOUT = VCC, CS High
VOUT = 0V, CS High
●
●
3
–3
µA
ISOURCE
Output Source Current
VOUT = 0V
–20
mA
ISINK
Output Sink Current
VOUT = VCC
20
mA
ICC
Positive Supply Current
CS High
ICC
Positive Supply Current
CS High,
Power
Shutdown
CLK Off
IREF
I
–
●
6
12
mA
LTC1294BC, LTC1294CC,
LTC1294DC, LTC1294BI,
LTC1294CI, LTC1294DI,
●
5
10
µA
LTC1294BM, LTC1294CM,
LTC1294DM
●
5
15
µA
Reference Current
CS High
●
10
50
µA
Negative Supply Current
CS High
●
1
50
µA
ISOURCEs
SSO Source Current
VSSO = 0V
●
0.8
1.5
mA
ISINKs
SSO Sink Current
VSSO = VCC
●
0.5
1.0
mA
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to DGND, AGND and REF – wired
together (unless otherwise noted).
Note 3: VCC = 5V, VREF+ = 5V, VREF– = 0V, V – = 0V for unipolar mode and
–5V for bipolar mode, CLK = 1.0MHz unless otherwise specified. The ●
denotes specifications which apply over the full operating temperature
range; all other limits and typicals TA = 25°C.
Note 4: These specs apply for both unipolar and bipolar modes. In bipolar
mode, one LSB is equal to the bipolar input span (2VREF) divided by 4096.
For example, when VREF = 5V, 1LSB (bipolar) = 2 (5V)/4096 = 2.44mV.
Note 5: Linearity error is specified between the actual end points of the A/
D transfer curve. The deviation is measured from the center of the
quantization band.
Note 6: Recommended operating conditions.
Note 7: Two on-chip diodes are tied to each reference and analog input
which will conduct for reference or analog input voltages one diode drop
below V – or one diode drop above VCC. Be careful during testing at low
VCC levels (4.5V), as high level reference or analog inputs (5V) can cause
this input diode to conduct, especially at elevated temperatures, and cause
errors for inputs near full scale. This spec allows 50mV forward bias of
either diode. This means that as long as the reference or analog input
does not exceed the supply voltage by more than 50mV, the output code
will be correct. To achieve an absolute 0V to 5V input voltage range will
therefore require a minimum supply voltage of 4.950V over initial
tolerance, temperature variations and loading.
Note 8: Channel leakage current is measured after the channel selection.
129346fs
4
LTC1293/LTC1294/LTC1296
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Supply Voltage
Unadjusted Offset Voltage vs
Reference Voltage
Supply Current vs Temperature
10
CLK = 1MHz
TA = 25°C
0.9
VCC = 5V
CLK = 1MHz
VCC = 5V
9
0.8
OFFSET (LSB = 1/4096 × VREF)
10
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
8
6
4
8
7
6
5
2
5
4
6
SUPPLY VOLTAGE (V)
0.1
Change in Gain vs Reference
Voltage
0.75
0.50
0.25
VCC = 5V
–0.2
–0.4
LTC1294/6
–0.6
–0.8
–1.0
LTC1293
0
5
1
2
3
4
REFERENCE VOLTAGE (V)
0.3
0.2
0.1
0
–50
5
–25
25
50
75 100
0
AMBIENT TEMPERATURE (°C)
125
LTC1293 G06
Minimum Clock Rate for 0.1LSB
Error
0.5
VCC = 5V
VREF = 5V
CLK = 1MHz
MAGNITUDE OF GAIN CHANGE (LSB)
MAGNITUDE OF LINEARITY CHANGE (LSB)
0.4
Change in Gain vs Temperature
0.5
0.3
0.2
0.1
0
–50
VCC = 5V
VREF = 5V
CLK = 1MHz
LTC1293 G05
LTC1293 G04
Change in Linearity vs
Temperature
5
Change in Offset vs Temperature
–1.2
0.4
3
2
4
REFERENCE VOLTAGE (V)
1
0.5
MAGNITUDE OF OFFSET CHANGE (LSB)
CHANGE IN GAIN (LSB = 1/4096 × VREF)
CHANGE IN LINEARITY (LSB = 1/4096 × VREF)
1.00
VOS = 0.125mV
LTC1293 G03
0
3
4
2
REFERENCE VOLTAGE (V)
VOS = 0.250mV
0.3
LTC1293 G02
1.25
1
0.4
3
–50 –30 –10 10 30 50 70 90 110 130
AMBIENT TEMPERATURE (°C)
Change in Linearity vs Reference
Voltage
0
0.5
0.2
LTC1293 G01
0
0.6
4
–25
25
50
75 100
0
AMBIENT TEMPERATURE (°C)
125
LTC1293 G07
0.4
VCC = 5V
VREF = 5V
CLK = 1MHz
VCC = 5V
MINIMUM CLK FREQUENCY* (MHz)
0
0.7
0.3
0.2
0.1
0
–50
–25
25
50
75 100
0
AMBIENT TEMPERATURE (°C)
125
LTC1293 G08
0.25
0.20
0.15
0.10
0.05
–50
–25
25
50
75 100
0
AMBIENT TEMPERATURE (°C)
125
LTC1293 G09
* AS THE CLK FREQUENCY IS DECREASED FROM 1MHz, MINIMUM CLK FREQUENCY (∆ERROR ≤ 0.1LSB) REPRESENTS
THE FREQUENCY AT WHICH A 0.1LSB SHIFT IN ANY CODE TRANSITION FROM ITS 1MHz VALUE IS FIRST DETECTED.
129346fs
5
LTC1293/LTC1294/LTC1296
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Maximum Clock Rate vs Source
Resistance
10k
1.0
250
VCC = 5V
VREF = 5V
CLK = 1MHz
MAXIMUM CLK FREQUENCY* (MHz)
MSB FIRST DATA
150
LSB FIRST DATA
100
50
0
–50
–25
25
50
75 100
0
AMBIENT TEMPERATURE (°C)
0.8
+VIN
0.6
RSOURCE–
1k
10k
RSOURCE – (Ω)
RSOURCE+
+
–
1
100
1000
RSOURCE+ (Ω)
10
10
LTC1293 G12
Noise Error vs Reference Voltage
2.25
900
GUARANTEED
800
700
600
500
400
300
200
ON CHANNEL
OFF CHANNEL
100
0
–50 –30 –10 10 30 50 70 90 110 130
AMBIENT TEMPERATURE (°C)
10000
LTC1292 G13
LTC1293 G14
LTC1296 SSO Source Current vs
VCC – VSSO
10k
100
1k
CYCLE TIME (µs)
LTC1293 G11
INPUT CHANNEL LEAKAGE CURRENT (nA)
S & H AQUISITION TIME TO 0.02% (µs)
VIN
+
100
100k
1000
10
CFILTER ≥1µF
–
Input Channel leakage Current vs
Temperature
VREF = 5V
VCC = 5V
TA = 25°C
0V TO 5V INPUT STEP
RFILTER
1
0
100
125
100
+VIN
1k
0.2
Sample and Hold Acquisition
Time vs Source Resistance
LTC1293/4/6 NOISE = 200µVp-p
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
0
1
5
4
3
2
REFERENCE VOLTAGE (V)
LTC1293 G15
LTC1296 SSO Sink Current vs
VSSO
500
* MAXIMUM CLK FREQUENCY REPRESENTS THE CLK
FREQUENCY AT WHICH A 0.1LSB SHIFT IN THE ERROR
AT ANY CODE TRANSITION FROM ITS 1MHz VALUE IS
FIRST DETECTED.
500
VCC = 5V
VCC = 5V
400
400
300
ISINK (µA)
ISOURCE (µA)
– –IN
0.4
LTC1293 G10
200
** MAXIMUM RFILTER REPRESENTS THE FILTER RESISTOR
VALUE AT WHICH A 0.1LSB CHANGE IN FULL SCALE ERROR
FROM ITS VALUE AT RFILTER = 0Ω IS FIRST DETECTED.
300
200
100
100
0
+ +IN
PEAK-TO-PEAK NOISE ERROR (LSB)
DOUT DELAY TIME FROM CLK↓ (ns)
VCC = 5V
200
Maximum Filter Resistor vs Cycle
Time
MAXIMUM RFILTER** (Ω)
DOUT Delay Time vs Temperature
0
0.1
0.5 0.6
0.2 0.3 0.4
VCC – VSSO VOLTAGE (V)
0
0.7
LTC1293 G16
0
0.2
0.6
0.4
VSSO VOLTAGE (V)
0.8
1.0
LTC1293 G17
129346fs
6
LTC1293/LTC1294/LTC1296
U
U
U
PI FU CTIO S
LTC1293
#
PIN
FUNCTION
1–6
7
CH0 – CH5
COM
Analog Inputs
Common
8
9
10
11
12
13
14
15
16
DGND
V–
AGND
VREF
DIN
DOUT
CS
CLK
VCC
DESCRIPTION
The analog inputs must be free of noise with respect to AGND.
The common pin defines the zero reference point for all single ended inputs. It must be free of noise and is
usually tied to the analog ground plane.
Digital Ground
This is the ground for the internal logic. Tie to the ground plane.
Negative Supply
Tie V – to most negative potential in the circuit (Ground in single supply applications).
Analog Ground
AGND should be tied directly to the analog ground plane.
Ref. Input
The reference inputs must be kept free of noise with respect to AGND.
Data Input
The A/D configuration word is shifted into this input.
Digital Data Output The A/D conversion result is shifted out of this output.
Chip Select Input
A logic low on this input enables data transfer.
Clock
This clock synchronizes the serial data transfer and controls A/D conversion rate.
Positive supply
This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane.
LTC1294
#
PIN
FUNCTION
1 –8
9
CH0 – CH7
COM
Analog Inputs
Common
10
11
12
13, 14
DGND
V–
AGND
REF –, REF +
15
16
17
18
19, 20
DIN
DOUT
CS
CLK
AVCC, DVCC
DESCRIPTION
The analog inputs must be free of noise with respect to AGND.
The common pin defines the zero reference point for all single ended inputs. It must be free of noise and is
usually tied to the analog ground plane.
Digital Ground
This is the ground for the internal logic. Tie to the ground plane.
Negative Supply
Tie V – to most negative potential in the circuit (Ground in single supply applications).
Analog Ground
AGND should be tied directly to the analog ground plane.
Ref. Inputs
The reference inputs must be kept free of noise with respect to AGND. The A/D sees a reference voltage equal
to the difference between REF + and REF –.
Data Input
The A/D configuration word is shifted into this input.
Digital Data Output The A/D conversion result is shifted out of this output.
Chip Select Input
A logic low on this input enables data transfer.
Clock
This clock synchronizes the serial data transfer and controls A/D converion rate.
Positive Supplies
These supplies must be kept free of noise and ripple by bypassing directly to the analog ground plane. AVCC
and DVCC must be tied together.
LTC1296
#
PIN
FUNCTION
1 –8
9
CH0 – CH7
COM
Analog Inputs
Common
10
11
12
13, 14
DGND
V–
AGND
REF –, REF +
15
16
17
18
19
DIN
DOUT
CS
CLK
SSO
20
VCC
DESCRIPTION
The analog inputs must be free of noise with respect to AGND.
The common pin defines the zero reference point for all single ended inputs. It must be free of noise and is
usually tied to the analog ground plane.
Digital Ground
This is the ground for the internal logic. Tie to the ground plane.
Negative Supply
Tie V – to most negative potential in the circuit (Ground in single supply applications).
Analog Ground
AGND should be tied directly to the analog ground plane.
Ref. Inputs
The reference inputs must be kept free of noise with respect to AGND. The A/D sees a reference voltage equal
to the difference between REF + and REF –.
Data Input
The A/D configuration word is shifted into this input.
Digital Data Output The A/D conversion result is shifted out of this output.
Chip Select Input
A logic low on this input enables data transfer.
Clock
This clock synchronizes the serial data transfer and controls A/D conversion rate.
System Shutdown System Shutdown Output pin will go low when power shutdown is requested.
Output
Positive Supply
This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane.
129346fs
7
LTC1293/LTC1294/LTC1296
W
BLOCK DIAGRA
(Pin numbers refer to LTC1294)
18
20
DVCC
AVCC 19
INPUT
SHIFT
REGISTER
15
DIN
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
OUTPUT
SHIFT
REGISTER
16
CLK
DOUT
1
SAMPLE
AND
HOLD
2
3
4
5
COMP
ANALOG
INPUT MUX
12-BIT
SAR
6
12-BIT
CAPACITIVE
DAC
7
8
9
11
10
12
V–
DGND
AGND
CONTROL
AND
TIMING
14
13
REF –
REF +
17
CS
LTC1293 BD
TEST CIRCUITS
Load Circuit for tdDO, tr and tf
Load Circuit for tenSSO and tdisSSO
1.4V
1.4V
3kΩ
3kΩ
DOUT
TEST POINT
TEST POINT
SSO
LT1296
100pF
100pF
LTC1293 TC08
LTC1293 TC02
On and Off Channel Leakage Current
Load Circuit for tdis and ten
5V
TEST POINT
ION
A
3k
5V tdis WAVEFORM 2, ten
IOFF
DOUT
100pF
ON CHANNEL
tdis WAVEFORM 1
A
OFF
CHANNELS
LTC1293 TC05
POLARITY
LTC1293 TC1
129346fs
8
LTC1293/LTC1294/LTC1296
TEST CIRCUITS
Voltage Waveforms for ten
CS
DIN
START
4
3
2
1
CLK
6
5
7
8
0.8V
DOUT
B11
ten
LTC1293 TC07
Voltage Waveform for tdisSSO
CS
Voltage Waveform for DOUT Rise and Fall Times, tr, tf
2.4V
DOUT
0.8V
tdisSSO
0.4V
tr
2.4V
SSO
tf
LTC1293 TC04
LTC1293 TC10
Voltage Waveform for for tenSSO
CLK
Voltage Waveform for tdis
2.0V
CS
0.8V
tenSSO
DOUT
WAVEFORM 1
(SEE NOTE 1)
SSO
90%
tdis
0.8V
DOUT
WAVEFORM 2
(SEE NOTE 2)
LTC1293 TC09
10%
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
Voltage Waveform for DOUT Delay Time, tdDO
LTC1293 TC06
CLK
0.8V
tdDO
2.4V
DOUT
0.4V
LTC1293 TC03
129346fs
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The LTC 1293/4/6 is a data acquisition component which
contains the following functional blocks:
1. 12-bit successive approximation capacitive A/D
converter
2. Analog multiplexer (MUX)
3. Sample and hold (S/H)
4. Synchronous, half duplex serial interface
5. Control and timing logic
INPUT DATA WORD
The LTC1293/4/6 seven-bit data word is clocked into the
DIN input on the rising edge of the clock after chip select
goes low and the start bit has been recognized. Further
inputs on the DIN pin are then ignored until the next CS
cycle. The input word is defined as follows:
UNIPOLAR/
BIPOLAR
START
DIGITAL CONSIDERATIONS
SGL/
DIFF
ODD/
SIGN
SELECT
1
MUX ADDRESS
Serial Interface
The LTC1293/4/6 communicates with microprocessors
and other external circuitry via a synchronous, half duplex,
four-wire serial interface (see Operating Sequence). The
clock (CLK) synchronizes the data transfer with each bit
being transmitted on the falling CLK edge and captured on
the rising CLK edge in both transmitting and receiving
systems. The input data is first received and then the A/D
conversion result is transmitted (half duplex). Because of
SELECT
0
UNI
POWER
SHUTDOWN
MSBF
MSB FIRST/
LSB FIRST
PS
LTC1293 AI02
Start Bit
The first "logical one" clocked into the DIN input after CS
goes low is the start bit. The start bit initiates the data
transfer and all leading zeroes which precede this logical
one will be ignored. After the start bit is received the
remaining bits of the input word will be clocked in. Further
inputs on the DIN pin are then ignored until the next CS
cycle.
CS
DIN 1
DIN 2
DOUT 1
SHIFT MUX 1 NULL
ADDRESS IN BIT
SHIFT A/D CONVERSION
RESULT OUT
the half duplex operation DIN and DOUT may be tied
together allowing transmission over just 3 wired: CS, CLK
and DATA (DIN/DOUT). Data transfer is initiated by a falling
chip select (CS) signal. After CS falls the LTC1293/4/6
looks for a start bit. After the start bit is received a 7-bit
input word is shifted into the DIN input which configures
the LTC1293/4/6 and starts the conversion. After one null
bit, the result of the conversion is output on the DOUT line.
With the half duplex serial interface the DOUT data is from
the current conversion. After the end of the data exchange
CS should be brought high. This resets the LTC1293/4/6
in preparation for the next data exchange.
DOUT 2
LTC1293 AI01
MUX Address
The four bits of the input word following the START BIT
assign the MUX configuration for the requested conversion. For a given channel selection, the converter will
measure the voltage between the two channels indicated
by the + and – signs in the selected row of the following
table. Note that in differential mode (SGL/DIFF = 0) measurements are limited to four adjacent input pairs with
either polarity. In single ended mode, all input channels
are measured with respect to COM. Only the +inputs have
sample and holds. Signals applied at the –inputs must not
change more than the required accuracy during the conversion.
129346fs
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Table 1a. LTC1294/6 Multiplexer Channel Selection
MUX ADDRESS
SGL/ ODD SELECT
DIFF SIGN 1 0
0
0
0 0
0
0
0 1
0
0
1 0
0
0
1 1
0
1
0 0
0
1
0 1
0
1
1 0
0
1
1 1
DIFFERENTIAL CHANNEL SELECTION
0
1
+
–
2
3
+
–
4
5
+
6
–
+
–
7
–
+
–
+
–
+
–
+
MUX ADDRESS
SGL/ ODD SELECT
DIFF SIGN 1 0
1
0
0 0
1
0
0 1
1
0
1 0
1
0
1 1
1
1
0 0
1
1
0 1
1
1
1 0
1
1
1 1
SINGLE-ENDED CHANNEL SELECTION
0
1
2
3
4
5
6
7
COM
+
–
–
–
–
–
–
–
–
+
+
+
+
+
+
+
Table 1b. LTC1293 Channel Selection
MUX ADDRESS
SGL/ ODD SELECT
DIFF SIGN 1 0
0
0
0 0
0
0
0 1
0
0
1 0
0
0
1 1
0
1
0 0
0
1
0 1
0
1
1 0
0
1
1 1
DIFFERENTIAL CHANNEL SELECTION
0
1
+
–
2
3
+
–
4
+
5
–
Not Used
–
+
–
+
–
Not Used
+
MUX ADDRESS
SGL/ ODD SELECT
DIFF SIGN 1 0
1
0
0 0
1
0
0 1
1
0
1 0
1
0
1 1
1
1
0 0
1
1
0 1
1
1
1 0
1
1
1 1
Unipolar/Bipolar (UNI)
The UNI bit determines whether the conversion will be
unipolar or bipolar. When UNI is a logical one, a unipolar
conversion will be performed on the selected input volt-
111111111111
111111111110
•
•
•
000000000001
000000000000
0
1
2
3
4
5
COM
+
–
–
–
+
+
Not Used
+
–
–
–
+
+
Not Used
age. When UNI is a logical zero, a bipolar conversion will
result. The input span and code assignment for each
conversion type are shown in the figures below:
Unipolar Output Code (UNI = 1)
Unipolar Transfer Curve (UNI = 1)
OUTPUT CODE
SINGLE-ENDED CHANNEL SELECTION
INPUT VOLTAGE
INPUT VOLTAGE
(VREF = 5V)
VREF – 1LSB
VREF – 2LSB
•
•
•
1LSB
0V
4.9988V
4.9976V
•
•
•
0.0012V
0V
111111111110
•
•
•
000000000001
000000000000
VIN
VREF
VREF–1LSB
VREF–2LSB
1LSB
0V
LTC1293 AI03a
111111111111
LTC1293 AI03b
129346fs
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Bipolar Transfer Curve (UNI = 0)
OUTPUT CODE
INPUT VOLTAGE
INPUT VOLTAGE
(VREF = 5V)
OUTPUT CODE
INPUT VOLTAGE
INPUT VOLTAGE
(VREF = 5V)
011111111111
011111111110
•
•
•
000000000001
000000000000
VREF – 1LSB
VREF – 2LSB
•
•
•
1LSB
0V
4.9976V
4.9851V
•
•
•
0.0024V
0V
111111111111
111111111110
•
•
•
100000000001
100000000000
–1LSB
–2LSB
•
•
•
–(VREF) + 1LSB
– (VREF)
–0.0024V
–0.0048V
•
•
•
–4.9976V
–5.00000V
LTC1293 AI04a
Bipolar Output Code (UNI = 0)
011111111111
011111111110
1LSB
–VREF + 1LSB
–VREF
•
•
•
000000000001
000000000000
VIN
VREF
–1LSB
–2LSB
•
•
•
VREF–1LSB
111111111110
VREF–2LSB
111111111111
100000000001
LTC1293 AI04b
100000000000
The following discussion will demonstrate how the two
reference pins are to be used in conjunction with the
analog input multiplexer. In unipolar mode the input span
of the A/D is set by the difference in voltage on the REF + pin
and the REF – pin. In the bipolar mode the input span is
twice the difference in voltage on the REF + pin and the
REF – pin. In the unipolar mode the lower value of the input
span is set by the voltage on the COM pin for single-ended
inputs and by the voltage on the minus input pin for
differential inputs. For the bipolar mode of operation the
voltage on the COM pin or the minus input pin set the
center of the input span.
The upper and lower value of the input span can now be
summarized in the following table:
INPUT
CONFIGURATION
UNIPOLAR MODE
BIPOLAR MODE
Single-Ended
Lower Value COM
–(REF + – REF – ) + COM
+
–
Upper Value (REF – REF ) + COM (REF+ – REF – ) + COM
Differential
Lower Value IN –
Upper Value (REF+ – REF – ) + IN –
–(REF + – REF – ) + IN –
(REF + – REF – ) + IN –
The reference voltages REF + and REF – can fall between
VCC and V –, but the difference (REF + –REF –) must be less
than or equal to VCC. The input voltages must be less than
or equal to VCC and greater than or equal to V –. For the
LTC1293 REF – = 0V.
The following examples are for a single-ended input configuration.
Example 1: Let VCC = 5V, V – = 0V, REF + = 4V, REF – = 1V
and COM = 0V. Unipolar mode of operation. The resulting
input span is 0V ≤ IN + ≤ 3V.
129346fs
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Example 2: The same conditions as Example 1 except
COM = 1V. The resulting input span is 1V ≤ IN + ≤ 4V. Note
if IN + ≥ 4V the resulting DOUT word is all 1’s. If IN + ≤ 1V
then the resulting DOUT word is all 0’s.
Example 3: Let VCC = 5V, V – = –5V, REF+ = 4V, REF – = 1V
and COM = 1V. Bipolar mode of operation. The resulting
input span is –2V ≤ IN + ≤ 4V.
For differential input configurations with the same conditions as in the above three examples the resulting input
spans are as follows:
Example 1 (Diff.): IN – ≤ IN + ≤ IN – + 3V.
Example 2 (Diff.): IN – ≤ IN + ≤ IN – + 3V.
Example 3 (Diff.): IN – – 3V ≤ IN + ≤ IN – + 3V.
MSB-First/LSB-First (MSBF)
The output data of the LTC1293/4/6 is programmed for
MSB-first or LSB-first sequence using the MSB bit. When
the MSBF bit is a logical one, data will appear on the DOUT
line in MSB-first format. Logical zeroes will be filled in
indefinitely following the last data bit to accommodate
longer word lengths required by some microprocessors.
When the MSBF bit is a logical zero, LSB first data will
follow the normal MSB first data on the DOUT line. In the
bipolar mode the sign bit will fill in after the MSB bit for
MSBF = 0 (see Operating Sequence).
Power Shutdowns (PS)
The power shutdown feature of the LTC1293/4/6 is activated by making the PS bit a logical zero. If CS remains low
after the PS bit has been received, a 12-bit DOUT word with
Operating Sequence
Example: Differential Inputs (CH4 +, CH5 –), Unipolar Mode
MSB-FIRST DATA (MSBF = 1)
tCYC
CS
DON'T
CARE
CLK
START
SEL1
UNI
PS
MSBF
DIN
DON'T CARE
SGL/ ODD/ SEL0
DIFF SIGN
HI-Z
DOUT
B11
B1 B0
FILLED WITH ZEROES
tSMPL
tCONV
MSB-FIRST DATA (MSBF = 0)
tCYC
CS
DON'T
CARE
CLK
START
SEL1
UNI
PS
DIN
DOUT
DON'T CARE
HI-Z
SGL/ ODD/ SEL0
DIFF SIGN
MSBF
B1 B0 B1
B11
B11
FILLED WITH
ZEROES
LTC1293 AI05
tSMPL
tCONV
129346fs
13
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Power Shutdown Operating Sequence
Example: Differential Inputs (CH4 +, CH5 –), Unipolar Mode and MSB-First Data
REQUEST POWER SHUTDOWN
CS
NEW CONVERSION BEGINS
SHUTDOWN*
CLK
START
SEL1
UNI
START
PS
DIN
SEL1
UNI
SEL1/ ODD/ SEL0 MSBF
DIFF SIGN
HI-Z
DOUT
B11
•
•
•
•
•
•
•
•
•
PS
MSBF
DON'T CARE
•
B0 FILLED
WITH
ZEROES
HI-Z
SEL1/ ODD/ SEL0
DIFF SIGN
LTC1293 AI06
*STOPPING THE CLOCK WILL HELP REDUCE POWER CONSUMPTION.
CS CAN BE BROUGHT HIGH ONCE THE DIN WORD HAS BEEN CLOCKED IN.
all logical ones will be shifted out followed by logical
zeroes till CS goes high. Then the DOUT line will go into its
high impedance state. The LTC 1293/4/6 will remain in the
shutdown mode till the next CS cycle. There is no warmup or wait period required after coming out of the power
shutdown cycle so a conversion can commence after CS
goes low (see Power Shutdown Operating Sequence). The
LTC1296 has a System Shutdown Output pin (SSO) which
will go low when power shutdown is activated. The pin will
stay low till next CS cycle.
Microprocessor Interfaces
The LTC1293/4/6 can interface directly (without external
hardware) to most popular microprocessors (MPU) synchronous serial formats (see Table 1). If an MPU without
a dedicated serial port is used, then three of the MPU’s
parallel port lines can be programmed to form the serial
link to the LTC1293/4/6. Included here are one serial
interface example and one example showing a parallel
port programmed to form the serial interface.
Microprocessor Interfaces
The LTC1293/4/6 can interface directly (without external
hardware) to most popular microprocessors (MPU) synchronous serial formats (see Table 1). If an MPU without
a dedicated serial port is used, then three of the MPU’s
parallel port lines can be programmed to form the serial
link to the LTC1293/4/6.
Table 1. Microprocessor with Hardware Serial Interfaces Compatible with the LTC1293/4/6**
PART NUMBER
Motorola
MC6805S2, S3
MC68HC11
MC68HC05
RCA
CDP68HC05
Hitachi
HD6305
HD6301
HD63701
HD6303
HD64180
National Semiconductor
COP400 Family
COP800 Family
NS8050U
HPC16000 Family
Texas Instruments
TMS7002
TMS7042
TMS70C02
TMS70C42
TMS32011*
TMS32020*
TMS370C050
TYPE OF INTERFACE
SPI
SPI
SPI
SPI
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
MICROWIRE†
MCROWIRE/PLUS†
MICROWIRE/PLUS
MICROWIRE/PLUS
Serial Port
Serial Port
Serial Port
Serial Port
Serial Port
Serial Port
SPI
* Requires external hardware
** Contact factory for interface information for processors not on this list
†
MICROWIRE and MICROWIRE/PLUS are trademarks of National
Semiconductor Corp.
129346fs
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Motorola SPI (MC68HC11)
The MC68HC11 has been chosen as an example of an MPU
with a dedicated serial port. This MPU transfers data MSBfirst and in 8-bit increments. The DIN word sent to the data
register starts the SPI process. With three 8-bit transfers,
the A/D result is read into the MPU. The second 8-bit
transfer clocks B11 through B8 of the A/D conversion
result into the processor. The third 8-bit transfer clocks
the remaining bits B7 through B0 into the MPU. The data
is right justified in the two memory locations. ANDing the
second byte with 0DHEX clears the four most significant
bits. This operation was not included in the code. It can
be inserted in the data gathering loop or outside the loop
when the data is processed.
Interfacing to the Parallel Port of the Intel 8051 Family
The Intel 8051 has been chosen to show the interface
between the LTC1293/4/6 and parallel port microprocessors. Usually the signals CS, DIN and CLK are generated
on three port lines and the DOUT signal is read on a fourth
port line. This works very well. One can save a line by tying
the DIN and DOUT lines together. The 8051 first sends the
start bit and DIN to the LTC1294 over the line connected to
P1.2. Then P1.2 is reconfigured as an input and the 8051
reads back the 12-bit A/D result over the same data line.
Data Exchange Between LTC1294 and MC68HC11
CS
CLK
SGL/
START DIFF
DIN
ODD/
EVEN
SEL
1
SEL
0
UNI
MSBF
DON'T CARE
PS
DOUT
B11
B10
B9
B8
B6
B7
B4
B5
B2
B3
B1
B0
START
MPU
TRANSMIT
WORD
0
0
0
1
SGL
ODD
SEL
1
SEL
0
UNI MSBF
PS
?
?
?
X
X
X
X
X
X
X
BYTE 2
BYTE 1
MPU
RECEIVED
WORD
X
?
?
?
?
?
?
?
?
0
B11
X
X
X
X
B2
B1
B0
BYTE 3 (DUMMY)
B10
B9
B7
B8
BYTE 2
BYTE 1
X
B6
B5
B4
B3
BYTE 3
LTC1293 TD01
Hardware and Software Interface to Motorola MC68HC11
DOUT FROM LTC1294 STORED ON MC68HC11 RAM
MSB
#62
O
O
O
O
B11
B10
B9
B8
BYTE 1
ANALOG
INPUTS
LSB
#63
B7
B6
B5
B4
B3
B2
B1
B0
CS
DO
CLK
SCK
DIN
MOSI
DOUT
MISO
MC68HC11
LTC1294
BYTE 2
LTC1293 TD01a
129346fs
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LTC1293/LTC1294/LTC1296
UO
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OPERAND
#$50
$1028
#$1B
$1009
#$10
$50
#$E0
$51
#$00
$52
#$1000
$08,X,$01
$50
$102A
$1029
WAIT1
$51
COMMENTS
CONFIGURATION DATA FOR SPCR
LOAD DATA INTO SPCR ($1028)
CONFIG. DATA FOR PORT D DDR
LOAD DATA INTO PORT D DDR
LOAD DIN WORD INTO ACC A
LOAD DIN DATA INTO $50
LOAD DIN WORD INTO ACC A
LOAD DIN DATA INTO $51
LOAD DUMMY DIN WORD INTO ACC A
LOAD DUMMY DIN DATA INTO $52
LOAD INDEX REGISTER X WITH $1000
D0 GOES LOW (CS GOES LOW)
LOAD DIN INTO ACC A FROM $50
LOAD DIN INTO SPI, START SCK
CHECK SPI STATUS REG
CHECK IF TRANSFER IS DONE
LOAD DIN INTO ACC A FROM $51
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MC68HC11 CODE
LABEL MNEMONIC
LDAA
STAA
LDAA
STAA
LDAA
STAA
LDAA
STAA
LDAA
STAA
LDX
LOOP BCLR
LDAA
STAA
LDAA
WAIT1 BPL
LDAA
LABEL MNEMONIC
STAA
WAIT2 LDAA
BPL
LDAA
STAA
LDAA
STAA
WAIT3 LDAA
BPL
BSET
LDAA
STAA
JMP
OPERAND COMMENTS
$102A
LOAD DIN INTO SPI, START SCK
$1029
CHECK SPI STATUS REG
WAIT2
CHECK IF TRANSFER IS DONE
$102A
LOAD LTC1294 MSBs INTO ACC A
$62
STORE MSBs IN $62
$52
LOAD DUMMY DIN INTO ACC A FROM
$52
$102A
LOAD DUMMY DIN INTO SPI, START
SCK
$1029
CHECK SPI STATUS REG
WAIT3
CHECK IF TRANSFER IS DONE
$08,X,$01 D0 GOES HIGH (CS GOES HIGH)
$102A
LOAD LTC1294 LSBs IN ACC
$63
STORE LSBs IN $63
LOOP
START NEXT CONVERSION
Hardware and Software Interface to Intel 8051
PS BIT LATCHED
INTO LTC1294
CS
1
2
4
3
6
5
7
8
CLK
DATA
(DIN/DOUT)
SGL/
DIFF
ODD/
SIGN
SEL
1
B10
SEL
0
UNI
MSB
PS
B11
START
B6
B8
B9
B7
B2
B4
B5
B3
B0
B1
LTC1293 TD02
LTC1294 SEND A/D RESULT
BACK TO 8051 P1.2
8051 P1.2 OUTPUT DATA
TO LTC1294
LTC1294 TAKES CONTROL OF DATA
LINE ON 8TH FALLING CLK
8051 P1.2 RECONFIGURED
AS INPUT AFTER THE 8TH RISING
CLK BEFORE THE 8TH FALLING CLK
Hardware and Software Interface to Intel 8051
DOUT FROM LTC1294 STORED IN 8051 RAM
MSB
R2
B11
B10
B9
B8
B7
B6
B5
B4
ANALOG
INPUTS
LSB
R3
B3
B2
B1
B0
0
0
0
0
CS
P1.4
CLK
P1.3
DOUT
P1.2
LTC1294
8051
DIN
MUX ADDRESS
LTC1293 TD02a
A/D RESULT
129346fs
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8051 CODE
LABEL MNEMONIC
SETB
CONT MOV
CLR
MOV
LOOP1 RLC
CLR
MOV
SETB
DJNZ
MOV
CLR
MOV
LOOP MOV
RLC
SETB
CLR
DJNZ
MOV
MOV
SETB
OPERAND
P1.4
A,#87H
P1.4
R4,#08H
A
P1.3
P1.2,C
P1.3
R4,LOOP1
P1,#04H
P1.3
R4,#09H
C,P1.2
A
P1.3
P1.3
R4,LOOP
R2,A
C,P1.2
P1.3
COMMENTS
CS GOES HIGH
DIN WORD FOR LTC1294
CS GOES LOW
LOAD COUNTER
ROTATE DIN BIT INTO CARRY
CLK GOES LOW
OUTPUT DIN BIT TO LTC1294
CLK GOES HIGH
NEXT DIN BIT
P1.2 BECOMES AN INPUT
CLK GOES LOW
LOAD COUNTER
READ DATA BIT INTO CARRY
ROTATE DATA BIT (B3) INTO ACC
CLK GOES HIGH
CLK GOES LOW
NEXT DOUT BIT
STORE MSBs IN R2
READ DATA BIT INTO CARRY
CLK GOES HIGH
2
1
LABEL MNEMONIC
CLR
CLR
RLC
MOV
RLC
SETB
CLR
MOV
RLC
SETB
CLR
MOV
SETB
RRC
RRC
RRC
RRC
MOV
AJMP
OPERAND
P1.3
A
A
C,P1.2
A
P1.3
P1.3
C,P1.2
A
P1.3
P1.3
C,P1.2
P1.4
A
A
A
A
R3,A
CONT
COMMENTS
CLK GOES LOW
CLEAR ACC
ROTATE DATA BIT (B3) INTO ACC
READ DATA BIT INTO CARRY
ROTATE DATA BIT (B2) INTO ACC
CLK GOES HIGH
CLK GOES LOW
READ DATA BIT INTO CARRY
ROTATE DATA BIT (B1) INTO ACC
CLK GOES HIGH
CLK GOES LOW
READ DATA BIT INTO CARRY
CS GOES HIGH
ROTATE DATA BIT (B0) INTO ACC
ROTATE RIGHT INTO ACC
ROTATE RIGHT INTO ACC
ROTATE RIGHT INTO ACC
STORE LSBs IN R3
START NEXT CONVERSION
0
OUTPUT PORT
SERIAL DATA
MPU
3-WIRE SERIAL
INTERFACE TO OTHER
PERIPHERALS OR LTC1293/4/6s
3
3
3
3
CS
LTC1294
CS
LTC1294
CS
LTC1294
8 CHANNELS
8 CHANNELS
8 CHANNELS
LTC1293 F03
Figure 3. Several LTC1294 Sharing One 3-Wire Serial Interface
Sharing the Serial Interface
The LTC1293/4/6 can share the same 3-wire serial interface with other peripheral components or other LTC1293/
4/6’s (Figure 3). Now, the CS signals decide which LTC1293/
4/6 is being addressed by the MPU.
ANALOG CONSIDERATIONS
Grounding
The LTC1293/4/6 should be used with an analog ground
plane and single point grounding techniques. Do not use
wire wrapping techniques to breadboard and evaluate the
device. To achieve the optimum performance use a PC
board. The analog ground pin (AGND) should be tied
directly to the ground plane with minimum lead length (a
low profile socket is fine). The digital ground pin (DGND)
also can be tied directly to this ground pin because
minimal digital noise is generated within the chip itself.
VCC should be bypassed to the ground plane with a 22µF
(minimum value) tantalum with leads as short as possible
and as close as possible to the pin. A 0.1µF ceramic disk
also should be placed in parallel with the 22µF and again
with leads as short as possible and as close to VCC as
possible. AVCC and DVCC should be tied together on the
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VERTICAL: 0.5mV/DIV
LTC1294. Figure 4 shows an example of an ideal LTC1293/
4/6 ground plane design for a two sided board. Of course
this much ground plane will not always be possible, but
users should strive to get as close to this ideal as possible.
HORIZONTAL: 10µs/DIV
VCC
22µF
TANTALUM
Figure 5. Poor VCC Bypassing.
Noise and Ripple Can Cause A/D Errors.
ANALOG
GROUND
PLANE
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VERTICAL: 0.5mV/DIV
0.1µF
CERAMIC
CS
VCC
HORIZONTAL: 10µs/DIV
Figure 6. Good VCC Bypassing Keeps Noise
and Ripple on VCC Below 1mV
V–
0.1µF
CERAMIC
DISK
LTC1293 F04
Figure 4. Ground Plane for the LTC1293/4/6
Bypassing
For good performance, VCC must be free of noise and
ripple. Any changes in the VCC voltage with respect to
ground during a conversion cycle can induce errors or
noise in the output code. VCC noise and ripple can be kept
below 0.5mV by bypassing the VCC pin directly to the
analog ground plane with a minimum of 22µF tantalum
capacitor and with leads as short as possible. The lead
from the device to the VCC supply also should be kept to a
minimum and the VCC supply should have a low output
impedance such as obtained from a voltage regulator
(e.g., LT323A). For high frequency bypassing a 0.1µF
ceramic disk placed in parallel with the 22µF is recommended. Again the leads should be kept to a minimum.
Figure 5 and 6 show the effects of good and poor VCC
bypassing.
Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1293/4/6
have capacitive switching input current spikes. These
current spikes settle quickly and do not cause a problem.
If large source resistances are used or if slow settling op
amps drive the inputs, take care to insure the transients
caused by the current spikes settle completely before the
conversion begins.
RSOURCE +
“+”
INPUT
LTC1293/4/6
VIN +
RSOURCE –
C1
6TH CLK↑
RON = 500Ω
“–”
INPUT
8TH CLK↓
CIN =
100pF
VIN –
C2
LTC1293 F07
Figure 7. Analog Input Equivalent Circuit
129346fs
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Source Resistance
The analog inputs of the LTC1293/4/6 look like a 100pF
capacitor (CIN) in series with a 500Ω resistor (RON). CIN
gets switched between (+) and (–) inputs once during each
conversion cycle. Large external source resistors and
capacitances will slow the settling of the inputs. It is
important that the overall RC time constant is short
enough to allow the analog inputs to settle completely
within the allowed time.
“+” Input Settling
The input capacitor is switched onto the “+” input during
the sample phase (tSMPL, see Figure 8). The sample period
2 1/2 CLK cycles before a conversion starts. The voltage on
the “+” input must settle completely within the sample
period. Minimizing RSOURCE + and C1 will improve the
settling time. If large “+” input source resistance must be
used, the sample time can be increased by using a slower
CLK frequency. With the minimum possible sample time
Ω and C1 < 20pF will provide
of 2.5µs RSOURCE + < 1.5kΩ
adequate settling time.
“–” Input Settling
At the end of the sample phase the input capacitor switches
to the “-” input and the conversion starts (see Figure 8).
During the conversion, the “+” input voltage is effectively
“held” by the sample and hold and will not affect the
conversion result. It is critical that the “–” input voltage be
free of noise and settle completely during the first CLK
cycle of the conversion. Minimizing RSOURCE – and C2 will
improve settling time. If large “–” input source resistance
must be used the time can be extended by using a slower
CLK frequency. At the maximum CLK frequency of 1MHz,
Ω and C2 < 20pF will provide adequate
RSOURCE – < 250Ω
settling.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settles within the allowed time
(see Figure 8). Again the “+” and “–” input sampling times
can be extended as described above to accommodate
slower op amps. Most op amps including the LT1006 and
LT1013 single supply op amps can be made to settle
HOLD
SAMPLE
CS
CLK
DIN
SGL/
DIFF
START
MSBF
PS
tSMPL
(+) INPUT MUST SETTLE DURING THIS TIME
DOUT
B11
HI-Z
1ST BIT TEST (–) INPUT MUST
SETTLE DURING THIS TIME
(+) INPUT
(–) INPUT
LTC1293 F08
Figure 8. “+” and “–” Input Settling Windows
129346fs
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VERTICAL: 5mV/DIV
within the minimum settling windows of 2.5µs (“+” input)
and 1µs(“–” input) that occurs at the maximum clock rate
of 1MHz. Figures 9 and 10 show examples of adequate
and poor op amp settling.
HORIZONTAL: 500ns/DIV
the cycle time as shown in the typical performance characteristic curve Maximum Filter Resistor vs Cycle Time.
Input Leakage Current
Input leakage currents also can create errors if the source
resistance gets too large. For example, the maximum input
leakage specification of 1µA (at 125°C) flowing through a
source resistance of 1kΩ will cause a voltage drop of 1mV
or 0.8LSB. This error will be much reduced at lower
temperatures because leakage drops rapidly (see typical
performance characteristic curve Input Channel Leakage
Current vs Temperature).
Figure 9. Adequate Settling of Op Amp Driving Analog Input
VERTICAL: 5mV/DIV
SAMPLE AND HOLD
HORIZONTAL: 20µs/DIV
Figure 10. Poor Op Amp Settling Can Cause A/D Errors
RC Input Filtering
It is possible to filter the inputs with an RC network as
shown in Figure 11. For large values of CF (e.g., 1µF) the
capacitive input switching currents are averaged into a net
DC current. A filter should be chosen with a small resistor
and large capacitor to prevent DC drops across the resistor. The magnitude of the DC current is approximately IDC
= 100pF × VIN/tCYC and is roughly proportional to VIN.
When running at the minimum cycle time of 21.5µs, the
input current equals 23µA at VIN = 5V. Here a filter resistor
of 5Ω will cause 0.1LSB of full-scale error. If a larger filter
resistor must be used, errors can be reduced by increasing
RFILTER
IIDC
VIN –
"+"
CFILTER
LTC1293/4/6
"–"
LTC1293 F11
Figure 11. RC Input Filtering
Single-Ended Input
The LTC1293/4/6 provides a built-in sample and hold
(S&H) function for all signals acquired in the single-ended
mode (COM pin grounded). The sample and hold allows
the LTC1293/4/6 to convert rapidly varying signals (see
typical performance characteristic curve of S&H Acquisition Time vs Source Resistance). The input voltage is
sampled during the tSMPL time as shown in Figure 8. The
sampling interval begins as the bit preceding the MSBF bit
is shifted in and continues until the falling edge of the PS
bit is received. On this falling edge the S&H goes into the
hold mode and the conversion begins.
Differential Input
With a differential input the A/D no longer converts a
single voltage but converts the difference between two
voltages. The voltage on the selected “+” input is sampled
and held and can be rapidly time varying. The voltage on
the “–” pin must remain constant and be free of noise and
ripple throughout the conversion time. Otherwise the
differencing operation will not be done accurately. The
conversion time is 12 CLK cycles. Therefore a change in
the –IN input voltage during this interval can cause conversion errors. For a sinusoidal voltage on the –IN input
this error would be:
⎛ 12 ⎞
VERROR (MAX) = 2πf(–)VPEAK ⎜
⎟
⎝ fCLK ⎠
(
)
Where f(–) is the frequency of the “–” input voltage, VPEAK
is its peak amplitude and fCLK is the frequency of the CLK.
129346fs
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Usually VERROR will not be significant. For a 60Hz signal
on the “–” input to generate a 0.25LSB error (300µV) with
the converter running at CLK = 1MHz, its peak value would
have to be 66mV. Rearranging the above equation the
maximum sinusoidal signal that can be digitized to a given
accuracy is given as:
Reference Input
The voltage on the reference input of the LTC1293/4/6
determines the voltage span of the A/D converter. The
reference input has transient capacitive switching currents due to the switched capacitor conversion technique
(see Figure 12). During each bit test of the conversion
(every CLK cycle) a capacitive current spike will be generated on the reference pin by the A/D. These current spikes
settle quickly and do not cause a problem. If slow settling
circuitry is used to drive the reference input, take care to
insure that transients caused by these current spikes settle
completely during each bit test of the conversion.
VREF
REF–
13
LTC1293/4/6
EVERY CLK CYCLE
RON
8pF – 40pF
VERTICAL: 0.5mV/DIV
For 0.25LSB error (300µV) the maximum input sinusoid
with a 5V peak amplitude that can be digitized is 0.8Hz.
Unused inputs should be tied to the ground plane.
ROUT
HORIZONTAL: 1µs/DIV
Figure 13. Adequate Reference Settling (LT1027)
⎛ VERROR(MAX) ⎞ ⎛ fCLK ⎞
f(–) MAX = ⎜
⎟
⎟⎜
⎝ 2πVPEAK ⎠ ⎝ 12 ⎠
REF+
14
VERTICAL: 0.5mV/DIV
S I FOR ATIO
HORIZONTAL: 1µs/DIV
Figure 14. Poor Reference Settling Can Cause A/D Errors
Reduced Reference Operation
The effective resolution of the LTC1293/4/6 can be increased by reducing the input span of the converter. The
LTC1293/4/6 exhibits good linearity over a range of reference voltages (see typical performance characteristics
curves of Change in Linearity vs Reference Voltage and
Change in Gain Error vs Reference Voltage). Care must be
taken when operating at low values of VREF because of the
reduced LSB step size and the resulting higher accuracy
requirement placed on the converter. Offset and Noise are
factors that must be considered when operating at low
VREF values. For the LTC1293 REF – has been tied to the
AGND pin. Any voltage drop from the AGND pin to the
ground plane will cause a gain error.
LTC 1293 F12
Figure 12. Reference Input Equivalent Circuit
Figure 13 and 14 show examples of both adequate and
poor settling. Using a slower CLK will allow more time for
the reference to settle. Even at the maximum CLK rate of
1MHz most references and op amps can be made to settle
within the 1µs bit time. For example the LT1027 will settle
adequately or with a 10µF bypass capacitor at VREF the
LT1021 also can be used.
Offset with Reduced VREF
The offset of the LTC1293/4/6 has a larger effect on the
output code when the A/D is operated with a reduced
reference voltage. The offset (which is typically a fixed
voltage) becomes a larger fraction of an LSB as the size of
the LSB is reduced. The typical performance characteristic curve of Unadjusted Offset Error vs Reference Voltage
shows how offset in LSB’s is related to reference voltage
for a typical value of VOS. For example a VOS of 0.1mV,
which is 0.1LSB with a 5V reference becomes 0.4LSB with
129346fs
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a 1.25 reference. If this offset is unacceptable, it can be
corrected digitally by the receiving system or by offsetting
the “–” input to the LTC1293/4/6.
Noise with Reduced VREF
The total input referred noise of the LTC1293/4/6 can be
reduced to approximately 200µV peak-to-peak using a
ground plane, good bypassing, good layout techniques
and minimizing noise on the reference inputs. This noise
is insignificant with a 5V reference input but will become
a larger fraction of an LSB as the size of the LSB is reduced.
The typical performance characteristic curve of Noise
Error vs Reference Voltage shows the LSB contribution of
this 200µV of noise.
For operation with a 5V reference, the 200µV noise is only
0.16LSB peak-to-peak. Here the LTC1293/4/6 noise will
contribute virtually no uncertainty to the output code. For
reduced references, the noise may become a significant
fraction of an LSB and cause undesirable jitter in the
output code. For example, with a 1.25V reference, this
200µV noise is 0.64LSB peak-to-peak. This will reduce
the range of input voltages over which a stable output code
can be achieved by 0.64LSB. Now averaging readings may
be necessary.
This noise data was taken in a very clean test fixture. Any
setup induced noise (noise or ripple on VCC, VREF or VIN)
will add to the internal noise. The lower the reference
voltage used, the more critical it becomes to have a noisefree setup.
Gain Error due to Reduced VREF
The gain error of the LTC1294/6 is very good over a wide
range of reference voltages. The error component that is
seen in the typical performance characteristics curve
Change in Gain Error vs Reference Voltage for the LTC1293
is due the voltage drop on the AGND pin from the device
to the ground plane. To minimize this error the LTC1293
should be soldered directly onto the PC board. The internal
reference point for VREF is tied to AGND. Any voltage drop
in the AGND pin will make the reference voltage, internal
to the device, less than what is applied externally (Figure
15). This drop is typically 400µV due to the product of the
pin resistance (RPIN) and the LTC1293 supply current. For
example, with VREF = 1.25V this will result in a gain error
change of –1.0LSB from the gain error measured with
VREF = 5V.
LTC1293
DAC
REF – REF +
AGND
ICC
RPIN
VREF
±
REFERENCE
VOLTAGE
LTC1293 F15
Figure 15. Parasitic Pin Resistance (RPIN)
LTC1293/4/6 AC Characteristics
Two commonly used figures of merit for specifying the
dynamic performance of the A/Ds in digital signal processing applications are the Signal-to-Noise Ratio (SNR) and
the “effective number of bits”(ENOB). SNR is the ratio of
the RMS magnitude of the fundamental to the RMS
magnitude of all the non-fundamental signals up to the
Nyquist frequency (half the sampling frequency). The
theoretical maximum SNR for a sine wave input is given
by:
SNR = (6.02N + 1.76dB)
where N is the number of bits. Thus the SNR depends on
the resolution of the A/D. For an ideal 12-bit A/D the SNR
is equal to 74dB. A Fast Fourier Transform (FFT) plot of the
output spectrum of the LTC1294 is shown in Figures 16a
and 16b. The input (fIN) frequencies are 1kHz and 22kHz
with the sampling frequency (fS) at 45.4kHz. The SNR
obtained from the plot are 72.7dB and 72.5dB.
Rewriting the SNR expression it is possible to obtain the
equivalent resolution based on the SNR measurement.
⎛ SNR – 1.76dB ⎞
N=⎜
⎟
6.02
⎝
⎠
This is the so-called effective number of bits (ENOB). For
the example shown in Figures 16a and 16b, N = 11.8 bits.
Figure 17 shows a plot of ENOB as a function of input
frequency. The top curve shows the A/D’s ENOB remains
at 11.8 for input frequencies up to fS/2 with ±5V supplies.
129346fs
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0
0
–20
–20
–40
–40
MAGNITUDE (dB)
MAGNITUDE (dB)
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–60
–80
–80
–100
–100
–120
–120
–140
–140
0
5
10
20
15
FREQUENCY (kHz)
25
1293 F16a
0
5
10
15
FREQUENCY (kHz)
20
25
1293 F8
Figure 18. LTC1294 FFT Plot
fIN1 = 5.1kHz, fIN2 = 5.6kHz, fS = 45.4kHz
with ±5V Supplies
Figure 16a. LTC1294 FFT Plot
fIN = 1kHz, fS = 45.4kHz,
SNR = 72.7dB with ±5V Supplies
For +5V supplies the ENOB decreases more rapidly. This
is due predominantly to the 2nd harmonic distortion term.
0
–20
MAGNITUDE (dB)
–60
Figure 18 shows a FFT plot of the output spectrum for two
tones applied to the input of the A/D. Nonlinearities in the
A/D will cause distortion products at the sum and difference frequencies of the fundamentals and products of the
fundamentals. This is classically referred to as
intermodulation distortion (IMD).
–40
–60
–80
–100
–120
–140
0
5
10
20
15
FREQUENCY (kHz)
25
1293 F16b
Figure 16b. LTC1294 FFT Plot
fIN = 22kHz, fS = 45.4kHz,
SNR = 72.5dB with ±5V Supplies
12.0
EFFECTIVE NUMBER OF BITS
11.5
±5V SUPPLIES
11.0
10.5
10.0
9.5
+5V SUPPLY
9.0
8.5
fS = 45.4kHz
8.0
0
20
40
60
FREQUENCY (kHz)
80
100
LT1293 F17
Figure 17. LTC1294 ENOB vs Input Frequency
Overvoltage Protection
Applying signals to the LTC1293/4/6’s analog inputs that
exceed the positive supply or that go below V – will
degrade the accuracy of the A/D and possibly damage the
device. For example this condition would occur if a signal
is applied to the analog inputs before power is applied to
the LTC1293/4/6. Another example is the input source is
operating from different supplies of larger value than the
LTC1293/4/6. These conditions should be prevented either with proper supply sequencing or by use of external
circuitry to clamp or current limit the input source. There
are two ways to protect the inputs. In Figure 19 diode
clamps from the inputs to VCC and V – are used. The
second method is to put resistors in series with the analog
inputs for current limiting. As shown in Figure 20a, a 1kΩ
resistor is enough to stand off ±15V (15mA for only one
channel). If more than one channel exceeds the supplies
than the following guidelines can be used. Limit the
current to 7mA per channel and 28mA for all channels.
129346fs
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This means four channels can handle 7mA of input current
each. Reducing CLK frequency from a maximum of 1MHz
(See typical performance characteristics curves Maximum CLK Frequency vs Source Resistance and Sample
and Hold Acquisition Time vs Source Resistance) allows
the use of larger current limiting resistors. The “+” input
can accept a resistor value of 1kΩ but the “–” input cannot
accept more than 250Ω when the maximum clock frequency of 1MHz is used. If the LTC1293/4/6 is clocked at
the maximum clock frequency and 250Ω is not enough to
current limit the “–” input source then the clamp diodes
are recommended (Figures 20a and 20b). The reason for
the limit on the resistor value is the MSB bit test is affected
by the value of the resistor placed at the “–” input (see
discussion on Analog Inputs and the typical performance
characteristics curve Maximum CLK Frequency vs Source
Resistance).
If VCC and VREF are not tied together, then VCC should be
turned on first, then VREF. If this sequence cannot be met
connecting a diode from VREF to VCC is recommended (see
Figure 21).
For dual supplies (bipolar mode) placing two Schottky
diodes from VCC and V – to ground (Figure 22) will prevent
1N4148 DIODES
+5V
VCC
1k
+
LTC1293/4/6
–
AGND
DGND
V–
–5V
LTC1293 F20b
Figure 20b. Overvoltage Protection for Inputs
power supply reversal from occuring when an input source
is applied to the analog MUX before power is applied to the
device. Power supply reversal occurs, for example, if the
input is pulled below V –. VCC will then pull a diode drop
below ground which could cause the device not to power
up properly. Likewise, if the input is pulled above VCC, V –
will be pulled a diode drop above ground. If no inputs are
present on the MUX, the Schottky diodes are not required
if V – is applied first then VCC.
Because a unique input protection structure is used on the
digital input pins, the signal levels on these pins can
exceed the device VCC without damaging the device.
1N4148 DIODES
VCC
+5V
VCC
+5V
1N4148
LTC1293/4/6
LTC1293/4/6
REF+
AGND
AGND
DGND
+5V
DGND
V–
–5V
LTC1293 F21
Figure 21
LTC1293 F19
Figure 19. Overvoltage Protection for Inputs
VCC
VCC
1k
250Ω
+5V
LTC1293/4/6
+
LTC1293/4/6
AGND
–
DGND
AGND
DGND
+5V
1N5817
V
–
–5V
LTC1293 F20a
Figure 20a. Overvoltage Protection for Inputs
V–
–5V
1N5817
LTC1293 F22
Figure 22. Power Supply Reversal
129346fs
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Unipolar conversion is requested and the data is output
MSB first. CS is driven at 1/64 the clock rate by the CD4520
and DOUT outputs the data. The output data from the DOUT
pin can be viewed on an oscilloscope that is set up to
trigger on the falling edge of CS (Figure 24).
A “Quick Look” Circuit for the LTC1294/6
Users can get a quick look at the function and timing of the
LTC1294/6 by using the following simple circuit (Figure
23). VREF is tied to VCC. DIN is tied high which means VIN
should be applied to the CH7 with respect to COM. A
+5V
f/64
22µF
CLK
CH0
CH1
CH2
CH3
CH4
LTC1294
CH5
CH6
CH7
COM
DGND
VIN
DVCC
AVCC
CLK
CS
DOUT
DIN
REF+
CLK
f
VDD
CS
EN
RESET
Q1
Q4
Q2
Q3
CD4520
Q3
Q2
Q4
Q1
RESET
EN
VSS
CLK
REF–
AGND
V–
DOUT
NULL
BIT
MSB
(B11)
LSB
(B0)
FILLS
ZEROES
VERTICAL: 5V/DIV
HORIZONTAL: 2µs/DIV
CLOCK IN
1MHz MAX
TO
OSCILLOSCOPE
LTC1293 F23
Figure 23. “Quick Look” Circuit for the LTC1294/6
Figure 24. Scope Trace of the
LTC1294/6 “Quick Look” Circuit
Showing A/D Output
101010101010 (AAAHEX)
UO
TYPICAL APPLICATI
S
Digitally Linearized Platinum RTD Signal Conditioner
5VOUT
+15V
LT1027
+
10µF
12k*
500k
400°C TRIM
12.5k*
+15V
+15V
+
A1
LT1101
A=10
–
1k*
Rplat.
+
1k
A2
LT1006
–
30.1k**
1µF
* TRW-IRC MAR-6 RESISTOR – 0.1%
** 1% FILM RESISTOR
Rplat. = 1kΩ AT 0°C – ROSEMOUNT #118MF
3.92M**
CH0
CH1
CH2
CH3
CH4
LTC1294
CH5
CH6
CH7
COM
DGND
DVCC
AVCC
CLK
CS
DOUT
DIN
REF+
22µF
TANTALUM
TO/FROM
68HC11
PROCESSOR
REF –
AGND
V–
500k
ZERO°C TRIM
LTC1293 TA03
129346fs
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LTC1293/LTC1294/LTC1296
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S
Micropower, 5000V Opto-Isolated, Multichannel,12-Bit Data
Acquisition System is Accessed Once Every Two Seconds
4N28s
10k
9V
5V
10k
2N3906
LT1027
10k
C1
2N3906
51k
150Ω
5V
10k
10µF*
SCK
150Ω
51k
5V
8
ANALOG
INPUTS
0–5V RANGE
CH0
DVCC
CH1
AVCC
CH2
CLK
CH3
CS
CH4
DOUT
LTC1294
CH5
DIN
CH6
REF+
CH7
REF –
COM
AGND
DGND
5.1k
(3)
10k
C0
150Ω
51k
TO
68HC11
5V
10k
51k
MOSI
150Ω
TO ADDITIONAL
LTC1294s
5.1k
51k
300Ω
V–
4N28
*SOLID TANTALUM
10k
4N28
MISO
2N3904
ISOLATION
BARRIER
5V
LT1292 TA02
NC
129346fs
26
LTC1293/LTC1294/LTC1296
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
J Package
20-Lead Ceramic DIP
0.290 - 0.320
(7.366 - 8.128)
GLASS
SEALANT
1.060
(26.924)
MAX
0.160
(4.064)
MAX
20
0.015 – 0.060
(0.381 – 1.524)
19
18
17
16
15
14
13
12
11
2
3
4
5
6
7
8
9
10
0.200
(5.080) 0.220 - 0.310
0.025
MAX (5.588 - 7.874) (0.635)
RAD TYP
0° – 15°
1
0.008 – 0.018
(0.203 – 0.457)
0.038 – 0.068
(0.965 – 1.727)
0.125
(3.175)
MIN
0.385 ± 0.025
(9.779 ± 0.635)
0.080
(2.032)
MAX
0.005
(0.127)
0.100 ± 0.010
(2.540 ± 0.254)
J20 12/91
0.014 – 0.026
(0.356 – 0.660)
TJMAX
θJA
150°C
80°C/W
OBSOLETE PACKAGE
N Package
16-Lead Plastic DIP
0.130 ± 0.005
(3.302 ± 0.127)
0.300 – 0.325
(7.620 – 8.255)
0.015
(0.381)
MIN
0.009 - 0.015
(0.229 - 0.381)
+0.025
0.325 –0.015
(
+0.635
8.255
–0.381
0.045 ± 0.015
(1.143 ± 0.381)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
0.260 ± 0.010
(6.604 ± 0.254)
0.065
(1.651)
TYP
0.125
(3.175)
MIN
)
0.770
(19.558)
0.045 – 0.065
(1.143 – 1.651)
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
N16 1291
TJMAX
θJA
110°C
100°C/W
N Package
20-Lead Plastic DIP
0.130 ± 0.005
(3.302 ± 0.127)
0.300 – 0.325
(7.620 – 8.255)
1.040
(26.416)
MAX
0.045 – 0.065
(1.143 – 1.651)
0.015
(0.381)
MIN
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
+0.025
0.325 –0.015
+0.635
8.255
–0.381
(
)
0.125
(3.175)
MIN
0.065 ± 0.015
(1.651 ± 0.381)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
0.260 ± 0.010
(6.604 ± 0.254)
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
N20 0192
TJMAX
θJA
110°C
100°C/W
129346fs
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC1293/LTC1294/LTC1296
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
S Package
16-Lead Plastic SOL
0.398 – 0.413
(10.109 – 10.490)
0.291 – 0.299
(7.391 – 7.595)
0.005
(0.127)
RAD MIN
0.037 – 0.045
(0.940 – 1.143)
0.093 – 0.104
(2.362 – 2.642)
0.010 – 0.029 × 45°
(0.254 – 0.737)
16
15
14
13
12
10
11
9
0° – 8° TYP
0.009 – 0.013
(0.229 – 0.330)
0.050
(1.270)
TYP
SEE NOTE
0.016 – 0.050
(0.406 – 1.270)
0.394 – 0.419
(10.008 – 10.643)
0.004 – 0.012 SEE NOTE
(0.102 – 0.305)
0.014 – 0.019
(0.356 – 0.483)
TYP
NOTE:
PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
1
2
3
5
4
7
6
8
SOL16 12/91
TJMAX
θJA
110°C
150°C/W
S Package
20-Lead Plastic SOL
0.005
(0.127)
RAD MIN
0.496 – 0.512
(12.598 – 13.995)
0.291 – 0.299
(7.391 – 7.595)
0.010 – 0.029 × 45°
(0.254 – 0.737)
0.093 – 0.104
(2.362 – 2.642)
0.037 – 0.045
(0.940 – 1.143)
20
19
18
17
16
15
14
13
12
11
0° – 8° TYP
0.009 – 0.013
(0.229 – 0.330)
SEE NOTE
0.016 – 0.050
(0.406 – 1.270)
0.050
(1.270)
TYP
0.004 – 0.012
(0.102 – 0.305)
0.394 – 0.419
(10.008 – 10.643)
SEE NOTE
0.014 – 0.019
(0.356 – 0.483)
TYP
NOTE:
PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
1
2
3
4
5
6
7
8
9
10
SOL20 12/91
TJMAX
θJA
110°C
150°C/W
129346fs
28
Linear Technology Corporation
LT/GP 0392 10K REV 0
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977
© LINEAR TECHNOLOGY CORPORATION 1992
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