LTC2637 Octal 12-/10-/8-Bit I2C VOUT DACs with 10ppm/°C Reference DESCRIPTION FEATURES n n n n n n n n n n n The LTC®2637 is a family of octal 12-, 10-, and 8-bit voltage-output DACs with an integrated, high-accuracy, low-drift 10ppm/°C reference in 14-lead DFN and 16-lead MSOP packages. It has a rail-to-rail output buffer and is guaranteed monotonic. The LTC2637-L has a full-scale output of 2.5V, and operates from a single 2.7V to 5.5V supply. The LTC2637-H has a full-scale output of 4.096V, and operates from a 4.5V to 5.5V supply. Each DAC can also operate with an external reference, which sets the DAC full-scale output to the external reference voltage. Integrated Precision Reference: 2.5V Full-Scale 10ppm/°C (LTC2637-L) 4.096V Full-Scale 10ppm/°C (LTC2637-H) Maximum INL Error: 2.5LSB (LTC2637-12) Low Noise: 0.75mVP-P 0.1Hz to 200KHz Guaranteed Monotonic Over –40°C to 125°C Temperature Range Selectable Internal or External Reference 2.7V to 5.5V Supply Range (LTC2637-L) Ultralow Crosstalk Between DACs (<3nV•s) Low Power: 100μA per DAC at 3V (LTC2637-L) Power-On-Reset to Zero-Scale/Mid-Scale Double-Buffered Data Latches Tiny 14-Lead 4mm × 3mm DFN and 16-Lead MSOP Packages These DACs communicate via a 2-wire I2C-compatible serial interface. The LTC2637 operates in both the standard mode (clock rate of 100kHz) and the fast mode (clock rate of 400kHz). The LTC2637 incorporates a power-on reset circuit. Options are available for reset to zero-scale or reset to mid-scale in internal reference mode, or reset to mid-scale in external reference mode after power-up. APPLICATIONS n n n n n n Mobile Communications Process Control and Industrial Automation Automatic Test Equipment Portable Equipment Automotive Optical Networking L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5396245, 5859606, 6891433, 6937178, 7414561. BLOCK DIAGRAM Integral Nonlinearity (LTC2637-LZ12) SWITCH INTERNAL REFERENCE REF VREF GND 2 VCC = 3V INTERNAL REF. DAC H VREF REGISTER REGISTER DAC B REGISTER VOUTB REGISTER VREF DAC G REGISTER REGISTER REGISTER DAC C REGISTER VOUTC DAC F (CA2) VOUTF –2 0 1024 2048 CODE 3072 4095 2637 TA01 DAC E VOUTE POWER-ON RESET CAO (CA1) REGISTER REGISTER REGISTER REGISTER DAC D 0 –1 VREF VREF VOUTD VOUTG VREF VREF 1 VOUTH INL (LSB) REGISTER REGISTER DAC A REGISTER VOUTA REGISTER VCC DECODE I2C ADDRESS DECODE SCL SDA I2C INTERFACE 2637 BD ( ) MSOP PACKAGE ONLY 2637fb 1 LTC2637 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VCC) ................................... –0.3V to 6V SCL, SDA ..................................................... –0.3V to 6V VOUTA - VOUTH, CA0, CA1, CA2...................–0.3V to Min(VCC + 0.3V, 6V) REF ...................................–0.3V to Min(VCC + 0.3V, 6V) Operating Temperature Range LTC2637C ................................................ 0°C to 70°C LTC2637I .............................................–40°C to 85°C LTC2637H (Note 3) ............................ –40°C to 125°C Maximum Junction Temperature .......................... 150°C Storage Temperature Range .................. –65°C to 150°C Lead Temperature (Soldering, 10 sec) MS Package ...................................................... 300°C PIN CONFIGURATION TOP VIEW VCC 1 14 GND VOUTA 2 VOUTB 3 13 VOUTH 12 VOUTG 15 VOUTC 4 VOUTD 5 11 VOUTF 10 VOUTE CA0 6 9 REF SCL 7 8 SDA DE PACKAGE 14-LEAD (4mm s 3mm) PLASTIC DFN TOP VIEW VCC 1 VOUTA 2 VOUTB 3 VOUTC 4 VOUTD 5 CA2 6 CA0 7 SCL 8 16 15 14 13 12 11 10 9 GND VOUTH VOUTG VOUTF VOUTE REF CA1 SDA MS PACKAGE 16-LEAD (4mm s 5mm) PLASTIC MSOP TJMAX = 150°C, θJA = 110°C/W TJMAX = 150°C, θJA = 37°C/W EXPOSED PAD (PIN 15) IS GND, MUST BE SOLDERED TO PCB 2637fb 2 LTC2637 ORDER INFORMATION LTC2637 C DE –L Z 12 #TR PBF LEAD FREE DESIGNATOR TAPE AND REEL TR = 2500-Piece Tape and Reel RESOLUTION 12 = 12-Bit 10 = 10-Bit 8 = 8-Bit POWER-ON RESET MI = Reset to Mid-Scale in Internal Reference Mode MX = Reset to Mid-Scale in External Reference Mode Z = Reset to Zero-Scale in Internal Reference Mode FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE L = 2.5V H = 4.096V PACKAGE TYPE DE = 14-Lead DFN MS = 16-Lead MSOP TEMPERATURE GRADE C = Commercial Temperature Range (0°C to 70°C) I = Industrial Temperature Range (–40°C to 85°C) H = Automotive Temperature Range (–40°C to 125°C) PRODUCT PART NUMBER Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2637fb 3 LTC2637 PRODUCT SELECTION GUIDE PART MARKING* POWER-ON RESET TO CODE POWER-ON REFERENCE MODE RESOLUTION VCC PART NUMBER DFN MSOP VFS WITH INTERNAL REFERENCE MAXIMUM INL LTC2637-LMI12 7LMI2 7LMI12 2.5V • (4095/4096) Mid-Scale Internal 12-Bit 2.7V to 5.5V LTC2637-LMI10 7LMI1 7LMI10 2.5V • (1023/1024) Mid-Scale Internal 10-Bit 2.7V to 5.5V ±1LSB LTC2637-LMI8 7LMI8 37LMI8 2.5V • (255/256) Mid-Scale Internal 8-Bit 2.7V to 5.5V ±0.5LSB LTC2637-LMX12 7LMX2 7LMX12 2.5V • (4095/4096) Mid-Scale External 12-Bit 2.7V to 5.5V ±2.5LSB LTC2637-LMX10 7LMX1 7LMX10 2.5V • (1023/1024) Mid-Scale External 10-Bit 2.7V to 5.5V ±1LSB LTC2637-LMX8 7LMX8 37LMX8 2.5V • (255/256) Mid-Scale External 8-Bit 2.7V to 5.5V ±0.5LSB LTC2637-LZ12 7LZ12 37LZ12 2.5V • (4095/4096) Zero-Scale Internal 12-Bit 2.7V to 5.5V ±2.5LSB LTC2637-LZ10 7LZ10 37LZ10 2.5V • (1023/1024) Zero-Scale Internal 10-Bit 2.7V to 5.5V ±1LSB LTC2637-LZ8 37LZ8 637LZ8 2.5V • (255/256) Zero-Scale Internal 8-Bit 2.7V to 5.5V ±0.5LSB LTC2637-HMI12 7HMI2 7HMI12 4.096V • (4095/4096) Mid-Scale Internal 12-Bit 4.5V to 5.5V ±2.5LSB LTC2637-HMI10 7HMI1 7HMI10 4.096V • (1023/1024) Mid-Scale Internal 10-Bit 4.5V to 5.5V ±1LSB 4.096V • (255/256) ±2.5LSB LTC2637-HMI8 7HMI8 37HMI8 Mid-Scale Internal 8-Bit 4.5V to 5.5V ±0.5LSB LTC2637-HMX12 7HMX2 7HMX12 4.096V • (4095/4096) Mid-Scale External 12-Bit 4.5V to 5.5V ±2.5LSB LTC2637-HMX10 7HMX1 7HMX10 4.096V • (1023/1024) Mid-Scale External 10-Bit 4.5V to 5.5V ±1LSB LTC2637-HMX8 7HMX8 37HMX8 4.096V • (255/256) Mid-Scale External 8-Bit 4.5V to 5.5V ±0.5LSB LTC2637-HZ12 7HZ12 37HZ12 4.096V • (4095/4096) Zero-Scale Internal 12-Bit 4.5V to 5.5V ±2.5LSB LTC2637-HZ10 7HZ10 37HZ10 4.096V • (1023/1024) Zero-Scale Internal 10-Bit 4.5V to 5.5V ±1LSB LTC2637-HZ8 37HZ8 637HZ8 4.096V • (255/256) Zero-Scale Internal 8-Bit 4.5V to 5.5V ±0.5LSB *Above options are available in a 14-lead DFN package (LTC2637xDE) or 16-lead MSOP package (LTC2637xMS). 2637fb 4 LTC2637 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2637-LMI12/ LTC2637-LMI10/ LTC2637-LMI8/ LTC2637-LMX12/ LTC2637-LMX10/ LTC2637-LMX8/ LTC2637-LZ12/ LTC2637-LZ10/ LTC2637-LZ8 (VFS = 2.5V) LTC2637-8 SYMBOL PARAMETER DNL CONDITIONS MIN TYP Resolution l 8 Monotonicity VCC = 3V, Internal Reference (Note 4) l 8 Differential Nonlinearity VCC = 3V, Internal Reference (Note 4) l LTC2637-10 LTC2637-12 MAX MIN TYP MAX MIN TYP 10 12 10 MAX Bits 12 ±0.5 UNITS Bits ±0.5 ±1 LSB INL Integral Nonlinearity VCC = 3V, Internal Reference (Note 4) l ±0.05 ±0.5 ±0.2 ±1 ±1 ±2.5 LSB ZSE Zero-Scale Error VCC = 3V, Internal Reference, Code = 0 l 0.5 5 0.5 5 0.5 5 mV VOS Offset Error VCC = 3V, Internal Reference (Note 5) l ±0.5 ±5 ±0.5 ±5 ±0.5 ±5 mV VOSTC VOS Temperature Coefficient VCC =3V, Internal Reference GE Gain Error VCC = 3V, Internal Reference GETC Gain Temperature Coefficient VCC = 3V, Internal Reference (Note 10) C-Grade I-Grade H-Grade Load Regulation Internal Reference, Mid-Scale, VCC = 3V±10%, –5mA ≤ IOUT ≤ 5mA VCC = 5V±10%, (Note 15) –10mA ≤ IOUT ≤ 10mA ROUT DC Output Impedance Internal Reference, Mid-Scale, VCC = 3V±10%, –5mA ≤ IOUT ≤ 5mA VCC = 5V±10%, (Note 15) –10mA ≤ IOUT ≤ 10mA ±10 l ±0.2 ±10 ±0.8 ±0.2 10 10 10 ±10 ±0.8 μV/°C ±0.2 10 10 10 ±0.8 10 10 10 %FSR ppm/°C ppm/°C ppm/°C l 0.009 0.016 0.035 0.064 0.14 0.256 LSB/mA l 0.009 0.016 0.035 0.064 0.14 0.256 LSB/mA l 0.09 0.156 0.09 0.156 0.09 0.156 Ω l 0.09 0.156 0.09 0.156 0.09 0.156 Ω SYMBOL PARAMETER CONDITIONS VOUT DAC Output Span External Reference Internal Reference MIN PSR Power Supply Rejection VCC = 3V±10% or 5V±10% ISC Short Circuit Output Current (Note 6) Sinking Sourcing VFS = VCC = 5.5V Zero-Scale; VOUT shorted to VCC Full-Scale; VOUT shorted to GND l l TYP MAX UNITS 0 to VREF 0 to 2.5 V V –80 dB 27 –28 48 –48 mA mA 5.5 V Power Supply VCC Positive Supply Voltage For Specified Performance l ICC Supply Current (Note 7) VCC = 3V, VREF =2.5V, External Reference VCC = 3V, Internal Reference VCC = 5V, VREF =2.5V, External Reference VCC = 5V, Internal Reference l l l l 0.8 0.9 0.9 1 1.1 1.3 1.3 1.5 mA mA mA mA ISD Supply Current in Power-Down Mode (Note 7) VCC = 5V, C-Grade, I-Grade VCC = 5V, H-Grade l l 1 1 20 30 μA μA 2.7 2637fb 5 LTC2637 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2637-LMI12/ LTC2637-LMI10/ LTC2637-LMI8/ LTC2637-LMX12/ LTC2637-LMX10/ LTC2637-LMX8/ LTC2637-LZ12/ LTC2637-LZ10/ LTC2637-LZ8 (VFS = 2.5V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCC V 200 kΩ Reference Input Input Voltage Range l 1 Resistance l 120 Capacitance IREF Reference Current, Power-Down Mode 160 12 DAC Powered Down l pF 0.005 1.5 μA 1.25 1.26 V Reference Output l Output Voltage 1.24 Reference Temperature Coefficient ±10 ppm/°C Output Impedance 0.5 kΩ Capacitive Load Driving 10 μF 2.5 mA Short Circuit Current VCC = 5.5V; REF Shorted to GND Digital I/O VIL Low Level Input Voltage (SDA and SCL) (Note 14) l –0.5 VIH High Level Input Voltage (SDA and SCL) (Note 11) l 0.7VCC VIL(CAn) Low Level Input Voltage on CAn (n = 0, 1, 2) See Test Circuit 1 l VIH(CAn) High Level Input Voltage on CAn (n = 0, 1, 2) See Test Circuit 1 l RINH Resistance from CAn (n=0, 1,2) to VCC to Set CAn = VCC See Test Circuit 2 l 10 kΩ RINL Resistance from CAn (n=0, 1,2) to GND to Set CAn = GND See Test Circuit 2 l 10 kΩ RINF Resistance from CAn (n=0, 1,2) to VCC or GND to Set CAn = Float See Test Circuit 2 l VOL Low Level Output Voltage Sink Current = 3mA l 0 0.4 V tOF Output Fall Time VO = VIH(MIN) to VO = VIL(MAX), CB = 10pF to 400pF (Note 12) l 20 + 0.1CB 250 ns tSP Pulse Width of Spikes Suppressed by Input Filter l 0 50 ns IIN Input Leakage 0.1VCC ≤ VIN ≤ 0.9VCC l ±1 μA CIN I/O Pin Capacitance (Note 8) l 10 pF 400 pF 10 pF CB Capacitive Load for Each Bus Line l CCAn External Capacitive Load on Address Pin CAn (n=0, 1,2) l 0.3VCC V V 0.15VCC 0.85VCC V V 2 MΩ 2637fb 6 LTC2637 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2637-LMI12/ LTC2637-LMI10/ LTC2637-LMI8/ LTC2637-LMX12/ LTC2637-LMX10/ LTC2637-LMX8/ LTC2637-LZ12/ LTC2637-LZ10/ LTC2637-LZ8 (VFS = 2.5V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS AC Performance tS Settling Time VCC = 3V (Note 9) ±0.39% (±1LSB at 8 Bits) ±0.098% (±1LSB at 10 Bits) ±0.024% (±1LSB at 12 Bits) Voltage Output Slew Rate Capacitive Load Driving en 3.5 4.1 4.5 μs μs μs 1.0 V/μs 500 pF 2.1 nV•s 1 DAC held at FS, 1 DAC Switched 0 to FS 2.6 nV•s External Reference 320 kHz Output Voltage Noise Density At f = 1kHz, External Reference At f = 10kHz, External Reference At f = 1kHz, Internal Reference At f = 10kHz, Internal Reference 180 160 200 180 nV/√Hz nV/√Hz nV/√Hz nV/√Hz Output Voltage Noise 0.1Hz to 10Hz, External Reference 0.1Hz to 10Hz, Internal Reference 0.1Hz to 200kHz, External Reference 0.1Hz to 200kHz, Internal Reference 35 40 680 730 μVP-P μVP-P μVP-P μVP-P Glitch Impulse At Mid-Scale Transition DAC-to-DAC Crosstalk Multiplying Bandwidth TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V. (See Figure 1) (Note 13) LTC2637-LMI12/ LTC2637-LMI10/ LTC2637-LMI8/ LTC2637-LMX12/ LTC2637-LMX10/ LTC2637-LMX8/ LTC2637-LZ12/ LTC2637-LZ10/ LTC2637-LZ8 (VFS = 2.5V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 400 kHz fSCL SCL Clock Frequency l tHD(STA) Hold Time (Repeated) Start Condition l 0.6 μs tLOW Low Period of the SCL Clock Pin l 1.3 μs tHIGH High Period of the SCL Clock Pin l 0.6 μs tSU(STA) Set-Up Time for a Repeated Start Condition l 0.6 μs 0 tHD(DAT) Data Hold Time l 0 tSU(DAT) Data Set-Up Time l 100 0.9 μs ns tr Rise Time of Both SDA and SCL Signals (Note 12) l 20 + 0.1CB 300 ns tf Fall Time of Both SDA and SCL Signals (Note 12) l 20 + 0.1CB 300 ns tSU(STO) Set-Up Time for Stop Condition l 0.6 μs tBUF Bus Free Time Between a Stop and Start Condition l 1.3 μs 2637fb 7 LTC2637 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2637-HMI12/ LTC2637-HMI10/ LTC2637-HMI8/ LTC2637-HMX12/ LTC2637-HMX10/ LTC2637-HMX8/ LTC2637-HZ12/ LTC2637-HZ10/ LTC2637-HZ8 (VFS =4.096V) LTC2637-8 SYMBOL PARAMETER CONDITIONS MIN Resolution DNL TYP LTC2637-10 MAX MIN TYP LTC2637-12 MAX MIN TYP MAX UNITS l 8 10 12 Bits 8 10 12 Bits Monotonicity VCC = 5V, Internal Reference (Note 4) l Differential Nonlinearity VCC = 5V, Internal Reference (Note 4) l ±0.5 ±0.5 ±1 LSB INL Integral Nonlinearity VCC = 5V, Internal Reference (Note 4) l ±0.05 ±0.5 ±0.2 ±1 ±1 ±2.5 LSB ZSE Zero-Scale Error VCC = 5V, Internal Reference, Code = 0 l 0.5 5 0.5 5 0.5 5 mV VOS Offset Error VCC = 5V, Internal Reference (Note 5) l ±0.5 ±5 ±0.5 ±5 ±0.5 ±5 mV VOSTC VOS Temperature Coefficient VCC = 5V, Internal Reference ±10 l ±10 ±10 μV/°C GE Gain Error VCC = 5V, Internal Reference GETC Gain Temperature Coefficient VCC = 5V, Internal Reference (Note 10) C-Grade I-Grade H-Grade Load Regulation VCC = 5V±10%, (Note 15) Internal Reference, Mid-Scale, –10mA ≤ IOUT ≤ 10mA l 0.006 0.01 0.022 0.04 0.09 DC Output Impedance VCC = 5V±10%, (Note 15) Internal Reference, Mid-Scale, –10mA ≤ IOUT ≤ 10mA l 0.09 0.156 0.09 0.156 0.09 0.156 ROUT ±0.2 ±0.8 ±0.2 10 10 10 SYMBOL PARAMETER CONDITIONS VOUT DAC Output Span External Reference Internal Reference ±0.8 ±0.2 10 10 10 10 10 10 MIN PSR Power Supply Rejection VCC = 5V±10% ISC Short Circuit Output Current (Note 6) Sinking Sourcing VFS = VCC = 5.5V Zero-Scale; VOUT Shorted to VCC Full-Scale; VOUT Shorted to GND l l ±0.8 TYP %FSR ppm/°C ppm/°C ppm/°C 0.16 LSB/mA MAX Ω UNITS 0 to VREF 0 to 4.096 V V –80 dB 27 –28 48 –48 mA mA 5.5 V Power Supply VCC Positive Supply Voltage For Specified Performance l ICC Supply Current (Note 7) VCC = 5V, VREF = 4.096V, External Reference VCC = 5V, Internal Reference l l 1.0 1.1 1.3 1.5 mA mA ISD Supply Current in Power-Down Mode (Note 7) VCC = 5V, C-Grade, I-Grade VCC = 5V, H-Grade l l 1 1 20 30 μA μA VCC V 200 kΩ 4.5 Reference Input Input Voltage Range l 1 Resistance l 120 Capacitance IREF Reference Current, Power-Down Mode 160 12 DAC Powered Down l pF 0.005 1.5 μA 2.048 2.064 V Reference Output Output Voltage Reference Temperature Coefficient l 2.032 ±10 ppm/°C 2637fb 8 LTC2637 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2637-HMI12/ LTC2637-HMI10/ LTC2637-HMI8/ LTC2637-HMX12/ LTC2637-HMX10/ LTC2637-HMX8/ LTC2637-HZ12/ LTC2637-HZ10/ LTC2637-HZ8 (VFS =4.096V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Output Impedance 0.5 kΩ Capacitive Load Driving 10 μF 4 mA Short Circuit Current VCC = 5.5V; REF Shorted to GND Digital I/O VIL Low Level Input Voltage (SDA and SCL) (Note 14) l –0.5 VIH High Level Input Voltage (SDA and SCL) (Note 11) l 0.7VCC VIL(CAn) Low Level Input Voltage on CAn (n = 0, 1, 2) See Test Circuit 1 l VIH(CAn) High Level Input Voltage on CAn (n = 0, 1, 2) See Test Circuit 1 l RINH Resistance from CAn (n=0, 1,2) to VCC to Set CAn = VCC See Test Circuit 2 l 10 kΩ RINL Resistance from CAn (n=0, 1,2) to GND to Set CAn = GND See Test Circuit 2 l 10 kΩ RINF Resistance from CAn (n=0, 1,2) to VCC or GND to Set CAn = Float See Test Circuit 2 l 2 VOL Low Level Output Voltage Sink Current = 3mA l 0 0.4 V tOF Output Fall Time VO = VIH(MIN) to VO = VIL(MAX), CB = 10pF to 400pF (Note 12) l 20 + 0.1CB 250 ns tSP Pulse Width of Spikes Suppressed by Input Filter l 0 50 ns IIN Input Leakage 0.1VCC ≤ VIN ≤ 0.9VCC l ±1 μA CIN I/O Pin Capacitance (Note 8) l 10 pF 400 pF 10 pF CB Capacitive Load for Each Bus Line l CCAn External Capacitive Load on Address Pin CAn (n=0, 1,2) l 0.3VCC V V 0.15VCC 0.85VCC V V MΩ AC Performance tS Settling Time VCC = 3V (Note 9) ±0.39% (±1LSB at 8 Bits) ±0.098% (±1LSB at 10 Bits) ±0.024% (±1LSB at 12 Bits) Voltage Output Slew Rate 1 Capacitive Load Driving en 3.9 4.3 5 500 μs μs μs V/μs pF Glitch Impulse At Mid-Scale Transition 3 nV•s DAC-to-DAC Crosstalk 1 DAC held at FS, 1 DAC Switched 0 to FS Multiplying Bandwidth External Reference 3 nV•s 320 kHz Output Voltage Noise Density At f = 1kHz, External Reference At f = 10kHz, External Reference At f = 1kHz, Internal Reference At f = 10kHz, Internal Reference 180 160 250 230 nV/√Hz nV/√Hz nV/√Hz nV/√Hz Output Voltage Noise 0.1Hz to 10Hz, External Reference 0.1Hz to 10Hz, Internal Reference 0.1Hz to 200kHz, External Reference 0.1Hz to 200kHz, Internal Reference 35 50 680 750 μVP-P μVP-P μVP-P μVP-P 2637fb 9 LTC2637 TIMING CHARACTERISTICS The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC =4.5V to 5.5V. (See Figure 1) (Note 13). LTC2637-HMI12/ LTC2637-HMI10/ LTC2637-HMI8/ LTC2637-HMX12/ LTC2637-HMX10/ LTC2637-HMX8/ LTC2637-HZ12/ LTC2637-HZ10/ LTC2637-HZ8 (VFS =4.096V) SYMBOL PARAMETER fSCL SCL Clock Frequency CONDITIONS l MIN 0 TYP MAX UNITS 400 kHz tHD(STA) Hold Time (Repeated) Start Condition l 0.6 μs tLOW Low Period of the SCL Clock Pin l 1.3 μs tHIGH High Period of the SCL Clock Pin l 0.6 μs tSU(STA) Set-Up Time for a Repeated Start Condition l 0.6 tHD(DAT) Data Hold Time l 0 tSU(DAT) Data Set-Up Time l 100 μs 0.9 μs ns tr Rise Time of Both SDA and SCL Signals (Note 12) l 20 + 0.1CB 300 ns tf Fall Time of Both SDA and SCL Signals (Note 12) l 20 + 0.1CB 300 ns tSU(STO) Set-Up Time for Stop Condition l 0.6 μs tBUF Bus Free Time Between a Stop and Start Condition l 1.3 μs Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltages are with respect to GND. Note 3: High temperatures degrade operating lifetimes. Operating lifetime is derated at temperatures greater than 105°C. Operating at temperatures above 110°C and with VCC > 4V requires VCC slew rates to be no greater than 110mV/ms. Note 4: Linearity and monotonicity are defined from code kL to code 2N–1, where N is the resolution and kL is given by kL = 0.016•(2N/ VFS), rounded to the nearest whole code. For VFS = 2.5V and N = 12, kL = 26 and linearity is defined from code 26 to code 4,095. For VFS = 4.096V and N = 12, kL = 16 and linearity is defined from code 16 to code 4,095. Note 5: Inferred from measurement at code 16 (LTC2637-12), code 4 (LTC2637-10) or code 1 (LTC2637-8), and at full-scale. Note 6: This IC includes current limiting that is intended to protect the device during momentary overload conditions. Junction temperature can exceed the rated maximum during current limiting. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 7: Digital inputs at 0V or VCC. Note 8: Guaranteed by design and not production tested. Note 9: Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. Load is 2kΩ in parallel with 100pF to GND. Note 10: Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. Note 11: Maximum VIH = VCC(MAX) + 0.5V. Note 12: CB = Capacitance of one bus line in pF. Note 13: All values refer to VIH = VIN(MIN) and VIL = VIL(MAX) levels. Note 14: Minimum VIL exceeds Absolute Maximum rating. This condition won’t damage the IC, but could degrade performance. Note 15: Thermal resistance of MSOP package limits IOUT to –5mA ≤ IOUT ≤ 5mA for H-grade MSOP parts and VCC = 5V ±10%. 2637fb 10 LTC2637 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. LTC2637-L12 (Internal Reference, VFS = 2.5V) Integral Nonlinearity (INL) Differential Nonlinearity (DNL) 1.0 1.0 VCC = 3V VCC = 3V 0.5 DNL (LSB) INL (LSB) 0.5 0 –0.5 –1.0 0 –0.5 1024 0 2048 CODE 3072 –1.0 4095 1024 0 3072 2048 CODE 4095 2637 G01 INL vs Temperature Reference Output Voltage vs Temperature DNL vs Temperature 1.0 1.0 VCC = 3V INL (POS) VCC = 3V 0.5 INL (NEG) –0.5 1.255 DNL (POS) VREF (V) 0 –1.0 –50 –25 1.260 VCC = 3V DNL (LSB) 0.5 INL (LSB) 2637 G02 0 DNL (NEG) –0.5 0 25 50 75 100 125 150 TEMPERATURE (°C) 1.245 –1.0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2637 G03 1.240 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2637 G04 Settling to ±1LSB Rising 2637 G05 Settling to ±1LSB Falling 9TH CLOCK OF 3RD DATA BYTE SCL 5V/DIV 1.250 3/4 SCALE TO 1/4 SCALE STEP VCC = 3V, VFS = 2.5V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS VOUT 1LSB/DIV 4.5μs 3.6μs VOUT 1LSB/DIV 1/4 SCALE TO 3/4 SCALE STEP VCC = 3V, VFS = 2.5V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 2μs/DIV 2637 G06 SCL 5V/DIV 9TH CLOCK OF 3RD DATA BYTE 2μs/DIV 2637 G07 2637fb 11 LTC2637 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. LTC2637-H12 (Internal Reference, VFS = 4.096V) Integral Nonlinearity (INL) Differential Nonlinearity (DNL) 1.0 1.0 VCC = 5V VCC = 5V 0.5 DNL (LSB) INL (LSB) 0.5 0 –0.5 –1.0 0 –0.5 1024 0 2048 CODE 3072 –1.0 4095 0 1024 3072 2048 CODE 4095 2637 G08 INL vs Temperature Reference Output Voltage vs Temperature DNL vs Temperature 1.0 2.068 1.0 VCC = 5V INL (POS) 2.058 INL (NEG) –0.5 DNL (POS) VREF (V) DNL (LSB) 0.5 0 –1.0 –50 –25 VCC = 5V VCC = 5V 0.5 INL (LSB) 2637 G09 0 DNL (NEG) 2.038 –0.5 0 25 50 75 100 125 150 TEMPERATURE (°C) –1.0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2637 G10 2.028 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2637 G12 2637 G11 Settling to ±1LSB Rising Settling to ±1LSB Falling 3/4 SCALE TO 1/4 SCALE STEP VCC = 5V, VFS = 4.095V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 9TH CLOCK OF 3RD DATA BYTE SCL 5V/DIV 2.048 VOUT 1LSB/DIV 5μs 4.1μs VOUT 1LSB/DIV 1/4 SCALE TO 3/4 SCALE STEP VCC = 5V, VFS = 4.095V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 2μs/DIV 2637 G13 SCL 5V/DIV 9TH CLOCK OF 3RD DATA BYTE 2μs/DIV 2637 G14 2637fb 12 LTC2637 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. LTC2637-10 Integral Nonlinearity (INL) Differential Nonlinearity (DNL) 1.0 1.0 VCC = 3V VFS = 2.5V INTERNAL REF. VCC = 3V VFS = 2.5V INTERNAL REF. 0.5 DNL (LSB) INL (LSB) 0.5 0 –0.5 –1.0 0 –0.5 256 0 768 512 CODE –1.0 1023 256 0 768 512 CODE 2637 G15 1023 2637 G16 LTC2637-8 Integral Nonlinearity (INL) Differential Nonlinearity (DNL) 0.50 0.50 VCC = 3V VFS = 2.5V INTERNAL REF. VCC = 3V VFS = 2.5V INTERNAL REF. 0.25 DNL (LSB) INL (LSB) 0.25 0 –0.25 –0.50 0 –0.25 64 0 192 128 CODE –0.50 255 64 0 192 128 CODE 2637 G17 255 2637 G18 LTC2637 Load Regulation Current Limiting 10 6 VCC = 5V (LTC2637-H) VCC = 5V (LTC2637-L) VCC = 3V (LTC2637-L) 0.15 2 $VOUT (V) $VOUT (mV) VCC = 5V (LTC2637-H) VCC = 5V (LTC2637-L) VCC = 3V (LTC2637-L) 2 0.10 4 0 –2 –4 0.05 0 –0.05 1 0 –1 –0.01 –6 INTERNAL REF. CODE = MID-SCALE –8 –10 –30 3 OFFSET ERROR (mV) 8 Offset Error vs Temperature 0.20 –20 –10 0 10 IOUT (mA) 20 30 2637 G19 –2 –0.15 –0.20 –30 INTERNAL REF. CODE = MID-SCALE –20 –10 0 10 IOUT (mA) 20 30 2637 G20 –3 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2637 G21 2637fb 13 LTC2637 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. LTC2637 Large-Signal Response Mid-Scale Glitch Impulse Power-On Reset Glitch LTC2637-L 9TH CLOCK OF 3RD DATA BYTE SCL 5V/DIV VCC 2V/DIV VOUT 0.5V/DIV LTC2637-H12 VCC = 5V, 3nV•s TYP VOUT 5mV/DIV ZERO-SCALE VOUT 5mV/DIV LTC2637-L12 VCC = 3V, 2.1nV•s TYP VFS = VCC = 5V 1/4 SCALE to 3/4 SCALE 2μs/DIV 2637 G23 2μs/DIV 200μs/DIV 2637 G22 2637 G24 Headroom at Rails vs Output Current Exiting Power-Down to Mid-Scale Power-On Reset to Mid-Scale 5.0 5V SOURCING 4.5 9TH CLOCK OF 3RD DATA BYTE SCL 5V/DIV 4.0 VCC 2V/DIV VOUT (V) 3.5 3V (LTC2637-L) SOURCING 3.0 LTC2637-H 2.5 2.0 1.5 DACs A TO G IN POWER-DOWN MODE 5V SINKING 1.0 0 VOUT 0.5V/DIV 3V (LTC2637-L) SINKING 0.5 0 1 2 3 4 5 6 IOUT (mA) VOUT 0.5V/DIV 7 8 9 2637 G26 5μs/DIV 10 LTC2637-L LTC2637H VCC = 5V INTERNAL REF 200μs/DIV 2637 G27 2637 G25 Supply Current vs Logic Voltage DAC to DAC Crosstalk (Dynamic) Multiplying Bandwidth 2 1.8 SWEEP SDA, SCL, BETWEEN 0V AND VCC 1.6 9TH CLOCK OF 3RD DATA BYTE SCL LTC2637-H12 5V/DIV VCC = 5V, 3nV•s TYP CREF = 0.1μF 1 DAC SWITCH 0 TO FS 2V/DIV VCC = 5V 1.2 1.0 VCC = 3V (LTC2637-L) –4 –6 dB 1.4 ICC (mA) 0 –2 –12 VOUT 2mV/DIV 0.8 –8 –10 VCC = 5V VREF(DC) = 2V VREF(AC) = 0.2VP-P CODE = FULL-SCALE –14 –16 0.6 0 1 2 3 LOGIC VOLTAGE (V) 4 5 2637 G28 2μs/DIV 2637 G29 –18 1k 10k 100k FREQUENCY (Hz) 1M 2637 G30 2637fb 14 LTC2637 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. LTC2637 Gain Error vs. Temperature Noise Voltage vs. Frequency 500 NOISE VOLTAGE (nV/√Hz) GAIN ERROR (%FSR) 1.0 0.5 0 –0.5 400 VCC = 5V CODE = MID-SCALE INTERNAL REF. 300 LTC2637-H 200 LTC2637-L 100 –1.0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 0 100 1k 100k 10k FREQUENCY (Hz) 2637 G31 2637 G32 0.1Hz to 10Hz Voltage Noise Gain Error vs Reference Input 1.0 VCC = 5V, VFS = 2.5V CODE = MID-SCALE INTERNAL REF. VCC = 5.5V 0.8 GAIN ERROR OF 8 CHANNELS 0.6 GAIN ERROR (%FSR) 1M 0.4 0.2 10μV/DIV 0 –0.2 –0.4 –0.6 –0.8 –1.0 1 1.5 2 2.5 3 3.5 4 4.5 REFERENCE VOLTAGE (V) 5 5.5 1s/DIV 2637 G35 2637 G34 2637fb 15 LTC2637 PIN FUNCTIONS (DFN/MSOP) VCC (Pin 1/Pin 1): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V (LTC2637-L) or 4.5V ≤ VCC ≤ 5.5V (LTC2637-H). Bypass to GND with a 0.1μF capacitor. VOUTA to VOUTH (Pins 2–5, 10–13/Pins 2–5, 12–15): DAC Analog Voltage Outputs. CAO (Pin 6/Pin 7): Chip Address Bit 0. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (See Tables 1 and 2). SCL (Pin 7/Pin 8): Serial Clock Input Pin. Data is shifted into the SDA pin at the rising edges of the clock. This high impedance pin requires a pull-up resistor or current source to VCC. SDA (Pin 8/Pin 9): Serial Data Bidirectional Pin. Data is shifted into the SDA pin and acknowledged by the SDA pin. This pin is high impedance while data is shifted in. Open drain N-channel output during acknowledgment. SDA requires a pull-up resistor or current source to VCC. REF (Pin 9/Pin 11): Reference Voltage Input or Output. When External Reference mode is selected, REF is an input (1V ≤ VREF ≤ VCC) where the voltage supplied sets the full-scale DAC output voltage. When Internal Reference is selected, the 10ppm/°C 1.25V (LTC2637-L) or 2.048V (LTC2637-H) internal reference (half full-scale) is available at the pin. This output may be bypassed to GND with up to 10μF, and must be buffered when driving external DC load current. GND (Pin 14/Pin 16): Ground. CA2 (Pin 6, MSOP only): Chip Address Bit 2. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (See Table 1). CA1 (Pin 10, MSOP only): Chip Address Bit 1. Tie this pin to VCC, GND or leave it floating to select an I2C slave address for the part (See Table 1). Exposed Pad (Pin 15, DFN Only): Ground. Must be soldered to PCB Ground. 2637fb 16 LTC2637 BLOCK DIAGRAM SWITCH INTERNAL REFERENCE REF VREF GND REGISTER REGISTER DAC A REGISTER VOUTA REGISTER VCC DAC H REGISTER REGISTER DAC B REGISTER REGISTER VOUTB DAC G REGISTER REGISTER DAC C REGISTER REGISTER VOUTC DAC F VOUTF VREF REGISTER REGISTER DAC D REGISTER VOUTD REGISTER VREF DAC E VOUTE POWER-ON RESET CAO (CA2) VOUTG VREF VREF (CA1) VOUTH VREF VREF DECODE I2C ADDRESS DECODE SCL SDA I2C INTERFACE 2637 BD ( ) MSOP PACKAGE ONLY TEST CIRCUITS Test Circuit 1 Test Circuit 2 VDD 100Ω CAn VIH(CAn)/VIL(CAn) RINH/RINL/RINF 2637 TC01 CAn GND 2637 TC01b 2637fb 17 18 SCL START A5 2 A6 1 3 A4 4 A3 5 A2 SLAVE ADDRESS 6 A1 tf 7 A0 SCL SDA tHD(STA) tHD(DAT) tr tHIGH tSU(DAT) tf tSU(STA) 8 W 9 ACK 1 C3 2 C2 3 C1 5 A3 6 A2 7 A1 8 A0 9 ACK 1 2 3 4 5 2ND DATA BYTE tHD(STA) Figure 2. Typical LTC2637 Write Transaction 4 C0 1ST DATA BYTE Sr Figure 1. I2C Timing ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS S tLOW 6 7 tSU(STO) tSP tr 8 P 9 ACK tBUF 1 S 2 2637 F01 3 4 5 X 3RD DATA BYTE 6 X 7 X 8 X 9 ACK 2637 F02 LTC2637 TIMING DIAGRAM 2637fb LTC2637 OPERATION The LTC2637 is a family of octal voltage output DACs in 14-lead DFN and 16-lead MSOP packages. Each DAC can operate rail-to-rail using an external reference, or with its full-scale voltage set by an integrated reference. Eighteen combinations of accuracy (12-, 10-, and 8-bit), power-on reset value (zero-scale, mid-scale in internal reference mode, or mid-scale in external reference mode), and fullscale voltage (2.5V or 4.096V) are available. The LTC2637 is controlled using a 2-wire I2C interface. Power-On Reset The LTC2637-HZ/ LTC2637-LZ clear the output to zero-scale when power is first applied, making system initialization consistent and repeatable. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC2637 contains circuitry to reduce the power-on glitch: the analog output typically rises less than 5mV above zeroscale during power on. In general, the glitch amplitude decreases as the power supply ramp time is increased. See “Power-On Reset Glitch” in the Typical Performance Characteristics section. Transfer Function The digital-to-analog transfer function is: ⎛ k ⎞ VOUT(IDEAL) = ⎜ N ⎟ VREF ⎝2 ⎠ where k is the decimal equivalent of the binary DAC input code, N is the resolution, and VREF is either 2.5V (LTC2637-LMI/LTC2637-LMX/LTC2637-LZ) or 4.096V (LTC2637-HMI/LTC2637-HMX/LTC2637-HZ) when in Internal Reference mode, and the voltage at REF when in External Reference mode. I2C Serial Interface The LTC2637 communicates with a host using the standard 2-wire I2C interface. The timing diagrams (Figures 1 and 2) show the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. The value of these pull-up resistors is dependent on the power supply and can be obtained from the I2C specifications. For an I2C bus operating in the fast mode, an active pull-up will be necessary if the bus capacitance is greater than 200pF. The LTC2637-HMI/LTC2637-HMX/LTC2637-LMI/ LTC2637-LMX provide an alternative reset, setting the output to mid-scale when power is first applied. The LTC2637-LMI and LTC2637-HMI power up in internal reference mode, with the output set to a mid-scale voltage of 1.25V and 2.048V, respectively. The LTC2637-LMX and LTC2637-HMX power-up in external reference mode, with the output set to mid-scale of the external reference. Default reference mode selection is described in the Reference Modes section. The LTC2637 is a receive-only (slave) device. The master can write to the LTC2637. The LTC2637 will not acknowledge (NAK) a read request from the master. Power Supply Sequencing When the master has finished communicating with the slave, it issues a STOP condition. A STOP condition is generated by transitioning SDA from low to high while SCL is high. The bus is then free for communication with another I2C device. The voltage at REF (Pin 9, DFN; Pin 11, MSOP) must be kept within the range –0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum Ratings). Particular care should be taken to observe these limits during power supply turnon and turn-off sequences, when the voltage at VCC is in transition. START (S) and STOP (P) Conditions When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a communication to a slave device by transmitting a START condition. A START condition is generated by transitioning SDA from high to low while SCL is high. 2637fb 19 LTC2637 OPERATION Acknowledge The Acknowledge (ACK) signal is used for handshaking between the master and the slave. An ACK (active LOW) generated by the slave lets the master know that the latest byte of information was properly received. The ACK related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the ACK clock pulse. The slave-receiver must pull down the SDA bus line during the ACK clock pulse so that it remains a stable LOW during the HIGH period of this clock pulse. The LTC2637 responds to a write by a master in this manner but does not acknowledge a read operation; in that case, SDA is retained HIGH during the period of the ACK clock pulse. Chip Address The state of pins CA0, CA1 and CA2 (CA1 and CA2 are only available on the MSOP package) determines the slave address of the part. These pins can each be set to any one of three states: VCC, GND or float. This results in 27 (MSOP Package) or 3 (DFN Package) selectable addresses for the part. The slave address assignments are shown in Tables 1 and 2. In addition to the address selected by the address pins, the part also responds to a global address. This address allows a common write to all LTC2637 parts to be accomplished using one 3-byte write transaction on the I2C bus. The global address, listed at the end of Tables 1 and 2, is a 7-bit hardwired address not selectable by CA0, CA1 or CA2. If another global address is required, please consult the factory. The maximum capacitive load allowed on the address pins (CA0, CA1 and CA2) is 10pF, as these pins are driven during address detection to determine if they are floating. Table 1. Slave Address Map (MSOP Package) CA2 CA1 CA0 A6 A5 A4 A3 A2 A1 A0 GND GND GND 0 0 1 0 0 0 0 GND GND FLOAT 0 0 1 0 0 0 1 GND GND VCC 0 0 1 0 0 1 0 GND FLOAT GND 0 0 1 0 0 1 1 GND FLOAT FLOAT 0 1 0 0 0 0 0 GND FLOAT VCC 0 1 0 0 0 0 1 GND VCC GND 0 1 0 0 0 1 0 GND VCC FLOAT 0 1 0 0 0 1 1 GND VCC VCC 0 1 1 0 0 0 0 FLOAT GND GND 0 1 1 0 0 0 1 FLOAT GND FLOAT 0 1 1 0 0 1 0 FLOAT GND VCC 0 1 1 0 0 1 1 FLOAT FLOAT GND 1 0 0 0 0 0 0 FLOAT FLOAT FLOAT 1 0 0 0 0 0 1 FLOAT FLOAT VCC 1 0 0 0 0 1 0 FLOAT VCC GND 1 0 0 0 0 1 1 FLOAT VCC FLOAT 1 0 1 0 0 0 0 FLOAT VCC VCC 1 0 1 0 0 0 1 VCC GND GND 1 0 1 0 0 1 0 VCC GND FLOAT 1 0 1 0 0 1 1 VCC GND VCC 1 1 0 0 0 0 0 VCC FLOAT GND 1 1 0 0 0 0 1 VCC FLOAT FLOAT 1 1 0 0 0 1 0 VCC FLOAT VCC 1 1 0 0 0 1 1 VCC VCC GND 1 1 1 0 0 0 0 VCC VCC FLOAT 1 1 1 0 0 0 1 VCC VCC VCC 1 1 1 0 0 1 0 1 1 1 0 0 1 1 GLOBAL ADDRESS Table 2. Slave Address Map (DFN Package) CA0 A6 A5 A4 A3 A2 A1 A0 GND 0 0 1 0 0 0 0 FLOAT 0 0 1 0 0 0 1 VCC 0 0 1 0 0 1 0 GLOBAL ADDRESS 1 1 1 0 0 1 1 2637fb 20 LTC2637 OPERATION Write Word Protocol The master initiates communication with the LTC2637 with a START condition and a 7-bit slave address followed by the Write bit (W) = 0. The LTC2637 acknowledges by pulling the SDA pin low at the 9th clock if the 7-bit slave address matches the address of the part (set by CA0, CA1 or CA2) or the global address. The master then transmits three bytes of data. The LTC2637 acknowledges each byte of data by pulling the SDA line low at the 9th clock of each data byte transmission. After receiving three complete bytes of data, the LTC2637 executes the command specified in the 24-bit input word. If more than three data bytes are transmitted after a valid 7-bit slave address, the LTC2637 does not acknowledge the extra bytes of data (SDA is high during the 9th clock). The format of the three data bytes is shown in Figure 3. The first byte of the input word consists of the 4-bit command, followed by the 4-bit DAC address. The next two bytes contain the 16-bit data word, which consists of the 12-, 10- or 8-bit input code, MSB to LSB, followed by 4, 6 or 8 don’t-care bits (LTC2637-12, LTC2637-10 and LTC2637-8, respectively). A typical LTC2637 write transaction is shown in Figure 4. The command bit assignments (C3-C0) and address (A3A0) assignments are shown in Tables 3 and 4. The first four commands in the table consist of write and update operations. A write operation loads a 16-bit data word from the 32-bit shift register into the input register. In an update operation, the data word is copied from the input register to the DAC register. Once copied into the DAC register, the data word becomes the active 12-, 10-, or 8-bit input code, and is converted to an analog voltage at the DAC output. Write to and Update combines the first two commands. The Update operation also powers up the DAC if it had been in power-down mode. The data path and registers are shown in the Block Diagram. Table 3. Command Codes COMMAND* C3 C2 C1 C0 0 0 0 0 Write to Input Register n 0 0 0 1 Update (Power Up) DAC Register n 0 0 1 0 Write to Input Register n, Update (Power Up) All 0 0 1 1 Write to and Update (Power Up) DAC Register n 0 1 0 0 Power Down n 0 1 0 1 Power Down Chip (All DAC’s and Reference) 0 1 1 0 Select Internal Reference (Power Up Reference) 0 1 1 1 Select External Reference (Power Down Internal Reference) 1 1 1 1 No Operation *Command codes not shown are reserved and should not be used. Table 4. Address Codes ADDRESS (n)* A3 A2 A1 A0 0 0 0 0 DAC A 0 0 0 1 DAC B 0 0 1 0 DAC C 0 0 1 1 DAC D 0 1 0 0 DAC E 0 1 0 1 DAC F 0 1 1 0 DAC G 0 1 1 1 DAC H 1 1 1 1 All DACs *Address codes not shown are reserved and should not be used. Reference Modes For applications where an accurate external reference is either not available, or not desirable due to limited space, the LTC2637 has a user-selectable, integrated reference. The integrated reference voltage is internally amplified by 2x to provide the full-scale DAC output voltage range. 2637fb 21 LTC2637 OPERATION Write Word Protocol for LTC2637 S SLAVE ADDRESS W ACK 1ST DATA BYTE ACK 2ND DATA BYTE ACK 3RD DATA BYTE ACK INPUT WORD Input Word (LTC2637-12) C3 C2 C1 C0 A3 A2 P A1 A1 D11 D10 D9 1ST DATA BYTE D8 D7 D6 D5 D4 D3 D2 D1 2ND DATA BYTE D0 X X X X X X X X 3RD DATA BYTE Input Word (LTC2637-10) C3 C2 C1 C0 A3 A2 A1 A0 D9 D8 1ST DATA BYTE D7 D6 D5 D4 D3 D2 D1 D0 X 2ND DATA BYTE X X X 3RD DATA BYTE Input Word (LTC2637-8) C3 C2 C1 C0 A3 A2 1ST DATA BYTE A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 X X X 2ND DATA BYTE X X X 3RD DATA BYTE 2637 F03 Figure 3. Command and Data Input Format The LTC2637-LMI/ LTC2637-LMX/ LTC2637-LZ provides a full-scale output of 2.5V. The LTC2637-HMI/ LTC2637HMX/ LTC2637-HZ provides a full-scale output of 4.096V. The internal reference can be useful in applications where the supply voltage is poorly regulated. Internal Reference mode can be selected by using command 0110b, and is the power-on default for LTC2637-HZ/ LTC2637-LZ, as well as for LTC2637-HMI/ LTC2637-LMI. The 10ppm/°C, 1.25V (LTC2637-LMI/ LTC2637-LMX/ LTC2637-LZ) or 2.048V (LTC2637-HMI/ LTC2637-HMX/ LTC2637-HZ) internal reference is available at the REF pin. Adding bypass capacitance to the REF pin will improve noise performance; and up to 10μF can be driven without oscillation. The REF output must be buffered when driving an external DC load current. Alternatively, the DAC can operate in External Reference mode using command 0111b. In this mode, an input voltage supplied externally to the REF pin provides the reference (1V ≤ VREF ≤ VCC) and the supply current is reduced. The external reference voltage supplied sets the full-scale DAC output voltage. External Reference mode is the power-on default for LTC2637-HMX/ LTC2637-LMX. The reference mode of LTC2637-HZ/ LTC2637-LZ/ LTC2637HMI/ LTC2637-LMI (internal reference power-on default), can be changed by software command after power up. The same is true for LTC2637-HMX/ LTC2637-LMX (external reference power-on default). Power-Down Mode For power-constrained applications, power-down mode can be used to reduce the supply current whenever less than eight DAC outputs are needed. When in power-down, the buffer amplifiers, bias circuits, and integrated reference circuits are disabled, and draw essentially zero current. The DAC outputs are put into a high-impedance state, and the output pins are passively pulled to ground through individual 200kΩ resistors. Input and DAC register contents are not disturbed during power down. Any DAC channel or combination of channels can be put into power-down mode by using command 0100b in combination with the appropriate DAC address, (n). The supply current is reduced approximately 10% for each DAC powered down. The integrated reference is automatically powered down when external reference is selected using 2637fb 22 LTC2637 OPERATION command 0111b. In addition, all the DAC channels and the integrated reference together can be put into powerdown mode using Power Down Chip command 0101b. When the integrated reference and all DAC channels are in power-down mode, the REF pin becomes high impedance (typically > 1GΩ). For all power-down commands the 16-bit data word is ignored. Normal operation resumes after executing any command that includes a DAC update, (as shown in Table 1). The selected DAC is powered up as its voltage output is updated. When a DAC which is in a powered-down state is powered up and updated, normal settling is delayed. If less than eight DACs are in a powered-down state prior to the update command, the power-up delay time is 10μs. However, if all eight DACs and the integrated reference are powered down, then the main bias generation circuit block has been automatically shut down in addition to the DAC amplifiers and reference buffers. In this case, the power up delay time is 12μs. The power-up of the integrated reference depends on the command that powered it down. If the reference is powered down using the Select External Reference Command (0111b), then it can only be powered back up using Select Internal Reference Command (0110b). However, if the reference was powered down using Power Down Chip Command (0101b), then in addition to Select Internal Reference Command (0110b), any command that powers up the DACs will also power up the integrated reference. Voltage Output The LTC2637’s DAC output integrated rail-to-rail amplifiers have guaranteed load regulation when sourcing or sinking up to 10mA at 5V, and 5mA at 3V. Load regulation is a measure of the amplifier’s ability to maintain the rated voltage accuracy over a wide range of load current. The measured change in output voltage per change in forced load current is expressed in LSB/mA. DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to ohms. The amplifier’s DC output impedance is 0.1Ω when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 50Ω typical channel resistance of the output devices (e.g., when sinking 1mA, the minimum output voltage is 50Ω • 1mA, or 50mV). See the graph “Headroom at Rails vs. Output Current” in the Typical Performance Characteristics section. The amplifier is stable driving capacitive loads of up to 500pF. Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Since the analog output of the DAC cannot go below ground, it may limit for the lowest codes as shown in Figure 5b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC, as shown in Figure 5c. No full-scale limiting can occur if VREF is less than VCC–FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. Board Layout The PC board should have separate areas for the analog and digital sections of the circuit. A single, solid ground plane should be used, with analog and digital signals carefully routed over separate areas of the plane. This keeps digital signals away from sensitive analog signals and minimizes the interaction between digital ground currents and the 2637fb 23 LTC2637 OPERATION analog section of the ground plane. The resistance from the LTC2637 GND pin to the ground plane should be as low as possible. Resistance here will add directly to the effective DC output impedance of the device (typically 0.1Ω). Note that the LTC2637 is no more susceptible to this effect than any other parts of this type; on the contrary, it allows layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. supply is connected to the board and the DAC ground pin. Thus the DAC ground pin becomes the common point for analog ground, digital ground, and power ground. When the LTC2637 is sinking large currents, this current flows out the ground pin and directly to the power ground trace without affecting the analog ground plane voltage. It is sometimes necessary to interrupt the ground plane to confine digital ground currents to the digital portion of the plane. When doing this, make the gap in the plane only as long as it needs to be to serve its purpose and ensure that no traces cross over the gap. Another technique for minimizing errors is to use a separate power ground return trace on another board layer. The trace should run between the point where the power COMMAND/ADDRESS SLAVE ADDRESS A6 A5 A4 A3 A2 A1 A0 SDA A6 A5 A4 A3 A2 A1 A0 SCL 1 2 3 4 5 6 7 W MS DATA C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 ACK C3 C2 C1 C0 A3 A2 A1 A0 ACK 2 3 4 5 6 7 8 D8 D7 LS DATA D6 D5 D3 D2 D4 D1 D0 X X X X START STOP 8 9 1 9 ACK 1 2 3 4 5 6 7 8 9 ACK 1 2 3 4 5 6 VOUT 7 8 9 FULL-SCALE VOLTAGE ZERO-SCALE VOLTAGE X = DON’T CARE 2637 F04 Figure 4. Typical LTC2637 Input Waveform—Programming DAC Output for Full-Scale VREF = VCC POSITIVE FSE VREF = VCC OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE (c) OUTPUT VOLTAGE 2637 F04 0V 0 4,095 (a) 0V NEGATIVE OFFSET 2,048 INPUT CODE INPUT CODE (b) Figure 5. Effects of Rail-to-Rail Operation On a DAC Transfer Curve (Shown for 12 Bits). (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero (c) Effect of Positive Full-Scale Error for Codes Near Full-Scale 2637fb 24 LTC2637 TYPICAL APPLICATION LTC2637 DACs Adjust LTC2755-16 Offsets, Amplified with LT1991 PGA to ±5V 5V 15 15V 0.1μF VDD LTC2755 0.1μF 8 7 + 5 4 – IOUT1A 59 2 – IOUT2A 2 3 + DAC A 6 0.1μF 8 1/2 LT1469 OUTA 4 0.1μF DAC D 5V 11 REF 0.1μF –15V –15V + – OUTD 15V 1 RVOSA 58 62 REFA + – 0.1μF 63 RCOM1 1/2 LT1469 LTC6240 15V RFBA 60 61 ROFSA 64 RIN1 2 VCC 1 0.1μF LTC2637MS-LMI12 DAC A DAC H DAC B DAC G 15 LT1634-1.25 LT1634-1.25 3 30k 1 P1 2 P3 3 P9 0.1μF 7 VCC LT1991 OUT 6 VOUT = ±5V REF VEE 5 4 14 LT1634-1.25 30k 8 M9 9 M3 10 M1 0.1μF –15V –15V OUTC + – –15V – + DAC C DAC B LT1634-1.25 30k OUTB 4 GND DAC F DAC D DAC E –15V 5 30k DAC C 13 12 19 –15V I2C BUS 9 SDA 8 SCL 7 CA0 10 CA1 CA2 6 16 GND 2637 TA02 2637fb 25 LTC2637 PACKAGE DESCRIPTION DE Package 14-Lead (4mm × 3mm) Plastic DFN (Reference LTC DWG # 05-08-1708 Rev B) R = 0.115 TYP 4.00 p 0.10 (2 SIDES) R = 0.05 TYP 0.70 p 0.05 3.30 p 0.05 3.60 p 0.05 2.20 p 0.05 14 3.30 p 0.10 3.00 p 0.10 (2 SIDES) 1.70 p 0.05 0.40 p 0.10 8 1.70 p 0.10 PIN 1 NOTCH R = 0.20 OR 0.35 s 45o CHAMFER PIN 1 PACKAGE TOP MARK OUTLINE (SEE NOTE 6) (DE14) DFN 0806 REV B 7 0.25 p 0.05 0.50 BSC 1 0.25 p 0.05 0.50 BSC 0.75 p 0.05 0.200 REF 3.00 REF 3.00 REF 0.00 – 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE MS Package 16-Lead (4mm × 5mm) Plastic MSOP (Reference LTC DWG # 05-08-1669 Rev Ø) 4.039 p 0.102 (.159 p .004) (NOTE 3) 0.889 p 0.127 (.035 p .005) 0.280 p 0.076 (.011 p .003) REF 16151413121110 9 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 0.254 (.010) DETAIL “A” 3.00 p 0.102 (.118 p .004) (NOTE 4) 4.90 p 0.152 (.193 p .006) 0o – 6o TYP GAUGE PLANE 0.305 p 0.038 (.0120 p .0015) TYP 0.53 p 0.152 (.021 p .006) 0.50 (.0197) BSC RECOMMENDED SOLDER PAD LAYOUT DETAIL “A” 0.18 (.007) SEATING PLANE 1234567 8 1.10 (.043) MAX 0.17 – 0.27 (.007 – .011) TYP 0.50 (.0197) BSC NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.86 (.034) REF 0.1016 p 0.0508 (.004 p .002) MSOP (MS16) 1107 REV Ø 2637fb 26 LTC2637 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 10/09 Update LTC2637-12 Maximum Limits B 06/10 5, 6, 8 Added details to Note 3 10 Revised Typical Application circuit 25 Added Typical Application drawing and revised Related Parts 28 2637fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LTC2637 TYPICAL APPLICATION LTC2637 DACs Adjust LTC2755-16 Offsets, Amplified with LT1991 PGA to ±5V 5V 15 15V 0.1μF VDD LTC2755 0.1μF 8 7 + IOUT1A 59 5 4 – 2 DAC A IOUT2A 2 6 – 8 0.1μF 1/2 LT1469 3 + 15V 1 OUTA 5V 4 11 0.1μF RVOSA 58 62 REFA + – 0.1μF 63 RCOM1 1/2 LT1469 LTC6240 15V RFBA 60 61 ROFSA 64 RIN1 0.1μF –15V –15V + – OUTD DAC D REF 2 VCC 1 0.1μF LTC2637MS-LMI12 DAC A DAC H DAC B DAC G 15 LT1634-1.25 LT1634-1.25 3 30k 1 P1 2 P3 3 P9 0.1μF 7 VCC LT1991 OUT 6 VOUT = ±5V REF VEE 5 4 14 LT1634-1.25 30k 8 M9 9 M3 10 M1 0.1μF –15V –15V + – –15V OUTC – + DAC C DAC B LT1634-1.25 30k OUTB 4 GND DAC F DAC D DAC E –15V 5 30k DAC C 13 19 I2C BUS –15V 9 SDA 8 SCL 12 7 CA0 10 CA1 CA2 6 16 GND 2637 TA03 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC2636 Octal 12-/10-/8-Bit, SPI VOUT DACs with 10ppm/°C Reference 125μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode, Rail-to-Rail Output, 14-Lead 4mm × 3mm DFN and 16-Lead MSOP Packages LTC1660/LTC1665 Octal 10/8-Bit VOUT DACs in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output LTC2605/LTC2615/ LTC2625 Octal 16-/14-/12-Bit VOUT DACs with I2C Interface LTC2600/LTC2610/ LTC2620 Octal 16-/14-/12-Bit VOUT DACs in 16-Lead Narrow SSOP 250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface LTC2656/LTC2657 Octal 16-/12 Bit, SPI/I2C VOUT DACs with 10ppm/°C Max Reference ±4LSB INL max at 16-Bits and ±2mV Offset Error, Rail-to-Rail Output, 20-Lead 4mm × 5mm QFN and 16-Lead TSSOP Packages LTC2654/LTC2655 Quad 16-/12 Bit, SPI/I2C VOUT DACs with 10ppm/°C Max Reference ±4LSB INL max at 16-Bits and ±2mV Offset Error, Rail-to-Rail Output, 20-Lead 4mm × 4mm QFN and 16-Lead Narrow SSOP Packages LTC2634/LTC2635 Quad 12-/10-/8-Bit SPI/I2C VOUT DACs with 10ppm/°C Reference ±2.5 LSB INL, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode, 16-Pin 3mm × 3mm QFN and 10-Lead MSOP Packages LTC2630/LTC2632 Single 12-/10-/8-Bit, SPI/ I2C VOUT DACs with 10ppm/°C Reference 180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, Rail-to-Rail Output, in SC70 (LTC2630)/ ThinSOT™(LTC2631) LTC2640 Single 12-/10-/8-Bit, SPI VOUT DACs with 10ppm/°C Reference 180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode, Rail-to-Rail Output, in ThinSOT LT1991 Precision, 100μA Gain Selectable Amplifier Gain Accuracy of 0.04%, Gains from –13 to 14, 100μA Precision Op-Amp LT1469 Dual 90MHz, 22V/μs 16-Bit Accurate Operational Amplifier 90MHz Gain Bandwidth, 125μV offset, 900ns , 22V/μs Slew Rate Precision Op-Amp 250μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output, I2C Interface Amplifiers 2637fb 28 Linear Technology Corporation LT 0610 REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2009