MC74LVXT4052 Analog Multiplexer/ Demultiplexer High−Performance Silicon−Gate CMOS The MC74LVXT4052 utilizes silicon−gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. This analog multiplexer/demultiplexer controls analog voltages that may vary across the complete power supply range (from VCC to VEE). The LVXT4052 is similar in pinout to the high−speed HC4052A and the metal−gate MC14052B. The Channel−Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input. When the Enable pin is HIGH, all analog switches are turned off. The Channel−Select and Enable inputs are compatible with standard TTL levels. This device has been designed so the ON resistance (RON) is more linear over input voltage than the RON of metal−gate CMOS analog switches and High−Speed CMOS analog switches. MARKING DIAGRAMS 16 SOIC−16 D SUFFIX CASE 751B 1 16 Select Pins Compatible with TTL Levels Fast Switching and Propagation Speeds LVXT 4052 ALYW 1 Low Crosstalk Between Switches Analog Power Supply Range (VCC − VEE) = 3.0 V to 3.0 V Digital (Control) Power Supply Range (VCC − GND) = 2.5 to 6.0 V Improved Linearity and Lower ON Resistance Than Metal−Gate, HSL, or VHC Counterparts Low Noise 16 SOEIAJ−16 M SUFFIX CASE 966 • • Designed to Operate on a Single Supply with VEE = GND, or Using • • LVXT4052 AWLYWW TSSOP−16 DT SUFFIX CASE 948F Features • • • • • • http://onsemi.com Split Supplies up to 3.0 V Break−Before−Make Circuitry Pb−Free Packages are Available* LVXT4052 ALYW 1 A WL or L Y WW or W = = = = Assembly Location Wafer Lot Year Work Week ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 2005 March, 2005 − Rev. 4 1 Publication Order Number: MC74LVXT4052/D MC74LVXT4052 VCC 16 X2 15 X1 14 X 13 X0 12 X3 11 A 10 B 9 FUNCTION TABLE Control Inputs Select 1 Y0 2 Y2 3 Y 4 Y3 5 Y1 6 7 Enable VEE Enable B A ON Channels L L L L H L L H H X L H L H X Y0 Y1 Y2 Y3 8 GND Figure 1. Pin Connection and Marking Diagram (Top View) X0 X1 X2 X3 NONE X = Don’t Care 12 ANALOG INPUTS/OUTPUTS CHANNEL-SELECT INPUTS X0 14 X1 15 X2 11 X3 Y0 Y1 Y2 Y3 A B ENABLE 13 X SWITCH X COMMON OUTPUTS/INPUTS 1 5 2 3 Y SWITCH Y 4 10 9 PIN 16 = VCC PIN 7 = VEE PIN 8 = GND 6 NOTE: This device allows independent control of each switch. Channel−Select Input A controls the X−Switch, Input B controls the Y−Switch. Figure 2. Logic Diagram Double−Pole, 4−Position Plus Common Off ORDERING INFORMATION Package Shipping† MC74LVXT4052D SOIC−16 48 Units / Rail MC74LVXT4052DG SOIC−16 (Pb−Free) 48 Units / Rail MC74LVXT4052DR2 SOIC−16 2500 Tape & Reel MC74LVXT4052DR2G SOIC−16 (Pb−Free) 2500 Tape & Reel MC74LVXT4052DT TSSOP−16* 96 Units / Rail MC74LVXT4052DTR2 TSSOP−16* 2500 Tape & Reel MC74LVXT4052M SOEIAJ−16 50 Units / Rail MC74LVXT4052MG SOEIAJ−16 (Pb−Free) 50 Units / Rail MC74LVXT4052MEL SOEIAJ−16 2000 Tape & Reel MC74LVXT4052MELG SOEIAJ−16 (Pb−Free) 2000 Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 2 MC74LVXT4052 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ MAXIMUM RATINGS Symbol Parameter VEE Negative DC Supply Voltage (Referenced to GND) VCC Positive DC Supply Voltage (Referenced to GND) (Referenced to VEE) VIS Analog Input Voltage VIN Digital Input Voltage I Value Unit 7.0 to 0.5 0.5 to 7.0 0.5 to 7.0 V VEE 0.5 to VCC 0.5 V 0.5 to 7.0 V (Referenced to GND) 20 mA 65 to 150 C 260 C DC Current, Into or Out of Any Pin TSTG Storage Temperature Range TL Lead Temperature, 1 mm from Case for 10 Seconds V TJ Junction Temperature under Bias 150 C JA Thermal Resistance SOIC TSSOP 143 164 °C/W PD Power Dissipation in Still Air, SOIC TSSOP 500 450 mW MSL Moisture Sensitivity FR Flammability Rating VESD Level 1 Oxygen Index: 30% − 35% Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) 2000 200 1000 V Above VCC and Below GND at 125°C (Note 4) 300 mA ESD Withstand Voltage ILATCHUP Latchup Performance UL 94−V0 @ 0.125 in Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Tested to EIA/JESD22−A114−A. 2. Tested to EIA/JESD22−A115−A. 3. Tested to JESD22−C101−A. 4. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ Symbol Parameter Min Max Unit VEE Negative DC Supply Voltage (Referenced to GND) 6.0 GND V VCC Positive DC Supply Voltage (Referenced to GND) (Referenced to VEE) 2.5 2.5 6.0 6.0 V VIS Analog Input Voltage VEE VCC V VIN Digital Input Voltage 0 6.0 V TA Operating Temperature Range, All Package Types 55 125 C tr, tf Input Rise/Fall Time (Channel Select or Enable Inputs) 0 0 100 20 ns/V (Note 5) (Referenced to GND) VCC = 3.0 V 0.3 V VCC = 5.0 V 0.5 V 5. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level. 47.9 100 178,700 20.4 110 79,600 9.4 120 37,000 4.2 130 17,800 2.0 140 8,900 1.0 TJ = 80C 419,300 TJ = 90C 90 TJ = 100C 117.8 TJ = 110C Time, Years 1,032,200 TJ = 120C Time, Hours 80 FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 130C Junction Temperature °C NORMALIZED FAILURE RATE DEVICE JUNCTION TEMPERATURE VERSUS TIME TO 0.1% BOND FAILURES 1 1 10 100 1000 TIME, YEARS Figure 3. Failure Rate vs. Time Junction Temperature http://onsemi.com 3 MC74LVXT4052 DC CHARACTERISTICS − Digital Section (Voltages Referenced to GND) VCC V Guaranteed Limit Symbol Parameter 55 to 25°C 85°C 125°C Unit VIH Minimum High−Level Input Voltage, Channel−Select or Enable Inputs 3.0 4.5 5.5 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 V VIL Maximum Low−Level Input Voltage, Channel−Select or Enable Inputs 3.0 4.5 5.5 0.5 0.8 0.8 0.5 0.8 0.8 0.5 0.8 0.8 V IIN Maximum Input Leakage Current, Channel−Select or Enable Inputs VIN = 6.0 or GND 0 V to 6.0 V 0.1 1.0 1.0 A ICC Maximum Quiescent Supply Current (per Package) Channel Select, Enable and VIS = VCC or GND 6.0 4.0 40 80 A Condition ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎ DC ELECTRICAL CHARACTERISTICS − Analog Section Symbol Parameter Test Conditions Guaranteed Limit VCC V VEE V 55 to 25°C 85C 125C Unit Maximum “ON” Resistance VIN = VIL or VIH VIS = ½ (VCC − VEE) |IS| = 2.0 mA (Figure 4) 3.0 4.5 3.0 0 0 3.0 86 37 26 108 46 33 120 55 37 RON Maximum Difference in “ON” Resistance Between Any Two Channels in the Same Package VIN = VIL or VIH VIS = ½ (VCC − VEE) |IS| = 2.0 mA 3.0 4.5 3.0 0 0 3.0 15 13 10 20 18 15 20 18 15 Ioff Maximum Off−Channel Leakage Current, Any One Channel Vin = VIL or VIH; VIO = VCC or GND; Switch Off (Figure 3) 5.5 +3.0 0 −3.0 0.1 0.1 0.5 0.5 1.0 1.0 A Maximum Off−Channel Leakage Current, Common Channel Vin = VIL or VIH; VIO = VCC or GND; Switch Off (Figure 4) 5.5 +3.0 0 −3.0 0.2 0.2 2.0 2.0 4.0 4.0 Maximum On−Channel Leakage Current, Channel−to−Channel Vin = VIL or VIH; Switch−to−Switch = VCC or GND; (Figure 5) 5.5 +3.0 0 −3.0 0.2 0.2 2.0 2.0 4.0 4.0 RON Ion A ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ AC CHARACTERISTICS (Input tr = tf = 3 ns) Guaranteed Limit Symbol tBBM Parameter Minimum Break−Before−Make Time Test Conditions VCC V VEE V 3.0 4.5 3.0 0.0 0.0 3.0 VIN = VIL or VIH VIS = VCC RL = 300 CL = 35 pF (Figures 12 and 13) *Typical Characteristics are at 25C. http://onsemi.com 4 55 to 25C Min Typ* 85C 125C Unit 1.0 1.0 1.0 6.5 5.0 3.5 − − − − − − ns MC74LVXT4052 AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 3 ns) Guaranteed Limit Symbol Parameter VCC V VEE V 55 to 25°C Min Typ Max 85°C Min Max 125°C Min Max Unit tPLH, tPHL Maximum Propagation Delay, Channel−Select to Analog Output (Figures 16 and 17) 2.5 3.0 4.5 3.0 0 0 0 3.0 40 28 23 23 45 30 25 25 50 35 30 28 ns tPLZ, tPHZ Maximum Propagation Delay, Enable to Analog Output (Figures 14 and 15) 2.5 3.0 4.5 3.0 0 0 0 3.0 40 28 23 23 45 30 25 25 50 35 30 28 ns tPZL, tPZH Maximum Propagation Delay, Enable to Analog Output (Figures 14 and 15) 2.5 3.0 4.5 3.0 0 0 0 3.0 40 28 23 23 45 30 25 25 50 35 30 28 ns Typical @ 25°C, VCC = 5.0 V, VEE = 0V CPD Power Dissipation Capacitance (Figure 18) (Note 6) 45 pF CIN Maximum Input Capacitance, Channel−Select or Enable Inputs 10 pF CI/O Maximum Capacitance (All Switches Off) 10 10 1.0 pF Analog I/O Common O/I Feedthrough 6. Used to determine the no−load dynamic power consumption: P D = CPD VCC2 f + ICC VCC . ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V) VCC V VEE V Typ 25°C Unit BW Maximum On−Channel Bandwidth or Minimum Frequency Response VIS = ½ (VCC − VEE) Ref and Test Attn = 10 dB Source Amplitude = 0 dB (Figure 7) 3.0 4.5 6.0 3.0 0.0 0.0 0.0 3.0 80 80 80 80 MHz VISO Off−Channel Feedthrough Isolation f = 1 MHz; VIS = ½ (VCC − VEE) Adjust Network Analyzer output to 10 dBm on each output from the power splitter. (Figures 8 and 9) 3.0 4.5 6.0 3.0 0.0 0.0 0.0 3.0 70 70 70 70 dB VONL Maximum Feedthrough On Loss VIS = ½ (VCC − VEE) Adjust Network Analyzer output to 10 dBm on each output from the power splitter. (Figure 11) 3.0 4.5 6.0 3.0 0.0 0.0 0.0 3.0 2 2 2 2 dB Charge Injection VIN = VCC to VEE, fIS = 1 kHz, tr = tf = 3 ns RIS = 0 , CL= 1000 pF, Q = CL * VOUT (Figure 10) 5.0 3.0 3.0 0.0 9.0 12 pC Total Harmonic Distortion THD + Noise fIS = 1 MHz, RL = 10 K, CL = 50 pF, VIS = 5.0 VPP sine wave VIS = 6.0 VPP sine wave (Figure 19) 6.0 3.0 0.0 3.0 0.10 0.05 Symbol Q THD Parameter Condition http://onsemi.com 5 % MC74LVXT4052 PLOTTER PROGRAMMABLE POWER SUPPLY MINI COMPUTER DC ANALYZER VCC DEVICE UNDER TEST ANALOG IN COMMON OUT GND GND Figure 4. On Resistance, Test Set−Up VCC VCC 16 VEE VCC A A OFF NC VCC COMMON O/I OFF VEE VEE 6 7 8 Figure 5. Maximum Off Channel Leakage Current, Any One Channel, Test Set−Up HP4195A Network Anl S1 R1 T1 6 7 8 Figure 6. Maximum On Channel Leakage Current, Channel to Channel, Test Set−Up 0.1 F VIS HP11667B Pwr Splitter VCC 100 K 0.1 F ON All untested Analog I/O pins OFF 50 K VEE 6 7 8 N/C COMMON O/I ANALOG I/O VIL VIH VCC ON VEE OFF VCC 16 A 9 − 11 Channel Selects connected to address pins on HP4195A and appropriately configured to test each switch. Figure 7. Maximum On Channel Bandwidth, Test Set−Up http://onsemi.com 6 MC74LVXT4052 HP4195A Network Anl S1 R1 T1 0.1 F HP11667B Pwr Splitter 0.1 F VIS VCC 100 K 16 OFF All untested Analog I/O pins ON 50 K VEE 6 7 8 Channel Selects connected to address pins on HP4195A and appropriately configured to test each switch. 9 − 11 Config = Network Format = T/R (dB) CAL = Trans Cal VISO(dB) = 20 log (VT1/VR1) Display = Rectan XAB Scale Ref = Auto Scale View = Off, Off, Off Trig = Cont Mode Source Amplitude = 13 dB Reference Attenuation = 20 dB Test Attenuation = 0 dB Figure 8. Maximum Off Channel Feedthrough Isolation, Test Set−Up HP4195A Network Anl S1 R1 T1 HP11667B Pwr Splitter 0.1 F VIS VCC 100 K 0.1 F 16 OFF ON 50 K All untested Analog I/O pins 50 VEE 6 7 8 Config = Network Format = T/R (dB) CAL = Trans Cal Display = Rectan XAB Scale Ref = Auto Scale View = Off, Off, Off Trig = Cont Mode Source Amplitude = 13 dB Reference Attenuation = 20 dB Test Attenuation = 0 dB 9 − 11 Channel Selects connected to address pins on HP4195A and appropriately configured to test each switch. VISOC(dB) = 20 log (VT1/VR1) Figure 9. Maximum Common−Channel Feedthrough Isolation, Test Set−Up http://onsemi.com 7 MC74LVXT4052 VCC 16 ON/OFF VOUT OFF/ON VIN Enable VEE 6 RIS 7 8 CL * Bias Channel Selects to test each combination of analog inputs to common analog output. 9 − 11 *Includes all probe and jig capacitance. VIH VIS VIL Q = CL * VOUT VOUT VOUT Figure 10. Charge Injection, Test Set−Up HP4195A Network Anl S1 R1 T1 0.1 F HP11667B Pwr Splitter 0.1 F VIS VCC 100 K 16 ON All untested Analog I/O pins OFF 50 VEE 6 7 8 Config = Network Format = T/R (dB) CAL = Trans Cal Display = Rectan XAB Scale Ref = Auto Scale View = Off, Off, Off Trig = Cont Mode Source Amplitude = 13 dB Reference Attenuation = 20 dB Test Attenuation = 20 dB 9 − 11 Channel Selects connected to address pins on HP4195A and appropriately configured to test each switch. VONL(dB) = 20 log (VT1/VR1) Figure 11. Maximum On Channel Feedthrough On Loss, Test Set−Up http://onsemi.com 8 MC74LVXT4052 Tek 11801B DSO COM INPUT VCC VCC VIN VOH 16 80% OFF ON VEE 80% of VOH CL RL Channel Selects connected to VIN and appropriately configured to test each switch. 6 7 8 9 − 11 GND tBBM VIN 50 Figure 12. Break−Before−Make, Test Set−Up Figure 13. Break−Before−Make Time VCC VCC 16 VCC CHANNEL SELECT COMMON O/I TEST POINT ON/OFF ANALOG I/O 50% OFF/ON GND tPLH ANALOG OUT CL * 6 7 8 tPHL 50% CHANNEL SELECT *Includes all probe and jig capacitance. Figure 14. Propagation Delays, Channel Select to Analog Out tf GND POSITION 1 WHEN TESTING tPHZ AND tPZH 1 POSITION 2 WHEN TESTING tPLZ AND tPZL tr 90% 50% 10% ENABLE tPZL ANALOG OUT tPLZ VCC 2 GND HIGH IMPEDANCE 10% tPHZ 90% VCC VCC 16 1 50% tPZH ANALOG OUT Figure 15. Propagation Delay, Test Set−Up Channel Select to Analog Out ANALOG I/O ON/OFF 2 VOL 1 K TEST POINT CL * ENABLE VOH 50% HIGH IMPEDANCE Figure 16. Propagation Delays, Enable to Analog Out 6 7 8 Figure 17. Propagation Delay, Test Set−Up Enable to Analog Out http://onsemi.com 9 MC74LVXT4052 VCC A VCC ON/OFF NC OFF/ON VIL 15 10 − 11, 13 − 14 12 Channel Select Figure 18. Power Dissipation Capacitance, Test Set−Up HP3466 DMM V COM HP3466 DMM V COM HP E3630A DC Pwr Supply COM 20 V HP 339 Distortion Measurement Set 20 V Analyzer Input COM Oscillator Output COM 16 ON RL OFF 50 K 6 7 8 9 − 11 CL Channel Selects connected to DC bias supply or ground and appropriately configured to test each switch. Figure 19. Total Harmonic Distortion, Test Set−Up http://onsemi.com 10 MC74LVXT4052 APPLICATIONS INFORMATION outputs to VCC or GND through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch. Although used here, balanced supplies are not a requirement. The only constraints on the power supplies are that: VEE − GND = 0 to 6 volts VCC − GND = 2.5 to 6 volts VCC − VEE = 2.5 to 6 volts and VEE GND When voltage transients above VCC and/or below VEE are anticipated on the analog channels, external Germanium or Schottky diodes (Dx) are recommended as shown in Figure 22. These diodes should be able to absorb the maximum anticipated current surges during clipping. The Channel Select and Enable control pins should be at VCC or GND logic levels. VCC being recognized as a logic high and GND being recognized as a logic low. In this example: VCC = 5 V = logic high GND = 0 V = logic low The maximum analog voltage swing is determined by the supply voltages VCC and VEE. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below VEE. In this example, the difference between VCC and VEE is five volts. Therefore, using the configuration of Figure 21, a maximum analog signal of five volts peak−to−peak can be controlled. Unused analog inputs/outputs may be left floating (i.e., not connected). However, tying unused analog inputs and +3.0 V +3.0 V −3.0 V +5 V +5 V 16 ANALOG SIGNAL −3.0 V 6 7 8 11 10 9 16 +3.0 V ANALOG SIGNAL ON −3.0 V ANALOG SIGNAL GND TO EXTERNAL CMOS CIRCUITRY 0 to 3.0 V DIGITAL SIGNALS 6 7 8 Figure 20. Application Example ANALOG SIGNAL ON 11 10 9 VCC Dx 16 VCC Dx ON/OFF Dx Dx VEE VEE VEE 7 8 Figure 22. External Germanium or Schottky Clipping Diodes http://onsemi.com 11 GND TO EXTERNAL CMOS CIRCUITRY 0 to 5 V DIGITAL SIGNALS Figure 21. Application Example VCC +5 V MC74LVXT4052 A 10 12 LEVEL SHIFTER 14 B 9 15 LEVEL SHIFTER 11 13 ENABLE 6 1 LEVEL SHIFTER 5 2 4 3 Figure 23. Function Diagram, LVXT4052 http://onsemi.com 12 X0 X1 X2 X3 X Y0 Y1 Y2 Y3 Y MC74LVXT4052 PACKAGE DIMENSIONS SOIC−16 D SUFFIX CASE 751B−05 ISSUE J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 16 9 −B− 1 P 8 PL 0.25 (0.010) 8 B M S G R K DIM A B C D F G J K M P R F X 45 C −T− SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 S TSSOP−16 DT SUFFIX CASE 948F−01 ISSUE A 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S K ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. 8 1 N 0.15 (0.006) T U S 0.25 (0.010) A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. M N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE H D DETAIL E G http://onsemi.com 13 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 MC74LVXT4052 SOEIAJ−16 M SUFFIX CASE 966−01 ISSUE O 16 LE 9 Q1 M E HE 1 8 L DETAIL P Z D e VIEW P A DIM A A1 b c D E e HE L LE M Q1 Z A1 b 0.13 (0.005) c NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). M 0.10 (0.004) MILLIMETERS MIN MAX −−− 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 0 0.70 0.90 −−− 0.78 INCHES MIN MAX −−− 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 0 0.028 0.035 −−− 0.031 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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