LY61L25616 256K X 16 BIT HIGH SPEED CMOS SRAM Rev. 2.5 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 2.0 Issue Date May.24.2006 Jan.22.2007 Jan.30.2007 Jun.23.2007 Rev. 2.2 Description Initial Issue Added Extended Grade Added PKG Type : 48-ball 6mm x 8mm TFBGA Revised ICC and ISB1 Added I grade Revised VTERM to VT1 and VT2 Revised FEATURES & ORDERING INFORMATION Lead free and green package available to Green package available Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS Added packing type in ORDERING INFORMATION Revised PACKAGE OUTLINE DIMENSION in page 11 Rev. 2.3 Revised ORDERING INFORMATION in page 12 Added “*Not recommended for new design.” in ORDERING INFORMATION. Revised PIN DESCRIPTION in page 2 Aug.25.2010 Rev.2.1 Rev. 2.4 Rev. 2.5 Revised ISB1 & ICC Revised IDR in DATA RETENTION CHARACTERISTICS Deleted -15/25ns Spec. Deleted PKG type : 48-ball 6mm x 8mm TFBGA Deleted WRITE CYCLE Notes : 1. WE#,CE#, LB#, UB# must be high during all address transitions. in page 8. Deleted -10/12ns Spec. Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 0 Apr.17.2009 May.06.2010 Dec.27.2016 Apr.19.2017 LY61L25616 256K X 16 BIT HIGH SPEED CMOS SRAM Rev. 2.5 FEATURES GENERAL DESCRIPTION Fast access time : 20ns Very low power consumption: Operating current: 50mA (TYP.) Standby current: 0.5mA (TYP.) 20µ A( (TYP. for LL version) Single 3.3V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data byte control : LB# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15) Data retention voltage : 2.0V (MIN.) Green package available Package : 44-pin 400 mil TSOP II The LY61L25616 is a 4,194,304-bit low power CMOS static random access memory organized as 262,144 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The LY61L25616 is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The LY61L25616 operates from a single power supply of 3.3V and all inputs and outputs are fully TTL compatible PRODUCT FAMILY Product Family LY61L25616 LY61L25616(E) LY61L25616(I) LY61L25616(LL) LY61L25616(LLE) LY61L25616(LLI) Operating Temperature 0 ~ 70℃ -20 ~ 80℃ -40 ~ 85℃ 0 ~ 70℃ -20 ~ 80℃ -40 ~ 85℃ VCC Range Speed 3.0 ~ 3.6V 3.0 ~ 3.6V 3.0 ~ 3.6V 3.0 ~ 3.6V 3.0 ~ 3.6V 3.0 ~ 3.6V 20ns 20ns 20ns 20ns 20ns 20ns Power Dissipation Standby(ISB1,TYP.) Operating(ICC,TYP.) 0.5mA 50mA 50mA 0.5mA 50mA 0.5mA 50mA 20µA 50mA 20µA 50mA 20µA Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 1 LY61L25616 256K X 16 BIT HIGH SPEED CMOS SRAM Rev. 2.5 FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION Vcc Vss A0-A17 DQ0-DQ7 Lower Byte DQ8-DQ15 Upper Byte CE# WE# OE# LB# UB# DECODER I/O DATA CIRCUIT 256Kx16 MEMORY ARRAY COLUMN I/O SYMBOL DESCRIPTION A0 - A17 Address Inputs DQ0 - DQ15 Data Inputs/Outputs CE# Chip Enable Input WE# Write Enable Input OE# Output Enable Input LB# Lower Byte Control UB# Upper Byte Control VCC Power Supply VSS Ground NC No Connection CONTROL CIRCUIT Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 2 LY61L25616 256K X 16 BIT HIGH SPEED CMOS SRAM Rev. 2.5 PIN CONFIGURATION 1 44 A5 A3 2 43 A6 A2 3 42 A7 A1 4 41 OE# A0 5 40 UB# CE# 6 39 LB# DQ0 7 38 DQ15 DQ1 8 37 DQ14 DQ2 9 36 DQ13 DQ3 10 35 DQ12 Vcc 11 34 Vss Vss 12 33 Vcc DQ4 13 32 DQ11 DQ5 14 31 DQ10 DQ6 15 30 DQ9 DQ7 16 29 DQ8 WE# 17 28 NC A17 18 27 A8 A16 19 26 A9 A15 20 25 A10 A14 21 24 A11 A13 22 23 A12 LY61L25616 XXXXXXXX XXXXXXXX A4 TSOP II ABSOLUTE MAXIMUN RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS Operating Temperature Storage Temperature Power Dissipation DC Output Current SYMBOL VT1 VT2 TA TSTG PD IOUT RATING -0.5 to 4.6 -0.5 to VCC+0.5 0 to 70(C grade) -20 to 80(E grade) -40 to 85(I grade) -65 to 150 1 50 UNIT V V ℃ ℃ W mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 3 LY61L25616 256K X 16 BIT HIGH SPEED CMOS SRAM Rev. 2.5 TRUTH TABLE MODE Standby Output Disable Read Write Note: CE# OE# H L L L L L L L L X H X L L L X X X WE# LB# X H X H H H L L L I/O OPERATION DQ0 - DQ7 DQ8 - DQ15 High-Z High-Z High-Z High-Z High-Z High-Z DOUT High-Z High-Z DOUT DOUT DOUT DIN High-Z High-Z DIN DIN DIN UB# X X H L H L L H L X X H H L L H L L SUPPLY CURRENT ISB1 ICC ICC ICC H = VIH, L = VIL, X = Don't care. DC ELECTRICAL CHARACTERISTICS SYMBOL TEST CONDITION PARAMETER Supply Voltage VCC Input High Voltage VIH*1 Input Low Voltage VIL*2 Input Leakage Current ILI VCC ≧ VIN ≧ VSS Output Leakage VCC ≧ VOUT ≧ VSS, ILO Current Output Disabled Output High Voltage VOH IOH = -4mA Output Low Voltage VOL IOL = 8mA Cycle time = MIN. Average Operating ICC CE# = VIL , II/O = 0mA Power supply Current Other pins at VIL or VIH -20 Standby Power CE# ≧ VCC - 0.2V, ISB1 Supply Current Others at 0.2V or VCC - 0.2V -20LL MIN. 3.0 2.2 - 0.3 -1 TYP. *4 MAX. 3.3 3.6 VCC+0.3 0.6 1 UNIT V V V µA -1 - 1 µA 2.4 - - 0.4 V V - 50 80 mA - 0.5 20 5*5 100*6 mA µA Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃ 5. 1mA for special request 6. 50µ A for special request CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - Note : These parameters are guaranteed by device characterization, but not production tested. Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 4 MAX. 8 10 UNIT pF pF LY61L25616 256K X 16 BIT HIGH SPEED CMOS SRAM Rev. 2.5 AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -8mA/16mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change LB#, UB# Access Time LB#, UB# to High-Z Output LB#, UB# to Low-Z Output SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH tBA tBHZ* tBLZ* LY61L25616-20 MIN. MAX. 20 20 20 8 4 0 8 8 3 8 8 4 - UNIT ns ns ns ns ns ns ns ns ns ns ns ns (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z LB#, UB# Valid to End of Write SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW * tWHZ* tBW LY61L25616-20 MIN. MAX. 20 16 16 0 11 0 9 0 5 9 16 - UNIT ns ns ns ns ns ns ns ns ns ns ns *These parameters are guaranteed by device characterization, but not production tested. Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 5 LY61L25616 256K X 16 BIT HIGH SPEED CMOS SRAM Rev. 2.5 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE LB#,UB# tBA OE# tOE tOH tOHZ tBHZ tCHZ tOLZ tBLZ tCLZ Dout High-Z Data Valid High-Z Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low. 3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise tAA is the limiting parameter. 4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ. Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 6 LY61L25616 256K X 16 BIT HIGH SPEED CMOS SRAM Rev. 2.5 WRITE CYCLE 1 (WE# Controlled) (1,2,4,5) tWC Address tAW CE# tCW tBW LB#,UB# tAS tWP tWR WE# tWHZ Dout tOW High-Z (4) tDW Din (4) tDH Data Valid WRITE CYCLE 2 (CE# Controlled) (1,4,5) tWC Address tAW CE# tAS tWR tCW tBW LB#,UB# tWP WE# tWHZ Dout High-Z (4) tDW Din tDH Data Valid Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 7 LY61L25616 256K X 16 BIT HIGH SPEED CMOS SRAM Rev. 2.5 WRITE CYCLE 3 (LB#,UB# Controlled) (1,4,5) tWC Address tAW tWR CE# tAS tCW tBW LB#,UB# tWP WE# tWHZ Dout High-Z (4) tDW Din tDH Data Valid Notes : 1.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low. 2.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 3.During this period, I/O pins are in the output state, and input signals must not be applied. 4.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 5.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 8 LY61L25616 256K X 16 BIT HIGH SPEED CMOS SRAM Rev. 2.5 DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention SYMBOL TEST CONDITION VDR CE# ≧ VCC - 0.2V 20 VCC = 2.0V, CE# ≧ VCC - 0.2V Data Retention Current IDR others at 0.2V or VCC - 0.2V 20LL Chip Disable to Data tCDR See Data Retention Waveforms (below) Retention Time Recovery Time tR tRC* = Read Cycle Time MIN. 2.0 - TYP. 0.5 10 MAX. 3.6 1 50 UNIT V mA µA 0 - - ns tRC* - - ns DATA RETENTION WAVEFORM VDR ≧ 2.0V Vcc Vcc(min.) Vcc(min.) tCDR CE# VIH tR CE# ≧ Vcc-0.2V VIH Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 9 LY61L25616 256K X 16 BIT HIGH SPEED CMOS SRAM Rev. 2.5 PACKAGE OUTLINE DIMENSION 44-pin 400mil TSOP Ⅱ Package Outline Dimension SYMBOLS A A1 A2 b c D E E1 e L ZD y Θ DIMENSIONS IN MILLMETERS MIN. NOM. MAX. 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.30 0.45 0.12 0.21 18.212 18.415 18.618 11.506 11.760 12.014 9.957 10.160 10.363 0.800 0.40 0.50 0.60 0.805 0.076 0o 3o 6o DIMENSIONS IN MILS MIN. NOM. MAX. 47.2 2.0 3.9 5.9 37.4 39.4 41.3 11.8 17.7 4.7 8.3 717 725 733 453 463 473 392 400 408 31.5 15.7 19.7 23.6 31.7 3 0o 3o 6o Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 10 LY61L25616 256K X 16 BIT HIGH SPEED CMOS SRAM Rev. 2.5 ORDERING INFORMATION Package Type Access Time Power Type Temperature Packing Range(℃) Type (Speed)(ns) 44-pin (400mil) 20 Normal Power 0℃~70℃ TSOP II -20℃~80℃ -40℃~85℃ 20 Ultra 0℃~70℃ Low Power -20℃~80℃ -40℃~85℃ Tray LY61L25616ML-20 Tape Reel LY61L25616ML-20T Tray LY61L25616ML-20E Tape Reel LY61L25616ML-20ET Tray LY61L25616ML-20I Tape Reel LY61L25616ML-20IT Tray LY61L25616ML-20LL Tape Reel LY61L25616ML-20LLT Tray LY61L25616ML-20LLE Tape Reel LY61L25616ML-20LLET Tray LY61L25616ML-20LLI Tape Reel LY61L25616ML-20LLIT Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 11 Lyontek Item No. LY61L25616 Rev. 2.5 256K X 16 BIT HIGH SPEED CMOS SRAM THIS PAGE IS LEFT BLANK INTENTIONALLY. Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 12