M24256 M24128 256/128 Kbit Serial I²C Bus EEPROM Without Chip Enable Lines ■ Compatible with I2C Extended Addressing ■ Two Wire I2C Serial Interface Supports 400 kHz Protocol ■ Single Supply Voltage: 8 – 4.5V to 5.5V for M24xxx – 2.5V to 5.5V for M24xxx-W ■ Hardware Write Control ■ BYTE and PAGE WRITE (up to 64 Bytes) ■ RANDOM and SEQUENTIAL READ Modes ■ Self-Timed Programming Cycle ■ Automatic Address Incrementing ■ Enhanced ESD/Latch-Up Behavior ■ More than 100,000 Erase/Write Cycles ■ More than 40 Year Data Retention DESCRIPTION These I 2C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 32Kx8 bits (M24256) and 16Kx8 bits (M24128), and operate down to 2.5 V (for the -W version of each device). The M24256B, M24128B and M24256A are also available, and offer the extra functionality of the chip enable inputs. Please see the separate data sheets for details of these products. The M24256 and M24128 are available in Plastic Dual-in-Line and Plastic Small Outline packages. These memory devices are compatible with the I2C extended memory standard. This is a two wire 1 PDIP8 (BN) 0.25 mm frame 8 8 1 1 SO8 (MN) 150 mil width SO8 (MW) 200 mil width Figure 1. Logic Diagram VCC SDA SCL M24256 M24128 Table 1. Signal Names SDA Serial Data/Address Input/ Output SCL Serial Clock WC Write Control VCC Supply Voltage VSS Ground WC VSS AI01882 June 2001 1/17 M24256, M24128 Figure 2B. SO Connections Figure 2A. DIP Connections M24256 M24128 NC NC NC VSS 1 2 3 4 8 7 6 5 M24256 M24128 VCC WC SCL SDA NC NC NC VSS 1 2 3 4 AI01883 8 7 6 5 VCC WC SCL SDA AI01884 Note: 1. NC = Not Connected Note: 1. NC = Not Connected serial interface that uses a bi-directional data bus and serial clock. The memory carries a built-in 4bit unique Device Type Identifier code (1010) in accordance with the I2C bus definition. The memory behaves as a slave device in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a START condition, generated by the bus master. The START condition is followed by a Device Select Code and RW bit (as described in Table 3), terminated by an acknowledge bit. When writing data to the memory, the memory inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a STOP condition after an Ack for WRITE, and after a NoAck for READ. Power On Reset: V CC Lock-Out Write Protect In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The internal reset is held active until the V CC voltage has reached the POR threshold value, and all operations are disabled – the device will not respond to any command. In the same way, when VCC drops from the operating voltage, below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable and valid V CC must be applied before applying any logic signal. SIGNAL DESCRIPTION Serial Clock (SCL) The SCL input pin is used to strobe all data in and out of the memory. In applications where this line is used by slaves to synchronize the bus to a slow- Table 2. Absolute Maximum Ratings 1 Symbol Value Unit Ambient Operating Temperature –40 to 125 °C TSTG Storage Temperature –65 to 150 °C TLEAD Lead Temperature during Soldering 260 235 °C TA Parameter PDIP: 10 seconds SO: 20 seconds (max) 2 VIO Input or Output range –0.6 to 6.5 V VCC Supply Voltage –0.3 to 6.5 V VESD Electrostatic Discharge Voltage (Human Body model) 3 4000 V Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents. 2. IPC/JEDEC J-STD-020A 3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω) 2/17 M24256, M24128 er clock, the master must have an open drain output, and a pull-up resistor must be connected from the SCL line to V CC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the master has a push-pull (rather than open drain) output. Serial Data (SDA) The SDA pin is bi-directional, and is used to transfer data in or out of the memory. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from the SDA bus to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). Write Control (WC) The hardware Write Control pin (WC) is useful for protecting the entire contents of the memory from inadvertent erase/write. The Write Control signal is used to enable (WC=VIL) or disable (WC=V IH) write instructions to the entire memory area. When unconnected, the WC input is internally read as VIL, and write operations are allowed. When WC=1, Device Select and Address bytes are acknowledged, Data bytes are not acknowledged. Please see the Application Note AN404 for a more detailed description of the Write Control feature. DEVICE OPERATION The memory device supports the I2C protocol. This is summarized in Figure 4, and is compared with other serial bus protocols in Application Note AN1001. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the master, and the other as the slave. A data transfer can only be initiated by the master, which will also provide the serial clock for synchronization. The memory device is always a slave device in all communication. Start Condition START is identified by a high to low transition of the SDA line while the clock, SCL, is stable in the high state. A START condition must precede any data transfer command. The memory device continuously monitors (except during a programming cycle) the SDA and SCL lines for a START condition, and will not respond unless one is given. Stop Condition STOP is identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition terminates communication between the memory device and the bus master. A STOP condition at the end of a Read command, after (and only after) a NoAck, forces the memory device into its standby state. A STOP condition at the end of a Write command triggers the internal EEPROM write cycle. Acknowledge Bit (ACK) An acknowledge signal is used to indicate a successful byte transfer. The bus transmitter, whether it be master or slave, releases the SDA bus after sending eight bits of data. During the 9th clock pulse period, the receiver pulls the SDA bus low to acknowledge the receipt of the eight data bits. Data Input During data input, the memory device samples the SDA bus signal on the rising edge of the clock, SCL. For correct device operation, the SDA signal Figure 3. Maximum R L Value versus Bus Capacitance (CBUS) for an I2C Bus VCC Maximum RP value (kΩ) 20 16 RL 12 RL SDA MASTER 8 fc = 100kHz 4 fc = 400kHz CBUS SCL CBUS 0 10 100 1000 CBUS (pF) AI01665 3/17 M24256, M24128 Figure 4. I2C Bus Protocol SCL SDA SDA Input START Condition SCL 1 SDA MSB 2 SDA Change STOP Condition 3 7 8 9 ACK START Condition SCL 1 SDA MSB 2 3 7 8 9 ACK STOP Condition AI00792B must be stable during the clock low-to-high transition, and the data must change only when the SCL line is low. Memory Addressing To start communication between the bus master and the slave memory, the master must initiate a START condition. Following this, the master sends the 8-bit byte, shown in Table 3, on the SDA bus line (most significant bit first). This consists of the 7-bit Device Select Code, and the 1-bit Read/Write Designator (RW). The Device Select Code is fur- ther subdivided into: a 4-bit Device Type Identifier, and a 3-bit Chip Enable “Address” (0, 0, 0). To address the memory array, the 4-bit Device Type Identifier is 1010b. The 8th bit is the RW bit. This is set to ‘1’ for read and ‘0’ for write operations. If a match occurs on the Device Select Code, the corresponding memory gives an acknowledgment on the SDA bus during the 9th bit time. If the memory does not match the Device Select Code, it deselects itself from the bus, and goes into stand-by mode. Table 3. Device Select Code 1 Device Type Identifier Device Select Code RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 1 0 0 0 0 RW Note: 1. The most significant bit, b7, is sent first. 4/17 Chip Enable M24256, M24128 Table 4. Operating Modes Mode Current Address Read RW bit WC 1 Data Bytes 1 X 1 0 X Initial Sequence START, Device Select, RW = ‘1’ START, Device Select, RW = ‘0’, Address Random Address Read 1 1 X reSTART, Device Select, RW = ‘1’ Sequential Read 1 X ≥1 Byte Write 0 VIL 1 START, Device Select, RW = ‘0’ Page Write 0 VIL ≤ 64 START, Device Select, RW = ‘0’ Similar to Current or Random Address Read Note: 1. X = VIH or VIL. There are two modes both for read and write. These are summarized in Table 4 and described later. A communication between the master and the slave is ended with a STOP condition. Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant Byte (Ta- ble 5) is sent first, followed by the Least significant Byte (Table 6). Bits b15 to b0 form the address of the byte in memory. Bit b15 is treated as a Don’t Care bit on the M24256 memory. Bits b15 and b14 are treated as Don’t Care bits on the M24128 memory. Figure 5. Write Mode Sequences with WC=1 (data write inhibited) WC ACK BYTE ADDR ACK BYTE ADDR NO ACK DATA IN STOP DEV SEL START BYTE WRITE ACK R/W WC ACK DEV SEL START PAGE WRITE ACK BYTE ADDR ACK BYTE ADDR NO ACK DATA IN 1 DATA IN 2 R/W WC (cont'd) NO ACK DATA IN N STOP PAGE WRITE (cont'd) NO ACK AI01120C 5/17 M24256, M24128 Figure 6. Write Mode Sequences with WC=0 (data write enabled) WC ACK BYTE ADDR ACK BYTE ADDR ACK DATA IN STOP DEV SEL START BYTE WRITE ACK R/W WC ACK DEV SEL START PAGE WRITE ACK BYTE ADDR ACK BYTE ADDR ACK DATA IN 1 DATA IN 2 R/W WC (cont'd) ACK ACK DATA IN N STOP PAGE WRITE (cont'd) AI01106B Table 5. Most Significant Byte b15 b14 b13 b12 b11 b10 b9 b8 Note: 1. b15 is treated as Don’t Care on the M24256 series. b15 and b14 are Don’t Care on the M24128 series. Table 6. Least Significant Byte b7 b6 b5 b4 b3 b2 b1 b0 Write Operations Following a START condition the master sends a Device Select Code with the RW bit set to ’0’, as shown in Table 4. The memory acknowledges this, and waits for two address bytes. The memory responds to each address byte with an acknowledge bit, and then waits for the data byte. Writing to the memory may be inhibited if the WC input pin is taken high. Any write command with WC=1 (during a period of time from the START 6/17 condition until the end of the two address bytes) will not modify the memory contents, and the accompanying data bytes will not be acknowledged, as shown in Figure 5. Byte Write In the Byte Write mode, after the Device Select Code and the address bytes, the master sends one data byte. If the addressed location is write protected by the WC pin, the memory replies with a NoAck, and the location is not modified. If, instead, the WC pin has been held at 0, as shown in Figure 6, the memory replies with an Ack. The master terminates the transfer by generating a STOP condition. Page Write The Page Write mode allows up to 64 bytes to be written in a single write cycle, provided that they are all located in the same ’row’ in the memory: that is the most significant memory address bits (b14-b6 for the M24256 and b13-b6 for the M24128) are the same. If more bytes are sent than M24256, M24128 Figure 7. Write Cycle Polling Flowchart using ACK WRITE Cycle in Progress START Condition DEVICE SELECT with RW = 0 NO First byte of instruction with RW = 0 already decoded by the device ACK Returned YES NO Next Operation is Addressing the Memory YES Send Address and Receive ACK ReSTART NO STOP START Condition YES DATA for the WRITE Operation DEVICE SELECT with RW = 1 Continue the WRITE Operation Continue the Random READ Operation will fit up to the end of the row, a condition known as ‘roll-over’ occurs. Data starts to become overwritten (in a way not formally specified in this data sheet). The master sends from one up to 64 bytes of data, each of which is acknowledged by the memory if the WC pin is low. If the WC pin is high, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck. After each byte is transferred, the internal byte address counter (the 6 least significant bits only) is incremented. The transfer is terminated by the master generating a STOP condition. When the master generates a STOP condition immediately after the Ack bit (in the “10th bit” time slot), either at the end of a byte write or a page write, the internal memory write cycle is triggered. A STOP condition at any other time does not trigger the internal write cycle. AI01847C During the internal write cycle, the SDA input is disabled internally, and the device does not respond to any requests. Minimizing System Delays by Polling On ACK During the internal write cycle, the memory disconnects itself from the bus, and copies the data from its internal latches to the memory cells. The maximum write time (t w) is shown in Table 10, but the typical time is shorter. To make use of this, an Ack polling sequence can be used by the master. The sequence, as shown in Figure 7, is: – Initial condition: a Write is in progress. – Step 1: the master issues a START condition followed by a Device Select Code (the first byte of the new instruction). – Step 2: if the memory is busy with the internal write cycle, no Ack will be returned and the master goes back to Step 1. If the memory has ter- 7/17 M24256, M24128 Figure 8. Read Mode Sequences ACK DATA OUT STOP START DEV SEL NO ACK R/W ACK START DEV SEL * ACK BYTE ADDR ACK DEV SEL * ACK NO ACK DATA OUT N R/W ACK ACK BYTE ADDR R/W ACK ACK BYTE ADDR ACK DEV SEL * START START DEV SEL * DATA OUT R/W ACK DATA OUT 1 NO ACK STOP START DEV SEL SEQUENTIAL RANDOM READ BYTE ADDR R/W ACK SEQUENTIAL CURRENT READ ACK START RANDOM ADDRESS READ STOP CURRENT ADDRESS READ ACK DATA OUT 1 R/W NO ACK STOP DATA OUT N AI01105C st th Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1 and 4 bytes) must be identical. minated the internal write cycle, it responds with an Ack, indicating that the memory is ready to receive the second part of the next instruction (the first byte of this instruction having been sent during Step 1). Read Operations Read operations are performed independently of the state of the WC pin. Random Address Read A dummy write is performed to load the address into the address counter, as shown in Figure 8. Then, without sending a STOP condition, the master sends another START condition, and repeats 8/17 the Device Select Code, with the RW bit set to ‘1’. The memory acknowledges this, and outputs the contents of the addressed byte. The master must not acknowledge the byte output, and terminates the transfer with a STOP condition. Current Address Read The device has an internal address counter which is incremented each time a byte is read. For the Current Address Read mode, following a START condition, the master sends a Device Select Code with the RW bit set to ‘1’. The memory acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then in- M24256, M24128 Table 7. DC Characteristics (TA = –40 to 85 °C; VCC = 4.5 to 5.5 V or 2.5 to 5.5 V) Symbol Parameter Test Condition Min. Max. Unit ILI Input Leakage Current (SCL, SDA) 0 V ≤ VIN ≤ VCC ±2 µA ILO Output Leakage Current 0 V ≤ VOUT ≤ VCC, SDA in Hi-Z ±2 µA VCC=5V, fc=400kHz (rise/fall time < 30ns) 2 mA ICC Supply Current VCC =2.5V, fc=400kHz (rise/fall time < 30ns) 1 mA VIN = VSS or VCC , VCC = 5 V 10 µA VIN = VSS or VCC , VCC = 2.5 V 2 µA -W series: ICC1 Supply Current (Stand-by) VIL Input Low Voltage (SCL, SDA) –0.3 0.3VCC V VIH Input High Voltage (SCL, SDA) 0.7VCC VCC+1 V VIL Input Low Voltage (WC) –0.3 0.5 V VIH Input High Voltage (WC) 0.7VCC VCC+1 V Output Low Voltage IOL = 3 mA, VCC = 5 V 0.4 V VOL IOL = 2.1 mA, VCC = 2.5 V 0.4 V -W series: -W series: Table 8. Input Parameters 1 (TA = 25 °C, f = 400 kHz) Symbol Parameter Test Condition Min. Max. Unit CIN Input Capacitance (SDA) 8 pF CIN Input Capacitance (other pins) 6 pF ZL Input Impedance (WC) VIN ≤ 0.5 V 5 kΩ ZH Input Impedance (WC) VIN ≥ 0.7VCC 500 kΩ tNS Low Pass Filter Input Time Constant (SCL and SDA) 100 ns Note: 1. Sampled only, not 100% tested. Table 9. AC Measurement Conditions Input Rise and Fall Times ≤ 50 ns Input Pulse Voltages 0.2VCC to 0.8VCC Input and Output Timing Reference Voltages 0.3VCC to 0.7VCC Figure 9. AC Testing Input Output Waveforms 0.8VCC 0.2VCC 0.7VCC 0.3VCC AI00825 9/17 M24256, M24128 Table 10. AC Characteristics M24256 / M24128 Symbol Alt. Parameter VCC=4.5 to 5.5 V TA=–40 to 85°C Min Max VCC=2.5 to 5.5 V TA=–40 to 85°C Min Unit Max tCH1CH2 tR Clock Rise Time 300 300 ns tCL1CL2 tF Clock Fall Time 300 300 ns tDH1DH2 2 tR SDA Rise Time 20 300 20 300 ns tDL1DL2 2 tF SDA Fall Time 20 300 20 300 ns tCHDX 1 tSU:STA Clock High to Input Transition 600 600 ns tCHCL tHIGH Clock Pulse Width High 600 600 ns tDLCL tHD:STA Input Low to Clock Low (START) 600 600 ns tCLDX tHD:DAT Clock Low to Input Transition 0 0 µs tCLCH tLOW Clock Pulse Width Low 1.3 1.3 µs tDXCX tSU:DAT Input Transition to Clock Transition 100 100 ns tCHDH tSU:STO Clock High to Input High (STOP) 600 600 ns tDHDL tBUF Input High to Input Low (Bus Free) 1.3 1.3 µs tCLQV 3 tAA Clock Low to Data Out Valid 200 tCLQX tDH Data Out Hold Time After Clock Low 200 fC fSCL Clock Frequency 400 400 kHz tW tWR Write Time 10 10 ms 900 200 900 200 ns ns Note: 1. For a reSTART condition, or following a write cycle. 2. Sampled only, not 100% tested. 3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. cremented. The master terminates the transfer with a STOP condition, as shown in Figure 8, without acknowledging the byte output. Sequential Read This mode can be initiated with either a Current Address Read or a Random Address Read. The master does acknowledge the data byte output in this case, and the memory continues to output the next byte in sequence. To terminate the stream of bytes, the master must not acknowledge the last byte output, and must generate a STOP condition. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter ‘rolls-over’ and the memory continues to output data from memory address 00h. 10/17 Acknowledge in Read Mode In all read modes, the memory waits, after each byte read, for an acknowledgment during the 9th bit time. If the master does not pull the SDA line low during this time, the memory terminates the data transfer and switches to its stand-by state. M24256, M24128 Figure 10. AC Waveforms tCHCL tCLCH SCL tDLCL SDA In tCHDX tCLDX START Condition SDA Input SDA tDXCX Change tCHDH tDHDL START STOP Condition Condition SCL SDA In tCHDH tW STOP Condition Write Cycle tCHDX START Condition SCL tCLQV SDA Out tCLQX Data Valid AI00795C 11/17 M24256, M24128 Table 11. Ordering Information Scheme Example: M24256 – W MN 1 T Memory Capacity 256 256 Kbit (32K x 8) 128 128 Kbit (16K x 8) Option T Tape and Reel Packing Temperature Range 6 –40 °C to 85 °C 5 –20 °C to 85 °C Operating Voltage blank1 4.5 V to 5.5 V W 2.5 V to 5.5 V Package BN PDIP8 (0.25 mm frame) MN2 SO8 (150 mil width) MW3 SO8 (200 mil width) Note: 1. Available only on request. 2. Available for M24128 only. 3. Available for M24256 only. ORDERING INFORMATION Devices are shipped from the factory with the memory content set at all 1s (FFh). The notation used for the device number is as shown in Table 11. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office. 12/17 M24256, M24128 PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame E b2 A2 A1 b A L c e eA eB D 8 E1 1 PDIP-8 Note: 1. Drawing is not to scale. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame mm inches Symb. Typ. Min. A Max. Typ. Min. 5.33 A1 Max. 0.210 0.38 0.015 A2 3.30 2.92 4.95 0.130 0.115 0.195 b 0.46 0.36 0.56 0.018 0.014 0.022 b2 1.52 1.14 1.78 0.060 0.045 0.070 c 0.25 0.20 0.36 0.010 0.008 0.014 D 9.27 9.02 10.16 0.365 0.355 0.400 E 7.87 7.62 8.26 0.310 0.300 0.325 E1 6.35 6.10 7.11 0.250 0.240 0.280 e 2.54 – – 0.100 – – eA 7.62 – – 0.300 – – eB L 10.92 3.30 2.92 3.81 0.430 0.130 0.115 0.150 13/17 M24256, M24128 SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width h x 45˚ A C B CP e D N E H 1 α A1 L SO-a Note: Drawing is not to scale. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width mm inches Symb. Typ. Min. Max. A 1.35 A1 Min. Max. 1.75 0.053 0.069 0.10 0.25 0.004 0.010 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.80 4.00 0.150 0.157 – – – – H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.40 0.90 0.016 0.035 α 0° 8° 0° 8° N 8 e CP 14/17 1.27 Typ. 0.050 8 0.10 0.004 M24256, M24128 SO8 wide – 8 lead Plastic Small Outline, 200 mils body width A A2 C B CP e D N E H 1 A1 α L SO-b Note: Drawing is not to scale. SO8 wide – 8 lead Plastic Small Outline, 200 mils body width mm inches Symb. Typ. Min. A Max. Typ. Min. 2.03 A1 0.10 A2 0.080 0.25 0.004 1.78 B 0.35 0.45 – – D 5.15 E Max. 0.010 0.070 0.014 0.018 – – 5.35 0.203 0.211 5.20 5.40 0.205 0.213 – – – – H 7.70 8.10 0.303 0.319 L 0.50 0.80 0.020 0.031 α 0° 10° 0° 10° N 8 C e CP 0.20 1.27 0.008 0.050 8 0.10 0.004 15/17 M24256, M24128 Table 12. Revision History Date Rev. Description of Revision 30-Mar-2001 2.2 References added to the M24256B and M24128B products Lead Soldering Temperature in the Absolute Maximum Ratings table amended Write Cycle Polling Flow Chart using ACK illustration updated References to PSDIP8 changed to PDIP8, and Package Mechanical data updated 01-Jun-2001 2.3 Document promoted from “Preliminary Data” to “Full Data Sheet” 16/17 M24256, M24128 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © 2001 STMicroelectronics - All Rights Reserved The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 17/17