STMicroelectronics M24512-RDW6P 512 kbit and 256 kbit serial i2c bus eeprom with three chip enable line Datasheet

M24512-W M24512-R
M24256-BW M24256-BR
512 Kbit and 256 Kbit Serial I²C bus EEPROM
with three Chip Enable lines
Feature summary
■
Two-wire I2C Serial interface
supports 400 kHz Protocol
■
Supply voltage ranges:
■
1.8 V to 5.5 V (M24xxx-R)
■
2.5 V to 5.5 V (M24xxx-W)
■
Write Control Input
■
Byte and Page Write
■
Random and sequential read modes
■
Self-timed programming cycle
■
Automatic Address Incrementing
■
Enhanced ESD/Latch-Up Protection
■
More than 1,000,000 Write cycles
■
More than 40-year data retention
■
Packages
– ECOPACK® (RoHS compliant)
8
1
SO8 (MW)
208 mils width
8
1
SO8 (MN)
150 mils width
TSSOP8 (DW)
October 2006
Rev 6
1/31
www.st.com
1
Contents
M24512-W, M24512-R, M24256-BW, M24256-BR
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5.1
3
2.5.2
Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Internal device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5.3
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1
Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2
Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3
Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4
Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5
Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.6
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.8
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.9
ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . . . 15
3.10
Minimizing System Delays by Polling On ACK . . . . . . . . . . . . . . . . . . . . . 16
3.11
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.12
Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.13
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.14
Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.15
Acknowledge in Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/31
M24512-W, M24512-R, M24256-BW, M24256-BR
Contents
6
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3/31
List of tables
M24512-W, M24512-R, M24256-BW, M24256-BR
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
4/31
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Most Significant address Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Least Significant address Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Operating conditions (M24xxx-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Operating conditions (M24xxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC characteristics (M24xxx-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC characteristics (M24xxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
AC characteristics (M24xxx-W, see Table 7 and Table 9) . . . . . . . . . . . . . . . . . . . . . . . . . 22
AC characteristics (M24xxx-R, see Table 8 and Table 9). . . . . . . . . . . . . . . . . . . . . . . . . . 23
SO8W – 8 lead Plastic Small Outline, 208 mils body width, package mechanical data . . . 25
SO8N – 8 lead Plastic Small Outline, 150 mils body width, package mechanical data . . . 26
TSSOP8 – 8 lead Thin Shrink Small Outline, package mechanical data . . . . . . . . . . . . . . 27
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
M24512-W, M24512-R, M24256-BW, M24256-BR
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SO and TSSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Maximum RP Value versus Bus Parasitic Capacitance (C) for an I2C Bus . . . . . . . . . . . . . 9
I2C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write Mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Cycle Polling Flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SO8W – 8 lead Plastic Small Outline, 208 mils body width, package outline. . . . . . . . . . . 25
SO8N – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . . . . . . . 26
TSSOP8 – 8 lead Thin Shrink Small Outline, package outline . . . . . . . . . . . . . . . . . . . . . . 27
5/31
Summary description
1
M24512-W, M24512-R, M24256-BW, M24256-BR
Summary description
The M24512-W, M24512-R, M24256-BW and M24256-BR devices are I2C-compatible
electrically erasable programmable memories (EEPROM). They are organized as 64 Kb × 8
bits and 32 Kb × 8 bits, respectively.
I2C uses a two-wire serial interface, comprising a bi-directional data line and a clock line.
The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the
I2C bus definition.
The device behaves as a slave in the I2C protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are initiated by a Start condition, generated
by the bus master. The Start condition is followed by a Device Select Code and Read/Write
bit (RW) (as described in Table 2), terminated by an acknowledge bit.
When writing data to the memory, the device inserts an acknowledge bit during the 9th bit
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages.
ECOPACK® packages are Lead-free and RoHS compliant.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 1.
Logic diagram
VCC
3
E0-E2
SCL
M24512-W
M24512-R
M24256-BW
M24256-BR
SDA
WC
VSS
AI02275c
Table 1.
6/31
Signal names
E0, E1, E2
Chip Enable
SDA
Serial Data
SCL
Serial Clock
WC
Write Control
VCC
Supply Voltage
VSS
Ground
M24512-W, M24512-R, M24256-BW, M24256-BR
Figure 2.
Summary description
SO and TSSOP connections
M24512-W
M24512-R
M24256-BW
M24256-BR
E0
E1
E2
VSS
1
2
3
4
8
7
6
5
VCC
WC
SCL
SDA
AI04035d
1. See Package mechanical section for package dimensions, and how to identify pin-1.
7/31
Signal description
M24512-W, M24512-R, M24256-BW, M24256-BR
2
Signal description
2.1
Serial Clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this
signal is used by slave devices to synchronize the bus to a slower clock, the bus master
must have an open drain output, and a pull-up resistor must be connected from Serial Clock
(SCL) to VCC. (Figure 4. indicates how the value of the pull-up resistor can be calculated). In
most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the bus master has a push-pull (rather than open
drain) output.
2.2
Serial Data (SDA)
This bi-directional signal is used to transfer data in or out of the device. It is an open drain
output that may be wire-OR’ed with other open drain or open collector signals on the bus. A
pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 4. indicates how
the value of the pull-up resistor can be calculated).
2.3
Chip Enable (E0, E1, E2)
These input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2, b1) of the 7-bit Device Select Code. These inputs must be tied to
VCC or VSS, to establish the Device Select Code. When not connected (left floating), these
inputs are read as Low (0,0,0).
Figure 3.
Device Select Code
VCC
VCC
M24xxx
M24xxx
Ei
Ei
VSS
VSS
Ai12806
2.4
Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven High. When unconnected, the signal is internally read as VIL, and
Write operations are allowed.
When Write Control (WC) is driven High, Device Select and Address bytes are
acknowledged, Data bytes are not acknowledged.
8/31
M24512-W, M24512-R, M24256-BW, M24256-BR
2.5
Supply voltage (VCC)
2.5.1
Operating supply voltage VCC
Signal description
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Table 7 and Table 8).
In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line
with a suitable capacitor (usually of the order of 10nF to 100nF) close to the VCC/VSS
package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (tW).
2.5.2
Internal device reset
In order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR)
circuit is included. At Power-up (continuous rise of VCC), the device does not respond to any
instruction until VCC has reached the Power On Reset threshold voltage (this threshold is
lower than the minimum VCC operating voltage defined in Table 7 and Table 8).
When VCC has passed the POR threshold, the device is reset and is in Standby Power
mode.
Power-down
At Power-down (continuous decrease of VCC), as soon as VCC drops from the normal
operating voltage to below the Power On Reset threshold voltage, the device stops
responding to any instruction sent to it.
During Power-down, the device must be deselected and in the Standby Power mode (that is
there should be no internal Write cycle in progress).
Figure 4.
Maximum RP Value versus Bus Parasitic Capacitance (C) for an I2C Bus
VCC
20
Maximum RP value (kΩ)
2.5.3
16
RP
12
RP
SDA
MASTER
8
fc = 100kHz
4
fc = 400kHz
C
SCL
C
0
10
100
1000
C (pF)
AI01665b
9/31
Signal description
Figure 5.
M24512-W, M24512-R, M24256-BW, M24256-BR
I2C Bus Protocol
SCL
SDA
SDA
Input
START
Condition
SCL
1
2
SDA
MSB
SDA
Change
STOP
Condition
3
7
8
9
ACK
START
Condition
SCL
1
SDA
MSB
2
3
7
8
9
ACK
STOP
Condition
AI00792B
Table 2.
Device Select Code
Device Type Identifier(1)
Chip Enable Address(2)
RW
b7
b6
b5
b4
b3
b2
b1
b0
1
0
1
0
E2
E1
E0
RW
Device Select Code
1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
Table 3.
b15
Table 4.
b7
10/31
Most Significant address Byte
b14
b13
b12
b11
b10
b9
b8
b3
b2
b1
b0
Least Significant address Byte
b6
b5
b4
M24512-W, M24512-R, M24256-BW, M24256-BR
3
Device operation
Device operation
The device supports the I2C protocol. This is summarized in Figure 5.. Any device that
sends data on to the bus is defined to be a transmitter, and any device that reads the data to
be a receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The M24512 device is always a slave in all
communication.
3.1
Start Condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the High state. A Start condition must precede any data transfer command. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition, and will not respond unless one is given.
3.2
Stop Condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven High. A Stop condition terminates communication between the device and the
bus master. A Read command that is followed by NoAck can be followed by a Stop condition
to force the device into the Stand-by mode. A Stop condition at the end of a Write command
triggers the internal Write cycle.
3.3
Acknowledge Bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to
acknowledge the receipt of the eight data bits.
3.4
Data Input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven Low.
11/31
Device operation
3.5
M24512-W, M24512-R, M24256-BW, M24256-BR
Memory Addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the Device Select Code,
shown in Table 2. (on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable
“Address” (E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is
1010b.
Up to eight memory devices can be connected on a single I2C bus. Each one is given a
unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the Device Select Code is
received, the device only responds if the Chip Enable Address is the same as the value on
the Chip Enable (E0, E1, E2) inputs.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match
the Device Select code, it deselects itself from the bus, and goes into Stand-by mode.
Table 5.
Operating modes
RW bit
WC(1)
Bytes
1
X
1
Random Address
Read
0
X
1
X
Sequential Read
1
X
≥1
Byte Write
0
VIL
1
Mode
Current Address
Read
Initial Sequence
START, Device Select, RW = 1
START, Device Select, RW = 0, Address
1
reSTART, Device Select, RW = 1
Similar to Current or Random Address
Read
START, Device Select, RW = 0
≤128 for 512
Kbit devices
Page Write
1. X = VIH or VIL.
12/31
0
VIL
≤64 for 256
Kbit devices
START, Device Select, RW = 0
M24512-W, M24512-R, M24256-BW, M24256-BR
Figure 6.
Device operation
Write mode sequences with WC = 1 (data write inhibited)
WC
ACK
BYTE ADDR
ACK
BYTE ADDR
NO ACK
DATA IN
STOP
DEV SEL
START
BYTE WRITE
ACK
R/W
WC
ACK
DEV SEL
START
PAGE WRITE
ACK
BYTE ADDR
ACK
BYTE ADDR
NO ACK
DATA IN 1
DATA IN 2
R/W
WC (cont'd)
NO ACK
DATA IN N
STOP
PAGE WRITE
(cont'd)
NO ACK
AI01120C
13/31
Device operation
3.6
M24512-W, M24512-R, M24256-BW, M24256-BR
Write operations
Following a Start condition the bus master sends a Device Select Code with the Read/Write
bit (RW) reset to 0. The device acknowledges this, as shown in Figure 7., and waits for two
address bytes. The device responds to each address byte with an acknowledge bit, and
then waits for the data byte.
Writing to the memory may be inhibited if Write Control (WC) is driven High. Any Write
instruction with Write Control (WC) driven High (during a period of time from the Start
condition until the end of the two address bytes) will not modify the memory contents, and
the accompanying data bytes are not acknowledged, as shown in Figure 6..
Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant
Byte (Table 3.) is sent first, followed by the Least Significant Byte (Table 4.). Bits b15 to b0
form the address of the byte in memory.
When the bus master generates a Stop condition immediately after the Ack bit (in the “10th
bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle is
triggered. A Stop condition at any other time slot does not trigger the internal Write cycle.
After the Stop condition, the delay tW, and the successful completion of a Write operation,
the device’s internal address counter is incremented automatically, to point to the next byte
address after the last one that was modified.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
3.7
Byte Write
After the Device Select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven High, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in Figure 7.
3.8
Page Write
The Page Write mode allows up to 64 bytes (for the M24256-BW and M24256-BR) or 128
bytes (for the M24512-W and M24512-R) to be written in a single Write cycle, provided that
they are all located in the same ’row’ in the memory: that is, the most significant memory
address bits (b15-b6 for the M24256-BW and M24256-BR, and b15-b7 for the M24512-W
and M24512-R) are the same. If more bytes are sent than will fit up to the end of the row, a
condition known as ‘roll-over’ occurs. This should be avoided, as data starts to become
overwritten in an implementation dependent way.
The bus master sends from 1 to 64 bytes (for the M24256-BW and M24256-BR) or from 1 to
128 bytes (for the M24512-W and M24512-R) of data, each of which is acknowledged by the
device if Write Control (WC) is Low. If Write Control (WC) is High, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck.
After each byte is transferred, the internal byte address counter (the 7 least significant
address bits only) is incremented. The transfer is terminated by the bus master generating a
Stop condition.
14/31
M24512-W, M24512-R, M24256-BW, M24256-BR
3.9
Device operation
ECC (Error Correction Code) and Write cycling
The M24512-W, M24512-R, M24256-BW and M24256-BR devices offer an ECC (Error
Correction Code) logic which compares each 4-byte packet with its associated ECC bits (6
EEPROM bits). As a result, if a single bit out of 4 bytes of data happens to be erroneous
during a Read operation, the ECC detects it and replaces it by the correct value. The read
reliability is therefore much improved by the use of this feature.
Note however that even if a single byte has to be written, 4 bytes are internally modified
(plus the ECC bits), that is, the addressed Byte is cycled together with the other three bytes
making up the packet. It is therefore recommended to write by packets of 4 bytes in order to
benefit from the larger amount of Write cycles.
The M24512-W, M24512-R, M24256-BW and M24256-BR devices are qualified at 1 million
(1,000,000) Write cycles, using a cycling routine that writes to the device by multiples of 4bytes.
Note that the M24512-W and M24512-R in SO8 Wide package (MW) are offered with either
the previous die qualified at 100.000 Write cycles or the new die (qualified at 1 Million Write
cycles). The two dice are distinguished by their respective process letter: "V" for the
previous die and " A" for the new die. Please contact your nearest ST sales office for more
information.
Figure 7.
Write Mode sequences with WC = 0 (data write enabled)
WC
ACK
ACK
BYTE ADDR
ACK
BYTE ADDR
ACK
DATA IN
STOP
DEV SEL
START
BYTE WRITE
R/W
WC
ACK
PAGE WRITE
DEV SEL
START
ACK
BYTE ADDR
ACK
BYTE ADDR
ACK
DATA IN 1
DATA IN 2
R/W
WC (cont'd)
ACK
PAGE WRITE
(cont'd)
ACK
DATA IN N
STOP
Caution:
AI01106C
15/31
Device operation
Figure 8.
M24512-W, M24512-R, M24256-BW, M24256-BR
Write Cycle Polling Flowchart using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
NO
First byte of instruction
with RW = 0 already
decoded by the device
ACK
Returned
YES
NO
Next
Operation is
Addressing the
Memory
YES
Send Address
and Receive ACK
ReSTART
NO
STOP
START
Condition
YES
DATA for the
WRITE Operation
DEVICE SELECT
with RW = 1
Continue the
WRITE Operation
Continue the
Random READ Operation
AI01847C
3.10
Minimizing System Delays by Polling On ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (tw) is
shown in Table 13., but the typical time is shorter. To make use of this, a polling sequence
can be used by the bus master.
The sequence, as shown in Figure 8., is:
16/31
●
Initial condition: a Write cycle is in progress.
●
Step 1: the bus master issues a Start condition followed by a Device Select Code (the
first byte of the new instruction).
●
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
M24512-W, M24512-R, M24256-BW, M24256-BR
3.11
Device operation
Read Operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device’s internal address counter is
incremented by one, to point to the next byte address.
3.12
Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 9.) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the Device Select Code, with the Read/Write bit (RW) set to 1. The
device acknowledges this, and outputs the contents of the addressed byte. The bus master
must not acknowledge the byte, and terminates the transfer with a Stop condition.
3.13
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a Device Select Code with the Read/Write bit (RW) set to 1. The device
acknowledges this, and outputs the byte addressed by the internal address counter. The
counter is then incremented. The bus master terminates the transfer with a Stop condition,
as shown in Figure 9., without acknowledging the byte.
3.14
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 9.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory address
00h.
17/31
Device operation
Read mode sequences
ACK
CURRENT
ADDRESS
READ
DATA OUT
STOP
START
DEV SEL
NO ACK
R/W
ACK
START
DEV SEL *
ACK
BYTE ADDR
ACK
DEV SEL *
ACK
DATA OUT 1
ACK
ACK
NO ACK
DATA OUT N
BYTE ADDR
ACK
BYTE ADDR
ACK
DEV SEL *
START
START
ACK
R/W
ACK
DATA OUT
R/W
R/W
DEV SEL *
NO ACK
STOP
START
DEV SEL
SEQUENTIAL
RANDOM
READ
BYTE ADDR
R/W
ACK
SEQUENTIAL
CURRENT
READ
ACK
START
RANDOM
ADDRESS
READ
STOP
Figure 9.
M24512-W, M24512-R, M24256-BW, M24256-BR
ACK
DATA OUT 1
R/W
NO ACK
STOP
DATA OUT N
AI01105C
1. The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 4th bytes)
must be identical.
3.15
Acknowledge in Read Mode
For all Read commands, the device waits, after each byte read, for an acknowledgment
during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this
time, the device terminates the data transfer and switches to its Stand-by mode.
18/31
M24512-W, M24512-R, M24256-BW, M24256-BR
4
Initial delivery state
Initial delivery state
The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).
5
Maximum rating
Stressing the device outside the ratings listed in Table 6 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the Operating sections of this specification, is not
implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant
quality documents.
Table 6.
Absolute maximum ratings
Symbol
TA
TSTG
TLEAD
Parameter
Min.
Max.
Unit
Ambient Operating Temperature
–40
130
°C
Storage Temperature
–65
150
°C
Lead Temperature during Soldering
See
note (1)
°C
VIO
Input or Output range
–0.50
6.5
V
VCC
Supply Voltage
–0.50
6.5
V
VESD
Electrostatic Discharge Voltage (Human Body model) (2)
–4000
4000
V
ECOPACK®
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω)
19/31
DC and AC parameters
6
M24512-W, M24512-R, M24256-BW, M24256-BR
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC Characteristic tables that
follow are derived from tests performed under the Measurement Conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 7.
Operating conditions (M24xxx-W)
Symbol
VCC
TA
Table 8.
Parameter
Min.
Max.
Unit
Supply Voltage
2.5
5.5
V
Ambient Operating Temperature
–40
85
°C
Min.
Max.
Unit
Supply Voltage
1.8
5.5
V
Ambient Operating Temperature
–40
85
°C
Operating conditions (M24xxx-R)
Symbol
VCC
TA
Table 9.
Parameter
AC test measurement conditions
Symbol
CL
Parameter
Min.
Load Capacitance
Max.
100
Input Rise and Fall Times
pF
50
ns
Input Levels
0.2VCC to 0.8VCC
V
Input and Output Timing Reference Levels
0.3VCC to 0.7VCC
V
Figure 10. AC test measurement I/O waveform
Input Levels
0.8VCC
0.2VCC
Input and Output
Timing Reference Levels
0.7VCC
0.3VCC
AI00825B
20/31
Unit
M24512-W, M24512-R, M24256-BW, M24256-BR
Table 10.
Symbol
DC and AC parameters
Input parameters
Parameter(1),(2)
Test Condition
Min.
Max.
Unit
CIN
Input Capacitance (SDA)
8
pF
CIN
Input Capacitance (other pins)
6
pF
ZL(3)
Input Impedance
(E2, E1, E0, WC)
VIN < 0.3VCC
30
kΩ
ZH(3)
Input Impedance
(E2, E1, E0, WC)
VIN > 0.7VCC
500
kΩ
Pulse width ignored
(Input Filter on SCL and SDA)
Single glitch
tNS
100
ns
1. TA = 25 °C, f = 400 kHz
2. Sampled only, not 100% tested.
3. E2,E1,E0: Input impedance when the memory is selected (after a Start condition).
Table 11.
Symbol
DC characteristics (M24xxx-W)
Parameter
Test conditions (see Table 7 and
Table 9)
Min.
Max.
Unit
ILI
Input Leakage Current
(SCL, SDA, E0, E1, E2)
VIN = VSS or VCC
device in Standby mode(1)
±2
µA
ILO
Output Leakage Current
VOUT = VSS or VCC, SDA in Hi-Z
±2
µA
VCC = 2.5V, fc=400kHz (rise/fall time
< 30ns)
1
mA
VCC = 5.5V, fc=400kHz (rise/fall time
< 30ns)
2
mA
During tW, 2.5V < VCC < 5.5V
5(2)
mA
VIN = VSS or VCC, VCC = 2.5 V
2
µA
VIN = VSS or VCC, VCC = 5.5 V
5
µA
ICC
Supply Current (Read)
ICC0
Supply Current (Write)
ICC1
Stand-by Supply Current
VIL
Input Low Voltage
(SCL, SDA, WC)
–0.45
0.3VCC
V
VIH
Input High Voltage
(SCL, SDA, WC)
0.7VCC
VCC+1
V
VOL
Output Low Voltage
0.4
V
IOL = 2.1 mA, VCC = 2.5 V
1. When the device is selected (after a START condition), the Ei inputs have a different input impedance, as
defined in Table 10.
2. Characterized value, not tested in production.
21/31
DC and AC parameters
Table 12.
M24512-W, M24512-R, M24256-BW, M24256-BR
DC characteristics (M24xxx-R)
Symbol
Parameter
Test conditions (see Table 8 and
Table 9)
ILI
Input Leakage Current
(SCL, SDA, E2, E1, E0)
ILO
Min.
Max.
Unit
VIN = VSS or VCC
device in Stand-by mode
±2
µA
Output Leakage
Current
VOUT = VSS or VCC, SDA in Hi-Z
±2
µA
ICC
Supply Current (Read)
VCC =1.8V, fc = 400kHz (rise/fall
time < 30ns)
1
mA
ICC0
Supply Current (Write)
During tW, 1.8V < VCC < 5.5V
5(1)
mA
ICC1
Standby Supply Current
VIN = VSS or VCC, VCC = 1.8 V
2
µA
VIL
Input Low Voltage
–0.45
0.3 VCC
V
VIH
Input High Voltage
0.7VCC
VCC+1
V
VOL
Output Low Voltage
0.2
V
IOL = 0.7 mA, VCC = 1.8 V
1. Characterized value, not tested in production.
Table 13.
AC characteristics (M24xxx-W, see Table 7 and Table 9)
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCL
Clock Frequency
400
kHz
tCHCL
tHIGH
Clock Pulse Width High
600
ns
tCLCH
tLOW
Clock Pulse Width Low
1300
ns
tCH1CH2
tR
Clock Rise Time
300
ns
tCL1CL2
tF
Clock Fall Time
300
ns
tDH1DH2(1)
tDL1DL2(1)
tR
SDA Rise Time
20
300
ns
tF
SDA Fall Time
20
300
ns
tDXCX
tSU:DAT
Data In Set Up Time
100
ns
tCLDX
tHD:DAT
Data In Hold Time
0
ns
tCLQX
tDH
Data Out Hold Time
200
ns
tCLQV(2)
tCHDX(3)
tAA
Clock Low to Next Data Valid (Access Time)
200
tSU:STA
Start Condition Set Up Time
600
ns
tDLCL
tHD:STA
Start Condition Hold Time
600
ns
tCHDH
tSU:STO
Stop Condition Set Up Time
600
ns
tDHDL
tBUF
Time between Stop Condition and Next Start
Condition
1300
ns
tW
tWR
Write Time
900
5
1. Sampled only, not 100% tested.
2. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the
falling or rising edge of SDA.
3. For a reSTART condition, or following a Write cycle.
22/31
ns
ms
M24512-W, M24512-R, M24256-BW, M24256-BR
Table 14.
DC and AC parameters
AC characteristics (M24xxx-R, see Table 8 and Table 9)
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCL
Clock Frequency
400
kHz
tCHCL
tHIGH
Clock Pulse Width High
600
ns
tCLCH
tLOW
Clock Pulse Width Low
1300
ns
tDL1DL2 (1)
tF
tDXCX
tSU:DAT
tCLDX
tHD:DAT Data In Hold Time
SDA Fall Time
20
300
ns
Data In Set Up Time
100
ns
0
ns
ns
tCLQX
tDH
Data Out Hold Time
200
tCLQV(2)
tAA
Clock Low to Next Data Valid (Access Time)
200
tCHDX(3)
tSU:STA
Start Condition Set Up Time
600
ns
900
ns
tDLCL
tHD:STA Start Condition Hold Time
600
ns
tCHDH
tSU:STO Stop Condition Set Up Time
600
ns
1300
ns
tDHDL
tBUF
Time between Stop Condition and Next Start
Condition
tW
tWR
Write Time
10
ms
1. Sampled only, not 100% tested.
2. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the
falling or rising edge of SDA.
3. For a reSTART condition, or following a Write cycle.
23/31
DC and AC parameters
M24512-W, M24512-R, M24256-BW, M24256-BR
Figure 11. AC Waveforms
tCHCL
tCLCH
SCL
tDLCL
SDA In
tCHDX
tCLDX
START
Condition
SDA
Input
SDA tDXCX
Change
tCHDH tDHDL
START
STOP
Condition Condition
SCL
SDA In
tCHDH
tW
STOP
Condition
Write Cycle
tCHDX
START
Condition
SCL
tCLQV
SDA Out
tCLQX
Data Valid
AI00795C
24/31
M24512-W, M24512-R, M24256-BW, M24256-BR
7
Package mechanical
Package mechanical
Figure 12. SO8W – 8 lead Plastic Small Outline, 208 mils body width, package
outline
A2
A
C
B
CP
e
D
N
E
H
1
A1
α
L
SO-b
1. Drawing is not to scale.
Table 15.
SO8W – 8 lead Plastic Small Outline, 208 mils body width, package
mechanical data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
2.03
A1
0.10
A2
0.080
0.25
0.004
1.78
B
0.35
0.45
–
–
D
5.15
E
Max
0.010
0.070
0.014
0.018
–
–
5.35
0.203
0.211
5.20
5.40
0.205
0.213
–
–
–
–
H
7.70
8.10
0.303
0.319
L
0.50
0.80
0.020
0.031
α
0°
10°
0°
10°
N
8
C
e
CP
0.20
1.27
0.008
0.050
8
0.10
0.004
25/31
Package mechanical
M24512-W, M24512-R, M24256-BW, M24256-BR
Figure 13. SO8N – 8 lead Plastic Small Outline, 150 mils body width, Package
Outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
GAUGE PLANE
D
k
8
E1
E
1
L
A1
L1
SO-A
1. Drawing is not to scale.
2.
Table 16.
SO8N – 8 lead Plastic Small Outline, 150 mils body width, package
mechanical data
millimeters
inches
Symbol
Typ
Min
A
Typ
Min
1.75
Max
0.069
A1
0.10
A2
1.25
b
0.28
0.48
0.011
0.019
c
0.17
0.23
0.007
0.009
ccc
0.25
0.004
0.010
0.049
0.10
0.004
D
4.90
4.80
5.00
0.193
0.189
0.197
E
6.00
5.80
6.20
0.236
0.228
0.244
E1
3.90
3.80
4.00
0.154
0.150
0.157
e
1.27
–
–
0.050
–
–
h
0.25
0.50
0.010
0.020
k
0°
8°
0°
8°
L
0.40
1.27
0.016
0.050
L1
26/31
Max
1.04
0.041
M24512-W, M24512-R, M24256-BW, M24256-BR
Package mechanical
Figure 14. TSSOP8 – 8 lead Thin Shrink Small Outline, package outline
D
8
5
c
E1
1
E
4
α
A1
A
L
A2
L1
CP
b
e
TSSOP8AM
1. Drawing is not to scale.
Table 17.
TSSOP8 – 8 lead Thin Shrink Small Outline, package mechanical data
millimeters
inches
Symbol
Typ
Min
A
Max
Min
1.200
A1
0.050
0.150
0.800
1.050
b
0.190
c
0.090
A2
Typ
1.000
CP
Max
0.0472
0.0020
0.0059
0.0315
0.0413
0.300
0.0075
0.0118
0.200
0.0035
0.0079
0.0394
0.100
0.0039
D
3.000
2.900
3.100
0.1181
0.1142
0.1220
e
0.650
–
–
0.0256
–
–
E
6.400
6.200
6.600
0.2520
0.2441
0.2598
E1
4.400
4.300
4.500
0.1732
0.1693
0.1772
L
0.600
0.450
0.750
0.0236
0.0177
0.0295
L1
1.000
0°
8°
0.0394
α
0°
N
8
8°
8
27/31
Part numbering
8
M24512-W, M24512-R, M24256-BW, M24256-BR
Part numbering
Table 18.
Ordering information scheme
Example:
M24512–
W MW 6
T
P
Device Type
M24 = I2C serial access EEPROM
Device Function
512– = 512 Kbit (64 Kb × 8)
256–B = 256 Kbit (32 Kb × 8)
Operating Voltage
W = VCC = 2.5 to 5.5V
R = VCC = 1.8 to 5.5V
Package
MW = SO8 (208 mils width)
MN = SO8 (150 mils body width)
DW = TSSOP8
Device Grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
P or G = ECOPACK® (RoHS compliant)
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST Sales Office.
The category of Second-Level Interconnect is marked on the package and on the inner box
label, in compliance with JEDEC Standard JESD97. The maximum ratings related to
soldering conditions are also marked on the inner box label.
28/31
M24512-W, M24512-R, M24256-BW, M24256-BR
9
Revision history
Revision history
Table 19.
Date
Document revision history
Revision
Changes
29-Jan-2001
1.1
Lead Soldering Temperature in the Absolute Maximum Ratings table
amended
Write Cycle Polling Flow Chart using ACK illustration updated
LGA8 and SO8(wide) packages added
References to PSDIP8 changed to PDIP8, and Package Mechanical data
updated
10-Apr-2001
1.2
LGA8 Package Mechanical data and illustration updated
SO16 package removed
16-Jul-2001
1.3
LGA8 Package given the designator “LA”
02-Oct-2001
1.4
LGA8 Package mechanical data updated
13-Dec-2001
1.5
Document becomes Preliminary Data
Test conditions for ILI, ILO, ZL and ZH made more precise
VIL and VIH values unified. tNS value changed
12-Jun-2001
1.6
Document promoted to Full Datasheet
22-Oct-2003
2.0
Table of contents, and Pb-free options added. Minor wording changes in
Summary Description, Power-On Reset, Memory Addressing, Write
Operations, Read Operations. VIL(min) improved to –0.45V.
3.0
LGA8 package is Not for New Design. 5V and -S supply ranges, and
Device Grade 5 removed. Absolute Maximum Ratings for VIO(min) and
VCC(min) changed. Soldering temperature information clarified for RoHS
compliant devices. Device grade information clarified. AEC-Q100-002
compliance. VIL specification unified for SDA, SCL and WC
4.0
Initial delivery state is FFh (not necessarily the same as Erased).
LGA package removed, TSSOP8 and SO8N packages added (see
Package mechanical section and <Blue>Table 18., Ordering information
scheme).
Voltage range R (1.8V to 5.5V) also offered. Minor wording changes.
ZL Test Conditions modified in <Blue>Table 10., Input parameters and
Note 3. added.
ICC and ICC1 values for VCC = 5.5V added to <Blue>Table 11., DC
characteristics (M24xxx-W).
Note added to <Blue>Table 11., DC characteristics (M24xxx-W).
Power On Reset paragraph specified.
tW max value modified in <Blue>Table 13., AC characteristics (M24xxxW, see Table 7 and Table 9) and note 4 added. Plating technology
changed in <Blue>Table 18., Ordering information scheme.
Resistance and capacitance renamed in <Blue>Figure 4., Maximum RP
Value versus Bus Parasitic Capacitance (C) for an I2C Bus.
02-Sep-2004
22-Feb-2005
29/31
Revision history
Table 19.
M24512-W, M24512-R, M24256-BW, M24256-BR
Document revision history (continued)
Date
05-May-2006
16-Oct-2006
30/31
Revision
Changes
5
Power On Reset paragraph replaced by Section 2.5: Supply voltage
(VCC). Figure 3: Device Select Code added.
ECC (Error Correction Code) and Write cycling added and specified at 1
Million cycles.
ICC0 added and ICC1 specified over the whole voltage range in Table 11
and Table 12.
PDIP8 package removed. Packages are ECOPACK® compliant. Small
text changes.
6
M24256-BW and M24256-BR part numbers added.
Section 3.9: ECC (Error Correction Code) and Write cycling updated.
ICC and ICC1 modified in Table 12: DC characteristics (M24xxx-R).
tW modified in Table 13: AC characteristics (M24xxx-W, see Table 7 and
Table 9).
SO8Narrow package specifications updated (see Table 16 and
Figure 13). Blank option removed from below Plating Technology in
Table 18: Ordering information scheme.
M24512-W, M24512-R, M24256-BW, M24256-BR
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