STMicroelectronics M24C08-WMB3TG 16kbit, 8kbit, 4kbit, 2kbit and 1kbit serial i2c bus eeprom Datasheet

M24C16, M24C08
M24C04, M24C02, M24C01
16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I²C Bus EEPROM
FEATURES SUMMARY
■
■
■
■
■
■
■
■
■
■
Two Wire I2C Serial Interface
Supports 400kHz Protocol
Single Supply Voltage:
– 4.5 to 5.5V for M24Cxx
– 2.5 to 5.5V for M24Cxx-W
– 1.8 to 5.5V for M24Cxx-R
Write Control Input
BYTE and PAGE WRITE (up to 16 Bytes)
RANDOM and SEQUENTIAL READ Modes
Self-Timed Programming Cycle
Automatic Address Incrementing
Enhanced ESD/Latch-Up Behavior
More than 1 Million Erase/Write Cycles
More than 40 Year Data Retention
Figure 1. Packages
8
1
PDIP8 (BN)
8
1
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
TSSOP8 (DS)
3x3mm² body size (MSOP)
UFDFPN8 (MB)
2x3mm² (MLP)
March 2004
1/29
M24C16, M24C08, M24C04, M24C02, M24C01
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Power On Reset: VCC Lock-Out Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. DIP, SO, TSSOP and MLP Connections (Top View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus . . . . . . . . . .
Figure 5. I2C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2. Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.....5
.....5
.....5
.....5
.....5
.....6
.....6
DEVICE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Write Mode Sequences with WC=1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Write Mode Sequences with WC=0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. Write Cycle Polling Flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Minimizing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Read Mode Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Acknowledge in Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2/29
M24C16, M24C08, M24C04, M24C02, M24C01
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Operating Conditions (M24Cxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6. Operating Conditions (M24Cxx-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7. Operating Conditions (M24Cxx-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 9. Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 10. DC Characteristics (M24Cxx, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 11. DC Characteristics (M24Cxx, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 12. DC Characteristics (M24Cxx-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 13. DC Characteristics (M24Cxx-W, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 14. DC Characteristics (M24Cxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 15. AC Characteristics (M24Cxx, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 16. AC Characteristics (M24Cxx, Device Grade 3; M24Cxx-W, Device Grade 6 or 3) . . . . . 18
Table 17. AC Characteristics (M24Cxx-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 11.AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 21
Table 18. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 21
Figure 13.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 22
Table 19. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
22
Figure 14.UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Outline
23
Table 20. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Data .
23
Figure 15.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 24
Table 21. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 24
Figure 16.TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline
25
Table 22. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Mechanical Data
25
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 23. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 24. How to Identify Current and New Products by the Process Identification Letter . . . . . . . 27
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 25. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3/29
M24C16, M24C08, M24C04, M24C02, M24C01
SUMMARY DESCRIPTION
These I 2C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 2048/1024/512/256/128 x 8 (M24C16,
M24C08, M24C04, M24C02, M24C01).
When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Figure 2. Logic Diagram
VCC
Table 1. Signal Names
E0, E1, E2
Chip Enable
SDA
Serial Data
SCL
Serial Clock
WC
Write Control
VCC
Supply Voltage
VSS
Ground
3
E0-E2
SCL
SDA
M24Cxx
WC
Power On Reset: VCC Lock-Out Write Protect
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. At Power-up, the
internal reset is held active until VCC has reached
the POR threshold value, and all operations are
disabled – the device will not respond to any command. In the same way, when VCC drops from the
operating voltage, below the POR threshold value,
all operations are disabled and the device will not
respond to any command.
A stable and valid VCC (as defined in Table 6. and
Table 7.) must be applied before applying any logic signal.
VSS
AI02033
I2C uses a two wire serial interface, comprising a
bi-directional data line and a clock line. The devices carry a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I 2C bus definition.
The device behaves as a slave in the I2C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a Device
Select Code and RW bit (as described in Table 2.),
terminated by an acknowledge bit.
Figure 3. DIP, SO, TSSOP and MLP Connections (Top View)
M24Cxx
16Kb /8Kb /4Kb /2Kb /1Kb
NC / NC / NC / E0 / E0
NC / NC / E1 / E1 / E1
NC / E2 / E2 / E2 / E2
VSS
1
2
3
4
8
7
6
5
VCC
WC
SCL
SDA
AI02034E
Note: 1. NC = Not Connected
2. See PACKAGE MECHANICAL section for package dimensions, and how to identify pin-1.
4/29
M24C16, M24C08, M24C04, M24C02, M24C01
SIGNAL DESCRIPTION
Serial Clock (SCL). This input signal is used to
strobe all data in and out of the device. In applications where this signal is used by slave devices to
synchronize the bus to a slower clock, the bus
master must have an open drain output, and a
pull-up resistor can be connected from Serial
Clock (SCL) to V CC. (Figure 4. indicates how the
value of the pull-up resistor can be calculated). In
most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the bus master
has a push-pull (rather than open drain) output.
Serial Data (SDA). This bi-directional signal is
used to transfer data in or out of the device. It is an
open drain output that may be wire-OR’ed with
other open drain or open collector signals on the
bus. A pull up resistor must be connected from Se-
rial Data (SDA) to VCC. (Figure 4. indicates how
the value of the pull-up resistor can be calculated).
Chip Enable (E0, E1, E2). These input signals
are used to set the value that is to be looked for on
the three least significant bits (b3, b2, b1) of the 7bit Device Select Code. These inputs must be tied
to V CC or VSS, to establish the Device Select
Code.
Write Control (WC). This input signal is useful
for protecting the entire contents of the memory
from inadvertent write operations. Write operations are disabled to the entire memory array when
Write Control (WC) is driven High. When unconnected, the signal is internally read as VIL, and
Write operations are allowed.
When Write Control (WC) is driven High, Device
Select and Address bytes are acknowledged,
Data bytes are not acknowledged.
Figure 4. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus
VCC
Maximum RP value (kΩ)
20
16
RL
12
RL
SDA
MASTER
8
fc = 100kHz
4
fc = 400kHz
CBUS
SCL
CBUS
0
10
100
1000
CBUS (pF)
AI01665
5/29
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 5. I2C Bus Protocol
SCL
SDA
SDA
Input
START
Condition
SCL
1
SDA
MSB
2
SDA
Change
STOP
Condition
3
7
8
9
ACK
START
Condition
SCL
1
SDA
MSB
2
3
7
8
9
ACK
STOP
Condition
AI00792B
Table 2. Device Select Code
Device Type Identifier1
Chip Enable2,3
RW
b7
b6
b5
b4
b3
b2
b1
b0
M24C01 Select Code
1
0
1
0
E2
E1
E0
RW
M24C02 Select Code
1
0
1
0
E2
E1
E0
RW
M24C04 Select Code
1
0
1
0
E2
E1
A8
RW
M24C08 Select Code
1
0
1
0
E2
A9
A8
RW
M24C16 Select Code
1
0
1
0
A10
A9
A8
RW
Note: 1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
3. A10, A9 and A8 represent most significant bits of the address.
6/29
M24C16, M24C08, M24C04, M24C02, M24C01
DEVICE OPERATION
The device supports the I2C protocol. This is summarized in Figure 5.. Any device that sends data
on to the bus is defined to be a transmitter, and
any device that reads the data to be a receiver.
The device that controls the data transfer is known
as the bus master, and the other as the slave device. A data transfer can only be initiated by the
bus master, which will also provide the serial clock
for synchronization. The M24Cxx device is always
a slave in all communication.
Start Condition
Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The device continuously
monitors (except during a Write cycle) Serial Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is given.
Stop Condition
Stop is identified by a rising edge of Serial Data
(SDA) while Serial Clock (SCL) is stable and driven High. A Stop condition terminates communication between the device and the bus master. A
Read command that is followed by NoAck can be
followed by a Stop condition to force the device
into the Stand-by mode. A Stop condition at the
end of a Write command triggers the internal EEPROM Write cycle.
Acknowledge Bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be
bus master or slave device, releases Serial Data
(SDA) after sending eight bits of data. During the
9th clock pulse period, the receiver pulls Serial
Data (SDA) Low to acknowledge the receipt of the
eight data bits.
Data Input
During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change only when Serial Clock (SCL) is driven Low.
Memory Addressing
To start communication between the bus master
and the slave device, the bus master must initiate
a Start condition. Following this, the bus master
sends the Device Select Code, shown in Table 2.
(on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device
Type Identifier, and a 3-bit Chip Enable “Address”
(E2, E1, E0). To address the memory array, the 4bit Device Type Identifier is 1010b.
Each device is given a unique 3-bit code on the
Chip Enable (E0, E1, E2) inputs. When the Device
Select Code is received, the device only responds
if the Chip Enable Address is the same as the value on the Chip Enable (E0, E1, E2) inputs. However, those devices with larger memory capacities
(the M24C16, M24C08 and M24C04) need more
address bits. E0 is not available for use on devices
that need to use address line A8; E1 is not available for devices that need to use address line A9,
and E2 is not available for devices that need to use
address line A10 (see Figure 3. and Table 2. for
details). Using the E0, E1 and E2 inputs, up to
eight M24C02 (or M24C01), four M24C04, two
M24C08 or one M24C16 devices can be connected to one I2C bus. In each case, and in the hybrid
cases, this gives a total memory capacity of
16 Kbits, 2 KBytes (except where M24C01 devices are used).
The 8th bit is the Read/Write bit (RW). This bit is
set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code, the
corresponding device gives an acknowledgment
on Serial Data (SDA) during the 9th bit time. If the
device does not match the Device Select code, it
deselects itself from the bus, and goes into Standby mode.
Table 3. Operating Modes
Mode
Current Address Read
RW bit
WC 1
Bytes
1
X
1
0
X
Random Address Read
Initial Sequence
START, Device Select, RW = 1
START, Device Select, RW = 0, Address
1
1
X
reSTART, Device Select, RW = 1
Sequential Read
1
X
≥1
Byte Write
0
VIL
1
START, Device Select, RW = 0
Page Write
0
VIL
≤ 16
START, Device Select, RW = 0
Similar to Current or Random Address Read
Note: 1. X = VIH or VIL.
7/29
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 6. Write Mode Sequences with WC=1 (data write inhibited)
WC
ACK
BYTE ADDR
NO ACK
DATA IN
STOP
DEV SEL
START
Byte Write
ACK
R/W
WC
ACK
DEV SEL
START
Page Write
ACK
BYTE ADDR
NO ACK
DATA IN 1
NO ACK
DATA IN 2
DATA IN 3
R/W
WC (cont'd)
NO ACK
DATA IN N
STOP
Page Write
(cont'd)
NO ACK
AI02803C
Write Operations
Following a Start condition the bus master sends
a Device Select Code with the RW bit reset to 0.
The device acknowledges this, as shown in Figure
7., and waits for an address byte. The device responds to the address byte with an acknowledge
bit, and then waits for the data byte.
When the bus master generates a Stop condition
immediately after the Ack bit (in the “10 th bit” time
slot), either at the end of a Byte Write or a Page
Write, the internal memory Write cycle is triggered.
A Stop condition at any other time slot does not
trigger the internal Write cycle.
During the internal Write cycle, Serial Data (SDA)
and Serial Clock (SCL) are ignored, and the device does not respond to any requests.
Byte Write
After the Device Select code and the address byte,
the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven High (during the period from
8/29
the Start condition until the end of the address
byte), the device replies to the data byte with
NoAck, as shown in Figure 6., and the location is
not modified. If, instead, the addressed location is
not Write-protected, the device replies with Ack.
The bus master terminates the transfer by generating a Stop condition, as shown in Figure 7..
Page Write
The Page Write mode allows up to 16 bytes to be
written in a single Write cycle, provided that they
are all located in the same page in the memory:
that is, the most significant memory address bits
are the same. If more bytes are sent than will fit up
to the end of the page, a condition known as ‘rollover’ occurs. This should be avoided, as data
starts to become overwritten in an implementation
dependent way.
The bus master sends from 1 to 16 bytes of data,
each of which is acknowledged by the device if
Write Control (WC) is Low. If the addressed location is Write-protected, by Write Control (WC) being driven High (during the period from the Start
M24C16, M24C08, M24C04, M24C02, M24C01
condition until the end of the address byte), the device replies to the data bytes with NoAck, as
shown in Figure 6., and the locations are not modified. After each byte is transferred, the internal
byte address counter (the 4 least significant address bits only) is incremented. The transfer is terminated by the bus master generating a Stop
condition.
Figure 7. Write Mode Sequences with WC=0 (data write enabled)
WC
ACK
BYTE ADDR
ACK
DATA IN
STOP
DEV SEL
START
BYTE WRITE
ACK
R/W
WC
ACK
DEV SEL
START
PAGE WRITE
ACK
BYTE ADDR
ACK
DATA IN 1
ACK
DATA IN 2
DATA IN 3
R/W
WC (cont'd)
ACK
DATA IN N
STOP
PAGE WRITE
(cont'd)
ACK
AI02804B
9/29
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 8. Write Cycle Polling Flowchart using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
NO
ACK
Returned
YES
First byte of instruction
with RW = 0 already
decoded by the device
NO
Next
Operation is
Addressing the
Memory
YES
Send Address
and Receive ACK
ReSTART
NO
STOP
YES
DATA for the
WRITE Operation
DEVICE SELECT
with RW = 1
Continue the
WRITE Operation
Continue the
Random READ Operation
Minimizing System Delays by Polling On ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the
data from its internal latches to the memory cells.
The maximum Write time (tw) is shown in Table
15. to Table 17., but the typical time is shorter. To
make use of this, a polling sequence can be used
by the bus master.
The sequence, as shown in Figure 8., is:
10/29
START
Condition
–
–
–
AI01847C
Initial condition: a Write cycle is in progress.
Step 1: the bus master issues a Start condition
followed by a Device Select Code (the first
byte of the new instruction).
Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the
bus master goes back to Step 1. If the device
has terminated the internal Write cycle, it
responds with an Ack, indicating that the
device is ready to receive the second part of
the instruction (the first byte of this instruction
having been sent during Step 1).
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 9. Read Mode Sequences
ACK
DATA OUT
STOP
START
DEV SEL
NO ACK
R/W
ACK
START
DEV SEL *
ACK
BYTE ADDR
R/W
ACK
START
DEV SEL
DATA OUT
R/W
ACK
ACK
NO ACK
DATA OUT N
DATA OUT 1
R/W
ACK
START
DEV SEL *
ACK
BYTE ADDR
R/W
ACK
ACK
DEV SEL *
START
SEQUENTIAL
RANDOM
READ
DEV SEL *
NO ACK
STOP
SEQUENTIAL
CURRENT
READ
ACK
START
RANDOM
ADDRESS
READ
STOP
CURRENT
ADDRESS
READ
ACK
DATA OUT 1
R/W
NO ACK
STOP
DATA OUT N
AI01942
Note: The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 3rd bytes) must be identical.
Read Operations
Read operations are performed independently of
the state of the Write Control (WC) signal.
The device has an internal address counter which
is incremented each time a byte is read.
Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in Figure 9.) but without sending a Stop condition. Then,
the bus master sends another Start condition, and
repeats the Device Select Code, with the RW bit
set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus
master must not acknowledge the byte, and terminates the transfer with a Stop condition.
Current Address Read
For the Current Address Read operation, following
a Start condition, the bus master only sends a Device Select Code with the RW bit set to 1. The device acknowledges this, and outputs the byte
addressed by the internal address counter. The
counter is then incremented. The bus master terminates the transfer with a Stop condition, as
shown in Figure 9., without acknowledging the
byte.
11/29
M24C16, M24C08, M24C04, M24C02, M24C01
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The bus
master does acknowledge the data byte output,
and sends additional clock pulses so that the device continues to output the next byte in sequence.
To terminate the stream of bytes, the bus master
must not acknowledge the last byte, and must
generate a Stop condition, as shown in Figure 9..
The output data comes from consecutive addresses, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’,
and the device continues to output data from
memory address 00h.
12/29
Acknowledge in Read Mode
For all Read commands, the device waits, after
each byte read, for an acknowledgment during the
9th bit time. If the bus master does not drive Serial
Data (SDA) Low during this time, the device terminates the data transfer and switches to its Standby mode.
INITIAL DELIVERY STATE
The device is delivered with the memory array
erased: all bits are set to 1 (each byte contains
FFh).
M24C16, M24C08, M24C04, M24C02, M24C01
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 4. Absolute Maximum Ratings
Symbol
Parameter
TSTG
Storage Temperature
TLEAD
Lead Temperature during Soldering
Min.
Max.
Unit
–65
150
°C
See note 1
°C
VIO
Input or Output range
–0.50
6.5
V
VCC
Supply Voltage
–0.50
6.5
V
VESD
Electrostatic Discharge Voltage (Human Body model) 2
–4000
4000
V
Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ® 7191395 specification, and
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
13/29
M24C16, M24C08, M24C04, M24C02, M24C01
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC
and AC Characteristic tables that follow are derived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parameters.
Table 5. Operating Conditions (M24Cxx)
Symbol
VCC
Parameter
Min.
Max.
Unit
Supply Voltage
4.5
5.5
V
Ambient Operating Temperature (Device Grade 6)
–40
85
°C
Ambient Operating Temperature (Device Grade 3)
–40
125
°C
Min.
Max.
Unit
Supply Voltage
2.5
5.5
V
Ambient Operating Temperature (Device Grade 6)
–40
85
°C
Ambient Operating Temperature (Device Grade 3)
–40
125
°C
Min.
Max.
Unit
Supply Voltage
1.8
5.5
V
Ambient Operating Temperature
–40
85
°C
TA
Note: 1. This range is Not for New Design, and will soon be replaced by the M24Cxx-W range.
Table 6. Operating Conditions (M24Cxx-W)
Symbol
VCC
Parameter
TA
Table 7. Operating Conditions (M24Cxx-R)
Symbol
VCC
TA
14/29
Parameter
M24C16, M24C08, M24C04, M24C02, M24C01
Table 8. AC Measurement Conditions
Symbol
CL
Parameter
Min.
Load Capacitance
Max.
Unit
100
Input Rise and Fall Times
pF
50
ns
Input Levels
0.2VCC to 0.8VCC
V
Input and Output Timing Reference Levels
0.3VCC to 0.7VCC
V
Figure 10. AC Measurement I/O Waveform
Input Levels
Input and Output
Timing Reference Levels
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI00825B
Table 9. Input Parameters
Symbol
Parameter1,2
Test Condition
Min.
Max.
Unit
CIN
Input Capacitance (SDA)
8
pF
CIN
Input Capacitance (other pins)
6
pF
70
kΩ
ZWCL
WC Input Impedance
VIN < 0.5 V
5
ZWCH
WC Input Impedance
VIN > 0.7VCC
500
Pulse width ignored
(Input Filter on SCL and SDA)
Single glitch
tNS
kΩ
100
ns
Note: 1. TA = 25°C, f = 400kHz
2. Sampled only, not 100% tested.
Table 10. DC Characteristics (M24Cxx, Device Grade 6)
Symbol
Parameter
Test Condition
(in addition to those in Table 5.)
Min.
Max.
Unit
VIN = VSS or VCC
±2
µA
VOUT = VSS or VCC, SDA in Hi-Z
±2
µA
VCC=5V, fc=400kHz (rise/fall time < 30ns)
2
mA
VIN = VSS or VCC , VCC = 5 V
1
µA
ILI
Input Leakage Current
(SCL, SDA)
ILO
Output Leakage Current
ICC
Supply Current
ICC1
Stand-by Supply Current
–0.45
0.3VCC
V
VIL
Input Low Voltage
(E2, E1, E0, SCL, SDA)
Input Low Voltage (WC)
–0.45
0.5
V
VIH
Input High Voltage
(E2, E1, E0, SCL, SDA, WC)
0.7VCC
VCC+1
V
VOL
Output Low Voltage
0.4
V
IOL = 3 mA, VCC = 5 V
Note: 1. This range is Not for New Design, and will soon be replaced by the M24Cxx-Wxx6 range.
15/29
M24C16, M24C08, M24C04, M24C02, M24C01
Table 11. DC Characteristics (M24Cxx, Device Grade 3)
Symbol
Parameter
Test Condition
(in addition to those in Table 5.)
Min.
Max.
Unit
VIN = VSS or VCC
±2
µA
VOUT = VSS or VCC, SDA in Hi-Z
±2
µA
VCC=5V, fc=400kHz (rise/fall time < 30ns)
3
mA
VIN = VSS or VCC , VCC = 5 V
5
µA
ILI
Input Leakage Current
(SCL, SDA)
ILO
Output Leakage Current
ICC
Supply Current
ICC1
Stand-by Supply Current
Input Low Voltage
(E2, E1, E0, SCL, SDA)
–0.45
0.3VCC
V
VIL
Input Low Voltage (WC)
–0.45
0.5
V
VIH
Input High Voltage
(E2, E1, E0, SCL, SDA, WC)
0.7VCC
VCC+1
V
VOL
Output Low Voltage
0.4
V
Max.
Unit
VIN = VSS or VCC
±2
µA
VOUT = VSS or VCC, SDA in Hi-Z
±2
µA
VCC =2.5V, fc=400kHz (rise/fall time < 30ns)
1
mA
VIN = VSS or VCC , VCC = 2.5 V
0.5
µA
IOL = 3 mA, VCC = 5 V
Note: 1. This range is Not for New Design, and will soon be replaced by the M24Cxx-Wxx3 range.
Table 12. DC Characteristics (M24Cxx-W, Device Grade 6)
Symbol
Parameter
Test Condition
(in addition to those in Table 6.)
Min.
ILI
Input Leakage Current
(SCL, SDA)
ILO
Output Leakage Current
ICC
Supply Current
ICC1
Stand-by Supply Current
Input Low Voltage
(E2, E1, E0, SCL, SDA)
–0.45
0.3VCC
V
VIL
Input Low Voltage (WC)
–0.45
0.5
V
VIH
Input High Voltage
(E2, E1, E0, SCL, SDA, WC)
0.7VCC
VCC+1
V
VOL
Output Low Voltage
0.4
V
16/29
IOL = 2.1 mA, VCC = 2.5 V
M24C16, M24C08, M24C04, M24C02, M24C01
Table 13. DC Characteristics (M24Cxx-W, Device Grade 3)
Symbol
Test Condition
(in addition to those in Table 6.)
Max.1
Unit
VIN = VSS or VCC
±2
µA
VOUT = VSS or VCC, SDA in Hi-Z
±2
µA
VCC =2.5V, fc=400kHz (rise/fall time < 30ns)
3
mA
VIN = VSS or VCC , VCC = 2.5 V
2
µA
Parameter
Min.1
ILI
Input Leakage Current
(SCL, SDA)
ILO
Output Leakage Current
ICC
Supply Current
ICC1
Stand-by Supply Current
Input Low Voltage
(E2, E1, E0, SCL, SDA)
–0.45
0.3VCC
V
VIL
Input Low Voltage (WC)
–0.45
0.5
V
VIH
Input High Voltage
(E2, E1, E0, SCL, SDA, WC)
0.7VCC
VCC+1
V
VOL
Output Low Voltage
0.4
V
Max.
Unit
VIN = VSS or VCC
±2
µA
VOUT = VSS or VCC, SDA in Hi-Z
±2
µA
VCC =1.8V, fc=400kHz (rise/fall time < 30ns)
0.8
mA
VIN = VSS or VCC , VCC = 1.8 V
0.3
µA
IOL = 2.1 mA, VCC = 2.5 V
Note: 1. This is preliminary data.
Table 14. DC Characteristics (M24Cxx-R)
Symbol
Parameter
ILI
Input Leakage Current
(SCL, SDA)
ILO
Output Leakage Current
ICC
Supply Current
ICC1
Stand-by Supply Current
VIL
Input Low Voltage
(E2, E1, E0, SCL, SDA)
Test Condition
(in addition to those in Table 7.)
Min.
2.5 V ≤ VCC
–0.45
0.3 VCC
V
1.8 V ≤ VCC < 2.5 V
–0.45
0.25 VCC
V
Input Low Voltage (WC)
–0.45
0.5
V
VIH
Input High Voltage
(E2, E1, E0, SCL, SDA, WC)
0.7VCC
VCC+1
V
VOL
Output Low Voltage
0.2
V
IOL = 0.7 mA, VCC = 1.8 V
17/29
M24C16, M24C08, M24C04, M24C02, M24C01
Table 15. AC Characteristics (M24Cxx, Device Grade 6)
Test conditions specified in Table 8. and Table 5.
Parameter
Min.4
Max.4
Unit
400
kHz
Symbol
Alt.
fC
fSCL
Clock Frequency
tCHCL
tHIGH
Clock Pulse Width High
600
ns
tCLCH
tLOW
Clock Pulse Width Low
1300
ns
tDL1DL2 2
tF
tDXCX
tSU:DAT
Data In Set Up Time
tCLDX
tHD:DAT
Data In Hold Time
tCLQX
tDH
tCLQV 3
tAA
tCHDX 1
SDA Fall Time
20
300
ns
100
ns
0
ns
Data Out Hold Time
200
ns
Clock Low to Next Data Valid (Access Time)
200
tSU:STA
Start Condition Set Up Time
600
ns
tDLCL
tHD:STA
Start Condition Hold Time
600
ns
tCHDH
tSU:STO
Stop Condition Set Up Time
600
ns
tDHDL
tBUF
Time between Stop Condition and Next Start Condition
1300
ns
tW
tWR
Write Time
Note: 1.
2.
3.
4.
900
5
ns
ms
For a reSTART condition, or following a Write cycle.
Sampled only, not 100% tested.
To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
This is preliminary data for M24Cxx-Wxx3.
Table 16. AC Characteristics (M24Cxx, Device Grade 3; M24Cxx-W, Device Grade 6 or 3)
Test conditions specified in Table 8. and Table 5. or Table 6.
Symbol
Alt.
Parameter
fC
fSCL
Clock Frequency
tCHCL
tHIGH
Clock Pulse Width High
600
ns
tCLCH
tLOW
Clock Pulse Width Low
1300
ns
tDL1DL2 2
tF
tDXCX
tSU:DAT
Data In Set Up Time
tCLDX
tHD:DAT
Data In Hold Time
tCLQX
tDH
tCLQV 3
tAA
tCHDX 1
SDA Fall Time
Min.
20
Max.
Unit
400
kHz
300
ns
100
ns
0
ns
Data Out Hold Time
200
ns
Clock Low to Next Data Valid (Access Time)
200
tSU:STA
Start Condition Set Up Time
600
ns
tDLCL
tHD:STA
Start Condition Hold Time
600
ns
tCHDH
tSU:STO
Stop Condition Set Up Time
600
ns
tDHDL
tBUF
Time between Stop Condition and Next Start Condition
1300
ns
tW
tWR
Write Time
Note: 1.
2.
3.
4.
18/29
900
10 or4 5
ns
ms
For a reSTART condition, or following a Write cycle.
Sampled only, not 100% tested.
To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
10ms write time is offered on the standard device. 5ms write time is offered on new products bearing the Process Identification letter
“W” or “G” on the package, as described in Table 24..
M24C16, M24C08, M24C04, M24C02, M24C01
Table 17. AC Characteristics (M24Cxx-R)
Test conditions specified in Table 8. and Table 7.
Parameter
Min.
Max.
Min.4
Max.4
Unit
400
kHz
Symbol
Alt.
fC
fSCL
Clock Frequency
tCHCL
tHIGH
Clock Pulse Width High
4000
600
ns
tCLCH
tLOW
Clock Pulse Width Low
4700
1300
ns
tDL1DL2 2
tF
tDXCX
100
SDA Fall Time
20
tSU:DAT
Data In Set Up Time
250
100
ns
tCLDX
tHD:DAT
Data In Hold Time
0
0
ns
tCLQX
tDH
Data Out Hold Time
200
200
ns
tCLQV 3
tAA
Clock Low to Next Data Valid (Access
Time)
200
tCHDX 1
tSU:STA
Start Condition Set Up Time
4700
600
ns
tDLCL
tHD:STA
Start Condition Hold Time
4000
600
ns
tCHDH
tSU:STO
Stop Condition Set Up Time
4000
600
ns
tDHDL
tBUF
Time between Stop Condition and
Next Start Condition
4700
1300
ns
tW
tWR
Write Time
Note: 1.
2.
3.
4.
300
3500
10
20
200
300
900
10
ns
ns
ms
For a reSTART condition, or following a Write cycle.
Sampled only, not 100% tested.
To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
100kHz clock frequency is offered on the standard device. 400kHz clock frequency is offered on new products bearing the Process
Identification letter “W” or “G” on the package, as described in Table 24..
19/29
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 11. AC Waveforms
tCHCL
tCLCH
SCL
tDLCL
SDA In
tCHDX
tCLDX
START
Condition
SDA
Input
SDA tDXCX
Change
tCHDH tDHDL
START
STOP
Condition Condition
SCL
SDA In
tCHDH
tW
STOP
Condition
Write Cycle
tCHDX
START
Condition
SCL
tCLQV
SDA Out
tCLQX
Data Valid
AI00795C
20/29
M24C16, M24C08, M24C04, M24C02, M24C01
PACKAGE MECHANICAL
Figure 12. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline
E
b2
A2
A1
b
A
L
c
e
eA
eB
D
8
E1
1
PDIP-B
Note: Drawing is not to scale.
Table 18. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
mm
inches
Symb.
Typ.
Min.
A
Max.
Typ.
Min.
5.33
A1
Max.
0.210
0.38
0.015
A2
3.30
2.92
4.95
0.130
0.115
0.195
b
0.46
0.36
0.56
0.018
0.014
0.022
b2
1.52
1.14
1.78
0.060
0.045
0.070
c
0.25
0.20
0.36
0.010
0.008
0.014
D
9.27
9.02
10.16
0.365
0.355
0.400
E
7.87
7.62
8.26
0.310
0.300
0.325
E1
6.35
6.10
7.11
0.250
0.240
0.280
e
2.54
–
–
0.100
–
–
eA
7.62
–
–
0.300
–
–
eB
L
10.92
3.30
2.92
3.81
0.430
0.130
0.115
0.150
21/29
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 13. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline
h x 45˚
A
C
B
CP
e
D
N
E
H
1
A1
α
L
SO-a
Note: Drawing is not to scale.
Table 19. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
mm
inches
Symb.
Typ.
Min.
Max.
A
1.35
A1
Min.
Max.
1.75
0.053
0.069
0.10
0.25
0.004
0.010
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
E
3.80
4.00
0.150
0.157
–
–
–
–
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.40
0.90
0.016
0.035
α
0°
8°
0°
8°
N
8
e
CP
22/29
1.27
Typ.
0.050
8
0.10
0.004
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 14. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Outline
e
D
b
L1
L3
E
E2
L
A
D2
ddd
A1
UFDFPN-01
Note: 1. Drawing is not to scale.
2. The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to VSS. It must not be allowed to be connected to
any other voltage or signal line on the PCB, for example during the soldering process.
Table 20. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Data
mm
inches
Symbol
A
Typ.
Min.
Max.
Typ.
Min.
Max.
0.55
0.50
0.60
0.022
0.020
0.024
0.00
0.05
0.000
0.002
0.20
0.30
0.008
0.012
0.061
0.065
A1
b
0.25
D
2.00
D2
0.079
1.55
ddd
E
0.010
1.65
0.05
3.00
E2
0.002
0.118
0.15
0.25
0.006
0.010
e
0.50
–
–
0.020
–
–
L
0.45
0.40
0.50
0.018
0.016
0.020
L1
0.15
L3
N
0.006
0.30
8
0.012
8
23/29
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 15. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline
D
8
5
c
E1
1
E
4
α
L
A1
A
A2
L1
CP
b
e
TSSOP8AM
Note: Drawing is not to scale.
Table 21. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data
mm
inches
Symbol
Typ.
Min.
A
0.050
0.150
0.800
1.050
b
0.190
c
0.090
A2
Typ.
Min.
1.200
A1
1.000
CP
Max.
0.0472
0.0020
0.0059
0.0315
0.0413
0.300
0.0075
0.0118
0.200
0.0035
0.0079
0.0394
0.100
0.0039
D
3.000
2.900
3.100
0.1181
0.1142
0.1220
e
0.650
–
–
0.0256
–
–
E
6.400
6.200
6.600
0.2520
0.2441
0.2598
E1
4.400
4.300
4.500
0.1732
0.1693
0.1772
L
0.600
0.450
0.750
0.0236
0.0177
0.0295
L1
1.000
0°
8°
α
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Max.
0.0394
0°
8°
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 16. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline
D
8
5
c
E1
1
E
4
α
L
A1
A
A2
L1
CP
b
e
TSSOP8BM
Note: Drawing is not to scale.
Table 22. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Mechanical Data
mm
inches
Symbol
Typ.
Min.
A
Max.
Min.
1.100
A1
0.050
0.150
0.750
0.950
b
0.250
c
A2
Typ.
0.850
Max.
0.0433
0.0020
0.0059
0.0295
0.0374
0.400
0.0098
0.0157
0.130
0.230
0.0051
0.0091
0.0335
D
3.000
2.900
3.100
0.1181
0.1142
0.1220
E
4.900
4.650
5.150
0.1929
0.1831
0.2028
E1
3.000
2.900
3.100
0.1181
0.1142
0.1220
e
0.650
–
–
0.0256
–
–
CP
0.100
L
0.550
L1
0.950
α
0.400
0.700
0.0039
0.0217
0.0157
0.0276
0°
6°
0.0374
0°
6°
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M24C16, M24C08, M24C04, M24C02, M24C01
PART NUMBERING
Table 23. Ordering Information Scheme
Example:
M24C08
–
W DW
6
T
P
/W
Device Type
M24 = I2C serial access EEPROM
Device Function
16 = 16 Kbit (2048 x 8)
08 = 8 Kbit (1024 x 8)
04 = 4 Kbit (512 x 8)
02 = 2 Kbit (256 x 8)
01 = 1 Kbit (128 x 8)
Operating Voltage
blank 4 = VCC = 4.5 to 5.5V (400kHz)
W 2 = VCC = 2.5 to 5.5V (400kHz)
R = VCC = 1.8 to 5.5V (400kHz)
Package
BN = PDIP8
MN = SO8 (150 mil width)
MB = UDFDFPN8 (MLP8)
DW = TSSOP8 (169 mil width)
DS = TSSOP8 (3x3mm² body size, MSOP8)
Device Grade
6 = Industrial: device tested with standard test flow over –40 to 85 °C
3 = Automotive: device tested with High Reliability Certified Flow1 over –40 to 125 °C
Option
T = Tape & Reel Packing
Plating Technology
blank = Standard SnPb plating
P = Lead-Free and RoHS compliant
G = Lead-Free, RoHS compliant, Sb2O3-free and TBBA-free
Process3
blank = F6SP20%
/W = F6SP36%
/G = F6SP36%
Note: 1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy.
2. 2.5 to 5.5V devices bearing the process letter “W” or “G” in the package marking (on the top side of the package, on the right side,
see Table 24.), guarantee a maximum write time of 5ms, instead of the standard 10ms. For more information about these devices,
and their device identification, please ask your ST Sales Office for Process Change Notices PCN MPG/EE/0061 and 0062
(PCEE0061 and PCEE0062).
3. Used only for Device Grade 3
4. This range is Not for New Design, and will soon be replaced by the M24Cxx-W range.
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M24C16, M24C08, M24C04, M24C02, M24C01
For a list of available options (speed, package,
etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Office.
Table 24. How to Identify Current and New Products by the Process Identification Letter
Markings on Current Products1
24CxxW6
ST xxxxL
Markings on New Products1
24CxxW6
ST xxxxW
24CxxW6
ST xxxxG
Note: 1. This example comes from the S08 package. Other packages have similar information. For further information, please ask your ST
Sales Office for Process Change Notices PCN MPG/EE/0061 and 0062 (PCEE0061 and PCEE0062).
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M24C16, M24C08, M24C04, M24C02, M24C01
REVISION HISTORY
Table 25. Document Revision History
Date
Version
10-Dec-1999
2.4
TSSOP8 Turned-Die package removed (p 2 and order information)
Lead temperature added for TSSOP8 in table 2
18-Apr-2000
2.5
Labelling change to Fig-2D, correction of values for ‘E’ and main caption for Tab-13
05-May-2000
2.6
Extra labelling to Fig-2D
23-Nov-2000
3.0
SBGA package information removed to an annex document
-R range changed to being the -S range, and the new -R range added
19-Feb-2001
3.1
SBGA package information put back in this document
Lead Soldering Temperature in the Absolute Maximum Ratings table amended
Write Cycle Polling Flow Chart using ACK illustration updated
References to PSDIP changed to PDIP and Package Mechanical data updated
Wording brought in to line with standard glossary
20-Apr-2001
3.2
Revision of DC and AC characteristics for the -S series
08-Oct-2001
3.3
Ball numbers added to the SBGA connections and package mechanical illustrations
09-Nov-2001
3.4
Specification of Test Condition for Leakage Currents in the DC Characteristics table
improved
30-Jul-2002
3.5
Document reformatted using new template. SBGA5 package removed
TSSOP8 (3x3mm² body size) package (MSOP8) added. -L voltage range added
04-Feb-2003
3.6
Document title spelt out more fully. “W”-marked devices with tw=5ms added.
05-May-2003
3.7
-R voltage range upgraded to 400kHz working, and no longer preliminary data.
5V voltage range at temperature range 3 (-xx3) no longer preliminary data.
-S voltage range removed. -Wxx3 voltage+temp ranged added as preliminary data.
07-Oct-2003
4.0
Table of contents, and Pb-free options added. Minor wording changes in Summary
Description, Power-On Reset, Memory Addressing, Read Operations. VIL(min) improved to
-0.45V. tW(max) value for -R voltage range corrected.
5.0
MLP package added. Absolute Maximum Ratings for VIO(min) and VCC(min) changed.
Soldering temperature information clarified for RoHS compliant devices. Device grade
information clarified. Process identification letter “G” information added. 2.2-5.5V range is
removed, and 4.5-5.5V range is now Not for New Design
17-Mar-2004
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Description of Revision
M24C16, M24C08, M24C04, M24C02, M24C01
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners.
© 2004 STMicroelectronics - All rights reserved
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