STMicroelectronics M24LR04E-R 4-kbit eeprom with password protection, dual interface & energy harvesting: 400 khz iâ²c bus & iso 15693 rf protocol at 13.56 mhz Datasheet

M24LR04E-R
4-Kbit EEPROM with password protection, dual interface & energy
harvesting: 400 kHz I²C bus & ISO 15693 RF protocol at 13.56 MHz
Datasheet − production data
Features
I2C interface
■
Two-wire I2C serial interface supports
400 kHz protocol
■
Single supply voltage:
– 1.8 V to 5.5 V
■
Byte and Page Write (up to 4 bytes)
■
Random and Sequential read modes
■
Self-timed programming cycle
■
Automatic address incrementing
■
Enhanced ESD/latch-up protection
■
I²C timeout
SO8 (MN)
150 mils width
UFDFPN8 (MC)
2 x 3 mm
TSSOP8 (DW)
Contactless interface
■
ISO 15693 and ISO 18000-3 mode 1
compatible
■
13.56 MHz ±7k Hz carrier frequency
■
To tag: 10% or 100% ASK modulation using
1/4 (26 Kbit/s) or 1/256 (1.6 Kbit/s) pulse
position coding
■
From tag: load modulation using Manchester
coding with 423 kHz and 484 kHz subcarriers
in low (6.6 kbit/s) or high (26 kbit/s) data rate
mode. Supports the 53 kbit/s data rate with
Fast commands
■
Internal tuning capacitance: 27.5pF
■
64-bit unique identifier (UID)
■
Read Block & Write (32-bit blocks)
Digital output pin
■
User configurable pin: RF write in progress or
RF busy mode
Energy harvesting
■
Analog pin for energy harvesting
■
4 sink current configurable ranges
June 2012
This is information on a product in full production.
Unsawn wafer size: 8”
Memory
■
4-Kbit EEPROM organized into:
– 512 bytes in I2C mode
– 128 blocks of 32 bits in RF mode
■
Write time
– I2C: 5 ms (max.)
– RF: 5.75 ms including the internal Verify
time
■
More than 1 million write cycles
■
More than 40-year data retention
■
Multiple password protection in RF mode
■
Single password protection in I2C mode
■
Package
– ECOPACK2® (RoHS compliant and
Halogen-free)
Doc ID 022208 Rev 5
1/142
www.st.com
1
Contents
M24LR04E-R
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1
Serial clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2
Serial data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3
RF Write in progress / RF Busy (RF WIP/BUSY) . . . . . . . . . . . . . . . . . . . 15
2.4
Energy harvesting analog output (Vout) . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5
Antenna coil (AC0, AC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5.1
Device reset in RF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.7
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.7.1
2.7.2
Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.7.3
Device reset in I²C mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.7.4
Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3
User memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4
System memory area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1
M24LR04E-R block security in RF mode . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1.1
4.2
M24LR04E-R block security in I²C mode (I2C_Write_Lock bit area) . . . . 26
4.3
Configuration byte and Control register . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.4
5
2/142
Example of the M24LR04E-R security protection in RF mode . . . . . . . 25
4.3.1
RF WIP/BUSY pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3.2
Energy harvesting configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3.3
FIELD_ON indicator bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3.4
Configuration byte access in I²C and RF modes . . . . . . . . . . . . . . . . . . 29
4.3.5
Control register access in I²C or RF mode . . . . . . . . . . . . . . . . . . . . . . 29
ISO 15693 system parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
I2C device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Doc ID 022208 Rev 4
M24LR04E-R
Contents
5.3
Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.4
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.5
I²C timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.5.1
I²C timeout on Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.5.2
I²C timeout on clock period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.6
Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.7
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.8
Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.9
Page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.10
Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 36
5.11
Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.12
Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.13
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.14
Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.15
Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.16
M24LR04E-R I2C password security . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.16.1
I2C present password command description . . . . . . . . . . . . . . . . . . . . . 39
5.16.2
I2C write password command description . . . . . . . . . . . . . . . . . . . . . . . 40
6
M24LR04E-R memory initial state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7
RF device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.1
RF communication and energy harvesting . . . . . . . . . . . . . . . . . . . . . . . . 42
7.2
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.3
Initial dialog for vicinity cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.3.1
Power transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.3.2
Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.3.3
Operating field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8
Communication signal from VCD to M24LR04E-R . . . . . . . . . . . . . . . . 45
9
Data rate and data coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.1
Data coding mode: 1 out of 256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.2
Data coding mode: 1 out of 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.3
VCD to M24LR04E-R frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Doc ID 022208 Rev 4
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Contents
M24LR04E-R
9.4
10
11
Communication signal from M24LR04E-R to VCD . . . . . . . . . . . . . . . . 52
10.1
Load modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.2
Subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.3
Data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Bit representation and coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.1
11.2
12
Start of frame (SOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Bit coding using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.1.1
High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.1.2
Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Bit coding using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.2.1
High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.2.2
Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
M24LR04E-R to VCD frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.1
12.2
12.3
12.4
SOF when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.1.1
High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.1.2
Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
SOF when using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12.2.1
High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12.2.2
Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
EOF when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
12.3.1
High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
12.3.2
Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
EOF when using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
12.4.1
High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
12.4.2
Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
13
Unique identifier (UID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
14
Application family identifier (AFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
15
Data storage format identifier (DSFID) . . . . . . . . . . . . . . . . . . . . . . . . . 62
15.1
16
4/142
CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
M24LR04E-R protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Doc ID 022208 Rev 4
M24LR04E-R
17
18
19
M24LR04E-R states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
17.1
Power-off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
17.2
Ready state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
17.3
Quiet state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
17.4
Selected state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
18.1
Addressed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
18.2
Non-addressed mode (general request) . . . . . . . . . . . . . . . . . . . . . . . . . 67
18.3
Select mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
19.1
20
21
Contents
Request flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
20.1
Response flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
20.2
Response error code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Anticollision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
21.1
Request parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
22
Request processing by the M24LR04E-R . . . . . . . . . . . . . . . . . . . . . . . 74
23
Explanation of the possible cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
24
Inventory Initiated command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
25
Timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
26
25.1
t1: M24LR04E-R response delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
25.2
t2: VCD new request delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
25.3
t3: VCD new request delay when no response is received
from the M24LR04E-R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Command codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
26.1
Inventory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
26.2
Stay Quiet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
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M24LR04E-R
26.3
Read Single Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
26.4
Write Single Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
26.5
Read Multiple Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
26.6
Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
26.7
Reset to Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
26.8
Write AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
26.9
Lock AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
26.10 Write DSFID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
26.11 Lock DSFID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
26.12 Get System Info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
26.13 Get Multiple Block Security Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
26.14 Write-sector Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
26.15 Lock-sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
26.16 Present-sector Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
26.17 Fast Read Single Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
26.18 Fast Inventory Initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
26.19 Fast Initiate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
26.20 Fast Read Multiple Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
26.21 Inventory Initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
26.22 Initiate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
26.23 ReadCfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
26.24 WriteEHCfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
26.25 WriteDOCfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
26.26 SetRstEHEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
26.27 CheckEHEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
27
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
28
I2C DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
29
RF electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
30
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
31
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
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Contents
Appendix A Anticollision algorithm (informative) . . . . . . . . . . . . . . . . . . . . . . . 137
A.1
Algorithm for pulsed slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Appendix B CRC (informative) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
B.1
CRC error detection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
B.2
CRC calculation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Appendix C Application family identifier (AFI) (informative) . . . . . . . . . . . . . . 140
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
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7/142
List of tables
M24LR04E-R
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
8/142
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Address most significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Address least significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Sector details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Sector security status byte area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Sector security status byte organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Read / Write protection bit setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Password control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Password system area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
M24LR04E-R sector security protection after power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
M24LR04E-R sector security protection after a valid presentation of password 1 . . . . . . . 25
I2C_Write_Lock bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Configuration byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
EH_enable bit value after power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
System parameter sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10% modulation parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Response data rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
UID format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
CRC transmission rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
VCD request frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
M24LR04E-R Response frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
M24LR04E-R response depending on Request_flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
General request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Definition of request flags 1 to 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Request flags 5 to 8 when Bit 3 = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Request flags 5 to 8 when Bit 3 = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
General response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Definitions of response flags 1 to 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Response error code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Inventory request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Example of the addition of 0-bits to an 11-bit mask value . . . . . . . . . . . . . . . . . . . . . . . . . 72
Timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Inventory request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Inventory response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Stay Quiet request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Read Single Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Read Single Block response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . 83
Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Read Single Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . 83
Write Single Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Write Single Block response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . 84
Write Single Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . 85
Read Multiple Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Read Multiple Block response format when Error_flag is NOT set. . . . . . . . . . . . . . . . . . . 88
Doc ID 022208 Rev 4
M24LR04E-R
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
List of tables
Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Read Multiple Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . 88
Select request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Select Block response format when Error_flag is NOT set. . . . . . . . . . . . . . . . . . . . . . . . . 89
Select response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Reset to Ready request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Reset to Ready response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . 91
Reset to ready response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Write AFI request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Write AFI response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Write AFI response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Lock AFI request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Lock AFI response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Lock AFI response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Write DSFID request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Write DSFID response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . 95
Write DSFID response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Lock DSFID request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Lock DSFID response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . 96
Lock DSFID response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Get System Info request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Get System Info response format when Protocol_extension_flag = 0 and
Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Get System Info response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Get Multiple Block Security Status request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Get Multiple Block Security Status response format when Error_flag is NOT set . . . . . . 100
Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Get Multiple Block Security Status response format when Error_flag is set . . . . . . . . . . . 101
Write-sector Password request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Write-sector Password response format when Error_flag is NOT set . . . . . . . . . . . . . . . 102
Write-sector Password response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . 102
Lock-sector request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Lock-sector response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . 103
Lock-sector response format when Error_flag is set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Present-sector Password request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Present-sector Password response format when Error_flag is NOT set . . . . . . . . . . . . . 105
Present-sector Password response format when Error_flag is set . . . . . . . . . . . . . . . . . . 105
Fast Read Single Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Fast Read Single Block response format when Error_flag is NOT set . . . . . . . . . . . . . . . 107
Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Fast Read Single Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . 107
Fast Inventory Initiated request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Fast Inventory Initiated response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Fast Initiate request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Fast Initiate response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Fast Read Multiple Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Fast Read Multiple Block response format when Error_flag is NOT set. . . . . . . . . . . . . . 111
Sector security status if Option_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Fast Read Multiple Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . 112
Inventory Initiated request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Inventory Initiated response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Doc ID 022208 Rev 4
9/142
List of tables
Table 100.
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
Table 125.
Table 126.
Table 127.
Table 128.
Table 129.
Table 130.
Table 131.
Table 132.
10/142
M24LR04E-R
Initiate request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Initiate Initiated response format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
ReadCfg request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
ReadCfg response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . . 115
ReadCfg response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
WriteEHCfg request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
WriteEHCfg response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . 116
WriteEHCfg response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
WriteDOCfg request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
WriteDOCfg response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . 118
WriteDOCfg response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
SetRstEHEn request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
SetRstEHEn response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . 119
SetRstEHEn response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
CheckEHEn request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
CheckEHEn response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . 120
CheckEHEn response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
I2C operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
I2C DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
I2C AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
RF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Energy harvesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
SO8N – 8-lead plastic small outline, 150 mils body width, package data. . . . . . . . . . . . . 133
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . 135
Ordering information scheme for bare die devices or packaged devices . . . . . . . . . . . . . 136
CRC definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
AFI coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Doc ID 022208 Rev 4
M24LR04E-R
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic
capacitance (Cbus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Memory sector organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
I²C timeout on Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Write mode sequences with I2C_Write_Lock bit = 1 (data write inhibited). . . . . . . . . . . . . 33
Write mode sequences with I2C_Write_Lock bit = 0 (data write enabled) . . . . . . . . . . . . . 35
Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
I2C present password command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
I2C write password command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
100% modulation waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10% modulation waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
1 out of 256 coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Detail of a time period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
1 out of 4 coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
1 out of 4 coding example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
SOF to select 1 out of 256 data coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SOF to select 1 out of 4 data coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
EOF for either data coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Logic 0, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Logic 0, high data rate, fast commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Logic 1, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Logic 1, high data rate, fast commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Logic 0, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Logic 0, low data rate, fast commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Logic 1, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Logic 1, low data rate, fast commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Logic 0, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Logic 1, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Logic 0, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Logic 1, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Start of frame, high data rate, one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Start of frame, high data rate, one subcarrier, fast commands. . . . . . . . . . . . . . . . . . . . . . 56
Start of frame, low data rate, one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Start of frame, low data rate, one subcarrier, fast commands . . . . . . . . . . . . . . . . . . . . . . 57
Start of frame, high data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Start of frame, low data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
End of frame, high data rate, one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
End of frame, high data rate, one subcarrier, fast commands . . . . . . . . . . . . . . . . . . . . . . 58
End of frame, low data rate, one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
End of frame, low data rate, one subcarrier, Fast commands . . . . . . . . . . . . . . . . . . . . . . 58
End of frame, high data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
End of frame, low data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
M24LR04E-R decision tree for AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Doc ID 022208 Rev 4
11/142
List of figures
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
Figure 86.
Figure 87.
Figure 88.
Figure 89.
12/142
M24LR04E-R
M24LR04E-R protocol timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
M24LR04E-R state transition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Principle of comparison between the mask, the slot number and the UID . . . . . . . . . . . . . 73
Description of a possible anticollision sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
M24LR04E RF-Busy management following Inventory command . . . . . . . . . . . . . . . . . . . 81
Stay Quiet frame exchange between VCD and M24LR04E-R . . . . . . . . . . . . . . . . . . . . . . 82
Read Single Block frame exchange between VCD and M24LR04E-R. . . . . . . . . . . . . . . . 84
Write Single Block frame exchange between VCD and M24LR04E-R . . . . . . . . . . . . . . . . 85
M24LR04E RF-Busy management following Write command . . . . . . . . . . . . . . . . . . . . . . 86
M24LR04E RF-Wip management following Write command . . . . . . . . . . . . . . . . . . . . . . . 87
Read Multiple Block frame exchange between VCD and M24LR04E-R . . . . . . . . . . . . . . 89
Select frame exchange between VCD and M24LR04E-R . . . . . . . . . . . . . . . . . . . . . . . . . 90
Reset to Ready frame exchange between VCD and M24LR04E-R . . . . . . . . . . . . . . . . . . 91
Write AFI frame exchange between VCD and M24LR04E-R . . . . . . . . . . . . . . . . . . . . . . . 93
Lock AFI frame exchange between VCD and M24LR04E-R . . . . . . . . . . . . . . . . . . . . . . . 94
Write DSFID frame exchange between VCD and M24LR04E-R . . . . . . . . . . . . . . . . . . . . 96
Lock DSFID frame exchange between VCD and M24LR04E-R. . . . . . . . . . . . . . . . . . . . . 97
Get System Info frame exchange between VCD and M24LR04E-R . . . . . . . . . . . . . . . . . 99
Get Multiple Block Security Status frame exchange between VCD and M24LR04E-R . . 101
Write-sector Password frame exchange between VCD and M24LR04E-R . . . . . . . . . . . 102
Lock-sector frame exchange between VCD and M24LR04E-R . . . . . . . . . . . . . . . . . . . . 104
Present-sector Password frame exchange between VCD and M24LR04E-R . . . . . . . . . 106
Fast Read Single Block frame exchange between VCD and M24LR04E-R. . . . . . . . . . . 108
Fast Initiate frame exchange between VCD and M24LR04E-R . . . . . . . . . . . . . . . . . . . . 110
Fast Read Multiple Block frame exchange between VCD and M24LR04E-R . . . . . . . . . 112
Initiate frame exchange between VCD and M24LR04E-R . . . . . . . . . . . . . . . . . . . . . . . . 114
ReadCfg frame exchange between VCD and M24LR04E-R . . . . . . . . . . . . . . . . . . . . . . 115
WriteEHCfg frame exchange between VCD and M24LR04E-R . . . . . . . . . . . . . . . . . . . . 117
WriteDOCfg frame exchange between VCD and M24LR04E-R. . . . . . . . . . . . . . . . . . . . 118
SetRstEHEn frame exchange between VCD and M24LR04E-R . . . . . . . . . . . . . . . . . . . 120
CheckEHEn frame exchange between VCD and M24LR04E-R. . . . . . . . . . . . . . . . . . . . 121
AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
I2C AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
ASK modulated signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Vout vs. Isink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Range 11 domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Range 10 domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Range 01 domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Range 00 domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . 133
UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 × 3mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . 135
Doc ID 022208 Rev 4
M24LR04E-R
1
Description
Description
The M24LR04E-R device is a dual-interface, electrically erasable programmable memory
(EEPROM). It features an I2C interface and can be operated from a VCC power supply. It is
also a contactless memory powered by the received carrier electromagnetic wave. The
M24LR04E-R is organized as 512 × 8 bits in the I2C mode and as 128 × 32 bits in RF mode.
The M24LR04E-R also features an energy harvesting analog output, as well as a userconfigurable digital output pin toggling during either RF write in progress or RF busy mode.
Figure 1.
Logic diagram
VCC
Vout
SCL
SDA
AC0
M24LR04E-R
AC1
RF WIP/
#64:
VSS
MS19765V1
I2C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The
devices carry a built-in 4-bit device type identifier code (1010) in accordance with the I2C
bus definition.
The device behaves as a slave in the I2C protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are initiated by a Start condition, generated
by the bus master. The Start condition is followed by a device select code and Read/Write
bit (RW) (as described in Table 2), terminated by an acknowledge bit.
When writing data to the memory, the device inserts an acknowledge bit during the 9th bit
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
In the ISO15693/ISO18000-3 mode 1 RF mode, the M24LR04E-R is accessed via the
13.56 MHz carrier electromagnetic wave on which incoming data are demodulated from the
received signal amplitude modulation (ASK: amplitude shift keying). When connected to an
antenna, the operating power is derived from the RF energy and no external power supply is
required. The received ASK wave is 10% or 100% modulated with a data rate of 1.6 Kbit/s
Doc ID 022208 Rev 5
13/142
Description
M24LR04E-R
using the 1/256 pulse coding mode or a data rate of 26 Kbit/s using the 1/4 pulse coding
mode.
Outgoing data are generated by the M24LR04E-R load variation using Manchester coding
with one or two subcarrier frequencies at 423 kHz and 484 kHz. Data are transferred from
the M24LR04E-R at 6.6 Kbit/s in low data rate mode and 26 Kbit/s high data rate mode. The
M24LR04E-R supports the 53 Kbit/s fast mode in high data rate mode using one subcarrier
frequency at 423 kHz.
The M24LR04E-R follows the ISO 15693 and ISO 18000-3 mode 1 recommendation for
radio-frequency power and signal interface.
The M24LR04E-R provides an Energy harvesting mode on the analog output pin Vout.
When the Energy harvesting mode is activated, the M24LR04E-R can output the excess
energy coming from the RF field on the Vout analog pin. In case the RF field strength is
insufficient or when Energy harvesting mode is disabled, the analog output pin Vout goes
into high-Z state and Energy harvesting mode is automatically stopped.
The M24LR04E-R features a user configurable digital out pin RF WIP/BUSY that can be
used to drive a micro controller interrupt input pin (available only when the M24LR04E-R is
correctly powered on the Vcc pin).
When configured in the RF write in progress mode (RF WIP mode), the RF WIP/BUSY pin is
driven low for the entire duration of the RF internal write operation. When configured in the
RF busy mode (RF BUSY mode), the RF WIP/BUSY pin is driven low for the entire duration
of the RF command progress.
The RF WIP/BUSY pin is an open drain output and must be connected to a pull-up resistor.
Table 1.
Signal names
Signal name
Function
Vout
Energy harvesting Output
Analog output
SDA
Serial Data
I/O
SCL
Serial Clock
Input
AC0, AC1
Antenna coils
I/O
VCC
Supply voltage
RF WIP/BUSY
Digital signal
VSS
Ground
Figure 2.
Digital output
8-pin package connections
Vout
AC0
AC1
VSS
1
2
3
4
8
7
6
5
VCC
RF WIP/BUSY
SCL
SDA
1. See Section 30 for package dimensions, and how to identify pin-1.
14/142
Direction
Doc ID 022208 Rev 5
MS19742V1
M24LR04E-R
Signal descriptions
2
Signal descriptions
2.1
Serial clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this
signal is used by slave devices to synchronize the bus to a slower clock, the bus master
must have an open drain output, and a pull-up resistor must be connected from Serial Clock
(SCL) to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). In
most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the bus master has a push-pull (rather than open
drain) output.
2.2
Serial data (SDA)
This bidirectional signal is used to transfer data in or out of the device. It is an open drain
output that may be wire-OR’ed with other open drain or open collector signals on the bus. A
pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 3 indicates how
the value of the pull-up resistor can be calculated).
2.3
RF Write in progress / RF Busy (RF WIP/BUSY)
This configurable output signal is used either to indicate that the M24LR04E-R is executing
an internal write cycle from the RF channel or that an RF command is in progress. RF WIP
and signals are available only when the M24LR04E-R is powered by the Vcc pin. It is an
open drain output and a pull up resistor must be connected from RF WIP/BUSY to VCC.
2.4
Energy harvesting analog output (Vout)
This analog output pin is used to deliver the analog voltage Vout available when the Energy
harvesting mode is enabled and the RF field strength is sufficient. When the Energy
harvesting mode is disabled or the RF field strength is not sufficient, the energy harvesting
analog voltage output Vout is in High-Z state.
2.5
Antenna coil (AC0, AC1)
These inputs are used to connect the device to an external coil exclusively. It is advised not
to connect any other DC or AC path to AC0 or AC1.
When correctly tuned, the coil is used to power and access the device using the ISO 15693
and ISO 18000-3 mode 1 protocols.
2.5.1
Device reset in RF mode
To ensure a proper reset of the RF circuitry, the RF field must be turned off (100%
modulation) for a minimum tRF_OFF period of time.
Doc ID 022208 Rev 5
15/142
Signal descriptions
2.6
M24LR04E-R
VSS ground
VSS is the reference for the VCC supply voltage and Vout analog output voltage.
2.7
Supply voltage (VCC)
This pin can be connected to an external DC supply voltage.
Note:
An internal voltage regulator allows the external voltage applied on VCC to supply the
M24LR04E-R, while preventing the internal power supply (rectified RF waveforms) to output
a DC voltage on the VCC pin.
2.7.1
Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Table 118). To
maintain a stable DC supply voltage, it is recommended to decouple the VCC line with a
suitable capacitor (usually of the order of 10 nF) close to the VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal I²C write cycle (tW).
2.7.2
Power-up conditions
When the power supply is turned on, VCC rises from VSS to VCC. The VCC rise time must not
vary faster than 1V/µs.
2.7.3
Device reset in I²C mode
In order to prevent inadvertent write operations during power-up, a power-on reset (POR)
circuit is included. At power-up (continuous rise of VCC), the device does not respond to any
I²C instruction until VCC has reached the power-on reset threshold voltage (this threshold is
lower than the minimum VCC operating voltage defined in Table 118). When VCC passes
over the POR threshold, the device is reset and enters the Standby power mode. However,
the device must not be accessed until VCC has reached a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range.
In a similar way, during power-down (continuous decrease in VCC), as soon as VCC drops
below the power-on reset threshold voltage, the device stops responding to any instruction
sent to it.
2.7.4
Power-down conditions
During power-down (continuous decay of VCC), the device must be in Standby power mode
(mode reached after decoding a Stop condition, assuming that there is no internal write
cycle in progress).
16/142
Doc ID 022208 Rev 5
M24LR04E-R
Signal descriptions
I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic
capacitance (Cbus)
Figure 3.
Bus line pull-up resistor
(k )
100
10
4 kΩ
When tLOW = 1.3 µs (min value for
fC = 400 kHz), the Rbus × Cbus
time constant must be below the
400 ns time constant line
represented on the left.
R
bu
s ×
C
bu
s =
Here Rbus × Cbus = 120 ns
4
VCC
Rbus
00
ns
I²C bus
master
SCL
M24xxx
SDA
1
30 pF
10
100
Bus line capacitor (pF)
Cbus
1000
ai14796b
Figure 4.
I2C bus protocol
SCL
SDA
SDA
Input
Start
Condition
SCL
1
SDA
MSB
2
SDA
Change
Stop
Condition
3
7
8
9
ACK
Start
Condition
SCL
1
SDA
MSB
2
3
7
8
9
ACK
Stop
Condition
AI00792B
Doc ID 022208 Rev 5
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Signal descriptions
Table 2.
M24LR04E-R
Device select code
Device type identifier(1)
Device select code
Chip Enable address
RW
b7
b6
b5
b4
b3
b2
b1
b0
1
0
1
0
E2(2)
1
1
RW
1. The most significant bit, b7, is sent first.
2. E2 is not connected to any external pin. It is however used to address the M24LR04E-R as described in
Section 3 and Section 4.
Table 3.
b15
Table 4.
b7
18/142
Address most significant byte
b14
b13
b12
b11
b10
b9
b8
b3
b2
b1
b0
Address least significant byte
b6
b5
b4
Doc ID 022208 Rev 5
M24LR04E-R
3
User memory organization
User memory organization
The M24LR04E-R is divided into 4 sectors of 32 blocks of 32 bits, as shown in Table 5.
Figure 6 shows the memory sector organization. Each sector can be individually readand/or write-protected using a specific password command. Read and write operations are
possible if the addressed data are not in a protected sector.
The M24LR04E-R also has a 64-bit block that is used to store the 64-bit unique identifier
(UID). The UID is compliant with the ISO 15963 description, and its value is used during the
anticollision sequence (Inventory). This block is not accessible by the user and its value is
written by ST on the production line.
The M24LR04E-R includes an AFI register that stores the application family identifier, and a
DSFID register that stores the data storage family identifier used in the anticollision
algorithm.
The M24LR04E-R has four 32-bit blocks that store an I2C password plus three RF password
codes.
Figure 5.
Circuit diagram
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User memory organization
Figure 6.
M24LR04E-R
Memory sector organization
Sector security
status
Sector
Area
0
1
2
3
1 Kbit EEPROM sector
1 Kbit EEPROM sector
1 Kbit EEPROM sector
1 Kbit EEPROM sector
5 bits
I²C password
RF password 1
RF password 2
RF password 3
8-bit DSFID
8-bit AFI
64-bit UID
8-bit configuration
System
16-bit I²C Write Lock_bit
20-bit SSS
System
System
5 bits
5 bits
5 bits
System
System
System
System
System
System
MS19766V1
Sector details
The M24LR04E-R user memory is divided into 4 sectors. Each sector contains 1024 bits.
The protection scheme is described in Section 4: System memory area.
In RF mode, a sector provides 32 blocks of 32 bits. Each read and write access is done by
block. Read and write block accesses are controlled by a Sector Security Status byte that
defines the access rights to the 32 blocks contained in the sector. If the sector is not
protected, a Write command updates the complete 32 bits of the selected block.
In I2C mode, a sector provides 128 bytes that can be individually accessed in Read and
Write modes. When protected by the corresponding I2C_Write_Lock bit, the entire sector is
write-protected. To access the user memory, the device select code used for any I2C
command must have the E2 Chip Enable address at 0.
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User memory organization
Table 5.
Sector
number
Sector details
RF block
address
I2C byte
address
Bits [31:24]
Bits [23:16]
Bits [15:8]
Bits [7:0]
0
0
user
user
user
user
1
4
user
user
user
user
2
8
user
user
user
user
3
12
user
user
user
user
4
16
user
user
user
user
5
20
user
user
user
user
6
24
user
user
user
user
7
28
user
user
user
user
8
32
user
user
user
user
9
36
user
user
user
user
10
40
user
user
user
user
11
44
user
user
user
user
12
48
user
user
user
user
13
52
user
user
user
user
14
56
user
user
user
user
15
60
user
user
user
user
16
64
user
user
user
user
17
68
user
user
user
user
18
72
user
user
user
user
19
76
user
user
user
user
20
80
user
user
user
user
21
84
user
user
user
user
22
88
user
user
user
user
23
92
user
user
user
user
24
96
user
user
user
user
25
100
user
user
user
user
26
104
user
user
user
user
27
108
user
user
user
user
28
112
user
user
user
user
29
116
user
user
user
user
30
120
user
user
user
user
31
124
user
user
user
user
0
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User memory organization
Table 5.
Sector
number
1
2
M24LR04E-R
Sector details (continued)
RF block
address
I2C byte
address
Bits [31:24]
Bits [23:16]
Bits [15:8]
Bits [7:0]
32
128
user
user
user
user
33
132
user
user
user
user
34
136
user
user
user
user
35
140
user
user
user
user
36
144
user
user
user
user
37
148
user
user
user
user
38
152
user
user
user
user
39
156
user
user
user
user
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
127
508
user
user
user
user
3
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System memory area
4
System memory area
4.1
M24LR04E-R block security in RF mode
The M24LR04E-R provides a special protection mechanism based on passwords. In RF
mode, each memory sector of the M24LR04E-R can be individually protected by one out of
three available passwords, and each sector can also have Read/Write access conditions
set.
Each memory sector of the M24LR04E-R is assigned with a Sector security status byte
including a Sector Lock bit, two Password Control bits and two Read/Write protection bits,
as shown in Table 7.
Table 6 describes the organization of the Sector security status byte, which can be read
using the Read Single Block and Read Multiple Block commands with the Option_flag set
to 1.
On delivery, the default value of the SSS bytes is set to 00h.
Table 6.
I2C
Sector security status byte area
byte address
E2 = 1
Table 7.
Bits [31:24]
Bits [23:16]
Bits [15:8]
Bits [7:0]
SSS 3
SSS 2
SSS 1
SSS 0
0
Sector security status byte organization
b7
b6
b5
0
0
0
b4
b3
Password control bits
b2
b1
b0
Read / Write
protection bits
Sector
Lock
When the Sector Lock bit is set to 1, for instance by issuing a Lock-sector command, the two
Read/Write protection bits (b1, b2) are used to set the Read/Write access of the sector as
described in Table 8.
Table 8.
Read / Write protection bit setting
Sector access
Sector access
when password presented
when password not presented
Sector
Lock
b2, b1
0
xx
Read
Write
Read
Write
1
00
Read
Write
Read
No Write
1
01
Read
Write
Read
Write
1
10
Read
Write
No Read
No Write
1
11
Read
No Write
No Read
No Write
The next two bits of the Sector security status byte (b3, b4) are the password control bits.
The value of these two bits is used to link a password to the sector, as defined in Table 9.
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System memory area
Table 9.
M24LR04E-R
Password control bits
b4, b3
Password
00
The sector is not protected by a password.
01
The sector is protected by password 1.
10
The sector is protected by password 2.
11
The sector is protected by password 3.
The M24LR04E-R password protection is organized around a dedicated set of commands,
plus a system area of three password blocks where the password values are stored. This
system area is described in Table 10.
Table 10.
Password system area
Add
1
Password 1
2
Password 2
3
Password 3
The dedicated commands for protection in RF mode are:
●
Write-sector password:
The Write-sector password command is used to write a 32-bit block into the password
system area. This command must be used to update password values. After the write
cycle, the new password value is automatically activated. It is possible to modify a
password value after issuing a valid Present-sector password command. On delivery,
the three default password values are set to 0000 0000h and are activated.
●
Lock-sector:
The Lock-sector command is used to set the sector security status byte of the selected
sector. Bits b4 to b1 of the sector security status byte are affected by the Lock-sector
command. The sector lock bit, b0, is set to 1 automatically. After issuing a Lock-sector
command, the protection settings of the selected sector are activated. The protection of
a locked block cannot be changed in RF mode. A Lock-sector command sent to a
locked sector returns an error code.
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M24LR04E-R
System memory area
●
Present-sector password:
The Present-sector password command is used to present one of the three passwords
to the M24LR04E-R in order to modify the access rights of all the memory sectors
linked to that password (Table 8) including the password itself. If the presented
password is correct, the access rights remain activated until the tag is powered off or
until a new Present-sector password command is issued. If the presented password
value is not correct, all the access rights of all the memory sectors are deactivated.
●
Sector security status byte area access conditions in I2C mode:
In I2C mode, read access to the sector security status byte area is always allowed.
Write access depends on the correct presentation of the I2C password (see
Section 5.16.1: I2C present password command description).
To access the Sector security status byte area, the device select code used for any I2C
command must have the E2 Chip Enable address at 1.
An I2C write access to a sector security status byte re-initializes the RF access
condition to the given memory sector.
4.1.1
Example of the M24LR04E-R security protection in RF mode
Table 11 and Table 12 show the sector security protections before and after a valid Presentsector password command. Table 11 shows the sector access rights of an M24LR04E-R
after power-up. After a valid Present-sector password command with password 1, the
memory sector access is changed as shown in Table 12.
Table 11.
M24LR04E-R sector security protection after power-up
Sector security status byte
Sector
address
b7b6b5
b4
b3
b2
b1
b0
0
Protection: standard
Read
No Write
xxx
0
0
0
0
1
1
Protection: pswd 1
Read
No Write
xxx
0
1
0
0
1
2
Protection: pswd 1
Read
Write
xxx
0
1
0
1
1
3
Protection: pswd 1
No Read
No Write
xxx
0
1
1
0
1
4
Protection: pswd 1
No Read
No Write
xxx
0
1
1
1
1
Table 12.
M24LR04E-R sector security protection after a valid presentation of
password 1
Sector security status byte
Sector
address
b7b6b5
b4 b3 b2 b1 b0
0
Protection: standard
Read
No Write
xxx
0
0
0
0
1
1
Protection: pswd 1
Read
Write
xxx
0
1
0
0
1
2
Protection: pswd 1
Read
Write
xxx
0
1
0
1
1
3
Protection: pswd 1
Read
Write
xxx
0
1
1
0
1
4
Protection: pswd 1
Read
No Write
xxx
0
1
1
1
1
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System memory area
4.2
M24LR04E-R
M24LR04E-R block security in I²C mode (I2C_Write_Lock bit
area)
In the I2C mode only, it is possible to protect individual sectors against Write operations.
This feature is controlled by the I2C_Write_Lock bits stored in the 2 bytes of the
I2C_Write_Lock bit area. I2C_Write_Lock bit area starts from location 2048 (see Table 13).
To access the I2C_Write_Lock bit area, the device select code used for any I2C command
must have the E2 Chip Enable address at 1.
Using these 16 bits, it is possible to write-protect all the 4 sectors of the M24LR04E-R
memory. Each bit controls the I2C write access to a specific sector as shown in Table 13. It
is always possible to unprotect a sector in the I2C mode. When an I2C_Write_Lock bit is
reset to 0, the corresponding sector is unprotected. When the bit is set to 1, the
corresponding sector is write-protected.
In I2C mode, read access to the I2C_Write_Lock bit area is always allowed. Write access
depends on the correct presentation of the I2C password.
On delivery, the default value of the two bytes of the I2C_Write_Lock bit area is reset to 00h.
m
Table 13.
I2C_Write_Lock bit
I2C
byte address
E2 = 1
4.3
2048
Bits [4:15]
Bits [3:0]
Don’t care
sectors 0-3
Configuration byte and Control register
The M24LR04E-R offers an 8-bit non-volatile Configuration byte located at I²C location 2320
of the system area used to store the RF WIP/BUSY pin and the energy harvesting
configuration (see Table 14).
The M24LR04E-R also offers an 8-bit volatile Control register located at I²C location 2336 of
the system area used to store the energy harvesting enable bit as well as a FIELD_ON bit
indicator (see Table 15).
4.3.1
RF WIP/BUSY pin configuration
The M24LR04E-R features a configurable open drain output RF WIP/BUSY pin used to
provide RF activity information to an external device.
The RF WIP/BUSY pin functionality depends on the value of bit 3 of the Configuration byte.
●
RF busy mode
When bit 3 of the Configuration byte is set to 0, the RF WIP/BUSY pin is configured in RF
busy mode.
The purpose of this mode is to indicate to the I²C bus master whether the M24LR04E-R is
busy in RF mode or not.
In this mode, the RF WIP/BUSY pin is tied to 0 from the RF command Start Of Frame (SOF)
until the end of the command execution.
If a bad RF command is received, the RF WIP/BUSY pin is tied to 0 from the RF command
SOF until the reception of the RF command CRC. Otherwise, the RF WIP/BUSY pin is in
high-Z state.
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System memory area
When tied to 0, the RF WIP/BUSY signal returns to High-Z state if the RF field is cut-off.
During execution of I²C commands, the RF WIP/BUSY pin remains in high-Z state.
●
RF Write in progress
When bit 3 of the Configuration byte is set to 1, the RF WIP/BUSY pin is configured in RF
Write in progress mode.
The purpose of this mode is to indicate to the I²C bus master that some data have been
changed in RF mode.
In this mode, the RF WIP/BUSY pin is tied to 0 for the duration of an internal write operation
(i.e. between the end of a valid RF write command and the beginning of the RF answer).
During execution of I²C write operations, the RF WIP/BUSY pin remains in high-Z state.
4.3.2
Energy harvesting configuration
The M24LR04E-R features an Energy harvesting mode on the Vout analog output.
The general purpose of the Energy harvesting mode is to deliver a part of the nonnecessary RF power received by the M24LR04E-R on the AC0-AC1 RF input in order to
supply an external device. The current consumption on the analog voltage output Vout is
limited to ensure that the M24LR04E-R is correctly supplied during the powering of the
external device.
When the Energy harvesting mode is enabled and the power delivered on the AC0-AC1 RF
input exceeds the minimum required PAC0-AC1_min, the M24LR04E-R is able to deliver a
limited and unregulated voltage on the Vout pin, assuming the current consumption on the
Vout does not exceed the Isink_max maximum value.
If one of the condition above is not met, the analog voltage output pin Vout is set in High-Z
state.
For robust applications using the Energy harvesting mode, four current fan-out levels can be
chosen.
●
Vout sink current configuration
The sink current level is chosen by programming EH_cfg1 and EH_cfg0 into the
Configuration byte (see Table 14).
The minimum power level required on AC0-AC1 RF input PAC0-AC1_min, the delivered
voltage Vout, as well as the maximum current consumption Isink_max on the Vout pin
corresponding to the <EH_cfg1,EH_cfg0> bit values are described in Table 125.
Table 14.
I2C
Configuration byte
byte address Bit 7 Bit 6 Bit 5 Bit 4
E2=1
2320
X(1)
X(1)
X(1)
X(1)
Bit 3
RF WIP/BUSY
Bit 2
BIT 1
BIT 0
EH_mode EH_cfg1 EH_cfg0
1. Bit 7 to Bit 4 are don’t care bits.
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System memory area
M24LR04E-R
Energy harvesting enable control
●
Delivery of Energy harvesting analog output voltage on the Vout pin depends on the value of
the EH_enable bit of the volatile Control register (see Table 15).
Table 15.
Control register
2
I C byte address
E2=1
2336
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0(1)
0(1)
0(1)
0(1)
0(1)
0(1)
BIT 1
BIT 0
FIELD_ON(1)
EH_enable
1. Bit 7 to Bit 1 are read-only bits.
●
–
When set to 1, the EH_enable bit enables the Energy harvesting mode, meaning
that the Vout analog output signal is delivered when the PAC0-AC1_min and Isink_max
conditions corresponding to the chosen sink current configuration bit are met (see
Table 125).
–
When set to 0, the EH_enable bit disable the Energy harvesting mode and the
analog output Vout remains in set in High-Z state.
Energy harvesting default mode control
At power-up, in I²C or RF mode, the EH_enable bit is updated according to the value of the
EH_mode bit stored in the non-volatile Configuration byte (see Table 16). In other words, the
EH_mode bit is used to configure whether the Energy harvesting mode is enabled or not by
default.
Table 16.
4.3.3
EH_enable bit value after power-up
Energy harvesting
EH_mode value
EH_enable after power-up
0
1
enabled
1
0
disabled
after power-up
FIELD_ON indicator bit
The FIELD_ON bit indicator located as Bit 1 of the Control register is a read-only bit used to
indicate when the RF power level delivered to the M24LR04E-R is sufficient to execute RF
commands.
Note:
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●
When FIELD_ON = 0, the M24LR04E-R is not able to execute any RF commands.
●
When FIELD_ON =1, the M24LR04E-R is able to execute any RF commands.
During read access to the Control register in RF mode, the FIELD_ON bit is always read
at 1.
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M24LR04E-R
4.3.4
System memory area
Configuration byte access in I²C and RF modes
In I²C mode, read and write accesses to the non-volatile Configuration byte are always
allowed. To access the Configuration byte, the device select code used for any I²C
command must have the E2 Chip enable address at 1.
The dedicated commands to access the Configuration byte in RF mode are:
●
Read configuration byte command (ReadCfg):
The ReadCfg command is used to read the eight bits of the Configuration byte.
●
Write energy harvesting configuration command (WriteEHCfg):
The WriteEHCfg command is used to write the EH_mode, EH_cfg1 and EH_cfg0 bits into
the Configuration byte.
●
Write RF WIP/BUSY pin configuration command (WriteDOCfg):
The WriteDOCfg command is used to write the RF WIP/BUSY bit into the Configuration
byte.
After any write access to the Configuration byte, the new configuration is automatically
applied.
4.3.5
Control register access in I²C or RF mode
In I²C mode, read and write accesses to the volatile Control register are always allowed. To
access the Control register, the device select code used for any I²C command must have the
E2 Chip enable address at 1.
The dedicated commands to access the Control register in RF mode are:
●
Check energy harvesting enable bit command (CheckEHEn):
The CheckEHEn command is used to read the eight bits of the Control register. When it is
run, the FIELD_ON bit is always read at 1.
●
Set/reset energy harvesting enable bit command (SetRstEHEn):
The SetRstEHEn command is used to set or reset the value of the EH_enable bit into the
Control register.
4.4
ISO 15693 system parameters
The M24LR04E-R provides the system area required by the ISO 15693 RF protocol, as
shown in Table 17.
The first 32-bit block starting from I2C address 2304 stores the I2C password. This password
is used to activate/deactivate the write protection of the protected sector in I2C mode. At
power-on, all user memory sectors protected by the I2C_Write_Lock bits can be read but
cannot be modified. To remove the write protection, it is necessary to use the I2C present
password described in Figure 12. When the password is correctly presented — that is, when
all the presented bits correspond to the stored ones — it is also possible to modify the I2C
password using the I2C write password command described in Figure 13.
The next three 32-bit blocks store the three RF passwords. These passwords are neither
read- nor write- accessible in the I2C mode.
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System memory area
M24LR04E-R
The next byte stores the Configuration byte, at I²C location 2320. This Control register is
used to store the three energy harvesting configuration bits and the RF WIP/BUSY
configuration bit.
The next two bytes are used to store the AFI, at I2C location 2322, and the DSFID, at I2C
location 2323. These two values are used during the RF inventory sequence. They are readonly in the I2C mode.
The next eight bytes, starting from location 2324, store the 64-bit UID programmed by ST on
the production line. Bytes at I2C locations 2332 to 2335 store the IC Ref and the Mem_Size
data used by the RF Get_System_Info command. The UID, Mem_Size and IC ref values are
read-only data.
Table 17.
System parameter sector
I2C byte address
Bits [31:24]
Bits [23:16]
2C
Bits [15:8]
password
Bits [7:0]
(1)
E2 = 1
2304
I
E2 = 1
2308
RF password 1(1)
E2 = 1
2312
RF password 2(1)
E2 = 1
2316
RF password 3 (1)
E2 = 1
2320
DSFID (FFh)
AFI (00h)
ST reserved
Configuration
byte (F4h)
E2 = 1
2324
UID
UID
UID
UID
E2 = 1
2328
UID (E0h)
UID (02h)
UID
UID
E2 = 1
2332
RFU
(FFh)
Mem_Size
(03 7F)
IC Ref (5A)
1. Delivery state: I2C password= 0000 0000h, RF password = 0000 0000h, Configuration byte = F4h
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I2C device operation
M24LR04E-R
5
I2C device operation
The device supports the I2C protocol. This is summarized in Figure 4. Any device that sends
data to the bus is defined as a transmitter, and any device that reads data is defined as a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which also
provides the serial clock for synchronization. The M24LR04E-R device is a slave in all
communications.
5.1
Start condition
Start is identified by a falling edge of serial data (SDA) while the serial clock (SCL) is stable
in the high state. A Start condition must precede any data transfer command. The device
continuously monitors (except during a write cycle) the SDA and the SCL for a Start
condition, and does not respond unless one is given.
5.2
Stop condition
Stop is identified by a rising edge of serial data (SDA) while the serial clock (SCL) is stable
and driven high. A Stop condition terminates communication between the device and the
bus master. A Read command that is followed by NoAck can be followed by a Stop condition
to force the device into the Standby mode. A Stop condition at the end of a Write command
triggers the internal write cycle.
5.3
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases the serial data (SDA) after sending eight
bits of data. During the 9th clock pulse period, the receiver pulls the SDA low to acknowledge
the receipt of the eight data bits.
5.4
Data input
During data input, the device samples serial data (SDA) on the rising edge of the serial clock
(SCL). For correct device operation, the SDA must be stable during the rising edge of the
SCL, and the SDA signal must change only when the SCL is driven low.
5.5
I²C timeout
During the execution of an I²C operation, RF communications are not possible.
To prevent RF communication freezing due to inadvertent unterminated instructions sent to
the I²C bus, the M24LR04E-R features a timeout mechanism that automatically resets the
I²C logic block.
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I2C device operation
5.5.1
M24LR04E-R
I²C timeout on Start condition
I²C communication with the M24LR04E-R starts with a valid Start condition, followed by a
device select code.
If the delay between the Start condition and the following rising edge of the Serial Clock
(SCL) that samples the most significant of the Device Select exceeds the tSTART_OUT time
(see Table 122), the I²C logic block is reset and further incoming data transfer is ignored
until the next valid Start Condition.
Figure 7.
5.5.2
I²C timeout on Start condition
I²C timeout on clock period
During data transfer on the I²C bus, the serial clock high pulse width High (tCHCL) or serial
clock pulse width Low (tCLCH) exceeds the maximum value specified in Table 122, the I²C
logic block is reset and any further incoming data transfer is ignored until the next valid Start
condition.
5.6
Memory addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 2 (on Serial Data (SDA), most significant bit first).
Only one memory device can be connected on a single I²C bus. In M24LR04E-R, E1 and E0
are internally set to 1.
The eighth bit is the Read/Write bit (RW). It is set to 1 for Read and to 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on serial data (SDA) during the ninth bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
Table 18.
Operating modes
Mode
Current address read
RW bit
Bytes
1
1
0
Random address read
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Start, device select, RW = 1
Start, device select, RW = 0, address
1
reStart, device select, RW = 1
1
Sequential read
Initial sequence
1
≥1
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Similar to current or random address read
I2C device operation
M24LR04E-R
Table 18.
Operating modes
Mode
RW bit
Bytes
Byte write
0
1
Start, device select, RW = 0
Page write
0
≤ 4 bytes
Start, device select, RW = 0
Figure 8.
Initial sequence
Write mode sequences with I2C_Write_Lock bit = 1 (data write inhibited)
ACK
Byte address
Start
Dev select
Data in
ACK
Byte address
ACK
Byte address
NO ACK
Data in 1
Data in 2
R/W
NO ACK
NO ACK
Data in N
Stop
Page Write
(cont'd)
Byte address
NO ACK
R/W
ACK
Page Write
ACK
Stop
Dev select
Start
Byte Write
ACK
AI15115
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I2C device operation
5.7
M24LR04E-R
Write operations
Following a Start condition, the bus master sends a device select code with the Read/Write
bit (RW) reset to 0. The device acknowledges this, as shown in Figure 8, and waits for two
address bytes. The device responds to each address byte with an acknowledge bit, and
then waits for the data byte.
Writing to the memory may be inhibited if the I2C_Write_Lock bit = 1. A Write instruction
issued with the I2C_Write_Lock bit = 1 and with no I2C_Password presented does not
modify the memory contents, and the accompanying data bytes are not acknowledged, as
shown in Figure 8.
Each data byte in the memory has a 16-bit (two byte wide) address. The most significant
byte (Table 3) is sent first, followed by the least significant byte (Table 4). Bits b15 to b0 form
the address of the byte in memory.
When the bus master generates a Stop condition immediately after the Ack bit (in the tenthbit time slot), either at the end of a byte write or a page write, the internal write cycle is
triggered. A Stop condition at any other time slot does not trigger the internal write cycle.
After the Stop condition, the delay tW, and the successful completion of a Write operation,
the device’s internal address counter is incremented automatically, to point to the next byte
address after the last one that was modified.
During the internal write cycle, the serial data (SDA) signal is disabled internally, and the
device does not respond to any requests.
5.8
Byte write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is write-protected by the I2C_Write_Lock bit (= 1), the device replies
with NoAck, and the location is not modified. If the addressed location is not write-protected,
the device replies with Ack. The bus master terminates the transfer by generating a Stop
condition, as shown in Figure 9.
5.9
Page write
The Page write mode allows up to four bytes to be written in a single write cycle, provided
that they are all located in the same “row” in the memory: that is, the most significant
memory address bits (b12-b2) are the same. If more bytes are sent than fit up to the end of
the row, a condition known as “roll-over” occurs. This should be avoided, as data starts to
become overwritten in an implementation-dependent way.
The bus master sends from one to four bytes of data, each of which is acknowledged by the
device if the I2C_Write_Lock bit = 0 or the I2C_Password was correctly presented. If the
I2C_Write_Lock_bit = 1 and the I2C_password are not presented, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck.
After each byte is transferred, the internal byte address counter (inside the page) is
incremented. The transfer is terminated by the bus master generating a Stop condition.
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M24LR04E-R
Figure 9.
Write mode sequences with I2C_Write_Lock bit = 0 (data write enabled)
ACK
Byte address
Data in
ACK
Byte address
ACK
Byte address
ACK
ACK
Data in 1
ACK
Data in N
Data in 2
Stop
Dev Select
Start
Byte address
ACK
R/W
ACK
Page Write
ACK
Stop
Dev Select
Start
Byte Write
ACK
R/W
AI15116
Figure 10. Write cycle polling flowchart using ACK
Write cycle
in progress
Start condition
Device select
with RW = 0
NO
First byte of instruction
with RW = 0 already
decoded by the device
ACK
Returned
YES
NO
Next
operation is
addressing the
memory
YES
Send address
and receive ACK
ReStart
Stop
NO
Start
condition
YES
Data for the
Write operation
Device select
with RW = 1
Continue the
Write operation
Continue the
Random Read operation
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I2C device operation
5.10
M24LR04E-R
Minimizing system delays by polling on ACK
During the internal write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum I²C write time (tw) is
shown in Table 122, but the typical time is shorter. To make use of this, a polling sequence
can be used by the bus master.
The sequence, as shown in Figure 10, is:
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1.
Initial condition: a write cycle is in progress.
2.
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
3.
Step 2: if the device is busy with the internal write cycle, no Ack is returned and the bus
master goes back to Step 1. If the device has terminated the internal write cycle, it
responds with an Ack, indicating that the device is ready to receive the second part of
the instruction (the first byte of this instruction having been sent during Step 1).
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I2C device operation
M24LR04E-R
Figure 11. Read mode sequences
ACK
Data out
Stop
Start
Dev select
NO ACK
R/W
ACK
Start
Dev select *
Byte address
Dev select *
ACK
ACK
Data out 1
ACK
NO ACK
Data out N
Byte address
ACK
Byte address
ACK
Dev select *
Start
Start
ACK
R/W
ACK
Data out
R/W
R/W
Dev select *
NO ACK
Stop
Start
Dev select
Sequential
Random
Read
ACK
Byte address
R/W
ACK
Sequential
Current
Read
ACK
Start
Random
Address
Read
ACK
Stop
Current
Address
Read
ACK
Data out 1
R/W
NO ACK
Stop
Data out N
AI01105d
1. The seven most significant bits of the device select code of a random read (in the first and fourth bytes)
must be identical.
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I2C device operation
5.11
M24LR04E-R
Read operations
Read operations are performed independently of the state of the I2C_Write_Lock bit.
After the successful completion of a read operation, the device’s internal address counter is
incremented by one, to point to the next byte address.
5.12
Random Address Read
A dummy write is first performed to load the address into this address counter (as shown in
Figure 11) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The
device acknowledges this, and outputs the contents of the addressed byte. The bus master
must not acknowledge the byte, and terminates the transfer with a Stop condition.
5.13
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges
this, and outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 11, without acknowledging the byte.
5.14
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 11.
The output data come from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter “rolls-over”, and the device continues to output data from memory
address 00h.
5.15
Acknowledge in Read mode
For all Read commands, the device waits, after each byte read, for an acknowledgment
during the ninth bit time. If the bus master does not drive Serial Data (SDA) low during this
time, the device terminates the data transfer and switches to its Standby mode.
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M24LR04E-R
M24LR04E-R I2C password security
5.16
The M24LR04E-R controls I2C sector write access using the 32-bit-long I2C password and
the 64-bit I2C_Write_Lock bit area. The I2C password value is managed using two I2C
commands: I2C present password and I2C write password.
5.16.1
I2C present password command description
The I2C present password command is used in I2C mode to present the password to the
M24LR04E-R in order to modify the write access rights of all the memory sectors protected
by the I2C_Write_Lock bits, including the password itself. If the presented password is
correct, the access rights remain activated until the M24LR04E-R is powered off or until a
new I2C present password command is issued.
Following a Start condition, the bus master sends a device select code with the Read/Write
bit (RW) reset to 0 and the Chip Enable bit E2 at 1. The device acknowledges this, as shown
in Figure 12, and waits for two I2C password address bytes 09h and 00h. The device
responds to each address byte with an acknowledge bit, and then waits for the four
password data bytes, the validation code, 09h, and a resend of the four password data
bytes. The most significant byte of the password is sent first, followed by the least significant
bytes.
It is necessary to send the 32-bit password twice to prevent any data corruption during the
sequence. If the two 32-bit passwords sent are not exactly the same, the M24LR04E-R does
not start the internal comparison.
When the bus master generates a Stop condition immediately after the Ack bit (during the
tenth bit time slot), an internal delay equivalent to the write cycle time is triggered. A Stop
condition at any other time does not trigger the internal delay. During that delay, the
M24LR04E-R compares the 32 received data bits with the 32 bits of the stored I2C
password. If the values match, the write access rights to all protected sectors are modified
after the internal delay. If the values do not match, the protected sectors remains protected.
During the internal delay, the serial data (SDA) signal is disabled internally, and the device
does not respond to any requests.
Figure 12. I2C present password command
Ack
Start
Device select
code
Ack
Password
address 09h
Ack
Password
address 00h
Ack
Password
[31:24]
Ack
Password
[23:16]
Ack
Password
[15:8]
Ack
Password
[7:0]
R/W
Ack
Validation
code 09h
Password
[31:24]
Ack
Password
[23:16]
Ack
Password
[15:8]
Ack
Password
[7:0]
Stop
Ack
Device select code = 1010 1 1 1
Ack generated during 9th bit time slot.
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I2C device operation
M24LR04E-R
I2C write password command description
5.16.2
The I2C write password command is used to write a 32-bit block into the M24LR04E-R I2C
password system area. This command is used in I2C mode to update the I2C password
value. It cannot be used to update any of the RF passwords. After the write cycle, the new
I2C password value is automatically activated. The I2C password value can only be modified
after issuing a valid I2C present password command.
On delivery, the I2C default password value is set to 0000 0000h and is activated.
Following a Start condition, the bus master sends a device select code with the Read/Write
bit (RW) reset to 0 and the Chip Enable bit E2 at 1. The device acknowledges this, as shown
in Figure 13, and waits for the two I2C password address bytes, 09h and 00h. The device
responds to each address byte with an acknowledge bit, and then waits for the four
password data bytes, the validation code, 07h, and a resend of the four password data
bytes. The most significant byte of the password is sent first, followed by the least significant
bytes.
It is necessary to send twice the 32-bit password to prevent any data corruption during the
write sequence. If the two 32-bit passwords sent are not exactly the same, the M24LR04E-R
does not modify the I2C password value.
When the bus master generates a Stop condition immediately after the Ack bit (during the
tenth bit time slot), the internal write cycle is triggered. A Stop condition at any other time
does not trigger the internal write cycle.
During the internal write cycle, the serial data (SDA) signal is disabled internally, and the
device does not respond to any requests.
Figure 13. I2C write password command
Ack
Start
Device select
code
Ack
Password
address 09h
Ack
Password
address 00h
Ack
New password
[31:24]
New password
[23:16]
Ack
New password
[15:8]
Ack
New password
[7:0]
R/W
Validation
code 07h
Ack
New password
[31:24]
Ack
New password
[23:16]
Ack
New password
[15:8]
Ack
New password
[7:0]
Stop
Ack
Device select code = 1010 1 1 1
Ack generated during 9th bit time slot.
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Ack
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6
M24LR04E-R memory initial state
M24LR04E-R memory initial state
The device is delivered with all bits set to 1 in the user memory array.
●
User Memory content : FFh
●
System bits delivery
●
I2C write lock bits 00h
●
Sector Security Status: 00h
●
I2C Password: 0000 0000 h
●
RF Password: 0000 0000 h
●
IC ref: 5Ah
●
UID: E0 02 xx xx xx xx h
●
DSFID: FFh
●
AFI: 00h
●
Memory size: 03 7Fh
●
Energy Harvesting Configuration byte: F4h
●
Bit 7 to bit 4: all set to 1
●
Bit 3: set to 0 (RF BUSY mode on RF WIP/BUSY pin)
●
Bit 2: set to 1 (Energy harvesting not activated by default)
●
Bit 1 and bit 0: set to 0 (fan-out setting)
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RF device operation
7
M24LR04E-R
RF device operation
The M24LR04E-R is divided into 4 sectors of 32 blocks of 32 bits, as shown in Table 5. Each
sector can be individually read- and/or write-protected using a specific lock or password
command.
Read and Write operations are possible if the addressed block is not protected. During a
Write, the 32 bits of the block are replaced by the new 32-bit value.
The M24LR04E-R also has a 64-bit block that is used to store the 64-bit unique identifier
(UID). The UID is compliant with the ISO 15963 description, and its value is used during the
anticollision sequence (Inventory). This block is not accessible by the user and its value is
written by ST on the production line.
The M24LR04E-R also includes an AFI register in which the application family identifier is
stored, and a DSFID register in which the data storage family identifier used in the
anticollision algorithm is stored.
The M24LR04E-R has three 32-bit blocks in which the password codes are stored and a 8bit Configuration byte in which the Energy harvesting mode and RF WIP/BUSY pin
configuration is stored.
7.1
RF communication and energy harvesting
Because current consumption can affect the AC signal delivered by the antenna, RF
communications with M24LR04E-R are not guaranteed during voltage delivery on the
energy harvesting analog output Vout.
RF communication can disturb and possibly stop Energy Harvesting mode.
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7.2
RF device operation
Commands
The M24LR04E-R supports the following commands:
●
Inventory, used to perform the anticollision sequence.
●
Stay quiet, used to put the M24LR04E-R in quiet mode, where it does not respond to
any inventory command.
●
Select, used to select the M24LR04E-R. After this command, the M24LR04E-R
processes all Read/Write commands with Select_flag set.
●
Reset to ready, used to put the M24LR04E-R in the ready state.
●
Read block, used to output the 32 bits of the selected block and its locking status.
●
Write block, used to write the 32-bit value in the selected block, provided that it is not
locked.
●
Read multiple blocks, used to read the selected blocks and send back their value.
●
Write AFI, used to write the 8-bit value in the AFI register.
●
Lock AFI, used to lock the AFI register.
●
Write DSFID, used to write the 8-bit value in the DSFID register.
●
Lock DSFID, used to lock the DSFID register.
●
Get system info, used to provide the system information value
●
Get multiple block security status, used to send the security status of the selected
block.
●
Initiate, used to trigger the tag response to the Inventory initiated sequence.
●
Inventory initiated, used to perform the anticollision sequence triggered by the Initiate
command.
●
Write-sector password, used to write the 32 bits of the selected password.
●
Lock-sector, used to write the sector security status bits of the selected sector.
●
Present-sector password, enables the user to present a password to unprotect the
user blocks linked to this password.
●
Fast initiate, used to trigger the tag response to the Inventory initiated sequence.
●
Fast inventory initiated, used to perform the anticollision sequence triggered by the
Initiate command.
●
Fast read single block, used to output the 32 bits of the selected block and its locking
status.
●
Fast read multiple blocks, used to read the selected blocks and send back their value.
●
ReadCfg, used to read the 8-bit Configuration byte and send back its value.
●
WriteEHCfg, used to write the energy harvesting configuration bits into the
Configuration byte.
●
WriteDOCfg, used to write the RF WIP/BUSY pin configuration bit into the
Configuration byte.
●
SetRstEHEn, used to set or reset the EH_enable bit into the volatile Control register.
●
CheckEHEn, used to send back the value of the volatile Control register.
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RF device operation
7.3
M24LR04E-R
Initial dialog for vicinity cards
The dialog between the vicinity coupling device or VCD (commonly the “RF reader”) and the
vicinity integrated circuit card or VICC (M24LR04E-R) takes place as follows:
●
activation of the M24LR04E-R by the RF operating field of the VCD,
●
transmission of a command by the VCD,
●
transmission of a response by the M24LR04E-R.
These operations use the RF power transfer and communication signal interface described
below (see Power transfer, Frequency and Operating field). This technique is called RTF
(Reader talk first).
7.3.1
Power transfer
Power is transferred to the M24LR04E-R by radio frequency at 13.56 MHz via coupling
antennas in the M24LR04E-R and the VCD. The RF operating field of the VCD is
transformed on the M24LR04E-R antenna to an AC voltage which is rectified, filtered and
internally regulated.
During communications, the amplitude modulation (ASK) on this received signal is
demodulated by the ASK demodulator.
7.3.2
Frequency
The ISO 15693 standard defines the carrier frequency (fC) of the operating field as
13.56 MHz ±7 kHz.
7.3.3
Operating field
The M24LR04E-R operates continuously between the minimum and maximum values of the
electromagnetic field H defined in Table 123. The VCD has to generate a field within these
limits.
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8
Communication signal from VCD to M24LR04E-R
Communication signal from VCD to M24LR04E-R
Communications between the VCD and the M24LR04E-R takes place using the modulation
principle of ASK (Amplitude shift keying). Two modulation indexes are used, 10% and 100%.
The M24LR04E-R decodes both. The VCD determines which index is used.
The modulation index is defined as [a – b]/[a + b], where a is the peak signal amplitude, and
b the minimum signal amplitude of the carrier frequency.
Depending on the choice made by the VCD, a “pause” is created as described in Figure 14
and Figure 15.
The M24LR04E-R is operational for the 100% modulation index or for any degree of
modulation index between 10% and 30% (see Table 123).
Figure 14. 100% modulation waveform
t1
t3
Carrier
Amplitude
t4
105%
a
95%
60%
t2
5%
t
b
t1
t2
t3
t4
Min (µs) Max (µs)
9,44
6,0
2,1
t1
0
4,5
0
0,8
The clock recovery shall be operational after t4 max.
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Communication signal from VCD to M24LR04E-R
Table 19.
M24LR04E-R
10% modulation parameters
Symbol
Parameter definition
Value
hr
0.1 x (a – b)
max
hf
0.1 x (a – b)
max
Figure 15. 10% modulation waveform
Carrier
Amplitude
t1
t2
t3
y
hf
a
b
hr
y
t
t1
t2
t3
Min
6,0 µs
3,0 µs
0
Max
9,44 µs
t1
4,5 µs
Modulation
Index
10%
30%
y
hf, hr
0,05 (a-b)
0,1 (a-b) max
The VICC shall be operational for any value of modulation index between 10 % and 30 %.
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9
Data rate and data coding
Data rate and data coding
The data coding implemented in the M24LR04E-R uses pulse position modulation. Both
data coding modes that are described in the ISO15693 are supported by the M24LR04E-R.
The selection is made by the VCD and indicated to the M24LR04E-R within the start of
frame (SOF).
9.1
Data coding mode: 1 out of 256
The value of one single byte is represented by the position of one pause. The position of the
pause on 1 of 256 successive time periods of 18.88 µs (256/fC) determines the value of the
byte. In this case, the transmission of one byte takes 4.833 ms and the resulting data rate is
1.65 Kbits/s (fC/8192).
Figure 16 illustrates this pulse position modulation technique. In this figure, data E1h (225
decimal) is sent by the VCD to the M24LR04E-R.
The pause occurs during the second half of the position of the time period that determines
the value, as shown in Figure 17.
A pause during the first period transmits the data value 00h. A pause during the last period
transmits the data value FFh (255 decimal).
Figure 16. 1 out of 256 coding mode
9.44 µs
Pulse
Modulated
Carrier
18.88 µs
0 1
2
3
. . . . . . . .
. . . . . . . . .
. . . . . . . . .
2
2
5
. . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . .
2
5
2
2
5
3
2
5
4
2
5
5
4.833 ms
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Data rate and data coding
M24LR04E-R
Figure 17. Detail of a time period
9.44 µs
18.88 µs
Pulse
Modulated
Carrier
.
.
.
.
.
.
.
.
2
2
4
2
2
5
.
.
.
.
.
2
2
6
Time Period
one of 256
9.2
.
AI06657
Data coding mode: 1 out of 4
The value of two bits is represented by the position of one pause. The position of the pause
on 1 of 4 successive time periods of 18.88 µs (256/fC) determines the value of the two bits.
Four successive pairs of bits form a byte, where the least significant pair of bits is
transmitted first.
In this case, the transmission of one byte takes 302.08 µs and the resulting data rate is
26.48 Kbits/s (fC/512). Figure 18 illustrates the 1 out of 4 pulse position technique and
coding. Figure 19 shows the transmission of E1h (225d - 1110 0001b) by the VCD.
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Data rate and data coding
Figure 18. 1 out of 4 coding mode
Pulse position for "00"
9.44 µs
9.44 µs
75.52 µs
Pulse position for "01" (1=LSB)
28.32 µs
9.44 µs
75.52 µs
Pulse position for "10" (0=LSB)
47.20µs
Pulse position for "11"
9.44 µs
75.52 µs
66.08 µs
9.44 µs
75.52 µs
AI06658
Figure 19. 1 out of 4 coding example
10
00
01
11
75.52µs
75.52µs
75.52µs
75.52µs
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Data rate and data coding
9.3
M24LR04E-R
VCD to M24LR04E-R frames
Frames are delimited by a start of frame (SOF) and an end of frame (EOF). They are
implemented using code violation. Unused options are reserved for future use.
The M24LR04E-R is ready to receive a new command frame from the VCD 311.5 µs (t2)
after sending a response frame to the VCD.
The M24LR04E-R takes a power-up time of 0.1 ms after being activated by the powering
field. After this delay, the M24LR04E-R is ready to receive a command frame from the VCD.
9.4
Start of frame (SOF)
The SOF defines the data coding mode the VCD is to use for the following command frame.
The SOF sequence described in Figure 20 selects the 1 out of 256 data coding mode. The
SOF sequence described in Figure 21 selects the 1 out of 4 data coding mode. The EOF
sequence for either coding mode is described in Figure 22.
Figure 20. SOF to select 1 out of 256 data coding mode
9.44µs
9.44µs
37.76µs
37.76µs
AI06661
Figure 21. SOF to select 1 out of 4 data coding mode
9.44µs
9.44µs
37.76µs
9.44µs
37.76µs
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Data rate and data coding
Figure 22. EOF for either data coding mode
9.44µs
9.44µs
37.76µs
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Communication signal from M24LR04E-R to VCD
10
M24LR04E-R
Communication signal from M24LR04E-R to VCD
The M24LR04E-R has several modes defined for some parameters, owing to which it can
operate in various noise environments and meet various application requirements.
10.1
Load modulation
The M24LR04E-R is capable of communication to the VCD via an inductive coupling area
whereby the carrier is loaded to generate a subcarrier with frequency fS. The subcarrier is
generated by switching a load in the M24LR04E-R.
The load-modulated amplitude received on the VCD antenna must be of at least 10 mV
when measured as described in the test methods defined in International Standard
ISO10373-7.
10.2
Subcarrier
The M24LR04E-R supports the one-subcarrier and two-subcarrier response formats. These
formats are selected by the VCD using the first bit in the protocol header. When one
subcarrier is used, the frequency fS1 of the subcarrier load modulation is 423.75 kHz (fC/32).
When two subcarriers are used, the frequency fS1 is 423.75 kHz (fC/32), and frequency fS2
is 484.28 kHz (fC/28). When using the two-subcarrier mode, the M24LR04E-R generates a
continuous phase relationship between fS1 and fS2.
10.3
Data rates
The M24LR04E-R can respond using the low or the high data rate format. The selection of
the data rate is made by the VCD using the second bit in the protocol header. For fast
commands, the selected data rate is multiplied by two. Table 20 shows the different data
rates produced by the M24LR04E-R using the different response format combinations.
Table 20.
Response data rates
Data rate
One subcarrier
Two subcarriers
Standard commands
6.62 Kbit/s (fc/2048)
6.67 Kbit/s (fc/2032)
Fast commands
13.24 Kbit/s (fc/1024)
not applicable
Standard commands
26.48 Kbit/s (fc/512)
26.69 Kbit/s (fc/508)
Fast commands
52.97 Kbit/s (fc/256)
not applicable
Low
High
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11
Bit representation and coding
Bit representation and coding
Data bits are encoded using Manchester coding, according to the following schemes. For
the low data rate, same subcarrier frequency or frequencies is/are used. In this case, the
number of pulses is multiplied by 4 and all times increase by this factor. For the Fast
commands using one subcarrier, all pulse numbers and times are divided by 2.
11.1
Bit coding using one subcarrier
11.1.1
High data rate
A logic 0 starts with eight pulses at 423.75 kHz (fC/32) followed by an unmodulated time of
18.88 µs, as shown in Figure 23.
Figure 23. Logic 0, high data rate
37.76µs
ai12076
For the fast commands, a logic 0 starts with four pulses at 423.75 kHz (fC/32) followed by an
unmodulated time of 9.44 µs, as shown in Figure 24.
Figure 24. Logic 0, high data rate, fast commands
18.88µs
ai12066
A logic 1 starts with an unmodulated time of 18.88 µs followed by eight pulses at 423.75 kHz
(fC/32), as shown in Figure 25.
Figure 25. Logic 1, high data rate
37.76µs
ai12077
For the Fast commands, a logic 1 starts with an unmodulated time of 9.44 µs followed by
four pulses of 423.75 kHz (fC/32), as shown in Figure 26.
Figure 26. Logic 1, high data rate, fast commands
18.88µs
ai12067
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Bit representation and coding
11.1.2
M24LR04E-R
Low data rate
A logic 0 starts with 32 pulses at 423.75 kHz (fC/32) followed by an unmodulated time of
75.52 µs, as shown in Figure 27.
Figure 27. Logic 0, low data rate
151.04µs
ai12068
For the Fast commands, a logic 0 starts with 16 pulses at 423.75 kHz (fC/32) followed by an
unmodulated time of 37.76 µs, as shown in Figure 28.
Figure 28. Logic 0, low data rate, fast commands
75.52µs
ai12069
A logic 1 starts with an unmodulated time of 75.52 µs followed by 32 pulses at 423.75 kHz
(fC/32), as shown in Figure 29.
Figure 29. Logic 1, low data rate
151.04µs
ai12070
For the Fast commands, a logic 1 starts with an unmodulated time of 37.76 µs followed by
16 pulses at 423.75 kHz (fC/32), as shown in Figure 30.
Figure 30. Logic 1, low data rate, fast commands
75.52µs
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ai12071
M24LR04E-R
Bit representation and coding
11.2
Bit coding using two subcarriers
11.2.1
High data rate
A logic 0 starts with eight pulses at 423.75 kHz (fC/32) followed by nine pulses at
484.28 kHz (fC/28), as shown in Figure 31. Bit coding using two subcarriers is not supported
for the Fast commands.
Figure 31. Logic 0, high data rate
37.46µs
ai12074
A logic 1 starts with nine pulses at 484.28 kHz (fC/28) followed by eight pulses at
423.75 kHz (fC/32), as shown in Figure 32. Bit coding using two subcarriers is not supported
for the Fast commands.
Figure 32. Logic 1, high data rate
37.46µs
11.2.2
ai12073
Low data rate
A logic 0 starts with 32 pulses at 423.75 kHz (fC/32) followed by 36 pulses at 484.28 kHz
(fC/28), as shown in Figure 33. Bit coding using two subcarriers is not supported for the Fast
commands.
Figure 33. Logic 0, low data rate
149.84µs
ai12072
A logic 1 starts with 36 pulses at 484.28 kHz (fC/28) followed by 32 pulses at 423.75 kHz
(fC/32) as shown in Figure 34. Bit coding using two subcarriers is not supported for the Fast
commands.
Figure 34. Logic 1, low data rate
149.84µs
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M24LR04E-R to VCD frames
12
M24LR04E-R
M24LR04E-R to VCD frames
Frames are delimited by an SOF and an EOF. They are implemented using code violation.
Unused options are reserved for future use. For the low data rate, the same subcarrier
frequency or frequencies is/are used. In this case, the number of pulses is multiplied by 4.
For the Fast commands using one subcarrier, all pulse numbers and times are divided by 2.
12.1
SOF when using one subcarrier
12.1.1
High data rate
The SOF includes an unmodulated time of 56.64 µs, followed by 24 pulses at 423.75 kHz
(fC/32), and a logic 1 that consists of an unmodulated time of 18.88 µs followed by eight
pulses at 423.75 kHz, as shown in Figure 35.
Figure 35. Start of frame, high data rate, one subcarrier
37.76µs
113.28µs
ai12078
For the Fast commands, the SOF comprises an unmodulated time of 28.32 µs, followed by
12 pulses at 423.75 kHz (fC/32), and a logic 1 that consists of an unmodulated time of
9.44 µs followed by four pulses at 423.75 kHz, as shown in Figure 36.
Figure 36. Start of frame, high data rate, one subcarrier, fast commands
56.64µs
18.88µs
ai12079
12.1.2
Low data rate
The SOF comprises an unmodulated time of 226.56 µs, followed by 96 pulses at 423.75 kHz
(fC/32), and a logic 1 that consists of an unmodulated time of 75.52 µs followed by 32 pulses
at 423.75 kHz, as shown in Figure 37.
Figure 37. Start of frame, low data rate, one subcarrier
453.12µs
151.04µs
ai12080
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M24LR04E-R to VCD frames
For the Fast commands, the SOF comprises an unmodulated time of 113.28 µs, followed by
48 pulses at 423.75 kHz (fC/32), and a logic 1 that includes an unmodulated time of 37.76 µs
followed by 16 pulses at 423.75 kHz, as shown in Figure 38.
Figure 38. Start of frame, low data rate, one subcarrier, fast commands
226.56µs
75.52µs
ai12081
12.2
SOF when using two subcarriers
12.2.1
High data rate
The SOF comprises 27 pulses at 484.28 kHz (fC/28), followed by 24 pulses at 423.75 kHz
(fC/32), and a logic 1 that includes nine pulses at 484.28 kHz followed by eight pulses at
423.75 kHz, as shown in Figure 39.
Bit coding using two subcarriers is not supported for the Fast commands.
Figure 39. Start of frame, high data rate, two subcarriers
112.39µs
12.2.2
37.46µs
ai12082
Low data rate
The SOF comprises 108 pulses at 484.28 kHz (fC/28), followed by 96 pulses at 423.75 kHz
(fC/32), and a logic 1 that includes 36 pulses at 484.28 kHz followed by 32 pulses at
423.75 kHz, as shown in Figure 40.
Bit coding using two subcarriers is not supported for the Fast commands.
Figure 40. Start of frame, low data rate, two subcarriers
449.56µs
149.84µs
ai12083
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M24LR04E-R to VCD frames
M24LR04E-R
12.3
EOF when using one subcarrier
12.3.1
High data rate
The EOF comprises a logic 0 that includes eight pulses at 423.75 kHz and an unmodulated
time of 18.88 µs, followed by 24 pulses at 423.75 kHz (fC/32), and by an unmodulated time
of 56.64 µs, as shown in Figure 41.
Figure 41. End of frame, high data rate, one subcarrier
37.76µs
113.28µs
ai12084
For the Fast commands, the EOF comprises a logic 0 that includes four pulses at
423.75 kHz and an unmodulated time of 9.44 µs, followed by 12 pulses at 423.75 kHz
(fC/32) and an unmodulated time of 37.76 µs, as shown in Figure 42.
Figure 42. End of frame, high data rate, one subcarrier, fast commands
18.88µs
56.64µs
ai12085
12.3.2
Low data rate
The EOF comprises a logic 0 that includes 32 pulses at 423.75 kHz and an unmodulated
time of 75.52 µs, followed by 96 pulses at 423.75 kHz (fC/32) and an unmodulated time of
226.56 µs, as shown in Figure 43.
Figure 43. End of frame, low data rate, one subcarrier
453.12µs
151.04µs
ai12086
For the Fast commands, the EOF comprises a logic 0 that includes 16 pulses at 423.75 kHz
and an unmodulated time of 37.76 µs, followed by 48 pulses at 423.75 kHz (fC/32) and an
unmodulated time of 113.28 µs, as shown in Figure 44.
Figure 44. End of frame, low data rate, one subcarrier, Fast commands
75.52µs
226.56µs
ai12087
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M24LR04E-R to VCD frames
12.4
EOF when using two subcarriers
12.4.1
High data rate
The EOF comprises a logic 0 that includes eight pulses at 423.75 kHz and nine pulses at
484.28 kHz, followed by 24 pulses at 423.75 kHz (fC/32) and 27 pulses at 484.28 kHz
(fC/28), as shown in Figure 45.
Bit coding using two subcarriers is not supported for the Fast commands.
Figure 45. End of frame, high data rate, two subcarriers
37.46µs
12.4.2
112.39µs
ai12088
Low data rate
The EOF comprises a logic 0 that includes 32 pulses at 423.75 kHz and 36 pulses at
484.28 kHz, followed by 96 pulses at 423.75 kHz (fC/32) and 108 pulses at 484.28 kHz
(fC/28), as shown in Figure 46.
Bit coding using two subcarriers is not supported for the Fast commands.
Figure 46. End of frame, low data rate, two subcarriers
149.84µs
449.56µs
ai12089
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Unique identifier (UID)
13
M24LR04E-R
Unique identifier (UID)
The M24LR04E-R is uniquely identified by a 64-bit unique identifier (UID). This UID
complies with ISO/IEC 15963 and ISO/IEC 7816-6. The UID is a read-only code and
comprises:
●
eight MSBs with a value of E0h,
●
the IC manufacturer code “ST 02h” on 8 bits (ISO/IEC 7816-6/AM1),
●
a unique serial number on 48 bits.
Table 21.
UID format
MSB
63
LSB
56 55
0xE0
48
47
0x02
0
Unique serial number
With the UID, each M24LR04E-R can be addressed uniquely and individually during the
anticollision loop and for one-to-one exchanges between a VCD and an M24LR04E-R.
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M24LR04E-R
14
Application family identifier (AFI)
Application family identifier (AFI)
The AFI (application family identifier) represents the type of application targeted by the VCD
and is used to identify, among all the M24LR04E-Rs present, only the M24LR04E-Rs that
meet the required application criteria.
Figure 47. M24LR04E-R decision tree for AFI
Inventory request
received
No
AFI flag
set ?
Yes
AFI value
=0?
No
Yes
AFI value
= Internal
value ?
No
Yes
Answer given by the M24RF64
to the Inventory request
No answer
AI15130
The AFI is programmed by the M24LR04E-R issuer (or purchaser) in the AFI register. Once
programmed and locked, it can no longer be modified.
The most significant nibble of the AFI is used to code one specific or all application families.
The least significant nibble of the AFI is used to code one specific or all application
subfamilies. Subfamily codes different from 0 are proprietary.
(See ISO 15693-3 documentation.)
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Data storage format identifier (DSFID)
15
M24LR04E-R
Data storage format identifier (DSFID)
The data storage format identifier indicates how the data is structured in the M24LR04E-R
memory. The logical organization of data can be known instantly using the DSFID. It can be
programmed and locked using the Write DSFID and Lock DSFID commands.
15.1
CRC
The CRC used in the M24LR04E-R is calculated as per the definition in ISO/IEC 13239. The
initial register contents are all ones: “FFFF”.
The two-byte CRC is appended to each request and response, within each frame, before
the EOF. The CRC is calculated on all the bytes after the SOF up to the CRC field.
Upon reception of a request from the VCD, the M24LR04E-R verifies that the CRC value is
valid. If it is invalid, the M24LR04E-R discards the frame and does not answer to the VCD.
Upon reception of a response from the M24LR04E-R, it is recommended that the VCD
verifies whether the CRC value is valid. If it is invalid, actions to be performed are left to the
discretion of the VCD designer.
The CRC is transmitted least significant byte first. Each byte is transmitted least significant
bit first.
Table 22.
CRC transmission rules
LSByte
MSByte
LSBit MSBit
LSBit MSBit
CRC 16 (8 bits)
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M24LR04E-R
16
M24LR04E-R protocol description
M24LR04E-R protocol description
The transmission protocol (or simply “the protocol”) defines the mechanism used to
exchange instructions and data between the VCD and the M24LR04E-R in both directions.
It is based on the concept of “VCD talks first”.
This means that an M24LR04E-R does not start transmitting unless it has received and
properly decoded an instruction sent by the VCD. The protocol is based on an exchange of:
●
a request from the VCD to the M24LR04E-R,
●
a response from the M24LR04E-R to the VCD.
Each request and each response are contained in a frame. The frame delimiters (SOF,
EOF) are described in Section 12: M24LR04E-R to VCD frames.
Each request consists of:
●
a request SOF (see Figure 20 and Figure 21),
●
flags,
●
a command code,
●
parameters depending on the command,
●
application data,
●
a 2-byte CRC,
●
a request EOF (see Figure 22).
Each response consists of:
●
an answer SOF (see Figure 35 to Figure 40),
●
flags,
●
parameters depending on the command,
●
application data,
●
a 2-byte CRC,
●
an answer EOF (see Figure 41 to Figure 46).
The protocol is bit-oriented. The number of bits transmitted in a frame is a multiple of eight
(8), that is an integer number of bytes.
A single-byte field is transmitted least significant bit (LSBit) first. A multiple-byte field is
transmitted least significant byte (LSByte) first and each byte is transmitted least significant
bit (LSBit) first.
The setting of the flags indicates the presence of the optional fields. When the flag is set (to
one), the field is present. When the flag is reset (to zero), the field is absent.
Table 23.
VCD request frame format
Request SOF Request_flags
Table 24.
Response
SOF
Command
code
Parameters
Data
2-byte CRC
Request
EOF
M24LR04E-R Response frame format
Response_flags
Parameters
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Data
2-byte CRC
Response
EOF
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M24LR04E-R protocol description
M24LR04E-R
Figure 48. M24LR04E-R protocol timing
VCD
Request
frame
(Table 23)
Request
frame
(Table 23)
Response
frame
(Table 24)
M24LR04
E-R
Timing
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<-t1->
Response
frame
(Table 24)
<-t2->
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<-t1->
<-t2->
M24LR04E-R
17
M24LR04E-R states
M24LR04E-R states
An M24LR04E-R can be in one of four states:
●
Power-off
●
Ready
●
Quiet
●
Selected
Transitions between these states are specified in Figure 49 and Table 25.
17.1
Power-off state
The M24LR04E-R is in the Power-off state when it does not receive enough energy from the
VCD.
17.2
Ready state
The M24LR04E-R is in the Ready state when it receives enough energy from the VCD.
When in the Ready state, the M24LR04E-R answers any request where the Select_flag is
not set.
17.3
Quiet state
When in the Quiet state, the M24LR04E-R answers any request except for Inventory
requests with the Address_flag set.
17.4
Selected state
In the Selected state, the M24LR04E-R answers any request in all modes (see Section 18):
●
Request in Select mode with the Select_flag set
●
Request in Addressed mode if the UID matches
●
Request in Non-Addressed mode as it is the mode for general requests
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M24LR04E-R states
Table 25.
M24LR04E-R
M24LR04E-R response depending on Request_flags
Address_flag
Flags
1
Addressed
0
Non addressed
M24LR04E-R in Ready or
Selected state (Devices in Quiet
state do not answer)
X
M24LR04E-R in Selected state
X
M24LR04E-R in Ready, Quiet or
Selected state (the device which
matches the UID)
X
Error (03h)
X
Select_flag
1
Selected
0
Non selected
X
X
X
X
Figure 49. M24LR04E-R state transition diagram
Power-off
In field
Out of field
after tRF_OFF
Any other Command
where Select_Flag
is not set
Ready
(U
iet
qu
ay
St
y
ad
re
o
tt
se
Re
Out of RF field
after tRF_OFF
e
er r
)
ID
wh o
y et D)
(U
ad s UI
ct
le
re is t
o ag en
Se
t t Fl er
se ct_ diff
Re ele ect(
S el
S
ID
)
Out of RF field
after tRF_OFF
Select (UID)
Quiet
Stay quiet(UID)
Any other command where the
Address_Flag is set AND
where Inventory_Flag is not set
Selected
Any other command
AI06681b
1. The M24LR04E-R returns to the Power Off state if the tag is out of the RF field for at least tRF_OFF. Please
refer to application note AN4125 for more information.
2. The intention of the state transition method is that only one M24LR04E-R should be in the Selected state at
a time.
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18
Modes
Modes
The term “mode” refers to the mechanism used in a request to specify the set of
M24LR04E-Rs that answers the request.
18.1
Addressed mode
When the Address_flag is set to 1 (Addressed mode), the request contains the Unique ID
(UID) of the addressed M24LR04E-R.
Any M24LR04E-R that receives a request with the Address_flag set to 1 compares the
received Unique ID to its own. If it matches, then the M24LR04E-R executes the request (if
possible) and returns a response to the VCD as specified in the command description.
If the UID does not match, then it remains silent.
18.2
Non-addressed mode (general request)
When the Address_flag is cleared to 0 (Non-Addressed mode), the request does not contain
a Unique ID. Any M24LR04E-R receiving a request with the Address_flag cleared to 0
executes it and returns a response to the VCD as specified in the command description.
18.3
Select mode
When the Select_flag is set to 1 (Select mode), the request does not contain an M24LR04ER Unique ID. The M24LR04E-R in the Selected state that receives a request with the
Select_flag set to 1 executes it and returns a response to the VCD as specified in the
command description.
Only M24LR04E-Rs in the Selected state answer a request where the Select_flag set to 1.
The system design ensures in theory that only one M24LR04E-R can be in the Select state
at a time.
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Request format
19
M24LR04E-R
Request format
The request consists of:
●
an SOF,
●
flags,
●
a command code,
●
parameters and data,
●
a CRC,
●
an EOF.
Table 26.
S
O
F
19.1
General request format
Request_flags
Command code
Parameters
Data
CRC
E
O
F
Request flags
In a request, the “flags” field specifies the actions to be performed by the M24LR04E-R and
whether corresponding fields are present or not.
The flags field consists of eight bits. Bit 3 (Inventory_flag) of the request flag defines the
contents of the four MSBs (bits 5 to 8). When bit 3 is reset (0), bits 5 to 8 define the
M24LR04E-R selection criteria. When bit 3 is set (1), bits 5 to 8 define the M24LR04E-R
Inventory parameters.
Table 27.
Bit No
Bit 1
Bit 2
Definition of request flags 1 to 4
Flag
Subcarrier_flag
Level
(1)
Data_rate_flag(2)
Bit 3
Inventory_flag
Bit 4
Protocol_extension_flag(3)
Description
0
A single subcarrier frequency is used by the
M24LR04E-R
1
Two subcarrier are used by the M24LR04E-R
0
Low data rate is used
1
High data rate is used
0
The meaning of flags 5 to 8 is described in Table 28
1
The meaning of flags 5 to 8 is described in Table 29
0
No Protocol format extension
1. Subcarrier_flag refers to the M24LR04E-R-to-VCD communication.
2. Data_rate_flag refers to the M24LR04E-R-to-VCD communication.
3. Protocol_extension_flag must always be set to 0.
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Request format
.
Table 28.
Request flags 5 to 8 when Bit 3 = 0
Bit No
Flag
Bit 5
Select flag(1)
Bit 6
Level
Description
0
Request is executed by any M24LR04E-R according to the setting
of Address_flag
1
Request is executed only by the M24LR04E-R in Selected state
0
Request is not addressed. UID field is not present. The request is
executed by all M24LR04E-Rs.
1
Request is addressed. UID field is present. The request is
executed only by the M24LR04E-R whose UID matches the UID
specified in the request.
0
Option not activated.
1
Option activated.
Address flag(1)
Bit 7
Bit 8
Option flag
RFU
0
1. If the Select_flag is set to 1, the Address_flag is set to 0 and the UID field is not present in the request.
Table 29.
Request flags 5 to 8 when Bit 3 = 1
Bit No
Flag
Bit 5
AFI flag
Bit 6
Level
Description
0
AFI field is not present
1
AFI field is present
0
16 slots
1
1 slot
Nb_slots flag
Bit 7
Option flag
0
Bit 8
RFU
0
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Response format
20
M24LR04E-R
Response format
The response consists of:
●
an SOF,
●
flags,
●
parameters and data,
●
a CRC,
●
an EOF.
Table 30.
S
O
F
20.1
General response format
Response_flags
Parameters
Data
CRC
E
O
F
Response flags
In a response, the flags indicate how actions have been performed by the M24LR04E-R and
whether corresponding fields are present or not. The response flags consist of eight bits.
Table 31.
Definitions of response flags 1 to 8
Bit No
Bit 1
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Flag
Level
Description
0
No error
1
Error detected. Error code is in the “Error” field.
Error_flag
Bit 2
RFU
0
Bit 3
RFU
0
Bit 4
Extension flag
0
Bit 5
RFU
0
Bit 6
RFU
0
Bit 7
RFU
0
Bit 8
RFU
0
No extension
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M24LR04E-R
20.2
Response format
Response error code
If the Error_flag is set by the M24LR04E-R in the response, the Error code field is present
and provides information about the error that occurred.
Error codes not specified in Table 32 are reserved for future use.
Table 32.
Response error code definition
Error code
Meaning
03h
The option is not supported.
0Fh
Error with no information given.
10h
The specified block is not available.
11h
The specified block is already locked and thus cannot be locked again.
12h
The specified block is locked and its contents cannot be changed.
13h
The specified block was not successfully programmed.
14h
The specified block was not successfully locked.
15h
The specified block is read-protected.
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Anticollision
21
M24LR04E-R
Anticollision
The purpose of the anticollision sequence is to inventory the M24LR04E-Rs present in the
VCD field using their unique ID (UID).
The VCD is the master of communications with one or several M24LR04E-Rs. It initiates
M24LR04E-R communication by issuing the Inventory request.
The M24LR04E-R sends its response in the determined slot or does not respond.
21.1
Request parameters
When issuing the Inventory Command, the VCD:
●
sets the Nb_slots_flag as desired,
●
adds the mask length and the mask value after the command field.
●
The mask length is the number of significant bits of the mask value.
●
The mask value is contained in an integer number of bytes. The mask length indicates
the number of significant bits. LSB is transmitted first.
●
If the mask length is not a multiple of 8 (bits), as many 0-bits as required are added to
the mask value MSB so that the mask value is contained in an integer number of bytes.
●
The next field starts at the next byte boundary.
Table 33.
Inventory request format
MSB
SOF
LSB
Request_
Command
flags
8 bits
8 bits
Optional
AFI
Mask
length
Mask value
CRC
8 bits
8 bits
0 to 8 bytes
16 bits
EOF
In the example provided in Table 34 and Figure 50, the mask length is 11 bits. Five 0-bits are
added to the mask value MSB. The 11-bit mask and the current slot number are compared
to the UID.
Table 34.
72/142
Example of the addition of 0-bits to an 11-bit mask value
(b15) MSB
LSB (b0)
0000 0
100 1100 1111
0-bits added
11-bit mask value
Doc ID 022208 Rev 5
M24LR04E-R
Anticollision
Figure 50. Principle of comparison between the mask, the slot number and the UID
MSB
LSB
0000 0100 1100 1111 b 16 bits
Mask value received in the Inventory command
MSB
LSB
100 1100 1111 b 11 bits
The Mask value less the padding 0s is loaded
into the Tag comparator
MSB LSB
xxxx
The Slot counter is calculated
Nb_slots_flags = 0 (16 slots), Slot Counter is 4 bits
The Slot counter is concatened to the Mask value
Nb_slots_flags = 0
The concatenated result is compared with
the least significant bits of the Tag UID.
4 bits
MSB
LSB
xxxx 100 1100 1111 b 15 bits
UID
b63
b0
xxxx xxxx ..... xxxx xxxx x xxx xxxx xxxx xxxx b
Bits ignored
64 bits
Compare
AI06682
The AFI field is present if the AFI_flag is set.
The pulse is generated according to the definition of the EOF in ISO/IEC 15693-2.
The first slot starts immediately after the request EOF is received. To switch to the next slot,
the VCD sends an EOF.
The following rules and restrictions apply:
●
If no M24LR04E-R answer is detected, the VCD may switch to the next slot by sending
an EOF.
●
If one or more M24LR04E-R answers are detected, the VCD waits until the complete
frame has been received before sending an EOF for switching to the next slot.
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Request processing by the M24LR04E-R
22
M24LR04E-R
Request processing by the M24LR04E-R
Upon reception of a valid request, the M24LR04E-R performs the following algorithm:
●
NbS is the total number of slots (1 or 16)
●
SN is the current slot number (0 to 15)
●
LSB (value, n) function returns the n Less Significant Bits of value
●
MSB (value, n) function returns the n Most Significant Bits of value
●
“&” is the concatenation operator
●
Slot_Frame is either an SOF or an EOF
SN = 0
if (Nb_slots_flag)
then NbS = 1
SN_length = 0
endif
else NbS = 16
SN_length = 4
endif
label1:
if LSB(UID, SN_length + Mask_length) =
LSB(SN,SN_length)&LSB(Mask,Mask_length)
then answer to inventory request
endif
wait (Slot_Frame)
if Slot_Frame = SOF
then Stop Anticollision
decode/process request
exit
endif
if Slot_Frame = EOF
if SN < NbS-1
then SN = SN + 1
goto label1
exit
endif
endif
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M24LR04E-R
23
Explanation of the possible cases
Explanation of the possible cases
Figure 51 summarizes the main possible cases that can occur during an anticollision
sequence when the number of slots is 16.
The sequence of steps is as follows:
Note:
●
The VCD sends an Inventory request, in a frame terminated by an EOF. The number of
slots is 16.
●
M24LR04E-R_1 transmits its response in Slot 0. It is the only one to do so, therefore no
collision occurs and its UID is received and registered by the VCD.
●
The VCD sends an EOF in order to switch to the next slot.
●
In Slot 1, two M24LR04E-Rs, M24LR04E-R_2 and M24LR04E-R_3 transmit a
response, thus generating a collision. The VCD records the event and registers that a
collision was detected in Slot 1.
●
The VCD sends an EOF in order to switch to the next slot.
●
In Slot 2, no M24LR04E-R transmits a response. Therefore the VCD does not detect
any M24LR04E-R SOF and switches to the next slot by sending an EOF.
●
In Slot 3, another collision occurs due to responses from M24LR04E-R_4 and
M24LR04E-R_5.
●
The VCD sends a request (for instance a Read Block) to M24LR04E-R_1 whose UID
has already been correctly received.
●
All M24LR04E-Rs detect an SOF and exit the anticollision sequence. They process this
request and since the request is addressed to M24LR04E-R_1, only M24LR04E-R_1
transmits a response.
●
All M24LR04E-Rs are ready to receive another request. If it is an Inventory command,
the slot numbering sequence restarts from 0.
The decision to interrupt the anticollision sequence is made by the VCD. It could have
continued to send EOFs until Slot 16 and only then sent the request to M24LR04E-R_1.
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SOF
Inventory
EOF
Request
Slot 2
EOF
EOF
Slot 3
EOF
SOF
Response
2
Request to
EOF
M24RF64_1
Response
4
Response
from
M24RF64_1
M24RF64s
Response
1
Timing
Comment
t1
Response
3
t2
No
collision
t1
Response
5
t2
Collision
t3
No
Response
t1
t2
t1
Collision
Figure 51. Description of a possible anticollision sequence
Doc ID 022208 Rev 5
VCD
Slot 1
Explanation of the possible cases
76/142
Slot 0
Time
AI15117
M24LR04E-R
M24LR04E-R
24
Inventory Initiated command
Inventory Initiated command
The M24LR04E-R provides a special feature to improve the inventory time response of
moving tags using the Initiate_flag value. This flag, controlled by the Initiate command,
allows tags to answer to Inventory Initiated commands.
For applications in which multiple tags are moving in front of a reader, it is possible to miss
tags using the standard inventory command. The reason is that the inventory sequence has
to be performed on a global tree search. For example, a tag with a particular UID value may
have to wait the run of a long tree search before being inventoried. If the delay is too long,
the tag may be out of the field before it has been detected.
Using the Initiate command, the inventory sequence is optimized. When multiple tags are
moving in front of a reader, the ones which are within the reader field are initiated by the
Initiate command. In this case, a small batch of tags answers to the Inventory Initiated
command, which optimizes the time necessary to identify all the tags. When finished, the
reader has to issue a new Initiate command in order to initiate a new small batch of tags
which are new inside the reader field.
It is also possible to reduce the inventory sequence time using the Fast Initiate and Fast
Inventory Initiated commands. These commands allow the M24LR04E-Rs to increase their
response data rate by a factor of 2, up to 53 Kbit/s.
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Timing definition
M24LR04E-R
25
Timing definition
25.1
t1: M24LR04E-R response delay
Upon detection of the rising edge of the EOF received from the VCD, the M24LR04E-R
waits for a time t1nom before transmitting its response to a VCD request or switching to the
next slot during an inventory process. Values of t1 are given in Table 35. The EOF is defined
in Figure 22.
25.2
t2: VCD new request delay
t2 is the time after which the VCD may send an EOF to switch to the next slot when one or
more M24LR04E-R responses have been received during an Inventory command. It starts
from the reception of the EOF from the M24LR04E-Rs.
The EOF sent by the VCD may be either 10% or 100% modulated regardless of the
modulation index used for transmitting the VCD request to the M24LR04E-R.
t2 is also the time after which the VCD may send a new request to the M24LR04E-R, as
described in Figure 48.
Values of t2 are given in Table 35.
25.3
t3: VCD new request delay when no response is received
from the M24LR04E-R
t3 is the time after which the VCD may send an EOF to switch to the next slot when no
M24LR04E-R response has been received.
The EOF sent by the VCD may be either 10% or 100% modulated regardless of the
modulation index used for transmitting the VCD request to the M24LR04E-R.
From the time the VCD has generated the rising edge of an EOF:
●
If this EOF is 100% modulated, the VCD waits for a time at least equal to t3min before
sending a new EOF.
●
If this EOF is 10% modulated, the VCD waits for a time at least equal to the sum of t3min
+ the M24LR04E-R nominal response time (which depends on the M24LR04E-R data
rate and subcarrier modulation mode) before sending a new EOF.
Table 35.
Timing values(1)
Minimum (min) values
Nominal (nom) values
Maximum (max) values
t1
318.6 µs
320.9 µs
323.3 µs
t2
309.2 µs
No tnom
No tmax
No tnom
No tmax
t3
t1max
(2)
+
tSOF(3)
1. The tolerance of specific timings is ± 32/fC.
2. t1max does not apply for write-alike requests. Timing conditions for write-alike requests are defined in the
command description.
3. tSOF is the time taken by the M24LR04E-R to transmit an SOF to the VCD. tSOF depends on the current
data rate: High data rate or Low data rate.
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M24LR04E-R
26
Command codes
Command codes
The M24LR04E-R supports the commands described in this section. Their codes are given
in Table 36.
Table 36.
Command codes
Command code
standard
Function
Command code
custom
Function
01h
Inventory
2Ch
Get Multiple Block Security
Status
02h
Stay Quiet
B1h
Write-sector Password
20h
Read Single Block
B2h
Lock-sector
21h
Write Single Block
B3h
Present-sector Password
23h
Read Multiple Block
C0h
Fast Read Single Block
25h
Select
C1h
Fast Inventory Initiated
26h
Reset to Ready
C2h
Fast Initiate
27h
Write AFI
C3h
Fast Read Multiple Block
28h
Lock AFI
D1h
Inventory Initiated
29h
Write DSFID
D2h
Initiate
2Ah
Lock DSFID
A0h
ReadCfg
2Bh
Get System Info
A1h
WriteEHCfg
A2h
SetRstEHEn
A3h
CheckEHEn
A4h
WriteDOCfg
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Command codes
26.1
M24LR04E-R
Inventory
When receiving the Inventory request, the M24LR04E-R runs the anticollision sequence.
The Inventory_flag is set to 1. The meaning of flags 5 to 8 is shown in Table 29.
The request contains:
●
the flags,
●
the Inventory command code (see Table 36),
●
the AFI if the AFI flag is set,
●
the mask length,
●
the mask value,
●
the CRC.
The M24LR04E-R does not generate any answer in case of error.
Table 37.
Inventory request format
Request
Request_flags Inventory
SOF
Optional
AFI
Mask
length
Mask
value
CRC16
8 bits
8 bits
8 bits
0 - 64 bits
16 bits
01h
Request
EOF
The response contains:
●
the flags,
●
the Unique ID.
Table 38.
Inventory response format
Response Response_
SOF
flags
8 bits
DSFID
UID
CRC16
8 bits
64 bits
16 bits
Response
EOF
During an Inventory process, if the VCD does not receive an RF M24LR04E-R response, it
waits for a time t3 before sending an EOF to switch to the next slot. t3 starts from the rising
edge of the request EOF sent by the VCD.
●
If the VCD sends a 100% modulated EOF, the minimum value of t3 is:
t3min = 4384/fC (323.3µs) + tSOF
●
If the VCD sends a 10% modulated EOF, the minimum value of t3 is:
t3min = 4384/fC (323.3µs) + tNRT
where:
●
tSOF is the time required by the M24LR04E-R to transmit an SOF to the VCD,
●
tNRT is the nominal response time of the M24LR04E-R.
tNRT and tSOF are dependent on the M24LR04E-R-to-VCD data rate and subcarrier
modulation mode.
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF
starting the inventory command to the end of the M24LR04E-R response. If the M24LR04ER does not receive the corresponding slot marker, the RF WIP/BUSY pin remains at 0 until
the next RF power-off.
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M24LR04E-R
Command codes
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
Figure 52. M24LR04E RF-Busy management following Inventory command
1) M24LR04E replies in slot n. RF_Busy is released after M24LR04E response.
Slot 1
S Inventory E
O
O
F command F
Slot n
E
O
F
E
O
F
E
O
F
S
E
Ireply
O
O
M24LR04E
F
F
RF_Busy
2) Slot n never occurs. RF_Busy is only released by Power-off.
Slot 1
S Inventory E
O
O
F command F
Slot n
E
O
F
Power-off
E
O
F
RF_Busy
3) VCD sends a Valid command before slot n. RF_Busy is released after M24LR04E
response.
Slot 1
S Inventory E
O
O
F command F
E
O
F
S
E
INew
O
O
command
F
F
S
E
Ireply
O
O
F M24LR04E F
RF_Busy
4) VCD sends a Bad command (unknown command code, false CRC...) before
slot n. RF_Busy is released after VCD command.
Slot 1
S Inventory E
O
O
F command F
E
O
F
S
E
IBad
O
O
F command F
RF_Busy
MS19767V2
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Command codes
26.2
M24LR04E-R
Stay Quiet
Command code = 0x02
On receiving the Stay Quiet command, the M24LR04E-R enters the Quiet State if no error
occurs, and does NOT send back a response. There is NO response to the Stay Quiet
command even if an error occurs.
When in the Quiet state:
●
the M24LR04E-R does not process any request if the Inventory_flag is set,
●
the M24LR04E-R processes any Addressed request.
The M24LR04E-R exits the Quiet State when:
●
it is reset (power off),
●
receiving a Select request. It then goes to the Selected state,
●
receiving a Reset to Ready request. It then goes to the Ready state.
Table 39.
Request
SOF
Stay Quiet request format
Request flags
Stay Quiet
UID
CRC16
8 bits
02h
64 bits
16 bits
Request
EOF
The Stay Quiet command must always be executed in Addressed mode (Select_flag is reset
to 0 and Address_flag is set to 1).
Figure 53. Stay Quiet frame exchange between VCD and M24LR04E-R
VCD
SOF
Stay Quiet
request
EOF
M24LR04E-R
Timing
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 during the Stay
Quiet command.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
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M24LR04E-R
26.3
Command codes
Read Single Block
On receiving the Read Single Block command, the M24LR04E-R reads the requested block
and sends back its 32-bit value in the response. The Protocol_extension_flag should be set
to 0 for the M24LR04E-R to operate correctly.
Table 40.
Read Single Block request format
Request Request_ Read Single
SOF
flags
Block
8 bits
20h
UID(1)
Block
number
CRC16
64 bits
8 bits
16 bits
Request
EOF
1. Gray means that the field is optional.
Request parameters:
●
Request flags
●
UID (optional)
●
Block number
Table 41.
Read Single Block response format when Error_flag is NOT set
Response
SOF
Response_flags
Sector
security
status(1)
Data
CRC16
8 bits
8 bits
32 bits
16 bits
Response
EOF
1. Gray means that the field is optional.
Response parameters:
●
Sector security status if Option_flag is set (see Table 42)
●
Four bytes of block data
Table 42.
b7
Sector security status
b6
b5
Reserved for future
use. All at 0.
Table 43.
b4
b3
Password
control bits
b2
b1
Read / Write
protection bits
b0
0: Current sector not locked
1: Current sector locked
Read Single Block response format when Error_flag is set
Response
SOF
Response_
flags
Error code
CRC16
8 bits
8 bits
16 bits
Response
EOF
Response parameter:
●
Error code as Error_flag is set
–
10h: the specified block is not available
–
15h: the specified block is read-protected
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Command codes
M24LR04E-R
Figure 54. Read Single Block frame exchange between VCD and M24LR04E-R
VCD
Read Single Block
request
SOF
EOF
M24LR04E-R
<-t1-> SOF
Read Single Block
response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Read Single Block command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
26.4
Write Single Block
On receiving the Write Single Block command, the M24LR04E-R writes the data contained
in the request to the requested block and reports whether the write operation was
successful in the response. The Protocol_extension_flag should be set to 0 for the
M24LR04E-R to operate correctly.
During the RF write cycle Wt, there should be no modulation (neither 100% nor 10%),
otherwise, the M24LR04E-R may not program correctly the data into the memory. The Wt
time is equal to t1nom + 18 × 302 µs.
Table 44.
Write Single Block request format
Request Request_
SOF
flags
Write
Single
Block
UID(1)
Block
number
Data
CRC16
21h
64 bits
8 bits
32 bits
16 bits
8 bits
Request
EOF
1. Gray means that the field is optional.
Request parameters:
●
Request flags
●
UID (optional)
●
Block number
●
Data
Table 45.
Write Single Block response format when Error_flag is NOT set
Response SOF
Response_flags
CRC16
8 bits
16 bits
Response parameter:
●
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No parameter. The response is send back after the writing cycle.
Doc ID 022208 Rev 5
Response EOF
M24LR04E-R
Command codes
Table 46.
Write Single Block response format when Error_flag is set
Response
SOF
Response_
flags
Error code
CRC16
8 bits
8 bits
16 bits
Response
EOF
Response parameter:
●
Error code as Error_flag is set:
–
0Fh: error with no information given
–
10h: the specified block is not available
–
12h: the specified block is locked and its contents cannot be changed
–
13h: the specified block was not successfully programmed
Figure 55. Write Single Block frame exchange between VCD and M24LR04E-R
VCD
SOF
Write Single
Block request
EOF
Write Single
Block response
M24LR04ER
<-t1-> SOF
M24LR04ER
<------------------- Wt ---------------> SOF
EOF
Write sequence when
error
Write Single
Block response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Write Single Block command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the
duration of the internal write cycle (from the end of a valid write single block command to the
beginning of the M24LR04E-R response).
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Command codes
M24LR04E-R
Figure 56. M24LR04E RF-Busy management following Write command
1) M24LR04E replies. RF_Busy is released after M24LR04E response.
Wt
S
E
Write
O
O
F command F
S
E
Ireply
O
O
F M24LR04E F
RF_Busy
2) M24LR04E replies when option flag is set. RF_Busy is released after M24LR04E
response.
Wt
S
E
Write
O
O
command
F
F
E
O
F
t1
S
E
Ireply
O
O
M24LR04E
F
F
RF_Busy
3) VCD sends a forbidden Write (sector lock, password-protected). RF_Busy is
released after M24LR04E command.
S
E
Write
O
O
command
F
F
t1
S
E
Ireply
O
O
M24LR04E
F
F
RF_Busy
MS19768V2
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M24LR04E-R
Command codes
When configuring in the RF Write in progress mode, the RF WIP/BUSY pin is tied to 0
during the Write & verify sequence, as shown in Figure 57.
Figure 57. M24LR04E RF-Wip management following Write command
1) M24LR04E replies. RF_Wip is released after M24LR04E response.
Wt
S
E
Write
O
O
F command F
S
E
Ireply
O
O
F M24LR04E F
RF_Wip
2) M24LR04E replies when option flag is set. RF_Wip is released after M24LR04E
response.
Wt
S
E
Write
O
O
command
F
F
E
O
F
t1
S
E
Ireply
O
O
M24LR04E
F
F
RF_Wip
3) VCD sends a forbidden Write (sector lock, password-protected). RF_Wip remains
at a high impedance.
S
E
Write
O
O
F command F
t1
S
E
Ireply
O
O
M24LR04E
F
F
RF_Wip
MS19769V2
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Command codes
26.5
M24LR04E-R
Read Multiple Block
When receiving the Read Multiple Block command, the M24LR04E-R reads the selected
blocks and sends back their value in multiples of 32 bits in the response. The blocks are
numbered from 00h to 1FFh in the request and the value is minus one (–1) in the field. For
example, if the “Number of blocks” field contains the value 06h, seven blocks are read. The
maximum number of blocks is fixed at 32 assuming that they are all located in the same
sector. If the number of blocks overlaps sectors, the M24LR04E-R returns an error code.
The Protocol_extension_flag should be set to 0 for the M24LR04E-R to operate correctly.
Table 47.
Read Multiple Block request format
Read
Request Request_
Multiple
SOF
flags
Block
UID(1)
First
block
number
Number
of blocks
CRC16
8 bits
64 bits
8 bits
8 bits
16 bits
23h
Request
EOF
1. Gray means that the field is optional.
Request parameters:
●
Request flags
●
UID (optional)
●
First block number
●
Number of blocks
Table 48.
Read Multiple Block response format when Error_flag is NOT set
Response Response_
SOF
flags
8 bits
Sector
security
status(1)
Data
CRC16
8 bits(2)
32 bits(2)
16 bits
Response
EOF
1. Gray means that the field is optional.
2. Repeated as needed.
Response parameters:
●
Sector security status if Option_flag is set (see Table 49)
●
N blocks of data
Table 49.
b7
Sector security status
b6
b5
Reserved for future
use. All at 0.
Table 50.
b3
Password
control bits
b2
b1
Read / Write
protection bits
b0
0: Current sector not locked
1: Current sector locked
Read Multiple Block response format when Error_flag is set
Response SOF
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b4
Response_flags
Error code
CRC16
8 bits
8 bits
16 bits
Doc ID 022208 Rev 5
Response EOF
M24LR04E-R
Command codes
Response parameter:
●
Error code as Error_flag is set:
–
0Fh: error with no information given
–
10h: the specified block is not available
–
15h: the specified block is read-protected
Figure 58. Read Multiple Block frame exchange between VCD and M24LR04E-R
VCD
SOF
Read Multiple
EOF
Block request
<-t1-> SOF
M24LR04E-R
Read Multiple
EOF
Block response
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Read Multiple Block command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
26.6
Select
When receiving the Select command:
●
If the UID is equal to its own UID, the M24LR04E-R enters or stays in the Selected
state and sends a response.
●
If the UID does not match its own, the selected M24LR04E-R returns to the Ready
state and does not send a response.
The M24LR04E-R answers an error code only if the UID is equal to its own UID. If not, no
response is generated. If an error occurs, the M24LR04E-R remains in its current state.
Table 51.
Select request format
Request Request_
SOF
flags
8 bits
Select
UID
CRC16
25h
64 bits
16 bits
Request
EOF
Request parameter:
●
UID
Table 52.
Response
SOF
Select Block response format when Error_flag is NOT set
Response_flags
CRC16
8 bits
16 bits
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Response
EOF
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Command codes
M24LR04E-R
Response parameter:
●
No parameter
Table 53.
Select response format when Error_flag is set
Response
SOF
Response_
flags
Error code
CRC16
8 bits
8 bits
16 bits
Response
EOF
Response parameter:
●
Error code as Error_flag is set:
–
03h: the option is not supported
Figure 59. Select frame exchange between VCD and M24LR04E-R
VCD
M24LR04E-R
SOF
Select
request
EOF
<-t1-> SOF
Select
response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Select command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
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M24LR04E-R
26.7
Command codes
Reset to Ready
On receiving a Reset to Ready command, the M24LR04E-R returns to the Ready state if no
error occurs. In the Addressed mode, the M24LR04E-R answers an error code only if the
UID is equal to its own UID. If not, no response is generated.
Table 54.
Reset to Ready request format
Request Request_ Reset to
SOF
flags
Ready
UID(1)
CRC16
8 bits
64 bits
16 bits
26h
Request
EOF
1. Gray means that the field is optional.
Request parameter:
●
UID (optional)
Table 55.
Reset to Ready response format when Error_flag is NOT set
Response
SOF
Response_flags
CRC16
8 bits
16 bits
Response
EOF
Response parameter:
●
No parameter
Table 56.
Reset to ready response format when Error_flag is set
Response
Response_flags
SOF
Error code
CRC16
8 bits
16 bits
8 bits
Response
EOF
Response parameter:
●
Error code as Error_flag is set:
–
03h: the option is not supported
Figure 60. Reset to Ready frame exchange between VCD and M24LR04E-R
VCD
M24LR04E-R
SOF
Reset to
Ready
request
EOF
<-t1->
Doc ID 022208 Rev 5
SOF
Reset to
Ready
response
EOF
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Command codes
M24LR04E-R
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Reset to ready command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
26.8
Write AFI
On receiving the Write AFI request, the M24LR04E-R programs the 8-bit AFI value to its
memory. The Option_flag is supported.
During the RF write cycle Wt, there should be no modulation (neither 100% nor 10%),
otherwise, the M24LR04E-R may not write correctly the AFI value into the memory. The Wt
time is equal to t1nom + 18 × 302 µs.
Table 57.
Write AFI request format
Request Request Write
SOF
_flags
AFI
8 bits
27h
UID(1)
AFI
CRC16
64 bits
8 bits
16 bits
Request
EOF
1. Gray means that the field is optional.
Request parameter:
●
Request flags
●
UID (optional)
●
AFI
Table 58.
Write AFI response format when Error_flag is NOT set
Response
SOF
Response_flags
CRC16
8 bits
16 bits
Response
EOF
Response parameter:
●
No parameter
Table 59.
Write AFI response format when Error_flag is set
Response
SOF
Response_
flags
Error code
CRC16
8 bits
8 bits
16 bits
Response parameter:
●
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Error code as Error_flag is set
–
12h: the specified block is locked and its contents cannot be changed
–
13h: the specified block was not successfully programmed
Doc ID 022208 Rev 5
Response
EOF
M24LR04E-R
Command codes
Figure 61. Write AFI frame exchange between VCD and M24LR04E-R
VCD
SOF
Write AFI
EOF
request
M24LR04E-R
<-t1-> SOF
EOF
Write sequence
when error
M24LR04E-R
<------------------ Wt --------------> SOF
Write AFI
EOF
response
Write AFI
response
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Write AFI command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the
duration of the internal write cycle (from the end of a valid Write AFI command to the
beginning of the M24LR04E-R response).
26.9
Lock AFI
On receiving the Lock AFI request, the M24LR04E-R locks the AFI value permanently. The
Option_flag is supported.
During the RF write cycle Wt, there should be no modulation (neither 100% nor 10%),
otherwise, the M24LR04E-R may not Lock correctly the AFI value in memory. The Wt time is
equal to t1nom + 18 × 302 µs.
Table 60.
Lock AFI request format
Request Request_
SOF
flags
8 bits
Lock
AFI
UID(1)
CRC16
28h
64 bits
16 bits
Request
EOF
1. Gray means that the field is optional.
Request parameter:
●
Request Flags
●
UID (optional)
Table 61.
Response
SOF
Lock AFI response format when Error_flag is NOT set
Response_flags
CRC16
8 bits
16 bits
Response
EOF
Response parameter:
●
No parameter
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Command codes
M24LR04E-R
Table 62.
Lock AFI response format when Error_flag is set
Response
SOF
Response_flags
Error code
CRC16
8 bits
8 bits
16 bits
Response
EOF
Response parameter:
●
Error code as Error_flag is set
–
11h: the specified block is already locked and thus cannot be locked again
–
14h: the specified block was not successfully locked
Figure 62. Lock AFI frame exchange between VCD and M24LR04E-R
VCD
SOF
Lock AFI
EOF
request
Lock AFI
response
M24LR04E-R
<-t1-> SOF
M24LR04E-R
<----------------- Wt -----------> SOF
EOF
Lock sequence
when error
Lock AFI
response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Lock AFI command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the
entire duration of the internal write cycle (from the end of valid Lock AFI command to the
beginning of the M24LR04E-R response).
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M24LR04E-R
26.10
Command codes
Write DSFID
On receiving the Write DSFID request, the M24LR04E-R programs the 8-bit DSFID value to
its memory. The Option_flag is supported.
During the RF write cycle Wt, there should be no modulation (neither 100% nor 10%),
otherwise, the M24LR04E-R may not write correctly the DSFID value in memory. The Wt
time is equal to t1nom + 18 × 302 µs.
Table 63.
Write DSFID request format
Request Request_ Write
SOF
flags
DSFID
8 bits
29h
UID(1)
DSFID
CRC16
64 bits
8 bits
16 bits
Request
EOF
1. Gray means that the field is optional.
Request parameter:
●
Request flags
●
UID (optional)
●
DSFID
Table 64.
Write DSFID response format when Error_flag is NOT set
Response
SOF
Response_flags
CRC16
8 bits
16 bits
Response
EOF
Response parameter:
●
No parameter
Table 65.
Write DSFID response format when Error_flag is set
Response
Response_flags
SOF
Error code
CRC16
8 bits
16 bits
8 bits
Response
EOF
Response parameter:
●
Error code as Error_flag is set
–
12h: the specified block is locked and its contents cannot be changed
–
13h: the specified block was not successfully programmed
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Command codes
M24LR04E-R
Figure 63. Write DSFID frame exchange between VCD and M24LR04E-R
VCD
SOF
Write DSFID
request
EO
F
SO
F
Write DSFID
response
M24LR04E-R
<-t1->
M24LR04E-R
<---------------- Wt ---------->
EO
F
Write sequence
when error
SO Write DSFID
EOF
F
response
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Write DSFID command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the
duration of the internal write cycle (from the end of a valid Write DSFID command to
beginning of the M24LR04E-R response).
26.11
Lock DSFID
On receiving the Lock DSFID request, the M24LR04E-R locks the DSFID value
permanently. The Option_flag is supported.
During the RF write cycle Wt, there should be no modulation (neither 100% nor 10%),
otherwise, the M24LR04E-R may not lock correctly the DSFID value in memory. The Wt time
is equal to t1nom + 18 × 302 µs.
Table 66.
Lock DSFID request format
Request Request_
SOF
flags
8 bits
Lock
DSFID
UID(1)
CRC16
2Ah
64 bits
16 bits
Request
EOF
1. Gray means that the field is optional.
Request parameter:
●
Request flags
●
UID (optional)
Table 67.
Response
SOF
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Lock DSFID response format when Error_flag is NOT set
Response_flags
CRC16
8 bits
16 bits
Doc ID 022208 Rev 5
Response
EOF
M24LR04E-R
Command codes
Response parameter:
●
No parameter.
Table 68.
Lock DSFID response format when Error_flag is set
Response
Response_flags
SOF
Error code
CRC16
8 bits
16 bits
8 bits
Response
EOF
Response parameter:
●
Error code as Error_flag is set:
–
11h: the specified block is already locked and thus cannot be locked again
–
14h: the specified block was not successfully locked
.
Figure 64. Lock DSFID frame exchange between VCD and M24LR04E-R
VCD
SOF
Lock
DSFID
request
EOF
Lock DSFID
response
M24LR04E-R
<-t1-> SOF
EOF
M24LR04E-R
<----------------- Wt ------------> SOF
Lock sequence
when error
Lock
DSFID
response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Lock DSFID command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the
duration of the internal write cycle (from the end of a valid Lock DSFID command to the
beginning of the M24LR04E-R response).
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Command codes
26.12
M24LR04E-R
Get System Info
When receiving the Get System Info command, the M24LR04E-R sends back its information
data in the response.The Option_flag is not supported. The Get System Info can be issued
in both Addressed and Non Addressed modes.
The Protocol_extension_flag must be set to 0. Table 70 shows the M24LR04E-R response
to the Get System Info command depending on the value of the Protocol_extension_flag.
Table 69.
Get System Info request format
Request Request Get System
SOF
_flags
Info
8 bits
2Bh
UID(1)
CRC16
64 bits
16 bits
Request
EOF
1. Gray means that the field is optional.
Request parameter:
●
Request flags
●
UID (optional)
Table 70.
Get System Info response format when Protocol_extension_flag = 0 and
Error_flag is NOT set
Response
SOF
Response Information
_flags
flags
00h
0Fh
UID
DSFID
AFI
Memory
size
IC
ref.
64
bits
8 bits
8 bits
037F
5A
CRC Response
16
EOF
16
bits
Response parameters:
●
Information flags set to 0Fh. DSFID, AFI, Memory Size and IC reference fields are
present.
●
UID code on 64 bits
●
DSFID value
●
AFI value
●
Memory size. The M24LR04E-R provides 128 blocks (7Fh) of 4 bytes (03h)
●
IC reference: the 8 bits are significant.
Table 71.
Get System Info response format when Error_flag is set
Response
SOF
Response_flags
Error code
CRC16
01h
8 bits
16 bits
Response parameter:
●
Error code as Error_flag is set:
–
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03h: Option not supported
Doc ID 022208 Rev 5
Response
EOF
M24LR04E-R
Command codes
.
Figure 65. Get System Info frame exchange between VCD and M24LR04E-R
VCD
M24LR04E-R
SOF
Get System Info
request
EOF
<-t1-> SOF
Get System Info
response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Get System Info command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
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Command codes
26.13
M24LR04E-R
Get Multiple Block Security Status
When receiving the Get Multiple Block Security Status command, the M24LR04E-R sends
back the sector security status. The blocks are numbered from 00h to 01FFh in the request
and the value is minus one (–1) in the field. For example, a value of '06' in the “Number of
blocks” field requests to return the security status of seven blocks.
The Protocol_extension_flag should be set to 0 for the M24LR04E-R to operate correctly.
During the M24LR04E-R response, if the internal block address counter reaches 01FFh, it
rolls over to 0000h and the Sector Security Status bytes for that location are sent back to the
reader.
Table 72.
Get Multiple Block Security Status request format
Request Request
SOF
_flags
Get
Multiple
Block
Security
Status
UID(1)
First
block
number
Number
of blocks
CRC16
2Ch
64 bits
8 bits
8 bits
16 bits
8 bits
Request
EOF
1. Gray means that the field is optional.
Request parameter:
●
Request flags
●
UID (optional)
●
First block number
●
Number of blocks
Table 73.
Response
SOF
Get Multiple Block Security Status response format when Error_flag is
NOT set
Response_
flags
Sector security
status
CRC16
8 bits
8 bits(1)
16 bits
Response
EOF
1. Repeated as needed.
Response parameters:
●
Sector security status (see Table 74)
Table 74.
b7
Sector security status
b6
b5
Reserved for future use. All
at 0.
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b4
b3
Password control
bits
b2
b1
Read / Write
protection bits
Doc ID 022208 Rev 5
b0
0: Current sector not locked
1: Current sector locked
M24LR04E-R
Command codes
Table 75.
Get Multiple Block Security Status response format when Error_flag is
set
Response
SOF
Response_
flags
Error code
CRC16
8 bits
8 bits
16 bits
Response
EOF
Response parameter:
●
Error code as Error_flag is set:
–
03h: the option is not supported
–
10h: the specified block is not available
Figure 66. Get Multiple Block Security Status frame exchange between VCD and
M24LR04E-R
VCD
SOF
Get Multiple Block
EOF
Security Status
M24LR04E-R
<-t1-> SOF
Get Multiple Block
Security Status
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Get Multiple Block Security Status command to the end of the M24LR04E-R
response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
26.14
Write-sector Password
On receiving the Write-sector Password command, the M24LR04E-R uses the data
contained in the request to write the password and reports whether the operation was
successful in the response. The Option_flag is supported.
During the RF write cycle time, Wt, there must be no modulation at all (neither 100% nor
10%), otherwise, the M24LR04E-R may not correctly program the data into the memory.
The Wt time is equal to t1nom + 18 × 302 µs. After a successful write, the new value of the
selected password is automatically activated. It is not required to present the new password
value until M24LR04E-R power-down.
Table 76.
Request
SOF
Write-sector Password request format
Request
_flags
Writesector
password
IC Mfg
code
UID(1)
Password
number
Data
CRC16
8 bits
B1h
02h
64 bits
8 bits
32 bits
16 bits
Request
EOF
1. Gray means that the field is optional.
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Command codes
M24LR04E-R
Request parameter:
●
Request flags
●
UID (optional)
●
Password number (01h = Pswd1, 02h = Pswd2, 03h = Pswd3, other = Error)
●
Data
Table 77.
Write-sector Password response format when Error_flag is NOT set
Response
SOF
Response_flags
CRC16
8 bits
16 bits
Response
EOF
Response parameter:
●
no parameter.
Table 78.
Write-sector Password response format when Error_flag is set
Response
SOF
Response_
flags
Error code
CRC16
8 bits
8 bits
16 bits
Response
EOF
Response parameter:
●
Error code as Error_flag is set:
–
10h: the password number is incorrect
–
12h: the session was not opened before the password update
–
13h: the specified block was not successfully programmed
–
0Fh: the presented password is incorrect
.
Figure 67. Write-sector Password frame exchange between VCD and M24LR04E-R
VCD
M24LR04E-R
M24LR04E-R
102/142
SOF
Writesector
Password
request
EOF
<-t1-> SOF
Write-sector
Password
response
EOF
<---------------- Wt -------------> SOF
Doc ID 022208 Rev 5
Write sequence
when error
Writesector
Password
response
EOF
M24LR04E-R
Command codes
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Write-sector Password command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the
duration of the internal write cycle (from the end of a valid Write sector password command
to the beginning of the M24LR04E-R response).
26.15
Lock-sector
On receiving the Lock-sector command, the M24LR04E-R sets the access rights and
permanently locks the selected sector. The Option_flag is supported.
A sector is selected by giving the address of one of its blocks in the Lock-sector request
(Sector number field). For example, addresses 0 to 31 are used to select sector 0 and
addresses 32 to 63 are used to select sector 1. Care must be taken when issuing the Locksector command as all the blocks belonging to the same sector are automatically locked by
a single command.
The Protocol_extension_flag should be set to 0 for the M24LR04E-R to operate correctly.
During the RF write cycle Wt, there should be no modulation (neither 100% nor 10%),
otherwise, the M24LR04E-R may not correctly lock the memory block. The Wt time is equal
to t1nom + 18 × 302 µs.
Table 79.
Request
SOF
Lock-sector request format
Request
_flags
Locksector
IC
Mfg
code
UID(1)
Sector
number
Sector
security
status
CRC16
8 bits
B2h
02h
64 bits
8 bits
8 bits
16 bits
Request
EOF
1. Gray means that the field is optional.
Request parameters:
●
Request flags
●
(optional) UID
●
Sector number
●
Sector security status (refer to Table 80)
Table 80.
Sector security status
b7
b6
b5
0
0
0
Table 81.
Response
SOF
b4
b3
password control bits
b2
b1
Read / Write protection
bits
b0
1
Lock-sector response format when Error_flag is NOT set
Response_flags
CRC16
8 bits
16 bits
Doc ID 022208 Rev 5
Response
EOF
103/142
Command codes
M24LR04E-R
Response parameter:
●
No parameter
Table 82.
Lock-sector response format when Error_flag is set
Response
SOF
Response_
flags
Error code
CRC16
8 bits
8 bits
16 bits
Response
EOF
Response parameter:
●
Error code as Error_flag is set:
–
10h: the specified block is not available
–
11h: the specified block is already locked and thus cannot be locked again
–
14h: the specified block was not successfully locked
Figure 68. Lock-sector frame exchange between VCD and M24LR04E-R
VCD
SOF
Lock-sector
EOF
request
M24LR04E-R
<-t1-> SOF
Lock-sector
EOF
response
Lock sequence
when error
M24LR04E-R
<--------------- Wt -----------> SOF
Lock-sector
EOF
response
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Lock-sector command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the
duration of the internal write cycle (from the end of a valid Lock sector command to the
beginning of the M24LR04E-R response).
26.16
Present-sector Password
On receiving the Present-sector Password command, the M24LR04E-R compares the
requested password with the data contained in the request and reports whether the
operation has been successful in the response. The Option_flag is supported.
During the comparison cycle equal to Wt, there should be no modulation (neither 100% nor
10%), otherwise, the M24LR04E-R the Password value may not be correctly compared. The
Wt time is equal to t1nom + 18 × 302 µs.
After a successful command, the access to all the memory blocks linked to the password is
changed as described in Section 4.1: M24LR04E-R block security in RF mode.
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M24LR04E-R
Command codes
Table 83.
Present-sector Password request format
Request
SOF
Request
_flags
Presentsector
Password
IC
Mfg
code
UID(1)
Password
number
Password
CRC16
8 bits
B3h
02h
64 bits
8 bits
32 bits
16 bits
Request
EOF
1. Gray means that the field is optional.
Request parameter:
●
Request flags
●
UID (optional)
●
Password Number (0x01 = Pswd1, 0x02 = Pswd2, 0x03 = Pswd3, other = Error)
●
Password
Table 84.
Present-sector Password response format when Error_flag is NOT set
Response
SOF
Response_flags
CRC16
8 bits
16 bits
Response
EOF
Response parameter:
●
No parameter. The response is send back after the write cycle.
Table 85.
Present-sector Password response format when Error_flag is set
Response
SOF
Response_
flags
Error code
CRC16
8 bits
8 bits
16 bits
Response
EOF
Response parameter:
●
Error code as Error_flag is set:
–
10h: the password number is incorrect
–
0Fh: the present password is incorrect
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Command codes
M24LR04E-R
Figure 69. Present-sector Password frame exchange between VCD and M24LR04E-R
VCD
M24LR04E-R
M24LR04E-R
Presentsector
password
SOF response EOF
OR error
0F (bad
password)
<-t1-> SOF
Presentsector
password
response
EOF
<---------------- Wt ------------> SOF
sequence when
error
Presentsector
password
response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Present Sector Password command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY remains in high-Z
state.
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M24LR04E-R
26.17
Command codes
Fast Read Single Block
On receiving the Fast Read Single Block command, the M24LR04E-R reads the requested
block and sends back its 32-bit value in the response. The Option_flag is supported. The
data rate of the response is multiplied by 2.
The Protocol_extension_flag should be set to 0 for the M24LR04E-R to operate correctly.
The subcarrier_flag should be set to 0, otherwise the M24LR04E-R answers with an error
code.
Table 86.
Fast Read Single Block request format
Request Request_
SOF
flags
Fast Read
IC Mfg
Single
code
Block
8 bits
C0h
02h
UID(1)
Block
number
CRC16
64 bits
8 bits
16 bits
Request
EOF
1. Gray means that the field is optional.
Request parameters:
●
Request flags
●
UID (optional)
●
Block number
Table 87.
Fast Read Single Block response format when Error_flag is NOT set
Response Response
SOF
_flags
Sector
security
status(1)
Data
CRC16
8 bits
32 bits
16 bits
8 bits
Response
EOF
1. Gray means that the field is optional.
Response parameters:
●
Sector security status if Option_flag is set (see Table 88)
●
Four bytes of block data
Table 88.
b7
Sector security status
b6
b5
Reserved for future used. All
at 0.
Table 89.
b4
b3
Password control
bits
b2
b1
Read / Write
protection bits
b0
0: Current sector not locked
1: Current sector locked
Fast Read Single Block response format when Error_flag is set
Response
Response_flags
SOF
8 bits
Error code
CRC16
8 bits
16 bits
Doc ID 022208 Rev 5
Response
EOF
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Command codes
M24LR04E-R
Response parameter:
●
Error code as Error_flag is set:
–
10h: the specified block is not available
–
15h: the specified block is read protected
.
Figure 70. Fast Read Single Block frame exchange between VCD and M24LR04E-R
VCD
SOF
Fast Read Single
Block request
EOF
<-t1-> SOF
M24LR04E-R
Fast Read Single
Block response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Fast Read Single block command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
26.18
Fast Inventory Initiated
Before receiving the Fast Inventory Initiated command, the M24LR04E-R must have
received an Initiate or a Fast Initiate command in order to set the Initiate_ flag. If not, the
M24LR04E-R does not answer to the Fast Inventory Initiated command.
The subcarrier_flag should be set to 0, otherwise the M24LR04E-R answers with an error
code.
On receiving the Fast Inventory Initiated request, the M24LR04E-R runs the anticollision
sequence. The Inventory_flag must be set to 1. The meaning of flags 5 to 8 is shown in
Table 29. The data rate of the response is multiplied by 2.
The request contains:
●
the flags,
●
the Inventory command code,
●
the AFI if the AFI flag is set,
●
the mask length,
●
the mask value,
●
the CRC.
The M24LR04E-R does not generate any answer in case of error.
Table 90.
Fast Inventory Initiated request format
Request Request
SOF
_flags
8 bits
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Fast
Inventory
Initiated
C1h
IC Mfg Optional Mask
Mask value
code
AFI
length
02h
8 bits
Doc ID 022208 Rev 5
8 bits
0 - 64 bits
CRC16
16 bits
Request
EOF
M24LR04E-R
Command codes
The Response contains:
●
the flags,
●
the Unique ID.
Table 91.
Fast Inventory Initiated response format
Response Response
DSFID
SOF
_flags
8 bits
8 bits
UID
CRC16
64 bits
16 bits
Response
EOF
During an Inventory process, if the VCD does not receive an RF M24LR04E-R response, it
waits for a time t3 before sending an EOF to switch to the next slot. t3 starts from the rising
edge of the request EOF sent by the VCD.
●
If the VCD sends a 100% modulated EOF, the minimum value of t3 is:
t3min = 4384/fC (323.3µs) + tSOF
●
If the VCD sends a 10% modulated EOF, the minimum value of t3 is:
t3min = 4384/fC (323.3µs) + tNRT
where:
●
tSOF is the time required by the M24LR04E-R to transmit an SOF to the VCD
●
tNRT is the nominal response time of the M24LR04E-R
tNRT and tSOF are dependent on the M24LR04E-R-to-VCD data rate and subcarrier
modulation mode.
When configured in the RF busy mode, the RF WIP/BUSY pin is driven to 0 from the SOF
starting the inventory command to the end of the M24LR04E-R response.If the M24LR04ER does not receive the corresponding slot marker, the RF WIP/BUSY pin remains at 0 till the
next RF power-off.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
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Command codes
26.19
M24LR04E-R
Fast Initiate
On receiving the Fast Initiate command, the M24LR04E-R sets the internal Initiate_flag and
sends back a response only if it is in the Ready state. The command has to be issued in the
Non Addressed mode only (Select_flag is reset to 0 and Address_flag is reset to 0). If an
error occurs, the M24LR04E-R does not generate any answer. The Initiate_flag is reset after
a power-off of the M24LR04E-R. The data rate of the response is multiplied by 2.
The subcarrier_flag should be set to 0, otherwise the M24LR04E-R answers with an error
code.
The request contains:
●
No data
Table 92.
Request
SOF
Fast Initiate request format
Request_flags
Fast
Initiate
IC Mfg
Code
CRC16
8 bits
C2h
02h
16 bits
Request
EOF
The response contains:
●
the flags,
●
the Unique ID.
Table 93.
Fast Initiate response format
Response Response
DSFID
SOF
_flags
8 bits
8 bits
UID
CRC16
64 bits
16 bits
Response
EOF
Figure 71. Fast Initiate frame exchange between VCD and M24LR04E-R
VCD
SOF
Fast Initiate
request
EOF
M24LR04E-R
<-t1-> SOF
Fast Initiate
response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Fast Initiate command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
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Doc ID 022208 Rev 5
M24LR04E-R
26.20
Command codes
Fast Read Multiple Block
On receiving the Fast Read Multiple Block command, the M24LR04E-R reads the selected
blocks and sends back their value in multiples of 32 bits in the response. The blocks are
numbered from 00h to 1FFh in the request and the value is minus one (–1) in the field. For
example, if the “Number of blocks” field contains the value 06h, seven blocks are read. The
maximum number of blocks is fixed to 32 assuming that they are all located in the same
sector. If the number of blocks overlaps sectors, the M24LR04E-R returns an error code.
The Protocol_extension_flag should be set to 0 for the M24LR04E-R to operate correctly.
The Option_flag is supported. The data rate of the response is multiplied by 2.
The subcarrier_flag should be set to 0, otherwise the M24LR04E-R answers with an error
code.
Table 94.
Fast Read Multiple Block request format
Request Request_
SOF
flags
Fast
Read
Multiple
Block
IC Mfg
code
UID(1)
C3h
02h
64 bits
8 bits
First
Number
Request
block
of
CRC16
EOF
number blocks
8 bits
8 bits
16 bits
1. Gray means that the field is optional.
Request parameters:
●
Request flag
●
UID (Optional)
●
First block number
●
Number of blocks
Table 95.
Fast Read Multiple Block response format when Error_flag is NOT set
Response Response_
SOF
flags
8 bits
Sector
security
status(1)
Data
CRC16
8 bits(2)
32 bits(2)
16 bits
Response
EOF
1. Gray means that the field is optional.
2. Repeated as needed.
Response parameters:
●
Sector security status if Option_flag is set (see Table 96)
●
N block of data
Table 96.
b7
Sector security status if Option_flag is set
b6
b5
Reserved for future use.
All at 0.
b4
b3
Password
control bits
b2
b1
Read / Write
protection bits
Doc ID 022208 Rev 5
b0
0: Current sector not locked
1: Current sector locked
111/142
Command codes
M24LR04E-R
Table 97.
Fast Read Multiple Block response format when Error_flag is set
Response SOF
Response_flags
Error code
CRC16
8 bits
8 bits
16 bits
Response EOF
Response parameter:
●
Error code as Error_flag is set:
–
03h: the option is not supported
–
10h: block address not available
–
15h: block read-protected
Figure 72. Fast Read Multiple Block frame exchange between VCD and M24LR04E-R
VCD
SOF
Fast Read
Multiple Block
request
M24LR04E-R
EOF
<-t1-> SOF
Fast Read
Multiple Block
response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Fast Read Multiple Block command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
26.21
Inventory Initiated
Before receiving the Inventory Initiated command, the M24LR04E-R must have received an
Initiate or a Fast Initiate command in order to set the Initiate_ flag. If not, the M24LR04E-R
does not answer to the Inventory Initiated command.
On receiving the Inventory Initiated request, the M24LR04E-R runs the anticollision
sequence. The Inventory_flag must be set to 1. The meaning of flags 5 to 8 is given in
Table 29.
The request contains:
●
the flags,
●
the Inventory Command code,
●
the AFI if the AFI flag is set,
●
the mask length,
●
the mask value,
●
the CRC.
The M24LR04E-R does not generate any answer in case of error.
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Doc ID 022208 Rev 5
M24LR04E-R
Command codes
Table 98.
Inventory Initiated request format
IC
Optional Mask
Mfg
AFI
length
code
Request Request Inventory
SOF
_flags
Initiated
8 bits
D1h
02h
8 bits
8 bits
Mask value
CRC16
0 - 64 bits
16 bits
Request
EOF
The response contains:
●
the flags,
●
the Unique ID.
Table 99.
Inventory Initiated response format
Response Response
SOF
_flags
8 bits
DSFID
UID
CRC16
8 bits
64 bits
16 bits
Response
EOF
During an Inventory process, if the VCD does not receive an RF M24LR04E-R response, it
waits for a time t3 before sending an EOF to switch to the next slot. t3 starts from the rising
edge of the request EOF sent by the VCD.
●
If the VCD sends a 100% modulated EOF, the minimum value of t3 is:
t3min = 4384/fC (323.3µs) + tSOF
●
If the VCD sends a 10% modulated EOF, the minimum value of t3 is:
t3min = 4384/fC (323.3µs) + tNRT
where:
●
tSOF is the time required by the M24LR04E-R to transmit an SOF to the VCD
●
tNRT is the nominal response time of the M24LR04E-R
tNRT and tSOF are dependent on the M24LR04E-R-to-VCD data rate and subcarrier
modulation mode.
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF
starting the inventory command to the end of the M24LR04E-R response. If the M24LR04ER does not receive the corresponding slot marker, the RF WIP/BUSY pin remains at 0 till the
next RF power-off.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
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Command codes
26.22
M24LR04E-R
Initiate
On receiving the Initiate command, the M24LR04E-R sets the internal Initiate_flag and
sends back a response only if it is in the ready state. The command has to be issued in the
Non Addressed mode only (Select_flag is reset to 0 and Address_flag is reset to 0). If an
error occurs, the M24LR04E-R does not generate any answer. The Initiate_flag is reset after
a power-off of the M24LR04E-R.
The request contains:
●
No data
Table 100. Initiate request format
Request
Request_flags
SOF
Initiate
IC Mfg
code
CRC16
D2h
02h
16 bits
8 bits
Request
EOF
The response contains:
●
the flags,
●
the Unique ID.
.
Table 101. Initiate Initiated response format
Response Response
SOF
_flags
8 bits
DSFID
UID
CRC16
8 bits
64 bits
16 bits
Response
EOF
Figure 73. Initiate frame exchange between VCD and M24LR04E-R
VCD
M24LR04E-R
SOF
Initiate
request
EOF
<-t1-> SOF
Initiate
response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the Initiate command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
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M24LR04E-R
26.23
Command codes
ReadCfg
On receiving the ReadCfg command, the M24LR04E-R reads the Configuration byte and
sends back its 8-bit value in the response.
The Protocol_extension_flag should be set to 0 for the M24LR04E-R to operate correctly. If
the Protocol_extension_flag is at 1, the M24LR04E-R answers with an error code. The
Option_flag is not supported. The Inventory_flag must be set to 0.
Table 102. ReadCfg request format
Request Request_
SOF
flags
ReadCfg
IC Mfg code
UID(1)
CRC16
A0h
02h
64 bits
16 bits
8 bits
Request
EOF
1. Gray means that the field is optional.
Request parameters:
●
UID (optional)
Table 103. ReadCfg response format when Error_flag is NOT set
Response SOF
Response_flags
Data
CRC16
8 bits
8 bits
16 bits
Response
EOF
Response parameters:
●
One byte of data: Configuration byte
Table 104. ReadCfg response format when Error_flag is set
Response
SOF
Response_
flags
Error code
CRC16
8 bits
8 bits
16 bits
Response
EOF
Response parameter:
●
Error code as Error_flag is set
–
03h: the option is not supported
–
0Fh: error with no information given
Figure 74. ReadCfg frame exchange between VCD and M24LR04E-R
VCD
SOF
ReadCfg request
EOF
M24LR04E-R
<-t1-> SOF
Doc ID 022208 Rev 5
ReadCfg response
EOF
115/142
Command codes
M24LR04E-R
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the ReadCfg command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
26.24
WriteEHCfg
On receiving the WriteEHCfg command, the M24LR04E-R writes the data contained in the
request to the Configuration byte and reports whether the write operation was successful in
the response. The Protocol_extension_flag should be set to 0 for the M24LR04E-R to
operate correctly. If the Protocol_extension_flag is at 1, the M24LR04E-R answers with an
error code.
The Option_flag is supported, the Inventory_flag is not supported.
During the RF write cycle Wt, there should be no modulation (neither 100% nor 10%),
otherwise, the M24LR04E-R may not program correctly the data into the Configuration byte.
The Wt time is equal to t1nom + 18 × 302 µs.
Table 105. WriteEHCfg request format
Request Request_
WriteEHCfg
SOF
flags
8 bits
IC Mfg
code
UID(1)
Data
CRC16
02h
64 bits
8 bits
16 bits
A1h
Request
EOF
1. Gray means that the field is optional.
Request parameters:
●
Request flags
●
UID (optional)
●
Data: during WriteEHCfg command, bit 3 of the data is ignored (see Table 14).
Table 106. WriteEHCfg response format when Error_flag is NOT set
Response SOF
Response_flags
CRC16
8 bits
16 bits
Response EOF
Response parameter:
●
No parameter. The response is send back after the writing cycle.
Table 107. WriteEHCfg response format when Error_flag is set
Response
SOF
Response_
flags
Error code
CRC16
8 bits
8 bits
16 bits
Response parameter:
●
Error code as Error_flag is set:
–
116/142
13h: the specified block was not successfully programmed
Doc ID 022208 Rev 5
Response
EOF
M24LR04E-R
Command codes
Figure 75. WriteEHCfg frame exchange between VCD and M24LR04E-R
VCD
SOF
WriteEHCfg
request
EOF
WriteEHCfg
response
M24LR04ER
<-t1-> SOF
M24LR04ER
<------------------- Wt ---------------> SOF
EOF
WriteEHCfg sequence
when error
WriteEHCfg
response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the WriteEHCfg command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the
entire duration of the internal write cycle (from the end of a valid WriteEHCfg command to
the beginning of the M24LR04E-R response).
26.25
WriteDOCfg
On receiving the WriteDOCfg command, the M24LR04E-R writes the data contained in the
request to the Configuration byte and reports whether the write operation was successful in
the response. The Protocol_extension_flag should be set to 0 for the M24LR04E-R to
operate correctly. If the Protocol_extension_flag is at 1, the M24LR04E-R answers with an
error code.
The Option_flag is supported, the Inventory_flag is not supported.
During the RF write cycle Wt, there should be no modulation (neither 100% nor 10%),
otherwise, the M24LR04E-R may not program correctly the data into the Configuration byte.
The Wt time is equal to t1nom + 18 × 302 µs.
Table 108. WriteDOCfg request format
Request
SOF
Request_
flags
WriteDOCfg
IC Mfg
code
UID(1)
Data
CRC16
8 bits
A4h
02h
64 bits
8 bits
16 bits
Request
EOF
1. Gray means that the field is optional.
Request parameters:
●
Request flag
●
UID (optional)
●
Data: during a WriteDOCfg command, bits 2 to 0 of the data are ignored (see
Table 14).
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Command codes
M24LR04E-R
Table 109. WriteDOCfg response format when Error_flag is NOT set
Response SOF
Response_flags
CRC16
8 bits
16 bits
Response EOF
Response parameter:
●
No parameter. The response is sent back after the writing cycle.
Table 110. WriteDOCfg response format when Error_flag is set
Response
SOF
Response_
flags
Error code
CRC16
8 bits
8 bits
16 bits
Response
EOF
Response parameter:
●
Error code as Error_flag is set:
–
13h: the specified block was not successfully programmed
Figure 76. WriteDOCfg frame exchange between VCD and M24LR04E-R
VCD
SOF
WriteDOCfg
request
EOF
WriteDOCfg
response
M24LR04E-R
<-t1-> SOF
EOF
M24LR04E-R
<----------------- Wt --------------> SOF
WriteDOCfg sequence
when error
WriteDOCfg
response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the WriteEHCfg command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin is tied to 0 for the
entire duration of the internal write cycle (from the end of a valid WriteDOCfg command to
the beginning of the M24LR04E-R response).
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M24LR04E-R
26.26
Command codes
SetRstEHEn
On receiving the SetRstEHEn command, the M24LR04E-R sets or resets the EH_enable bit
in the volatile Control register. The Protocol_extension_flag should be set to 0 for the
M24LR04E-R to operate correctly. If the Protocol_extension_flag is at 1, the M24LR04E-R
answers with an error code. The Option_flag and the Inventory_flag are not supported.
Table 111. SetRstEHEn request format
Request Request_
SetRstEHEn
SOF
flags
8 bits
IC Mfg
code
UID(1)
Data
CRC16
02h
64 bits
8 bits
16 bits
A2h
Request
EOF
1. Gray means that the field is optional.
Request parameters:
●
Request flags
●
UID (optional)
●
Data: during a SetRstEHEn command, bits 7 to 1 are ignored. Bit 0 is the EH_enable
bit.
Table 112. SetRstEHEn response format when Error_flag is NOT set
Response SOF
Response_flags
CRC16
8 bits
16 bits
Response EOF
Response parameter:
●
No parameter. The response is sent back after t1.
Table 113. SetRstEHEn response format when Error_flag is set
Response
SOF
Response_
flags
Error code
CRC16
8 bits
8 bits
16 bits
Response
EOF
Response parameter:
●
Error code as Error_flag is set:
–
03h: the option is not supported
Doc ID 022208 Rev 5
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Command codes
M24LR04E-R
Figure 77. SetRstEHEn frame exchange between VCD and M24LR04E-R
VCD
SOF
SetRstEHEn
request
EOF
M24LR04E-R
<-t1-> SOF
SetRstEHEn
response
EOF
WriteEHCfg sequence
when no error
M24LR04E-R
<-t1-> SOF
SetRstEHEn
response
EOF
WriteEHCfg sequence
when error
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the SetRstEHEn command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
26.27
CheckEHEn
On receiving the CheckEHEn command, the M24LR04E-R reads the Control register and
sends back its 8-bit value in the response.
The Protocol_extension_flag should be set to 0 for the M24LR04E-R to operate correctly. If
the Protocol_extension_flag is at 1, the M24LR04E-R answers with an error code. The
Option_flag is not supported. The Inventory_flag must be set to 0.
Table 114. CheckEHEn request format
Request Request_
SOF
flags
CheckEHEn
IC Mfg code
UID(1)
CRC16
A3h
02h
64 bits
16 bits
8 bits
Request
EOF
1. Gray means that the field is optional.
Request parameters:
●
UID (optional)
Table 115. CheckEHEn response format when Error_flag is NOT set
Response SOF
Response_flags
Data
CRC16
8 bits
8 bits
16 bits
Response parameters:
●
120/142
One byte of data: volatile Control register (see Table 15)
Doc ID 022208 Rev 5
Response
EOF
M24LR04E-R
Command codes
Table 116. CheckEHEn response format when Error_flag is set
Response
SOF
Response_
flags
Error code
CRC16
8 bits
8 bits
16 bits
Response
EOF
Response parameter:
●
Error code as Error_flag is set
–
03h: the option is not supported
Figure 78. CheckEHEn frame exchange between VCD and M24LR04E-R
VCD
SOF CheckEHEn request EOF
<-t1-> SOF
M24LR04E-R
CheckEHEn
response
EOF
When configured in the RF busy mode, the RF WIP/BUSY pin is tied to 0 from the SOF that
starts the CheckEHEn command to the end of the M24LR04E-R response.
When configured in the RF write in progress mode, the RF WIP/BUSY pin remains in high-Z
state.
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Maximum rating
27
M24LR04E-R
Maximum rating
Stressing the device above the rating listed in Table 117 may cause permanent damage to
the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect the device
reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality
documents.
Table 117. Absolute maximum ratings
Symbol
TA
Parameter
Ambient operating temperature
TSTG,
Storage conditions
hSTG, tSTG
Min.
Max.
Unit
–40
85
°C
15
25
°C
6(1)
months
Sawn wafer on UV
tape
kept in its original
packing form
TSTG
Storage temperature
UFDFPN8 (MLP8),
SO8, TSSOP8
TLEAD
Lead temperature during
soldering
UFDFPN8 (MLP8),
SO8, TSSOP8
VIO
I2C input or output range
–0.50
6.5
V
VCC
I2C supply voltage
–0.50
6.5
V
DC output current on pin SDA or
RF WIP/BUSY (when equal to 0)
5
mA
RF supply current AC0 - AC1
50
mA
27
V
11
V
IOL_MAX
ICC(3)
RF input voltage amplitude peak
VMAX_1(3) to peak between AC0 and AC1,
GND pad left floating
VMAX_2(3)
VESD
–65
150
see note (2)
VAC0-VAC1
AC voltage between AC0 and
GND, or AC1 and GND
VAC0-GND, or
VAC1-GND
Electrostatic discharge voltage
(human body model)(4)
AC0, AC1
1000
Other pads
3500
Electrostatic discharge voltage (Machine model)
-1
400
1. Counted from ST shipment date.
2. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
3. Based on characterization, not tested in production.
4. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω)
122/142
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°C
°C
V
I2C DC and AC parameters
M24LR04E-R
28
I2C DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device in I2C mode. The parameters in the DC and AC characteristic
tables that follow are derived from tests performed under the measurement conditions
summarized in the relevant tables. Designers should check that the operating conditions in
their circuit match the measurement conditions when relying on the quoted parameters.
Table 118. I2C operating conditions
Symbol
VCC
TA
Parameter
Min.
Max.
Unit
Supply voltage
1.8
5.5
V
Ambient operating temperature
–40
85
°C
Min.
Max.
Unit
Table 119. AC test measurement conditions
Symbol
CL
Parameter
Load capacitance
100
Input rise and fall times
pF
50
ns
Input levels
0.2VCC to 0.8VCC
V
Input and output timing reference levels
0.3VCC to 0.7VCC
V
Figure 79. AC test measurement I/O waveform
Input Levels
Input and Output
Timing Reference Levels
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI00825B
Table 120. Input parameters
Symbol
Parameter
Min.
Max.
Unit
CIN
Input capacitance (SDA)
-
8
pF
CIN
Input capacitance (other pins)
-
6
pF
Pulse width ignored (Input filter on SCL and SDA)
-
80
ns
tNS(1)
1. Characterized only.
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I2C DC and AC parameters
M24LR04E-R
Table 121. I2C DC characteristics
Symbol
Parameter
Test condition
Min.
Unit
ILI
Input leakage current
(SCL, SDA)
VIN = VSS or VCC
device in Standby mode
±2
µA
ILO_Vout
Vout output leakage
current
external voltage applied on
Vout: VSS or VCC
±5
µA
SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
±2
µA
VCC = 1.8 V, fc = 100 kHz
(rise/fall time < 50 ns)
50
VCC = 1.8 V, fc = 400 kHz
(rise/fall time < 50 ns)
100
VCC = 2.5 V, fc = 400 kHz
(rise/fall time < 50 ns)
200
VCC = 5.5 V, fc = 400 kHz
(rise/fall time < 50 ns)
400
VCC = 1.8 - 5.5 V
220
VIN = VSS or VCC
VCC = 1.8 V
30
VIN = VSS or VCC
VCC = 2.5 V
30
VIN = VSS or VCC
VCC = 5.5 V
40
ILO
ICC
ICC0
ICC1
VIL
VIH
VOL
Output leakage current
Supply current
(Read)(1)
Supply current (Write)(1)
Standby supply current
Input low voltage (SDA,
SCL)
Input high voltage (SDA,
SCL)
Output low voltage
µA
VCC = 1.8 V
–0.45
0.25VCC
VCC = 2.5 V
–0.45
0.25VCC
VCC = 5.5 V
–0.45
0.3VCC
VCC = 1.8 V
0.75VCC
VCC+1
VCC = 2.5 V
0.75VCC
VCC+1
VCC = 5.5 V
0.7VCC
VCC+1
IOL = 2.1 mA, VCC = 1.8 V or
IOL = 3 mA, VCC = 5.5 V
1. SCL, SDA connected to Ground or VCC. SDA connected to VCC through a pull-up resistor.
124/142
Max.
Doc ID 022208 Rev 5
0.4
µA
µA
V
V
V
I2C DC and AC parameters
M24LR04E-R
Table 122. I2C AC characteristics
Test conditions specified in Table 118
Symbol
Alt.
fC
fSCL
Parameter
Clock frequency
Min.
Max.
Unit
25
400
kHz
(1)
µs
µs
tCHCL
tHIGH
Clock pulse width high
0.6
20000
tCLCH
tLOW
Clock pulse width low
1.3
20000(2)
I²C timeout on Start condition
40
tSTART_OU
ms
T
tXH1XH2(3)
tR
Input signal rise time
20
300
ns
(3)
tF
Input signal fall time
20
300
ns
tF
SDA (out) fall time
20
100
ns
tDXCX
tSU:DAT Data in set up time
100
ns
tCLDX
tHD:DAT Data in hold time
0
ns
ns
tXL1XL2
tDL1DL2
tCLQX
tDH
Data out hold time
100
tCLQV(4)(5)
tAA
Clock low to next data valid (access time)
100
tCHDX(6)
tSU:STA Start condition set up time
900
ns
600
ns
35000(7)
tDLCL
tHD:STA Start condition hold time
0.6
tCHDH
tSU:STO Stop condition set up time
600
ns
1300
ns
tDHDL
tBUF
tW
Time between Stop condition and next Start
condition
I²C write time
5
µs
ms
1. tCHCL timeout
2. tCLCH timeout
3. Values recommended by the I²C-bus Fast-Mode specification.
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8VCC in a
compatible way with the I2C specification (which specifies tSU:DAT (min) = 100 ns), assuming that the Rbus
× Cbus time constant is less than 500 ns (as specified in Figure 3).
6. For a reStart condition, or following a write cycle.
7. tDLCL timeout
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I2C DC and AC parameters
M24LR04E-R
Figure 80. I2C AC waveforms
tXL1XL2
tCHCL
tXH1XH2
tCLCH
SCL
tDLCL
tXL1XL2
SDA In
tCHDX
tCLDX
tXH1XH2
Start
condition
SDA
Input
SDA tDXCX
Change
tCHDH tDHDL
Start
Stop
condition condition
SCL
SDA In
tW
tCHDH
tCHDX
Stop
condition
Write cycle
Start
condition
tCHCL
SCL
tCLQV
SDA Out
tCLQX
Data valid
tDL1DL2
Data valid
AI00795e
126/142
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M24LR04E-R
29
RF electrical parameters
RF electrical parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device in RF mode.
The parameters in the DC and AC Characteristic tables that follow are derived from tests
performed under the Measurement Conditions summarized in the relevant tables. Designers
should check that the operating conditions in their circuit match the measurement conditions
when relying on the quoted parameters.
Table 123. RF characteristics(1) (2)
Symbol
fCC
Parameter
Condition
External RF signal frequency
Operating field according to ISO
MICARRIER
10% carrier modulation index (3)
MI=(A-B)/(A+B)
tRFSBL
TA = -40 °C to 85 °C
tRFR, tRFF
100% rise and fall time
Unit
150
mA/
m
5000
15
30
H_ISO > 1000 mA/m
10
30
0.5
3.0
µs
7.1
9.44
µs
95
100
%
0.5
3.5
µs
7
9.44
µs
1
ms
10% minimum pulse width for bit
100% carrier modulation index
Max
150 mA/m > H_ISO > 1000
mA/m
10% rise and fall time
MICARRIER
Typ
13.553 13.56 13.567 MHz
H_ISO
tRFR, tRFF
Min
MI=(A-B)/(A+B)(4)
%
tRFSBL
100% minimum pulse width for bit
tMIN CD
Minimum time from carrier
generation to first data
From H-field min
fSH
Subcarrier frequency high
FCC/32
423.75
kHz
fSL
Subcarrier frequency low
FCC/28
484.28
kHz
t1
Time for M24LR04E-R response
4224/FS
318.6
320.9
323.3
µs
t2
Time between commands
4224/FS
309
311.5
314
µs
Wt
RF write time (including internal
Verify)
ICC_RF
Operating current (Read)(5)
VAC0-VAC1 (4 V peak to peak)
(6)
CTUN
Internal tuning capacitor in SO8
VBACK
Backscattered level as defined by
ISO test
f = 13.56 MHz
24.8
ISO10373-7
10
Doc ID 022208 Rev 5
5.75
ms
20
µA
27.5
30.2
pF
mV
127/142
RF electrical parameters
M24LR04E-R
Table 123. RF characteristics(1) (2) (continued)
Symbol
Parameter
VMAX_1(3)
RF input voltage amplitude
between AC0 and AC1, GND pad
left floating, VAC0-VAC1 peak to
peak(7)
VMAX_2(3)
AC voltage between AC0 and
GND or between AC1 and GND
Inventory and Read operations
VMIN_1(3)
RF input voltage amplitude
between AC0 and AC1, GND pad
left floating, VAC0-VAC1 peak to
peak(7)
VMIN_2(3)
AC voltage between AC0 and
GND or between AC1 and GND
tRF_OFF
Condition
Min
Typ
Max
Unit
20
V
8.5
V
4
4.5
V
Write operations
4.5
5
V
Inventory and Read operations
1.8
2
V
Write operations
2
2.2
V
-1
RF OFF time
Chip reset
2
ms
1. TA = –40 to 85 °C. Characterized only.
2. All timing characterizations were performed between 0 °C and 50 °C on a reference antenna with the following
characteristics:
External size: 75 mm x 48 mm
Number of turns: 5
Width of conductor: 0.5 mm
Space between two conductors: 0.3 mm
Value of the tuning capacitor in SO8: 27.5 pF (M24LR04E-R)
Value of the coil: 5 µH
Tuning frequency: 13.56 MHz.
3. 15% (or more) carrier modulation index offers a better signal/noise ratio and therefore a wider operating range with a better
noise immunity.
4. Temperature range 0 °C to 90 °C
5. Characterized on bench.
6. Characterized only, at room temperature only, measured at VAC0-VAC1 = 1 V peak to peak.
7. Characterized only, at room temperature only.
Table 124. Operating conditions
Symbol
TA
Parameter
Ambient operating temperature
Min.
Max.
Unit
–40
85
°C
Figure 81 shows an ASK modulated signal from the VCD to the M24LR04E-R. The test
condition for the AC/DC parameters are:
128/142
●
Close coupling condition with tester antenna (1 mm)
●
M24LR04E-R performance measured at the tag antenna
●
M24LR04E-R synchronous timing, transmit and receive
Doc ID 022208 Rev 5
M24LR04E-R
RF electrical parameters
Figure 81. ASK modulated signal
A
B
tRFF
tRFR
fCC
tRFSBL
tMIN CD
MS19784V1
Table 125 below summarizes respectively the minimum AC0-AC1 input power level PAC0AC1_min required for the Energy harvesting mode, the corresponding maximum current
consumption Isink_max and variation of the analog voltage Vout for the various Energy
harvesting fan-out configurations defined by bits b0 and b1 of the Configuration byte.
Table 125. Energy harvesting(1) (2)
Range
Hmin(3)
Pmin(4)
Vout@I=0
Vout@Isink_max
Isink_max@Pmin
00
3.5 A/m
100 mW
2.7 V min
4.5 V max
1.7 V
6 mA
01
2.4 A/m
60 mW
2.7 V min
4.5 V max
1.9 V
3 mA
10
1.6 A/m
30 mW
2.7 V min
4.5 V max
2.1 V
1 mA
11
1.0 A/m
16 mW
2.7 V min
4.5 V max
2.3 V
300 µA
1. Characterized only
2. Valid from -40 °C to +85 °C
3. Hmin characterized according to ISO10373-7 test method
4. Pmin calculated from DC measurements
Note:
We recommend to choose the Energy Harvesting Range in respect with the maximum
current requested by the application to avoid any disabling of Energy Harvesting mode (for
example, choose Range 01 for a max consumption of 2 mA).
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RF electrical parameters
M24LR04E-R
Figure 82. Vout vs. Isink
7PVU
7
7
7
7
7
N"
N"
N"
N"
*TJOL
MS19777V1
Figure 83. Range 11 domain
Fan out
(A)
6 mA
Working domain when
Range 11 is selected
3 mA
1 mA
0.3 mA
1 A/m 1.6 A/m 2.4 A/m
3.5 A/m
5 A/m
Field
(Hrms)
MS19790V1
130/142
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M24LR04E-R
RF electrical parameters
Figure 84. Range 10 domain
Fan out
(A)
6 mA
Working domain when
Range 10 is selected
3 mA
1 mA
0.3 mA
1 A/m 1.6 A/m 2.4 A/m
3.5 A/m
5 A/m
Field
(Hrms)
MS19791V1
Figure 85. Range 01 domain
Fan out
(A)
6 mA
Working domain when
Range 01 is selected
3 mA
1 mA
0.3 mA
1 A/m 1.6 A/m 2.4 A/m
3.5 A/m
5 A/m
Field
(Hrms)
MS19792V1
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RF electrical parameters
M24LR04E-R
Figure 86. Range 00 domain
Fan out
(A)
Working domain when
Range 00 is selected
6 mA
3 mA
1 mA
0.3 mA
1 A/m 1.6 A/m 2.4 A/m
3.5 A/m
5 A/m
Field
(Hrms)
MS19793V1
132/142
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M24LR04E-R
30
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 87. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
GAUGE PLANE
D
k
8
E1
E
1
A1
L
L1
SO-A
1. Drawing is not to scale.
Table 126. SO8N – 8-lead plastic small outline, 150 mils body width, package data
inches(1)
millimeters
Symbol
Typ
Min
A
Max
Typ
Min
1.75
Max
0.0689
A1
0.10
A2
1.25
b
0.28
0.48
0.0110
0.0189
c
0.17
0.23
0.0067
0.0091
ccc
0.25
0.0039
0.0098
0.0492
0.10
0.0039
D
4.90
4.80
5.00
0.1929
0.1890
0.1969
E
6.00
5.80
6.20
0.2362
0.2283
0.2441
E1
3.90
3.80
4.00
0.1535
0.1496
0.1575
e
1.27
–
–
0.0500
–
–
h
0.25
0.50
k
0°
8°
0°
8°
L
0.40
1.27
0.0157
0.0500
L1
1.04
0.0410
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package mechanical data
M24LR04E-R
Figure 88. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 × 3mm, package outline
MB
e
D
MC
e
b
L1
L3
E
b
L1
L3
E2
Pin 1
E2
K
K
L
L
A
D2
D2
eee
A1
ZW_MEe
1. Drawing is not to scale.
2. The central pad (E2 × D2 area in the above illustration) is internally pulled to VSS. It must not be allowed to
be connected to any other voltage or signal line on the PCB, for example during the soldering process.
3. The circle in the top view of the package indicates the position of pin 1.
Table 127. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data
inches(1)
millimeters
Symbol
Typ
Min
Max
Typ
Min
Max
A
0.550
0.450
0.600
0.0217
0.0177
0.0236
A1
0.020
0.000
0.050
0.0008
0.0000
0.0020
b
0.250
0.200
0.300
0.0098
0.0079
0.0118
D
2.000
1.900
2.100
0.0787
0.0748
0.0827
1.200
1.600
0.0472
0.0630
2.900
3.100
0.1142
0.1220
1.200
1.600
0.0472
0.0630
D2 (rev MC)
E
3.000
E2 (rev MC)
e
0.500
0.1181
0.0197
K
0.300
L
0.300
L1
0.0118
0.500
0.0118
0.150
0.0197
0.0059
L3
0.300
0.0118
eee(2)
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.
134/142
Doc ID 022208 Rev 5
M24LR04E-R
Package mechanical data
Figure 89. TSSOP8 – 8-lead thin shrink small outline, package outline
D
8
5
c
E1
1
E
4
α
A1
A
L
A2
L1
CP
b
e
TSSOP8AM
1. Drawing is not to scale.
Table 128. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
inches(1)
millimeters
Symbol
Typ
Min
A
Max
Min
1.2
A1
0.05
0.15
0.8
1.05
b
0.19
c
0.09
A2
Typ
1
CP
Max
0.0472
0.002
0.0059
0.0315
0.0413
0.3
0.0075
0.0118
0.2
0.0035
0.0079
0.0394
0.1
0.0039
D
3
2.9
3.1
0.1181
0.1142
0.122
e
0.65
-
-
0.0256
-
-
E
6.4
6.2
6.6
0.252
0.2441
0.2598
E1
4.4
4.3
4.5
0.1732
0.1693
0.1772
L
0.6
0.45
0.75
0.0236
0.0177
0.0295
L1
1
0°
8°
a
N
0.0394
0°
8°
8
8
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 022208 Rev 5
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Part numbering
31
M24LR04E-R
Part numbering
Table 129. Ordering information scheme for bare die devices or packaged devices
Example:
M24LR04E-R
MN
6
T
/2
Device type
M24LR = dual interface EEPROM
04 = memory size in Kbit
E = support for energy harvesting
Operating voltage
R = VCC = 1.8 to 5.5 V
Package
MN = SO8N (150 mils width)
MC = UFDFPN8 (MLP8)
DW = TSSOP8
UW20 = inkless, unsawn wafer, with no backgrinding(1)
Device grade(2)
6 = industrial: device tested with standard
test flow over –40 to 85 °C
Option(2)
T = Tape and reel packing
Capacitance
/2 = 27.5 pF
1. Delivery type: wafer tested, unsawn, without backgrinding. Wafer thickness: 725 µm ±20 µm.
Bad chip identification by STIF wafer maps provided by STMicroelectronics.
2. For packaged devices only.
136/142
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M24LR04E-R
Appendix A
Anticollision algorithm (informative)
Anticollision algorithm (informative)
The following pseudocode describes how anticollision could be implemented on the VCD,
using recursivity.
A.1
Algorithm for pulsed slots
function
function
function
function
push (mask, address); pushes on private stack
pop (mask, address); pops from private stack
pulse_next_pause; generates a power pulse
store(M24LR04E-R_UID); stores M24LR04E-R_UID
function poll_loop (sub_address_size as integer)
pop (mask, address)
mask = address & mask; generates new mask
; send the request
mode = anticollision
send_Request (Request_cmd, mode, mask length, mask value)
for sub_address = 0 to (2^sub_address_size - 1)
pulse_next_pause
if no_collision_is_detected ; M24LR04E-R is inventoried
then
store (M24LR04E-R_UID)
else ; remember a collision was detected
push(mask,address)
endif
next sub_address
if stack_not_empty ; if some collisions have been detected and
then
; not yet processed, the function calls itself
poll_loop (sub_address_size); recursively to process the
last stored collision
endif
end poll_loop
main_cycle:
mask = null
address = null
push (mask, address)
poll_loop(sub_address_size)
end_main_cycle
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CRC (informative)
Appendix B
B.1
M24LR04E-R
CRC (informative)
CRC error detection method
The cyclic redundancy check (CRC) is calculated on all data contained in a message, from
the start of the flags through to the end of Data. The CRC is used from VCD to M24LR04ER and from M24LR04E-R to VCD.
Table 130. CRC definition
CRC definition
CRC type
ISO/IEC 13239
Length
16 bits
Polynomial
16
X
+
X12
+
X5
+ 1 = 8408h
Direction
Preset
Residue
Backward
FFFFh
F0B8h
To add extra protection against shifting errors, a further transformation on the calculated
CRC is made. The one’s complement of the calculated CRC is the value attached to the
message for transmission.
To check received messages, the two CRC bytes are often also included in the recalculation, for ease of use. In this case, the expected value for the generated CRC is the
residue F0B8h.
B.2
CRC calculation example
This example in C language illustrates one method of calculating the CRC on a given set of
bytes comprising a message.
C-example to calculate or check the CRC16 according to ISO/IEC 13239
#define
#define
#define
POLYNOMIAL0x8408//
PRESET_VALUE0xFFFF
CHECK_VALUE0xF0B8
x^16 + x^12 + x^5 + 1
#define
#define
#define
NUMBER_OF_BYTES4// Example: 4 data bytes
CALC_CRC1
CHECK_CRC0
void main()
{
unsigned int current_crc_value;
unsigned char array_of_databytes[NUMBER_OF_BYTES + 2] = {1, 2, 3,
4, 0x91, 0x39};
int
number_of_databytes = NUMBER_OF_BYTES;
int
calculate_or_check_crc;
int
i, j;
calculate_or_check_crc = CALC_CRC;
// calculate_or_check_crc = CHECK_CRC;// This could be an other
example
if (calculate_or_check_crc == CALC_CRC)
{
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CRC (informative)
number_of_databytes = NUMBER_OF_BYTES;
}
else
// check CRC
{
number_of_databytes = NUMBER_OF_BYTES + 2;
}
current_crc_value = PRESET_VALUE;
for (i = 0; i < number_of_databytes; i++)
{
current_crc_value = current_crc_value ^ ((unsigned
int)array_of_databytes[i]);
for (j = 0; j < 8; j++)
{
if (current_crc_value & 0x0001)
{
current_crc_value = (current_crc_value >> 1) ^
POLYNOMIAL;
}
else
{
current_crc_value = (current_crc_value >> 1);
}
}
}
if (calculate_or_check_crc == CALC_CRC)
{
current_crc_value = ~current_crc_value;
printf ("Generated CRC is 0x%04X\n", current_crc_value);
//
stream
//
}
else
{
if
{
current_crc_value is now ready to be appended to the data
(first LSByte, then MSByte)
// check CRC
(current_crc_value == CHECK_VALUE)
printf ("Checked CRC is ok (0x%04X)\n",
current_crc_value);
}
else
{
printf ("Checked CRC is NOT ok (0x%04X)\n",
current_crc_value);
}
}
}
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Application family identifier (AFI) (informative)
Appendix C
M24LR04E-R
Application family identifier (AFI)
(informative)
The AFI (application family identifier) represents the type of application targeted by the VCD
and is used to extract from all the M24LR04E-Rs present only the M24LR04E-R meeting the
required application criteria.
It is programmed by the M24LR04E-R issuer (the purchaser of the M24LR04E-R). Once
locked, it cannot be modified.
The most significant nibble of the AFI is used to code one specific or all application families,
as defined in Table 131.
The least significant nibble of the AFI is used to code one specific or all application
subfamilies. Subfamily codes different from 0 are proprietary.
Table 131. AFI coding(1)
AFI
AFI
most
significant
nibble
least
significant
nibble
‘0’
‘0’
All families and subfamilies
No applicative preselection
‘X’
'0
All subfamilies of family X
Wide applicative preselection
'X
'‘Y’
Only the Yth subfamily of family X
‘0’
‘Y’
Proprietary subfamily Y only
‘1
'‘0’, ‘Y’
Transport
Mass transit, bus, airline,...
'2
'‘0’, ‘Y’
Financial
IEP, banking, retail,...
'3
'‘0’, ‘Y’
Identification
Access control,...
'4
'‘0’, ‘Y’
Telecommunication
Public telephony, GSM,...
‘5’
‘0’, ‘Y’
Medical
'6
'‘0’, ‘Y’
Multimedia
'7
'‘0’, ‘Y’
Gaming
8
'‘0’, ‘Y’
Data Storage
'9
'‘0’, ‘Y’
Item management
'A
'‘0’, ‘Y’
Express parcels
'B
'‘0’, ‘Y’
Postal services
'C
'‘0’, ‘Y’
Airline bags
'D
'‘0’, ‘Y’
RFU
'E
'‘0’, ‘Y’
RFU
‘F’
‘0’, ‘Y’
RFU
Meaning
VICCs respond from
1. X = '1' to 'F', Y = '1' to 'F'
140/142
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Examples / Note
Internet services....
Portable files,...
M24LR04E-R
Revision history
Revision history
Table 132. Document revision history
Date
Revision
Changes
06-Dec-2011
1
Initial release.
06-Feb-2012
2
Updated Table 125: Energy harvesting and added note under the
table.
Replaced figures 82 to 86.
21-Feb-2012
3
Changed datasheet status to “Full datasheet”.
21-May-2012
4
Updated Table 122: I2C AC characteristics and Section 31: Part
numbering.
12-Jun-2012
5
Updated Figure 49: M24LR04E-R state transition diagram on page 66.
Doc ID 022208 Rev 5
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M24LR04E-R
Please Read Carefully:
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right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
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All ST products are sold pursuant to ST’s terms and conditions of sale.
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